2 * drivers/usb/gadget/dwc2_udc_otg.c
3 * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
5 * Copyright (C) 2008 for Samsung Electronics
7 * BSP Support for Samsung's UDC driver
9 * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
11 * State machine bugfixes:
12 * Marek Szyprowski <m.szyprowski@samsung.com>
15 * Marek Szyprowski <m.szyprowski@samsung.com>
16 * Lukasz Majewski <l.majewski@samsumg.com>
18 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/errno.h>
23 #include <linux/list.h>
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
29 #include <asm/byteorder.h>
30 #include <asm/unaligned.h>
33 #include <asm/mach-types.h>
35 #include "dwc2_udc_otg_regs.h"
36 #include "dwc2_udc_otg_priv.h"
37 #include <usb/lin_gadget_compat.h>
39 /***********************************************************/
41 #define OTG_DMA_MODE 1
46 #define DEBUG_OUT_EP 0
49 #include <usb/dwc2_udc.h>
54 static char *state_names[] = {
57 "DATA_STATE_NEED_ZLP",
58 "WAIT_FOR_OUT_STATUS",
61 "WAIT_FOR_OUT_COMPLETE",
62 "WAIT_FOR_IN_COMPLETE",
63 "WAIT_FOR_NULL_COMPLETE",
66 #define DRIVER_DESC "DWC2 HS USB OTG Device Driver, (c) Samsung Electronics"
67 #define DRIVER_VERSION "15 March 2009"
69 struct dwc2_udc *the_controller;
71 static const char driver_name[] = "dwc2-udc";
72 static const char driver_desc[] = DRIVER_DESC;
73 static const char ep0name[] = "ep0-control";
76 static unsigned int ep0_fifo_size = 64;
77 static unsigned int ep_fifo_size = 512;
78 static unsigned int ep_fifo_size2 = 1024;
79 static int reset_available = 1;
81 static struct usb_ctrlrequest *usb_ctrl;
82 static dma_addr_t usb_ctrl_dma_addr;
87 static int dwc2_ep_enable(struct usb_ep *ep,
88 const struct usb_endpoint_descriptor *);
89 static int dwc2_ep_disable(struct usb_ep *ep);
90 static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
92 static void dwc2_free_request(struct usb_ep *ep, struct usb_request *);
94 static int dwc2_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
95 static int dwc2_dequeue(struct usb_ep *ep, struct usb_request *);
96 static int dwc2_fifo_status(struct usb_ep *ep);
97 static void dwc2_fifo_flush(struct usb_ep *ep);
98 static void dwc2_ep0_read(struct dwc2_udc *dev);
99 static void dwc2_ep0_kick(struct dwc2_udc *dev, struct dwc2_ep *ep);
100 static void dwc2_handle_ep0(struct dwc2_udc *dev);
101 static int dwc2_ep0_write(struct dwc2_udc *dev);
102 static int write_fifo_ep0(struct dwc2_ep *ep, struct dwc2_request *req);
103 static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status);
104 static void stop_activity(struct dwc2_udc *dev,
105 struct usb_gadget_driver *driver);
106 static int udc_enable(struct dwc2_udc *dev);
107 static void udc_set_address(struct dwc2_udc *dev, unsigned char address);
108 static void reconfig_usbd(struct dwc2_udc *dev);
109 static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed);
110 static void nuke(struct dwc2_ep *ep, int status);
111 static int dwc2_udc_set_halt(struct usb_ep *_ep, int value);
112 static void dwc2_udc_set_nak(struct dwc2_ep *ep);
114 void set_udc_gadget_private_data(void *p)
116 debug_cond(DEBUG_SETUP != 0,
117 "%s: the_controller: 0x%p, p: 0x%p\n", __func__,
119 the_controller->gadget.dev.device_data = p;
122 void *get_udc_gadget_private_data(struct usb_gadget *gadget)
124 return gadget->dev.device_data;
127 static struct usb_ep_ops dwc2_ep_ops = {
128 .enable = dwc2_ep_enable,
129 .disable = dwc2_ep_disable,
131 .alloc_request = dwc2_alloc_request,
132 .free_request = dwc2_free_request,
135 .dequeue = dwc2_dequeue,
137 .set_halt = dwc2_udc_set_halt,
138 .fifo_status = dwc2_fifo_status,
139 .fifo_flush = dwc2_fifo_flush,
142 #define create_proc_files() do {} while (0)
143 #define remove_proc_files() do {} while (0)
145 /***********************************************************/
147 void __iomem *regs_otg;
148 struct dwc2_usbotg_reg *reg;
150 bool dfu_usb_get_reset(void)
152 return !!(readl(®->gintsts) & INT_RESET);
155 __weak void otg_phy_init(struct dwc2_udc *dev) {}
156 __weak void otg_phy_off(struct dwc2_udc *dev) {}
158 /***********************************************************/
160 #include "dwc2_udc_otg_xfer_dma.c"
163 * udc_disable - disable USB device controller
165 static void udc_disable(struct dwc2_udc *dev)
167 debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
169 udc_set_address(dev, 0);
171 dev->ep0state = WAIT_FOR_SETUP;
172 dev->gadget.speed = USB_SPEED_UNKNOWN;
173 dev->usb_address = 0;
179 * udc_reinit - initialize software state
181 static void udc_reinit(struct dwc2_udc *dev)
185 debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
187 /* device/ep0 records init */
188 INIT_LIST_HEAD(&dev->gadget.ep_list);
189 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
190 dev->ep0state = WAIT_FOR_SETUP;
192 /* basic endpoint records init */
193 for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
194 struct dwc2_ep *ep = &dev->ep[i];
197 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
201 INIT_LIST_HEAD(&ep->queue);
205 /* the rest was statically initialized, and is read-only */
208 #define BYTES2MAXP(x) (x / 8)
209 #define MAXP2BYTES(x) (x * 8)
211 /* until it's enabled, this UDC should be completely invisible
214 static int udc_enable(struct dwc2_udc *dev)
216 debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
221 debug_cond(DEBUG_SETUP != 0,
222 "DWC2 USB 2.0 OTG Controller Core Initialized : 0x%x\n",
223 readl(®->gintmsk));
225 dev->gadget.speed = USB_SPEED_UNKNOWN;
231 Register entry point for the peripheral controller driver.
233 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
235 struct dwc2_udc *dev = the_controller;
237 unsigned long flags = 0;
239 debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
242 || (driver->speed != USB_SPEED_FULL
243 && driver->speed != USB_SPEED_HIGH)
244 || !driver->bind || !driver->disconnect || !driver->setup)
251 spin_lock_irqsave(&dev->lock, flags);
252 /* first hook up the driver ... */
253 dev->driver = driver;
254 spin_unlock_irqrestore(&dev->lock, flags);
256 if (retval) { /* TODO */
257 printf("target device_add failed, error %d\n", retval);
261 retval = driver->bind(&dev->gadget);
263 debug_cond(DEBUG_SETUP != 0,
264 "%s: bind to driver --> error %d\n",
265 dev->gadget.name, retval);
272 debug_cond(DEBUG_SETUP != 0,
273 "Registered gadget driver %s\n", dev->gadget.name);
280 * Unregister entry point for the peripheral controller driver.
282 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
284 struct dwc2_udc *dev = the_controller;
285 unsigned long flags = 0;
289 if (!driver || driver != dev->driver)
292 spin_lock_irqsave(&dev->lock, flags);
294 stop_activity(dev, driver);
295 spin_unlock_irqrestore(&dev->lock, flags);
297 driver->unbind(&dev->gadget);
299 disable_irq(IRQ_OTG);
306 * done - retire a request; caller blocked irqs
308 static void done(struct dwc2_ep *ep, struct dwc2_request *req, int status)
310 unsigned int stopped = ep->stopped;
312 debug("%s: %s %p, req = %p, stopped = %d\n",
313 __func__, ep->ep.name, ep, &req->req, stopped);
315 list_del_init(&req->queue);
317 if (likely(req->req.status == -EINPROGRESS))
318 req->req.status = status;
320 status = req->req.status;
322 if (status && status != -ESHUTDOWN) {
323 debug("complete %s req %p stat %d len %u/%u\n",
324 ep->ep.name, &req->req, status,
325 req->req.actual, req->req.length);
328 /* don't modify queue heads during completion callback */
332 printf("calling complete callback\n");
334 int i, len = req->req.length;
336 printf("pkt[%d] = ", req->req.length);
339 for (i = 0; i < len; i++) {
340 printf("%02x", ((u8 *)req->req.buf)[i]);
347 spin_unlock(&ep->dev->lock);
348 req->req.complete(&ep->ep, &req->req);
349 spin_lock(&ep->dev->lock);
351 debug("callback completed\n");
353 ep->stopped = stopped;
357 * nuke - dequeue ALL requests
359 static void nuke(struct dwc2_ep *ep, int status)
361 struct dwc2_request *req;
363 debug("%s: %s %p\n", __func__, ep->ep.name, ep);
365 /* called with irqs blocked */
366 while (!list_empty(&ep->queue)) {
367 req = list_entry(ep->queue.next, struct dwc2_request, queue);
368 done(ep, req, status);
372 static void stop_activity(struct dwc2_udc *dev,
373 struct usb_gadget_driver *driver)
377 /* don't disconnect drivers more than once */
378 if (dev->gadget.speed == USB_SPEED_UNKNOWN)
380 dev->gadget.speed = USB_SPEED_UNKNOWN;
382 /* prevent new request submissions, kill any outstanding requests */
383 for (i = 0; i < DWC2_MAX_ENDPOINTS; i++) {
384 struct dwc2_ep *ep = &dev->ep[i];
386 nuke(ep, -ESHUTDOWN);
389 /* report disconnect; the driver is already quiesced */
391 spin_unlock(&dev->lock);
392 driver->disconnect(&dev->gadget);
393 spin_lock(&dev->lock);
396 /* re-init driver-visible data structures */
400 static void reconfig_usbd(struct dwc2_udc *dev)
402 /* 2. Soft-reset OTG Core and then unreset again. */
404 unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl);
405 uint32_t dflt_gusbcfg;
406 uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
408 debug("Reseting OTG controller\n");
411 0<<15 /* PHY Low Power Clock sel*/
412 |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
413 |0x5<<10 /* Turnaround time*/
414 |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
415 /* 1:SRP enable] H1= 1,1*/
416 |0<<7 /* Ulpi DDR sel*/
417 |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
418 |0<<4 /* 0: utmi+, 1:ulpi*/
419 #ifdef CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8
420 |0<<3 /* phy i/f 0:8bit, 1:16bit*/
422 |1<<3 /* phy i/f 0:8bit, 1:16bit*/
424 |0x7<<0; /* HS/FS Timeout**/
426 if (dev->pdata->usb_gusbcfg)
427 dflt_gusbcfg = dev->pdata->usb_gusbcfg;
429 writel(dflt_gusbcfg, ®->gusbcfg);
431 /* 3. Put the OTG device core in the disconnected state.*/
432 uTemp = readl(®->dctl);
433 uTemp |= SOFT_DISCONNECT;
434 writel(uTemp, ®->dctl);
438 /* 4. Make the OTG device core exit from the disconnected state.*/
439 uTemp = readl(®->dctl);
440 uTemp = uTemp & ~SOFT_DISCONNECT;
441 writel(uTemp, ®->dctl);
443 /* 5. Configure OTG Core to initial settings of device mode.*/
444 /* [][1: full speed(30Mhz) 0:high speed]*/
445 writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, ®->dcfg);
449 /* 6. Unmask the core interrupts*/
450 writel(GINTMSK_INIT, ®->gintmsk);
452 /* 7. Set NAK bit of EP0, EP1, EP2*/
453 writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[EP0_CON].doepctl);
454 writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[EP0_CON].diepctl);
456 for (i = 1; i < DWC2_MAX_ENDPOINTS; i++) {
457 writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->out_endp[i].doepctl);
458 writel(DEPCTL_EPDIS|DEPCTL_SNAK, ®->in_endp[i].diepctl);
461 /* 8. Unmask EPO interrupts*/
462 writel(((1 << EP0_CON) << DAINT_OUT_BIT)
463 | (1 << EP0_CON), ®->daintmsk);
465 /* 9. Unmask device OUT EP common interrupts*/
466 writel(DOEPMSK_INIT, ®->doepmsk);
468 /* 10. Unmask device IN EP common interrupts*/
469 writel(DIEPMSK_INIT, ®->diepmsk);
471 rx_fifo_sz = RX_FIFO_SIZE;
472 np_tx_fifo_sz = NPTX_FIFO_SIZE;
473 tx_fifo_sz = PTX_FIFO_SIZE;
475 if (dev->pdata->rx_fifo_sz)
476 rx_fifo_sz = dev->pdata->rx_fifo_sz;
477 if (dev->pdata->np_tx_fifo_sz)
478 np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
479 if (dev->pdata->tx_fifo_sz)
480 tx_fifo_sz = dev->pdata->tx_fifo_sz;
482 /* 11. Set Rx FIFO Size (in 32-bit words) */
483 writel(rx_fifo_sz, ®->grxfsiz);
485 /* 12. Set Non Periodic Tx FIFO Size */
486 writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
489 for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
490 writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) |
491 tx_fifo_sz << 16, ®->dieptxf[i-1]);
493 /* Flush the RX FIFO */
494 writel(RX_FIFO_FLUSH, ®->grstctl);
495 while (readl(®->grstctl) & RX_FIFO_FLUSH)
496 debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
498 /* Flush all the Tx FIFO's */
499 writel(TX_FIFO_FLUSH_ALL, ®->grstctl);
500 writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, ®->grstctl);
501 while (readl(®->grstctl) & TX_FIFO_FLUSH)
502 debug("%s: waiting for DWC2_UDC_OTG_GRSTCTL\n", __func__);
504 /* 13. Clear NAK bit of EP0, EP1, EP2*/
506 /* EP0: Control OUT */
507 writel(DEPCTL_EPDIS | DEPCTL_CNAK,
508 ®->out_endp[EP0_CON].doepctl);
510 /* 14. Initialize OTG Link Core.*/
511 writel(GAHBCFG_INIT, ®->gahbcfg);
514 static void set_max_pktsize(struct dwc2_udc *dev, enum usb_device_speed speed)
516 unsigned int ep_ctrl;
519 if (speed == USB_SPEED_HIGH) {
522 ep_fifo_size2 = 1024;
523 dev->gadget.speed = USB_SPEED_HIGH;
528 dev->gadget.speed = USB_SPEED_FULL;
531 dev->ep[0].ep.maxpacket = ep0_fifo_size;
532 for (i = 1; i < DWC2_MAX_ENDPOINTS; i++)
533 dev->ep[i].ep.maxpacket = ep_fifo_size;
535 /* EP0 - Control IN (64 bytes)*/
536 ep_ctrl = readl(®->in_endp[EP0_CON].diepctl);
537 writel(ep_ctrl|(0<<0), ®->in_endp[EP0_CON].diepctl);
539 /* EP0 - Control OUT (64 bytes)*/
540 ep_ctrl = readl(®->out_endp[EP0_CON].doepctl);
541 writel(ep_ctrl|(0<<0), ®->out_endp[EP0_CON].doepctl);
544 static int dwc2_ep_enable(struct usb_ep *_ep,
545 const struct usb_endpoint_descriptor *desc)
548 struct dwc2_udc *dev;
549 unsigned long flags = 0;
551 debug("%s: %p\n", __func__, _ep);
553 ep = container_of(_ep, struct dwc2_ep, ep);
554 if (!_ep || !desc || ep->desc || _ep->name == ep0name
555 || desc->bDescriptorType != USB_DT_ENDPOINT
556 || ep->bEndpointAddress != desc->bEndpointAddress
557 || ep_maxpacket(ep) <
558 le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
560 debug("%s: bad ep or descriptor\n", __func__);
564 /* xfer types must match, except that interrupt ~= bulk */
565 if (ep->bmAttributes != desc->bmAttributes
566 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
567 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
569 debug("%s: %s type mismatch\n", __func__, _ep->name);
573 /* hardware _could_ do smaller, but driver doesn't */
574 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK &&
575 le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) >
576 ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
578 debug("%s: bad %s maxpacket\n", __func__, _ep->name);
583 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
585 debug("%s: bogus device state\n", __func__);
592 ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
594 /* Reset halt state */
595 dwc2_udc_set_nak(ep);
596 dwc2_udc_set_halt(_ep, 0);
598 spin_lock_irqsave(&ep->dev->lock, flags);
599 dwc2_udc_ep_activate(ep);
600 spin_unlock_irqrestore(&ep->dev->lock, flags);
602 debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
603 __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
610 static int dwc2_ep_disable(struct usb_ep *_ep)
613 unsigned long flags = 0;
615 debug("%s: %p\n", __func__, _ep);
617 ep = container_of(_ep, struct dwc2_ep, ep);
618 if (!_ep || !ep->desc) {
619 debug("%s: %s not enabled\n", __func__,
620 _ep ? ep->ep.name : NULL);
624 spin_lock_irqsave(&ep->dev->lock, flags);
626 /* Nuke all pending requests */
627 nuke(ep, -ESHUTDOWN);
632 spin_unlock_irqrestore(&ep->dev->lock, flags);
634 debug("%s: disabled %s\n", __func__, _ep->name);
638 static struct usb_request *dwc2_alloc_request(struct usb_ep *ep,
641 struct dwc2_request *req;
643 debug("%s: %s %p\n", __func__, ep->name, ep);
645 req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
649 memset(req, 0, sizeof *req);
650 INIT_LIST_HEAD(&req->queue);
655 static void dwc2_free_request(struct usb_ep *ep, struct usb_request *_req)
657 struct dwc2_request *req;
659 debug("%s: %p\n", __func__, ep);
661 req = container_of(_req, struct dwc2_request, req);
662 WARN_ON(!list_empty(&req->queue));
666 /* dequeue JUST ONE request */
667 static int dwc2_dequeue(struct usb_ep *_ep, struct usb_request *_req)
670 struct dwc2_request *req;
671 unsigned long flags = 0;
673 debug("%s: %p\n", __func__, _ep);
675 ep = container_of(_ep, struct dwc2_ep, ep);
676 if (!_ep || ep->ep.name == ep0name)
679 spin_lock_irqsave(&ep->dev->lock, flags);
681 /* make sure it's actually queued on this endpoint */
682 list_for_each_entry(req, &ep->queue, queue) {
683 if (&req->req == _req)
686 if (&req->req != _req) {
687 spin_unlock_irqrestore(&ep->dev->lock, flags);
691 done(ep, req, -ECONNRESET);
693 spin_unlock_irqrestore(&ep->dev->lock, flags);
698 * Return bytes in EP FIFO
700 static int dwc2_fifo_status(struct usb_ep *_ep)
705 ep = container_of(_ep, struct dwc2_ep, ep);
707 debug("%s: bad ep\n", __func__);
711 debug("%s: %d\n", __func__, ep_index(ep));
713 /* LPD can't report unclaimed bytes from IN fifos */
723 static void dwc2_fifo_flush(struct usb_ep *_ep)
727 ep = container_of(_ep, struct dwc2_ep, ep);
728 if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
729 debug("%s: bad ep\n", __func__);
733 debug("%s: %d\n", __func__, ep_index(ep));
736 static const struct usb_gadget_ops dwc2_udc_ops = {
737 /* current versions must always be self-powered */
740 static struct dwc2_udc memory = {
743 .ops = &dwc2_udc_ops,
744 .ep0 = &memory.ep[0].ep,
748 /* control endpoint */
753 .maxpacket = EP0_FIFO_SIZE,
757 .bEndpointAddress = 0,
760 .ep_type = ep_control,
763 /* first group of endpoints */
766 .name = "ep1in-bulk",
768 .maxpacket = EP_FIFO_SIZE,
772 .bEndpointAddress = USB_DIR_IN | 1,
773 .bmAttributes = USB_ENDPOINT_XFER_BULK,
775 .ep_type = ep_bulk_out,
781 .name = "ep2out-bulk",
783 .maxpacket = EP_FIFO_SIZE,
787 .bEndpointAddress = USB_DIR_OUT | 2,
788 .bmAttributes = USB_ENDPOINT_XFER_BULK,
790 .ep_type = ep_bulk_in,
798 .maxpacket = EP_FIFO_SIZE,
802 .bEndpointAddress = USB_DIR_IN | 3,
803 .bmAttributes = USB_ENDPOINT_XFER_INT,
805 .ep_type = ep_interrupt,
811 * probe - binds to the platform device
814 int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata)
816 struct dwc2_udc *dev = &memory;
819 debug("%s: %p\n", __func__, pdata);
823 reg = (struct dwc2_usbotg_reg *)pdata->regs_otg;
825 /* regs_otg = (void *)pdata->regs_otg; */
827 dev->gadget.is_dualspeed = 1; /* Hack only*/
828 dev->gadget.is_otg = 0;
829 dev->gadget.is_a_peripheral = 0;
830 dev->gadget.b_hnp_enable = 0;
831 dev->gadget.a_hnp_support = 0;
832 dev->gadget.a_alt_hnp_support = 0;
834 the_controller = dev;
836 usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE,
837 ROUND(sizeof(struct usb_ctrlrequest),
838 CONFIG_SYS_CACHELINE_SIZE));
840 error("No memory available for UDC!\n");
844 usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl;
851 int usb_gadget_handle_interrupts(int index)
853 u32 intr_status = readl(®->gintsts);
854 u32 gintmsk = readl(®->gintmsk);
856 if (intr_status & gintmsk)
857 return dwc2_udc_irq(1, (void *)the_controller);