2 * Copyright 2015 Broadcom Corporation.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/sysmap.h>
12 #include <usb/s3c_udc.h>
13 #include "bcm_udc_otg.h"
15 void otg_phy_init(struct s3c_udc *dev)
17 /* set Phy to driving mode */
18 wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
19 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
23 /* clear Soft Disconnect */
24 wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
25 HSOTG_DCTL_SFTDISCON_MASK);
27 /* invoke Reset (active low) */
28 wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
29 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
31 /* Reset needs to be asserted for 2ms */
35 wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
36 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
37 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
40 void otg_phy_off(struct s3c_udc *dev)
43 wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
44 HSOTG_DCTL_SFTDISCON_MASK,
45 HSOTG_DCTL_SFTDISCON_MASK);
47 /* set Phy to non-driving (reset) mode */
48 wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
49 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
50 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);