drivers/usb/gadget/bcm_udc_otg_phy.c

   1 /*
   2  * Copyright 2015 Broadcom Corporation.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <config.h>
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/sysmap.h>
  11
  12 #include "dwc2_udc_otg_priv.h"
  13 #include "bcm_udc_otg.h"
  14
  15 void otg_phy_init(struct dwc2_udc *dev)
  16 {
  17         /* set Phy to driving mode */
  18         wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
  19                    HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
  20
  21         udelay(100);
  22
  23         /* clear Soft Disconnect */
  24         wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
  25                    HSOTG_DCTL_SFTDISCON_MASK);
  26
  27         /* invoke Reset (active low) */
  28         wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
  29                    HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
  30
  31         /* Reset needs to be asserted for 2ms */
  32         udelay(2000);
  33
  34         /* release Reset */
  35         wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
  36                  HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
  37                  HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
  38 }
  39
  40 void otg_phy_off(struct dwc2_udc *dev)
  41 {
  42         /* Soft Disconnect */
  43         wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
  44                  HSOTG_DCTL_SFTDISCON_MASK,
  45                  HSOTG_DCTL_SFTDISCON_MASK);
  46
  47         /* set Phy to non-driving (reset) mode */
  48         wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
  49                  HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
  50                  HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
  51 }