2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
14 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
15 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
16 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
18 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
19 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
22 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
23 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
24 * can be used with gadget ether.
28 /* #define UDC_VERBOSE */
31 #define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
32 #define UDC_DRIVER_VERSION_STRING "01.00.0206"
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/ioport.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/errno.h>
43 #include <linux/init.h>
44 #include <linux/timer.h>
45 #include <linux/list.h>
46 #include <linux/interrupt.h>
47 #include <linux/ioctl.h>
49 #include <linux/dmapool.h>
50 #include <linux/moduleparam.h>
51 #include <linux/device.h>
53 #include <linux/irq.h>
54 #include <linux/prefetch.h>
56 #include <asm/byteorder.h>
57 #include <asm/unaligned.h>
60 #include <linux/usb/ch9.h>
61 #include <linux/usb/gadget.h>
64 #include "amd5536udc.h"
67 static void udc_tasklet_disconnect(unsigned long);
68 static void empty_req_queue(struct udc_ep *);
69 static int udc_probe(struct udc *dev);
70 static void udc_basic_init(struct udc *dev);
71 static void udc_setup_endpoints(struct udc *dev);
72 static void udc_soft_reset(struct udc *dev);
73 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
74 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
75 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
76 static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
77 unsigned long buf_len, gfp_t gfp_flags);
78 static int udc_remote_wakeup(struct udc *dev);
79 static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
80 static void udc_pci_remove(struct pci_dev *pdev);
83 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
84 static const char name[] = "amd5536udc";
86 /* structure to hold endpoint function pointers */
87 static const struct usb_ep_ops udc_ep_ops;
89 /* received setup data */
90 static union udc_setup_data setup_data;
92 /* pointer to device object */
93 static struct udc *udc;
95 /* irq spin lock for soft reset */
96 static DEFINE_SPINLOCK(udc_irq_spinlock);
98 static DEFINE_SPINLOCK(udc_stall_spinlock);
101 * slave mode: pending bytes in rx fifo after nyet,
102 * used if EPIN irq came but no req was available
104 static unsigned int udc_rxfifo_pending;
106 /* count soft resets after suspend to avoid loop */
107 static int soft_reset_occured;
108 static int soft_reset_after_usbreset_occured;
111 static struct timer_list udc_timer;
112 static int stop_timer;
114 /* set_rde -- Is used to control enabling of RX DMA. Problem is
115 * that UDC has only one bit (RDE) to enable/disable RX DMA for
116 * all OUT endpoints. So we have to handle race conditions like
117 * when OUT data reaches the fifo but no request was queued yet.
118 * This cannot be solved by letting the RX DMA disabled until a
119 * request gets queued because there may be other OUT packets
120 * in the FIFO (important for not blocking control traffic).
121 * The value of set_rde controls the correspondig timer.
123 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
124 * set_rde 0 == do not touch RDE, do no start the RDE timer
125 * set_rde 1 == timer function will look whether FIFO has data
126 * set_rde 2 == set by timer function to enable RX DMA on next call
128 static int set_rde = -1;
130 static DECLARE_COMPLETION(on_exit);
131 static struct timer_list udc_pollstall_timer;
132 static int stop_pollstall_timer;
133 static DECLARE_COMPLETION(on_pollstall_exit);
135 /* tasklet for usb disconnect */
136 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
137 (unsigned long) &udc);
140 /* endpoint names used for print */
141 static const char ep0_string[] = "ep0in";
142 static const char *const ep_string[] = {
144 "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
145 "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
146 "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
147 "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
148 "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
149 "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
150 "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
154 static bool use_dma = 1;
155 /* packet per buffer dma */
156 static bool use_dma_ppb = 1;
157 /* with per descr. update */
158 static bool use_dma_ppb_du;
159 /* buffer fill mode */
160 static int use_dma_bufferfill_mode;
161 /* full speed only mode */
162 static bool use_fullspeed;
163 /* tx buffer size for high speed */
164 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
166 /* module parameters */
167 module_param(use_dma, bool, S_IRUGO);
168 MODULE_PARM_DESC(use_dma, "true for DMA");
169 module_param(use_dma_ppb, bool, S_IRUGO);
170 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
171 module_param(use_dma_ppb_du, bool, S_IRUGO);
172 MODULE_PARM_DESC(use_dma_ppb_du,
173 "true for DMA in packet per buffer mode with descriptor update");
174 module_param(use_fullspeed, bool, S_IRUGO);
175 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
177 /*---------------------------------------------------------------------------*/
178 /* Prints UDC device registers and endpoint irq registers */
179 static void print_regs(struct udc *dev)
181 DBG(dev, "------- Device registers -------\n");
182 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
183 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
184 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
186 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
187 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
189 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
190 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
192 DBG(dev, "USE DMA = %d\n", use_dma);
193 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
194 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
195 "WITHOUT desc. update)\n");
196 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
197 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
198 DBG(dev, "DMA mode = PPBDU (packet per buffer "
199 "WITH desc. update)\n");
200 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
202 if (use_dma && use_dma_bufferfill_mode) {
203 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
204 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
207 dev_info(&dev->pdev->dev, "FIFO mode\n");
208 DBG(dev, "-------------------------------------------------------\n");
211 /* Masks unused interrupts */
212 static int udc_mask_unused_interrupts(struct udc *dev)
216 /* mask all dev interrupts */
217 tmp = AMD_BIT(UDC_DEVINT_SVC) |
218 AMD_BIT(UDC_DEVINT_ENUM) |
219 AMD_BIT(UDC_DEVINT_US) |
220 AMD_BIT(UDC_DEVINT_UR) |
221 AMD_BIT(UDC_DEVINT_ES) |
222 AMD_BIT(UDC_DEVINT_SI) |
223 AMD_BIT(UDC_DEVINT_SOF)|
224 AMD_BIT(UDC_DEVINT_SC);
225 writel(tmp, &dev->regs->irqmsk);
227 /* mask all ep interrupts */
228 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
233 /* Enables endpoint 0 interrupts */
234 static int udc_enable_ep0_interrupts(struct udc *dev)
238 DBG(dev, "udc_enable_ep0_interrupts()\n");
241 tmp = readl(&dev->regs->ep_irqmsk);
242 /* enable ep0 irq's */
243 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
244 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
245 writel(tmp, &dev->regs->ep_irqmsk);
250 /* Enables device interrupts for SET_INTF and SET_CONFIG */
251 static int udc_enable_dev_setup_interrupts(struct udc *dev)
255 DBG(dev, "enable device interrupts for setup data\n");
258 tmp = readl(&dev->regs->irqmsk);
260 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
261 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
262 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
263 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
264 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
265 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
266 writel(tmp, &dev->regs->irqmsk);
271 /* Calculates fifo start of endpoint based on preceding endpoints */
272 static int udc_set_txfifo_addr(struct udc_ep *ep)
278 if (!ep || !(ep->in))
282 ep->txfifo = dev->txfifo;
285 for (i = 0; i < ep->num; i++) {
286 if (dev->ep[i].regs) {
288 tmp = readl(&dev->ep[i].regs->bufin_framenum);
289 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
296 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
297 static u32 cnak_pending;
299 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
301 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
302 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
303 cnak_pending |= 1 << (num);
306 cnak_pending = cnak_pending & (~(1 << (num)));
310 /* Enables endpoint, is called by gadget driver */
312 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
317 unsigned long iflags;
322 || usbep->name == ep0_string
324 || desc->bDescriptorType != USB_DT_ENDPOINT)
327 ep = container_of(usbep, struct udc_ep, ep);
330 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
332 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
335 spin_lock_irqsave(&dev->lock, iflags);
340 /* set traffic type */
341 tmp = readl(&dev->ep[ep->num].regs->ctl);
342 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
343 writel(tmp, &dev->ep[ep->num].regs->ctl);
345 /* set max packet size */
346 maxpacket = usb_endpoint_maxp(desc);
347 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
348 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
349 ep->ep.maxpacket = maxpacket;
350 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
355 /* ep ix in UDC CSR register space */
356 udc_csr_epix = ep->num;
358 /* set buffer size (tx fifo entries) */
359 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
360 /* double buffering: fifo size = 2 x max packet size */
363 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
366 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
368 /* calc. tx fifo base addr */
369 udc_set_txfifo_addr(ep);
372 tmp = readl(&ep->regs->ctl);
373 tmp |= AMD_BIT(UDC_EPCTL_F);
374 writel(tmp, &ep->regs->ctl);
378 /* ep ix in UDC CSR register space */
379 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
381 /* set max packet size UDC CSR */
382 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
383 tmp = AMD_ADDBITS(tmp, maxpacket,
385 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
387 if (use_dma && !ep->in) {
388 /* alloc and init BNA dummy request */
389 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
390 ep->bna_occurred = 0;
393 if (ep->num != UDC_EP0OUT_IX)
394 dev->data_ep_enabled = 1;
398 tmp = readl(&dev->csr->ne[udc_csr_epix]);
400 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
402 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
404 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
406 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
408 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
410 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
412 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
414 writel(tmp, &dev->csr->ne[udc_csr_epix]);
417 tmp = readl(&dev->regs->ep_irqmsk);
418 tmp &= AMD_UNMASK_BIT(ep->num);
419 writel(tmp, &dev->regs->ep_irqmsk);
422 * clear NAK by writing CNAK
423 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
425 if (!use_dma || ep->in) {
426 tmp = readl(&ep->regs->ctl);
427 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
428 writel(tmp, &ep->regs->ctl);
430 UDC_QUEUE_CNAK(ep, ep->num);
432 tmp = desc->bEndpointAddress;
433 DBG(dev, "%s enabled\n", usbep->name);
435 spin_unlock_irqrestore(&dev->lock, iflags);
439 /* Resets endpoint */
440 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
444 VDBG(ep->dev, "ep-%d reset\n", ep->num);
447 ep->ep.ops = &udc_ep_ops;
448 INIT_LIST_HEAD(&ep->queue);
450 ep->ep.maxpacket = (u16) ~0;
452 tmp = readl(&ep->regs->ctl);
453 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
454 writel(tmp, &ep->regs->ctl);
457 /* disable interrupt */
458 tmp = readl(®s->ep_irqmsk);
459 tmp |= AMD_BIT(ep->num);
460 writel(tmp, ®s->ep_irqmsk);
463 /* unset P and IN bit of potential former DMA */
464 tmp = readl(&ep->regs->ctl);
465 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
466 writel(tmp, &ep->regs->ctl);
468 tmp = readl(&ep->regs->sts);
469 tmp |= AMD_BIT(UDC_EPSTS_IN);
470 writel(tmp, &ep->regs->sts);
473 tmp = readl(&ep->regs->ctl);
474 tmp |= AMD_BIT(UDC_EPCTL_F);
475 writel(tmp, &ep->regs->ctl);
478 /* reset desc pointer */
479 writel(0, &ep->regs->desptr);
482 /* Disables endpoint, is called by gadget driver */
483 static int udc_ep_disable(struct usb_ep *usbep)
485 struct udc_ep *ep = NULL;
486 unsigned long iflags;
491 ep = container_of(usbep, struct udc_ep, ep);
492 if (usbep->name == ep0_string || !ep->desc)
495 DBG(ep->dev, "Disable ep-%d\n", ep->num);
497 spin_lock_irqsave(&ep->dev->lock, iflags);
498 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
500 ep_init(ep->dev->regs, ep);
501 spin_unlock_irqrestore(&ep->dev->lock, iflags);
506 /* Allocates request packet, called by gadget driver */
507 static struct usb_request *
508 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
510 struct udc_request *req;
511 struct udc_data_dma *dma_desc;
517 ep = container_of(usbep, struct udc_ep, ep);
519 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
520 req = kzalloc(sizeof(struct udc_request), gfp);
524 req->req.dma = DMA_DONT_USE;
525 INIT_LIST_HEAD(&req->queue);
528 /* ep0 in requests are allocated from data pool here */
529 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
536 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
539 (unsigned long)req->td_phys);
540 /* prevent from using desc. - set HOST BUSY */
541 dma_desc->status = AMD_ADDBITS(dma_desc->status,
542 UDC_DMA_STP_STS_BS_HOST_BUSY,
544 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
545 req->td_data = dma_desc;
546 req->td_data_last = NULL;
553 /* Frees request packet, called by gadget driver */
555 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
558 struct udc_request *req;
560 if (!usbep || !usbreq)
563 ep = container_of(usbep, struct udc_ep, ep);
564 req = container_of(usbreq, struct udc_request, req);
565 VDBG(ep->dev, "free_req req=%p\n", req);
566 BUG_ON(!list_empty(&req->queue));
568 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
570 /* free dma chain if created */
571 if (req->chain_len > 1)
572 udc_free_dma_chain(ep->dev, req);
574 pci_pool_free(ep->dev->data_requests, req->td_data,
580 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
581 static void udc_init_bna_dummy(struct udc_request *req)
585 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
586 /* set next pointer to itself */
587 req->td_data->next = req->td_phys;
590 = AMD_ADDBITS(req->td_data->status,
591 UDC_DMA_STP_STS_BS_DMA_DONE,
594 pr_debug("bna desc = %p, sts = %08x\n",
595 req->td_data, req->td_data->status);
600 /* Allocate BNA dummy descriptor */
601 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
603 struct udc_request *req = NULL;
604 struct usb_request *_req = NULL;
606 /* alloc the dummy request */
607 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
609 req = container_of(_req, struct udc_request, req);
610 ep->bna_dummy_req = req;
611 udc_init_bna_dummy(req);
616 /* Write data to TX fifo for IN packets */
618 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
624 unsigned remaining = 0;
629 req_buf = req->buf + req->actual;
631 remaining = req->length - req->actual;
633 buf = (u32 *) req_buf;
635 bytes = ep->ep.maxpacket;
636 if (bytes > remaining)
640 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
641 writel(*(buf + i), ep->txfifo);
643 /* remaining bytes must be written by byte access */
644 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
645 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
649 /* dummy write confirm */
650 writel(0, &ep->regs->confirm);
653 /* Read dwords from RX fifo for OUT transfers */
654 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
658 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
660 for (i = 0; i < dwords; i++)
661 *(buf + i) = readl(dev->rxfifo);
665 /* Read bytes from RX fifo for OUT transfers */
666 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
671 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
674 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
675 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
677 /* remaining bytes must be read by byte access */
678 if (bytes % UDC_DWORD_BYTES) {
679 tmp = readl(dev->rxfifo);
680 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
681 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
682 tmp = tmp >> UDC_BITS_PER_BYTE;
689 /* Read data from RX fifo for OUT transfers */
691 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
696 unsigned finished = 0;
698 /* received number bytes */
699 bytes = readl(&ep->regs->sts);
700 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
702 buf_space = req->req.length - req->req.actual;
703 buf = req->req.buf + req->req.actual;
704 if (bytes > buf_space) {
705 if ((buf_space % ep->ep.maxpacket) != 0) {
707 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
708 ep->ep.name, bytes, buf_space);
709 req->req.status = -EOVERFLOW;
713 req->req.actual += bytes;
716 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
717 || ((req->req.actual == req->req.length) && !req->req.zero))
720 /* read rx fifo bytes */
721 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
722 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
727 /* create/re-init a DMA descriptor or a DMA descriptor chain */
728 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
733 VDBG(ep->dev, "prep_dma\n");
734 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
735 ep->num, req->td_data);
737 /* set buffer pointer */
738 req->td_data->bufptr = req->req.dma;
741 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
743 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
746 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
748 if (retval == -ENOMEM)
749 DBG(ep->dev, "Out of DMA memory\n");
753 if (req->req.length == ep->ep.maxpacket) {
755 req->td_data->status =
756 AMD_ADDBITS(req->td_data->status,
758 UDC_DMA_IN_STS_TXBYTES);
766 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
767 "maxpacket=%d ep%d\n",
768 use_dma_ppb, req->req.length,
769 ep->ep.maxpacket, ep->num);
771 * if bytes < max packet then tx bytes must
772 * be written in packet per buffer mode
774 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
775 || ep->num == UDC_EP0OUT_IX
776 || ep->num == UDC_EP0IN_IX) {
778 req->td_data->status =
779 AMD_ADDBITS(req->td_data->status,
781 UDC_DMA_IN_STS_TXBYTES);
782 /* reset frame num */
783 req->td_data->status =
784 AMD_ADDBITS(req->td_data->status,
786 UDC_DMA_IN_STS_FRAMENUM);
789 req->td_data->status =
790 AMD_ADDBITS(req->td_data->status,
791 UDC_DMA_STP_STS_BS_HOST_BUSY,
794 VDBG(ep->dev, "OUT set host ready\n");
796 req->td_data->status =
797 AMD_ADDBITS(req->td_data->status,
798 UDC_DMA_STP_STS_BS_HOST_READY,
802 /* clear NAK by writing CNAK */
804 tmp = readl(&ep->regs->ctl);
805 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
806 writel(tmp, &ep->regs->ctl);
808 UDC_QUEUE_CNAK(ep, ep->num);
816 /* Completes request packet ... caller MUST hold lock */
818 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
819 __releases(ep->dev->lock)
820 __acquires(ep->dev->lock)
825 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
830 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
835 /* set new status if pending */
836 if (req->req.status == -EINPROGRESS)
837 req->req.status = sts;
839 /* remove from ep queue */
840 list_del_init(&req->queue);
842 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
843 &req->req, req->req.length, ep->ep.name, sts);
845 spin_unlock(&dev->lock);
846 req->req.complete(&ep->ep, &req->req);
847 spin_lock(&dev->lock);
851 /* frees pci pool descriptors of a DMA chain */
852 static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
856 struct udc_data_dma *td;
857 struct udc_data_dma *td_last = NULL;
860 DBG(dev, "free chain req = %p\n", req);
862 /* do not free first desc., will be done by free for request */
863 td_last = req->td_data;
864 td = phys_to_virt(td_last->next);
866 for (i = 1; i < req->chain_len; i++) {
868 pci_pool_free(dev->data_requests, td,
869 (dma_addr_t) td_last->next);
871 td = phys_to_virt(td_last->next);
877 /* Iterates to the end of a DMA chain and returns last descriptor */
878 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
880 struct udc_data_dma *td;
883 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
884 td = phys_to_virt(td->next);
890 /* Iterates to the end of a DMA chain and counts bytes received */
891 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
893 struct udc_data_dma *td;
897 /* received number bytes */
898 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
900 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
901 td = phys_to_virt(td->next);
902 /* received number bytes */
904 count += AMD_GETBITS(td->status,
905 UDC_DMA_OUT_STS_RXBYTES);
913 /* Creates or re-inits a DMA chain */
914 static int udc_create_dma_chain(
916 struct udc_request *req,
917 unsigned long buf_len, gfp_t gfp_flags
920 unsigned long bytes = req->req.length;
923 struct udc_data_dma *td = NULL;
924 struct udc_data_dma *last = NULL;
925 unsigned long txbytes;
926 unsigned create_new_chain = 0;
929 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
931 dma_addr = DMA_DONT_USE;
933 /* unset L bit in first desc for OUT */
935 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
937 /* alloc only new desc's if not already available */
938 len = req->req.length / ep->ep.maxpacket;
939 if (req->req.length % ep->ep.maxpacket)
942 if (len > req->chain_len) {
943 /* shorter chain already allocated before */
944 if (req->chain_len > 1)
945 udc_free_dma_chain(ep->dev, req);
946 req->chain_len = len;
947 create_new_chain = 1;
951 /* gen. required number of descriptors and buffers */
952 for (i = buf_len; i < bytes; i += buf_len) {
953 /* create or determine next desc. */
954 if (create_new_chain) {
956 td = pci_pool_alloc(ep->dev->data_requests,
957 gfp_flags, &dma_addr);
962 } else if (i == buf_len) {
964 td = (struct udc_data_dma *) phys_to_virt(
968 td = (struct udc_data_dma *) phys_to_virt(last->next);
974 td->bufptr = req->req.dma + i; /* assign buffer */
979 if ((bytes - i) >= buf_len) {
986 /* link td and assign tx bytes */
988 if (create_new_chain)
989 req->td_data->next = dma_addr;
992 req->td_data->next = virt_to_phys(td);
997 req->td_data->status =
998 AMD_ADDBITS(req->td_data->status,
1000 UDC_DMA_IN_STS_TXBYTES);
1002 td->status = AMD_ADDBITS(td->status,
1004 UDC_DMA_IN_STS_TXBYTES);
1007 if (create_new_chain)
1008 last->next = dma_addr;
1011 last->next = virt_to_phys(td);
1014 /* write tx bytes */
1015 td->status = AMD_ADDBITS(td->status,
1017 UDC_DMA_IN_STS_TXBYTES);
1024 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1025 /* last desc. points to itself */
1026 req->td_data_last = td;
1032 /* Enabling RX DMA */
1033 static void udc_set_rde(struct udc *dev)
1037 VDBG(dev, "udc_set_rde()\n");
1038 /* stop RDE timer */
1039 if (timer_pending(&udc_timer)) {
1041 mod_timer(&udc_timer, jiffies - 1);
1044 tmp = readl(&dev->regs->ctl);
1045 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1046 writel(tmp, &dev->regs->ctl);
1049 /* Queues a request packet, called by gadget driver */
1051 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1055 unsigned long iflags;
1057 struct udc_request *req;
1061 /* check the inputs */
1062 req = container_of(usbreq, struct udc_request, req);
1064 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1065 || !list_empty(&req->queue))
1068 ep = container_of(usbep, struct udc_ep, ep);
1069 if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1072 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1075 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1078 /* map dma (usually done before) */
1080 VDBG(dev, "DMA map req %p\n", req);
1081 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1086 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1087 usbep->name, usbreq, usbreq->length,
1088 req->td_data, usbreq->buf);
1090 spin_lock_irqsave(&dev->lock, iflags);
1092 usbreq->status = -EINPROGRESS;
1095 /* on empty queue just do first transfer */
1096 if (list_empty(&ep->queue)) {
1098 if (usbreq->length == 0) {
1099 /* IN zlp's are handled by hardware */
1100 complete_req(ep, req, 0);
1101 VDBG(dev, "%s: zlp\n", ep->ep.name);
1103 * if set_config or set_intf is waiting for ack by zlp
1106 if (dev->set_cfg_not_acked) {
1107 tmp = readl(&dev->regs->ctl);
1108 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1109 writel(tmp, &dev->regs->ctl);
1110 dev->set_cfg_not_acked = 0;
1112 /* setup command is ACK'ed now by zlp */
1113 if (dev->waiting_zlp_ack_ep0in) {
1114 /* clear NAK by writing CNAK in EP0_IN */
1115 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1116 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1117 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1118 dev->ep[UDC_EP0IN_IX].naking = 0;
1119 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1121 dev->waiting_zlp_ack_ep0in = 0;
1126 retval = prep_dma(ep, req, gfp);
1129 /* write desc pointer to enable DMA */
1131 /* set HOST READY */
1132 req->td_data->status =
1133 AMD_ADDBITS(req->td_data->status,
1134 UDC_DMA_IN_STS_BS_HOST_READY,
1138 /* disabled rx dma while descriptor update */
1140 /* stop RDE timer */
1141 if (timer_pending(&udc_timer)) {
1143 mod_timer(&udc_timer, jiffies - 1);
1146 tmp = readl(&dev->regs->ctl);
1147 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1148 writel(tmp, &dev->regs->ctl);
1152 * if BNA occurred then let BNA dummy desc.
1153 * point to current desc.
1155 if (ep->bna_occurred) {
1156 VDBG(dev, "copy to BNA dummy desc.\n");
1157 memcpy(ep->bna_dummy_req->td_data,
1159 sizeof(struct udc_data_dma));
1162 /* write desc pointer */
1163 writel(req->td_phys, &ep->regs->desptr);
1165 /* clear NAK by writing CNAK */
1167 tmp = readl(&ep->regs->ctl);
1168 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1169 writel(tmp, &ep->regs->ctl);
1171 UDC_QUEUE_CNAK(ep, ep->num);
1176 tmp = readl(&dev->regs->ep_irqmsk);
1177 tmp &= AMD_UNMASK_BIT(ep->num);
1178 writel(tmp, &dev->regs->ep_irqmsk);
1180 } else if (ep->in) {
1182 tmp = readl(&dev->regs->ep_irqmsk);
1183 tmp &= AMD_UNMASK_BIT(ep->num);
1184 writel(tmp, &dev->regs->ep_irqmsk);
1187 } else if (ep->dma) {
1190 * prep_dma not used for OUT ep's, this is not possible
1191 * for PPB modes, because of chain creation reasons
1194 retval = prep_dma(ep, req, gfp);
1199 VDBG(dev, "list_add\n");
1200 /* add request to ep queue */
1203 list_add_tail(&req->queue, &ep->queue);
1205 /* open rxfifo if out data queued */
1210 if (ep->num != UDC_EP0OUT_IX)
1211 dev->data_ep_queued = 1;
1213 /* stop OUT naking */
1215 if (!use_dma && udc_rxfifo_pending) {
1216 DBG(dev, "udc_queue(): pending bytes in "
1217 "rxfifo after nyet\n");
1219 * read pending bytes afer nyet:
1222 if (udc_rxfifo_read(ep, req)) {
1224 complete_req(ep, req, 0);
1226 udc_rxfifo_pending = 0;
1233 spin_unlock_irqrestore(&dev->lock, iflags);
1237 /* Empty request queue of an endpoint; caller holds spinlock */
1238 static void empty_req_queue(struct udc_ep *ep)
1240 struct udc_request *req;
1243 while (!list_empty(&ep->queue)) {
1244 req = list_entry(ep->queue.next,
1247 complete_req(ep, req, -ESHUTDOWN);
1251 /* Dequeues a request packet, called by gadget driver */
1252 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1255 struct udc_request *req;
1257 unsigned long iflags;
1259 ep = container_of(usbep, struct udc_ep, ep);
1260 if (!usbep || !usbreq || (!ep->desc && (ep->num != 0
1261 && ep->num != UDC_EP0OUT_IX)))
1264 req = container_of(usbreq, struct udc_request, req);
1266 spin_lock_irqsave(&ep->dev->lock, iflags);
1267 halted = ep->halted;
1269 /* request in processing or next one */
1270 if (ep->queue.next == &req->queue) {
1271 if (ep->dma && req->dma_going) {
1273 ep->cancel_transfer = 1;
1277 /* stop potential receive DMA */
1278 tmp = readl(&udc->regs->ctl);
1279 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1282 * Cancel transfer later in ISR
1283 * if descriptor was touched.
1285 dma_sts = AMD_GETBITS(req->td_data->status,
1286 UDC_DMA_OUT_STS_BS);
1287 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1288 ep->cancel_transfer = 1;
1290 udc_init_bna_dummy(ep->req);
1291 writel(ep->bna_dummy_req->td_phys,
1294 writel(tmp, &udc->regs->ctl);
1298 complete_req(ep, req, -ECONNRESET);
1299 ep->halted = halted;
1301 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1305 /* Halt or clear halt of endpoint */
1307 udc_set_halt(struct usb_ep *usbep, int halt)
1311 unsigned long iflags;
1317 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1319 ep = container_of(usbep, struct udc_ep, ep);
1320 if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1322 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1325 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1326 /* halt or clear halt */
1329 ep->dev->stall_ep0in = 1;
1333 * rxfifo empty not taken into acount
1335 tmp = readl(&ep->regs->ctl);
1336 tmp |= AMD_BIT(UDC_EPCTL_S);
1337 writel(tmp, &ep->regs->ctl);
1340 /* setup poll timer */
1341 if (!timer_pending(&udc_pollstall_timer)) {
1342 udc_pollstall_timer.expires = jiffies +
1343 HZ * UDC_POLLSTALL_TIMER_USECONDS
1345 if (!stop_pollstall_timer) {
1346 DBG(ep->dev, "start polltimer\n");
1347 add_timer(&udc_pollstall_timer);
1352 /* ep is halted by set_halt() before */
1354 tmp = readl(&ep->regs->ctl);
1355 /* clear stall bit */
1356 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1357 /* clear NAK by writing CNAK */
1358 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1359 writel(tmp, &ep->regs->ctl);
1361 UDC_QUEUE_CNAK(ep, ep->num);
1364 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1368 /* gadget interface */
1369 static const struct usb_ep_ops udc_ep_ops = {
1370 .enable = udc_ep_enable,
1371 .disable = udc_ep_disable,
1373 .alloc_request = udc_alloc_request,
1374 .free_request = udc_free_request,
1377 .dequeue = udc_dequeue,
1379 .set_halt = udc_set_halt,
1380 /* fifo ops not implemented */
1383 /*-------------------------------------------------------------------------*/
1385 /* Get frame counter (not implemented) */
1386 static int udc_get_frame(struct usb_gadget *gadget)
1391 /* Remote wakeup gadget interface */
1392 static int udc_wakeup(struct usb_gadget *gadget)
1398 dev = container_of(gadget, struct udc, gadget);
1399 udc_remote_wakeup(dev);
1404 static int amd5536_start(struct usb_gadget_driver *driver,
1405 int (*bind)(struct usb_gadget *));
1406 static int amd5536_stop(struct usb_gadget_driver *driver);
1407 /* gadget operations */
1408 static const struct usb_gadget_ops udc_ops = {
1409 .wakeup = udc_wakeup,
1410 .get_frame = udc_get_frame,
1411 .start = amd5536_start,
1412 .stop = amd5536_stop,
1415 /* Setups endpoint parameters, adds endpoints to linked list */
1416 static void make_ep_lists(struct udc *dev)
1418 /* make gadget ep lists */
1419 INIT_LIST_HEAD(&dev->gadget.ep_list);
1420 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1421 &dev->gadget.ep_list);
1422 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1423 &dev->gadget.ep_list);
1424 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1425 &dev->gadget.ep_list);
1428 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1429 if (dev->gadget.speed == USB_SPEED_FULL)
1430 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1431 else if (dev->gadget.speed == USB_SPEED_HIGH)
1432 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1433 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1436 /* init registers at driver load time */
1437 static int startup_registers(struct udc *dev)
1441 /* init controller by soft reset */
1442 udc_soft_reset(dev);
1444 /* mask not needed interrupts */
1445 udc_mask_unused_interrupts(dev);
1447 /* put into initial config */
1448 udc_basic_init(dev);
1449 /* link up all endpoints */
1450 udc_setup_endpoints(dev);
1453 tmp = readl(&dev->regs->cfg);
1455 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1457 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1458 writel(tmp, &dev->regs->cfg);
1463 /* Inits UDC context */
1464 static void udc_basic_init(struct udc *dev)
1468 DBG(dev, "udc_basic_init()\n");
1470 dev->gadget.speed = USB_SPEED_UNKNOWN;
1472 /* stop RDE timer */
1473 if (timer_pending(&udc_timer)) {
1475 mod_timer(&udc_timer, jiffies - 1);
1477 /* stop poll stall timer */
1478 if (timer_pending(&udc_pollstall_timer))
1479 mod_timer(&udc_pollstall_timer, jiffies - 1);
1481 tmp = readl(&dev->regs->ctl);
1482 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1483 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1484 writel(tmp, &dev->regs->ctl);
1486 /* enable dynamic CSR programming */
1487 tmp = readl(&dev->regs->cfg);
1488 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1489 /* set self powered */
1490 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1491 /* set remote wakeupable */
1492 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1493 writel(tmp, &dev->regs->cfg);
1497 dev->data_ep_enabled = 0;
1498 dev->data_ep_queued = 0;
1501 /* Sets initial endpoint parameters */
1502 static void udc_setup_endpoints(struct udc *dev)
1508 DBG(dev, "udc_setup_endpoints()\n");
1510 /* read enum speed */
1511 tmp = readl(&dev->regs->sts);
1512 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1513 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1514 dev->gadget.speed = USB_SPEED_HIGH;
1515 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1516 dev->gadget.speed = USB_SPEED_FULL;
1518 /* set basic ep parameters */
1519 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1522 ep->ep.name = ep_string[tmp];
1524 /* txfifo size is calculated at enable time */
1525 ep->txfifo = dev->txfifo;
1528 if (tmp < UDC_EPIN_NUM) {
1529 ep->fifo_depth = UDC_TXFIFO_SIZE;
1532 ep->fifo_depth = UDC_RXFIFO_SIZE;
1536 ep->regs = &dev->ep_regs[tmp];
1538 * ep will be reset only if ep was not enabled before to avoid
1539 * disabling ep interrupts when ENUM interrupt occurs but ep is
1540 * not enabled by gadget driver
1543 ep_init(dev->regs, ep);
1547 * ep->dma is not really used, just to indicate that
1548 * DMA is active: remove this
1549 * dma regs = dev control regs
1551 ep->dma = &dev->regs->ctl;
1553 /* nak OUT endpoints until enable - not for ep0 */
1554 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1555 && tmp > UDC_EPIN_NUM) {
1557 reg = readl(&dev->ep[tmp].regs->ctl);
1558 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1559 writel(reg, &dev->ep[tmp].regs->ctl);
1560 dev->ep[tmp].naking = 1;
1565 /* EP0 max packet */
1566 if (dev->gadget.speed == USB_SPEED_FULL) {
1567 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;
1568 dev->ep[UDC_EP0OUT_IX].ep.maxpacket =
1569 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1570 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1571 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
1572 dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
1576 * with suspend bug workaround, ep0 params for gadget driver
1577 * are set at gadget driver bind() call
1579 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1580 dev->ep[UDC_EP0IN_IX].halted = 0;
1581 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1583 /* init cfg/alt/int */
1584 dev->cur_config = 0;
1589 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1590 static void usb_connect(struct udc *dev)
1593 dev_info(&dev->pdev->dev, "USB Connect\n");
1597 /* put into initial config */
1598 udc_basic_init(dev);
1600 /* enable device setup interrupts */
1601 udc_enable_dev_setup_interrupts(dev);
1605 * Calls gadget with disconnect event and resets the UDC and makes
1606 * initial bringup to be ready for ep0 events
1608 static void usb_disconnect(struct udc *dev)
1611 dev_info(&dev->pdev->dev, "USB Disconnect\n");
1615 /* mask interrupts */
1616 udc_mask_unused_interrupts(dev);
1618 /* REVISIT there doesn't seem to be a point to having this
1619 * talk to a tasklet ... do it directly, we already hold
1620 * the spinlock needed to process the disconnect.
1623 tasklet_schedule(&disconnect_tasklet);
1626 /* Tasklet for disconnect to be outside of interrupt context */
1627 static void udc_tasklet_disconnect(unsigned long par)
1629 struct udc *dev = (struct udc *)(*((struct udc **) par));
1632 DBG(dev, "Tasklet disconnect\n");
1633 spin_lock_irq(&dev->lock);
1636 spin_unlock(&dev->lock);
1637 dev->driver->disconnect(&dev->gadget);
1638 spin_lock(&dev->lock);
1641 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1642 empty_req_queue(&dev->ep[tmp]);
1648 &dev->ep[UDC_EP0IN_IX]);
1651 if (!soft_reset_occured) {
1652 /* init controller by soft reset */
1653 udc_soft_reset(dev);
1654 soft_reset_occured++;
1657 /* re-enable dev interrupts */
1658 udc_enable_dev_setup_interrupts(dev);
1659 /* back to full speed ? */
1660 if (use_fullspeed) {
1661 tmp = readl(&dev->regs->cfg);
1662 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1663 writel(tmp, &dev->regs->cfg);
1666 spin_unlock_irq(&dev->lock);
1669 /* Reset the UDC core */
1670 static void udc_soft_reset(struct udc *dev)
1672 unsigned long flags;
1674 DBG(dev, "Soft reset\n");
1676 * reset possible waiting interrupts, because int.
1677 * status is lost after soft reset,
1678 * ep int. status reset
1680 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1681 /* device int. status reset */
1682 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1684 spin_lock_irqsave(&udc_irq_spinlock, flags);
1685 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1686 readl(&dev->regs->cfg);
1687 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1691 /* RDE timer callback to set RDE bit */
1692 static void udc_timer_function(unsigned long v)
1696 spin_lock_irq(&udc_irq_spinlock);
1700 * open the fifo if fifo was filled on last timer call
1704 /* set RDE to receive setup data */
1705 tmp = readl(&udc->regs->ctl);
1706 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1707 writel(tmp, &udc->regs->ctl);
1709 } else if (readl(&udc->regs->sts)
1710 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1712 * if fifo empty setup polling, do not just
1715 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1717 add_timer(&udc_timer);
1720 * fifo contains data now, setup timer for opening
1721 * the fifo when timer expires to be able to receive
1722 * setup packets, when data packets gets queued by
1723 * gadget layer then timer will forced to expire with
1724 * set_rde=0 (RDE is set in udc_queue())
1727 /* debug: lhadmot_timer_start = 221070 */
1728 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1730 add_timer(&udc_timer);
1734 set_rde = -1; /* RDE was set by udc_queue() */
1735 spin_unlock_irq(&udc_irq_spinlock);
1741 /* Handle halt state, used in stall poll timer */
1742 static void udc_handle_halt_state(struct udc_ep *ep)
1745 /* set stall as long not halted */
1746 if (ep->halted == 1) {
1747 tmp = readl(&ep->regs->ctl);
1748 /* STALL cleared ? */
1749 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1751 * FIXME: MSC spec requires that stall remains
1752 * even on receivng of CLEAR_FEATURE HALT. So
1753 * we would set STALL again here to be compliant.
1754 * But with current mass storage drivers this does
1755 * not work (would produce endless host retries).
1756 * So we clear halt on CLEAR_FEATURE.
1758 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1759 tmp |= AMD_BIT(UDC_EPCTL_S);
1760 writel(tmp, &ep->regs->ctl);*/
1762 /* clear NAK by writing CNAK */
1763 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1764 writel(tmp, &ep->regs->ctl);
1766 UDC_QUEUE_CNAK(ep, ep->num);
1771 /* Stall timer callback to poll S bit and set it again after */
1772 static void udc_pollstall_timer_function(unsigned long v)
1777 spin_lock_irq(&udc_stall_spinlock);
1779 * only one IN and OUT endpoints are handled
1782 ep = &udc->ep[UDC_EPIN_IX];
1783 udc_handle_halt_state(ep);
1786 /* OUT poll stall */
1787 ep = &udc->ep[UDC_EPOUT_IX];
1788 udc_handle_halt_state(ep);
1792 /* setup timer again when still halted */
1793 if (!stop_pollstall_timer && halted) {
1794 udc_pollstall_timer.expires = jiffies +
1795 HZ * UDC_POLLSTALL_TIMER_USECONDS
1797 add_timer(&udc_pollstall_timer);
1799 spin_unlock_irq(&udc_stall_spinlock);
1801 if (stop_pollstall_timer)
1802 complete(&on_pollstall_exit);
1805 /* Inits endpoint 0 so that SETUP packets are processed */
1806 static void activate_control_endpoints(struct udc *dev)
1810 DBG(dev, "activate_control_endpoints\n");
1813 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1814 tmp |= AMD_BIT(UDC_EPCTL_F);
1815 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1817 /* set ep0 directions */
1818 dev->ep[UDC_EP0IN_IX].in = 1;
1819 dev->ep[UDC_EP0OUT_IX].in = 0;
1821 /* set buffer size (tx fifo entries) of EP0_IN */
1822 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1823 if (dev->gadget.speed == USB_SPEED_FULL)
1824 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1825 UDC_EPIN_BUFF_SIZE);
1826 else if (dev->gadget.speed == USB_SPEED_HIGH)
1827 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1828 UDC_EPIN_BUFF_SIZE);
1829 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1831 /* set max packet size of EP0_IN */
1832 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1833 if (dev->gadget.speed == USB_SPEED_FULL)
1834 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1835 UDC_EP_MAX_PKT_SIZE);
1836 else if (dev->gadget.speed == USB_SPEED_HIGH)
1837 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1838 UDC_EP_MAX_PKT_SIZE);
1839 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1841 /* set max packet size of EP0_OUT */
1842 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1843 if (dev->gadget.speed == USB_SPEED_FULL)
1844 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1845 UDC_EP_MAX_PKT_SIZE);
1846 else if (dev->gadget.speed == USB_SPEED_HIGH)
1847 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1848 UDC_EP_MAX_PKT_SIZE);
1849 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1851 /* set max packet size of EP0 in UDC CSR */
1852 tmp = readl(&dev->csr->ne[0]);
1853 if (dev->gadget.speed == USB_SPEED_FULL)
1854 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1855 UDC_CSR_NE_MAX_PKT);
1856 else if (dev->gadget.speed == USB_SPEED_HIGH)
1857 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1858 UDC_CSR_NE_MAX_PKT);
1859 writel(tmp, &dev->csr->ne[0]);
1862 dev->ep[UDC_EP0OUT_IX].td->status |=
1863 AMD_BIT(UDC_DMA_OUT_STS_L);
1864 /* write dma desc address */
1865 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1866 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1867 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1868 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1869 /* stop RDE timer */
1870 if (timer_pending(&udc_timer)) {
1872 mod_timer(&udc_timer, jiffies - 1);
1874 /* stop pollstall timer */
1875 if (timer_pending(&udc_pollstall_timer))
1876 mod_timer(&udc_pollstall_timer, jiffies - 1);
1878 tmp = readl(&dev->regs->ctl);
1879 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1880 | AMD_BIT(UDC_DEVCTL_RDE)
1881 | AMD_BIT(UDC_DEVCTL_TDE);
1882 if (use_dma_bufferfill_mode)
1883 tmp |= AMD_BIT(UDC_DEVCTL_BF);
1884 else if (use_dma_ppb_du)
1885 tmp |= AMD_BIT(UDC_DEVCTL_DU);
1886 writel(tmp, &dev->regs->ctl);
1889 /* clear NAK by writing CNAK for EP0IN */
1890 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1891 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1892 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1893 dev->ep[UDC_EP0IN_IX].naking = 0;
1894 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1896 /* clear NAK by writing CNAK for EP0OUT */
1897 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1898 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1899 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1900 dev->ep[UDC_EP0OUT_IX].naking = 0;
1901 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1904 /* Make endpoint 0 ready for control traffic */
1905 static int setup_ep0(struct udc *dev)
1907 activate_control_endpoints(dev);
1908 /* enable ep0 interrupts */
1909 udc_enable_ep0_interrupts(dev);
1910 /* enable device setup interrupts */
1911 udc_enable_dev_setup_interrupts(dev);
1916 /* Called by gadget driver to register itself */
1917 static int amd5536_start(struct usb_gadget_driver *driver,
1918 int (*bind)(struct usb_gadget *))
1920 struct udc *dev = udc;
1924 if (!driver || !bind || !driver->setup
1925 || driver->max_speed < USB_SPEED_HIGH)
1932 driver->driver.bus = NULL;
1933 dev->driver = driver;
1934 dev->gadget.dev.driver = &driver->driver;
1936 retval = bind(&dev->gadget);
1938 /* Some gadget drivers use both ep0 directions.
1939 * NOTE: to gadget driver, ep0 is just one endpoint...
1941 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1942 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1945 DBG(dev, "binding to %s returning %d\n",
1946 driver->driver.name, retval);
1948 dev->gadget.dev.driver = NULL;
1952 /* get ready for ep0 traffic */
1956 tmp = readl(&dev->regs->ctl);
1957 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1958 writel(tmp, &dev->regs->ctl);
1965 /* shutdown requests and disconnect from gadget */
1967 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1968 __releases(dev->lock)
1969 __acquires(dev->lock)
1973 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
1974 spin_unlock(&dev->lock);
1975 driver->disconnect(&dev->gadget);
1976 spin_lock(&dev->lock);
1979 /* empty queues and init hardware */
1980 udc_basic_init(dev);
1981 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1982 empty_req_queue(&dev->ep[tmp]);
1984 udc_setup_endpoints(dev);
1987 /* Called by gadget driver to unregister itself */
1988 static int amd5536_stop(struct usb_gadget_driver *driver)
1990 struct udc *dev = udc;
1991 unsigned long flags;
1996 if (!driver || driver != dev->driver || !driver->unbind)
1999 spin_lock_irqsave(&dev->lock, flags);
2000 udc_mask_unused_interrupts(dev);
2001 shutdown(dev, driver);
2002 spin_unlock_irqrestore(&dev->lock, flags);
2004 driver->unbind(&dev->gadget);
2005 dev->gadget.dev.driver = NULL;
2009 tmp = readl(&dev->regs->ctl);
2010 tmp |= AMD_BIT(UDC_DEVCTL_SD);
2011 writel(tmp, &dev->regs->ctl);
2014 DBG(dev, "%s: unregistered\n", driver->driver.name);
2019 /* Clear pending NAK bits */
2020 static void udc_process_cnak_queue(struct udc *dev)
2026 DBG(dev, "CNAK pending queue processing\n");
2027 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2028 if (cnak_pending & (1 << tmp)) {
2029 DBG(dev, "CNAK pending for ep%d\n", tmp);
2030 /* clear NAK by writing CNAK */
2031 reg = readl(&dev->ep[tmp].regs->ctl);
2032 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2033 writel(reg, &dev->ep[tmp].regs->ctl);
2034 dev->ep[tmp].naking = 0;
2035 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2038 /* ... and ep0out */
2039 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2040 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2041 /* clear NAK by writing CNAK */
2042 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2043 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2044 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2045 dev->ep[UDC_EP0OUT_IX].naking = 0;
2046 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2047 dev->ep[UDC_EP0OUT_IX].num);
2051 /* Enabling RX DMA after setup packet */
2052 static void udc_ep0_set_rde(struct udc *dev)
2056 * only enable RXDMA when no data endpoint enabled
2059 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2063 * setup timer for enabling RDE (to not enable
2064 * RXFIFO DMA for data endpoints to early)
2066 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2068 jiffies + HZ/UDC_RDE_TIMER_DIV;
2071 add_timer(&udc_timer);
2078 /* Interrupt handler for data OUT traffic */
2079 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2081 irqreturn_t ret_val = IRQ_NONE;
2084 struct udc_request *req;
2086 struct udc_data_dma *td = NULL;
2089 VDBG(dev, "ep%d irq\n", ep_ix);
2090 ep = &dev->ep[ep_ix];
2092 tmp = readl(&ep->regs->sts);
2095 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2096 DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
2097 ep->num, readl(&ep->regs->desptr));
2099 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2100 if (!ep->cancel_transfer)
2101 ep->bna_occurred = 1;
2103 ep->cancel_transfer = 0;
2104 ret_val = IRQ_HANDLED;
2109 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2110 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
2113 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2114 ret_val = IRQ_HANDLED;
2118 if (!list_empty(&ep->queue)) {
2121 req = list_entry(ep->queue.next,
2122 struct udc_request, queue);
2125 udc_rxfifo_pending = 1;
2127 VDBG(dev, "req = %p\n", req);
2132 if (req && udc_rxfifo_read(ep, req)) {
2133 ret_val = IRQ_HANDLED;
2136 complete_req(ep, req, 0);
2138 if (!list_empty(&ep->queue) && !ep->halted) {
2139 req = list_entry(ep->queue.next,
2140 struct udc_request, queue);
2146 } else if (!ep->cancel_transfer && req != NULL) {
2147 ret_val = IRQ_HANDLED;
2149 /* check for DMA done */
2151 dma_done = AMD_GETBITS(req->td_data->status,
2152 UDC_DMA_OUT_STS_BS);
2153 /* packet per buffer mode - rx bytes */
2156 * if BNA occurred then recover desc. from
2159 if (ep->bna_occurred) {
2160 VDBG(dev, "Recover desc. from BNA dummy\n");
2161 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2162 sizeof(struct udc_data_dma));
2163 ep->bna_occurred = 0;
2164 udc_init_bna_dummy(ep->req);
2166 td = udc_get_last_dma_desc(req);
2167 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2169 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2170 /* buffer fill mode - rx bytes */
2172 /* received number bytes */
2173 count = AMD_GETBITS(req->td_data->status,
2174 UDC_DMA_OUT_STS_RXBYTES);
2175 VDBG(dev, "rx bytes=%u\n", count);
2176 /* packet per buffer mode - rx bytes */
2178 VDBG(dev, "req->td_data=%p\n", req->td_data);
2179 VDBG(dev, "last desc = %p\n", td);
2180 /* received number bytes */
2181 if (use_dma_ppb_du) {
2182 /* every desc. counts bytes */
2183 count = udc_get_ppbdu_rxbytes(req);
2185 /* last desc. counts bytes */
2186 count = AMD_GETBITS(td->status,
2187 UDC_DMA_OUT_STS_RXBYTES);
2188 if (!count && req->req.length
2189 == UDC_DMA_MAXPACKET) {
2191 * on 64k packets the RXBYTES
2194 count = UDC_DMA_MAXPACKET;
2197 VDBG(dev, "last desc rx bytes=%u\n", count);
2200 tmp = req->req.length - req->req.actual;
2202 if ((tmp % ep->ep.maxpacket) != 0) {
2203 DBG(dev, "%s: rx %db, space=%db\n",
2204 ep->ep.name, count, tmp);
2205 req->req.status = -EOVERFLOW;
2209 req->req.actual += count;
2211 /* complete request */
2212 complete_req(ep, req, 0);
2215 if (!list_empty(&ep->queue) && !ep->halted) {
2216 req = list_entry(ep->queue.next,
2220 * DMA may be already started by udc_queue()
2221 * called by gadget drivers completion
2222 * routine. This happens when queue
2223 * holds one request only.
2225 if (req->dma_going == 0) {
2227 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2229 /* write desc pointer */
2230 writel(req->td_phys,
2238 * implant BNA dummy descriptor to allow
2239 * RXFIFO opening by RDE
2241 if (ep->bna_dummy_req) {
2242 /* write desc pointer */
2243 writel(ep->bna_dummy_req->td_phys,
2245 ep->bna_occurred = 0;
2249 * schedule timer for setting RDE if queue
2250 * remains empty to allow ep0 packets pass
2254 && !timer_pending(&udc_timer)) {
2257 + HZ*UDC_RDE_TIMER_SECONDS;
2260 add_timer(&udc_timer);
2262 if (ep->num != UDC_EP0OUT_IX)
2263 dev->data_ep_queued = 0;
2268 * RX DMA must be reenabled for each desc in PPBDU mode
2269 * and must be enabled for PPBNDU mode in case of BNA
2274 } else if (ep->cancel_transfer) {
2275 ret_val = IRQ_HANDLED;
2276 ep->cancel_transfer = 0;
2279 /* check pending CNAKS */
2281 /* CNAk processing when rxfifo empty only */
2282 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2283 udc_process_cnak_queue(dev);
2286 /* clear OUT bits in ep status */
2287 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2292 /* Interrupt handler for data IN traffic */
2293 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2295 irqreturn_t ret_val = IRQ_NONE;
2299 struct udc_request *req;
2300 struct udc_data_dma *td;
2304 ep = &dev->ep[ep_ix];
2306 epsts = readl(&ep->regs->sts);
2309 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2310 dev_err(&dev->pdev->dev,
2311 "BNA ep%din occurred - DESPTR = %08lx\n",
2313 (unsigned long) readl(&ep->regs->desptr));
2316 writel(epsts, &ep->regs->sts);
2317 ret_val = IRQ_HANDLED;
2322 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2323 dev_err(&dev->pdev->dev,
2324 "HE ep%dn occurred - DESPTR = %08lx\n",
2325 ep->num, (unsigned long) readl(&ep->regs->desptr));
2328 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2329 ret_val = IRQ_HANDLED;
2333 /* DMA completion */
2334 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2335 VDBG(dev, "TDC set- completion\n");
2336 ret_val = IRQ_HANDLED;
2337 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2338 req = list_entry(ep->queue.next,
2339 struct udc_request, queue);
2341 * length bytes transferred
2342 * check dma done of last desc. in PPBDU mode
2344 if (use_dma_ppb_du) {
2345 td = udc_get_last_dma_desc(req);
2348 AMD_GETBITS(td->status,
2350 /* don't care DMA done */
2351 req->req.actual = req->req.length;
2354 /* assume all bytes transferred */
2355 req->req.actual = req->req.length;
2358 if (req->req.actual == req->req.length) {
2360 complete_req(ep, req, 0);
2362 /* further request available ? */
2363 if (list_empty(&ep->queue)) {
2364 /* disable interrupt */
2365 tmp = readl(&dev->regs->ep_irqmsk);
2366 tmp |= AMD_BIT(ep->num);
2367 writel(tmp, &dev->regs->ep_irqmsk);
2371 ep->cancel_transfer = 0;
2375 * status reg has IN bit set and TDC not set (if TDC was handled,
2376 * IN must not be handled (UDC defect) ?
2378 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2379 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2380 ret_val = IRQ_HANDLED;
2381 if (!list_empty(&ep->queue)) {
2383 req = list_entry(ep->queue.next,
2384 struct udc_request, queue);
2388 udc_txfifo_write(ep, &req->req);
2389 len = req->req.length - req->req.actual;
2390 if (len > ep->ep.maxpacket)
2391 len = ep->ep.maxpacket;
2392 req->req.actual += len;
2393 if (req->req.actual == req->req.length
2394 || (len != ep->ep.maxpacket)) {
2396 complete_req(ep, req, 0);
2399 } else if (req && !req->dma_going) {
2400 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2407 * unset L bit of first desc.
2410 if (use_dma_ppb && req->req.length >
2412 req->td_data->status &=
2417 /* write desc pointer */
2418 writel(req->td_phys, &ep->regs->desptr);
2420 /* set HOST READY */
2421 req->td_data->status =
2423 req->td_data->status,
2424 UDC_DMA_IN_STS_BS_HOST_READY,
2427 /* set poll demand bit */
2428 tmp = readl(&ep->regs->ctl);
2429 tmp |= AMD_BIT(UDC_EPCTL_P);
2430 writel(tmp, &ep->regs->ctl);
2434 } else if (!use_dma && ep->in) {
2435 /* disable interrupt */
2437 &dev->regs->ep_irqmsk);
2438 tmp |= AMD_BIT(ep->num);
2440 &dev->regs->ep_irqmsk);
2443 /* clear status bits */
2444 writel(epsts, &ep->regs->sts);
2451 /* Interrupt handler for Control OUT traffic */
2452 static irqreturn_t udc_control_out_isr(struct udc *dev)
2453 __releases(dev->lock)
2454 __acquires(dev->lock)
2456 irqreturn_t ret_val = IRQ_NONE;
2458 int setup_supported;
2462 struct udc_ep *ep_tmp;
2464 ep = &dev->ep[UDC_EP0OUT_IX];
2467 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2469 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2470 /* check BNA and clear if set */
2471 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2472 VDBG(dev, "ep0: BNA set\n");
2473 writel(AMD_BIT(UDC_EPSTS_BNA),
2474 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2475 ep->bna_occurred = 1;
2476 ret_val = IRQ_HANDLED;
2480 /* type of data: SETUP or DATA 0 bytes */
2481 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2482 VDBG(dev, "data_typ = %x\n", tmp);
2485 if (tmp == UDC_EPSTS_OUT_SETUP) {
2486 ret_val = IRQ_HANDLED;
2488 ep->dev->stall_ep0in = 0;
2489 dev->waiting_zlp_ack_ep0in = 0;
2491 /* set NAK for EP0_IN */
2492 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2493 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2494 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2495 dev->ep[UDC_EP0IN_IX].naking = 1;
2496 /* get setup data */
2499 /* clear OUT bits in ep status */
2500 writel(UDC_EPSTS_OUT_CLEAR,
2501 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2503 setup_data.data[0] =
2504 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2505 setup_data.data[1] =
2506 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2507 /* set HOST READY */
2508 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2509 UDC_DMA_STP_STS_BS_HOST_READY;
2512 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2515 /* determine direction of control data */
2516 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2517 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2519 udc_ep0_set_rde(dev);
2522 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2524 * implant BNA dummy descriptor to allow RXFIFO opening
2527 if (ep->bna_dummy_req) {
2528 /* write desc pointer */
2529 writel(ep->bna_dummy_req->td_phys,
2530 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2531 ep->bna_occurred = 0;
2535 dev->ep[UDC_EP0OUT_IX].naking = 1;
2537 * setup timer for enabling RDE (to not enable
2538 * RXFIFO DMA for data to early)
2541 if (!timer_pending(&udc_timer)) {
2542 udc_timer.expires = jiffies +
2543 HZ/UDC_RDE_TIMER_DIV;
2545 add_timer(&udc_timer);
2550 * mass storage reset must be processed here because
2551 * next packet may be a CLEAR_FEATURE HALT which would not
2552 * clear the stall bit when no STALL handshake was received
2553 * before (autostall can cause this)
2555 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2556 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2557 DBG(dev, "MSC Reset\n");
2560 * only one IN and OUT endpoints are handled
2562 ep_tmp = &udc->ep[UDC_EPIN_IX];
2563 udc_set_halt(&ep_tmp->ep, 0);
2564 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2565 udc_set_halt(&ep_tmp->ep, 0);
2568 /* call gadget with setup data received */
2569 spin_unlock(&dev->lock);
2570 setup_supported = dev->driver->setup(&dev->gadget,
2571 &setup_data.request);
2572 spin_lock(&dev->lock);
2574 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2575 /* ep0 in returns data (not zlp) on IN phase */
2576 if (setup_supported >= 0 && setup_supported <
2577 UDC_EP0IN_MAXPACKET) {
2578 /* clear NAK by writing CNAK in EP0_IN */
2579 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2580 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2581 dev->ep[UDC_EP0IN_IX].naking = 0;
2582 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2584 /* if unsupported request then stall */
2585 } else if (setup_supported < 0) {
2586 tmp |= AMD_BIT(UDC_EPCTL_S);
2587 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2589 dev->waiting_zlp_ack_ep0in = 1;
2592 /* clear NAK by writing CNAK in EP0_OUT */
2594 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2595 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2596 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2597 dev->ep[UDC_EP0OUT_IX].naking = 0;
2598 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2602 /* clear OUT bits in ep status */
2603 writel(UDC_EPSTS_OUT_CLEAR,
2604 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2607 /* data packet 0 bytes */
2608 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2609 /* clear OUT bits in ep status */
2610 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2612 /* get setup data: only 0 packet */
2614 /* no req if 0 packet, just reactivate */
2615 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2618 /* set HOST READY */
2619 dev->ep[UDC_EP0OUT_IX].td->status =
2621 dev->ep[UDC_EP0OUT_IX].td->status,
2622 UDC_DMA_OUT_STS_BS_HOST_READY,
2623 UDC_DMA_OUT_STS_BS);
2625 udc_ep0_set_rde(dev);
2626 ret_val = IRQ_HANDLED;
2630 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2631 /* re-program desc. pointer for possible ZLPs */
2632 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2633 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2635 udc_ep0_set_rde(dev);
2639 /* received number bytes */
2640 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2641 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2642 /* out data for fifo mode not working */
2645 /* 0 packet or real data ? */
2647 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2649 /* dummy read confirm */
2650 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2651 ret_val = IRQ_HANDLED;
2656 /* check pending CNAKS */
2658 /* CNAk processing when rxfifo empty only */
2659 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2660 udc_process_cnak_queue(dev);
2667 /* Interrupt handler for Control IN traffic */
2668 static irqreturn_t udc_control_in_isr(struct udc *dev)
2670 irqreturn_t ret_val = IRQ_NONE;
2673 struct udc_request *req;
2676 ep = &dev->ep[UDC_EP0IN_IX];
2679 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2681 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2682 /* DMA completion */
2683 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2684 VDBG(dev, "isr: TDC clear\n");
2685 ret_val = IRQ_HANDLED;
2688 writel(AMD_BIT(UDC_EPSTS_TDC),
2689 &dev->ep[UDC_EP0IN_IX].regs->sts);
2691 /* status reg has IN bit set ? */
2692 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2693 ret_val = IRQ_HANDLED;
2697 writel(AMD_BIT(UDC_EPSTS_IN),
2698 &dev->ep[UDC_EP0IN_IX].regs->sts);
2700 if (dev->stall_ep0in) {
2701 DBG(dev, "stall ep0in\n");
2703 tmp = readl(&ep->regs->ctl);
2704 tmp |= AMD_BIT(UDC_EPCTL_S);
2705 writel(tmp, &ep->regs->ctl);
2707 if (!list_empty(&ep->queue)) {
2709 req = list_entry(ep->queue.next,
2710 struct udc_request, queue);
2713 /* write desc pointer */
2714 writel(req->td_phys, &ep->regs->desptr);
2715 /* set HOST READY */
2716 req->td_data->status =
2718 req->td_data->status,
2719 UDC_DMA_STP_STS_BS_HOST_READY,
2720 UDC_DMA_STP_STS_BS);
2722 /* set poll demand bit */
2724 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2725 tmp |= AMD_BIT(UDC_EPCTL_P);
2727 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2729 /* all bytes will be transferred */
2730 req->req.actual = req->req.length;
2733 complete_req(ep, req, 0);
2737 udc_txfifo_write(ep, &req->req);
2739 /* lengh bytes transferred */
2740 len = req->req.length - req->req.actual;
2741 if (len > ep->ep.maxpacket)
2742 len = ep->ep.maxpacket;
2744 req->req.actual += len;
2745 if (req->req.actual == req->req.length
2746 || (len != ep->ep.maxpacket)) {
2748 complete_req(ep, req, 0);
2755 dev->stall_ep0in = 0;
2758 writel(AMD_BIT(UDC_EPSTS_IN),
2759 &dev->ep[UDC_EP0IN_IX].regs->sts);
2767 /* Interrupt handler for global device events */
2768 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2769 __releases(dev->lock)
2770 __acquires(dev->lock)
2772 irqreturn_t ret_val = IRQ_NONE;
2779 /* SET_CONFIG irq ? */
2780 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2781 ret_val = IRQ_HANDLED;
2783 /* read config value */
2784 tmp = readl(&dev->regs->sts);
2785 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2786 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2787 dev->cur_config = cfg;
2788 dev->set_cfg_not_acked = 1;
2790 /* make usb request for gadget driver */
2791 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2792 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2793 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2795 /* programm the NE registers */
2796 for (i = 0; i < UDC_EP_NUM; i++) {
2800 /* ep ix in UDC CSR register space */
2801 udc_csr_epix = ep->num;
2806 /* ep ix in UDC CSR register space */
2807 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2810 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2812 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2815 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2817 /* clear stall bits */
2819 tmp = readl(&ep->regs->ctl);
2820 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2821 writel(tmp, &ep->regs->ctl);
2823 /* call gadget zero with setup data received */
2824 spin_unlock(&dev->lock);
2825 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2826 spin_lock(&dev->lock);
2828 } /* SET_INTERFACE ? */
2829 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2830 ret_val = IRQ_HANDLED;
2832 dev->set_cfg_not_acked = 1;
2833 /* read interface and alt setting values */
2834 tmp = readl(&dev->regs->sts);
2835 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2836 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2838 /* make usb request for gadget driver */
2839 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2840 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2841 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2842 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2843 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2845 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2846 dev->cur_alt, dev->cur_intf);
2848 /* programm the NE registers */
2849 for (i = 0; i < UDC_EP_NUM; i++) {
2853 /* ep ix in UDC CSR register space */
2854 udc_csr_epix = ep->num;
2859 /* ep ix in UDC CSR register space */
2860 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2865 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2867 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2869 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2871 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2874 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2876 /* clear stall bits */
2878 tmp = readl(&ep->regs->ctl);
2879 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2880 writel(tmp, &ep->regs->ctl);
2883 /* call gadget zero with setup data received */
2884 spin_unlock(&dev->lock);
2885 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2886 spin_lock(&dev->lock);
2889 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2890 DBG(dev, "USB Reset interrupt\n");
2891 ret_val = IRQ_HANDLED;
2893 /* allow soft reset when suspend occurs */
2894 soft_reset_occured = 0;
2896 dev->waiting_zlp_ack_ep0in = 0;
2897 dev->set_cfg_not_acked = 0;
2899 /* mask not needed interrupts */
2900 udc_mask_unused_interrupts(dev);
2902 /* call gadget to resume and reset configs etc. */
2903 spin_unlock(&dev->lock);
2904 if (dev->sys_suspended && dev->driver->resume) {
2905 dev->driver->resume(&dev->gadget);
2906 dev->sys_suspended = 0;
2908 dev->driver->disconnect(&dev->gadget);
2909 spin_lock(&dev->lock);
2911 /* disable ep0 to empty req queue */
2912 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2913 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2915 /* soft reset when rxfifo not empty */
2916 tmp = readl(&dev->regs->sts);
2917 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2918 && !soft_reset_after_usbreset_occured) {
2919 udc_soft_reset(dev);
2920 soft_reset_after_usbreset_occured++;
2924 * DMA reset to kill potential old DMA hw hang,
2925 * POLL bit is already reset by ep_init() through
2928 DBG(dev, "DMA machine reset\n");
2929 tmp = readl(&dev->regs->cfg);
2930 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2931 writel(tmp, &dev->regs->cfg);
2933 /* put into initial config */
2934 udc_basic_init(dev);
2936 /* enable device setup interrupts */
2937 udc_enable_dev_setup_interrupts(dev);
2939 /* enable suspend interrupt */
2940 tmp = readl(&dev->regs->irqmsk);
2941 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2942 writel(tmp, &dev->regs->irqmsk);
2945 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2946 DBG(dev, "USB Suspend interrupt\n");
2947 ret_val = IRQ_HANDLED;
2948 if (dev->driver->suspend) {
2949 spin_unlock(&dev->lock);
2950 dev->sys_suspended = 1;
2951 dev->driver->suspend(&dev->gadget);
2952 spin_lock(&dev->lock);
2955 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2956 DBG(dev, "ENUM interrupt\n");
2957 ret_val = IRQ_HANDLED;
2958 soft_reset_after_usbreset_occured = 0;
2960 /* disable ep0 to empty req queue */
2961 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2962 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2964 /* link up all endpoints */
2965 udc_setup_endpoints(dev);
2966 dev_info(&dev->pdev->dev, "Connect: %s\n",
2967 usb_speed_string(dev->gadget.speed));
2970 activate_control_endpoints(dev);
2972 /* enable ep0 interrupts */
2973 udc_enable_ep0_interrupts(dev);
2975 /* session valid change interrupt */
2976 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2977 DBG(dev, "USB SVC interrupt\n");
2978 ret_val = IRQ_HANDLED;
2980 /* check that session is not valid to detect disconnect */
2981 tmp = readl(&dev->regs->sts);
2982 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2983 /* disable suspend interrupt */
2984 tmp = readl(&dev->regs->irqmsk);
2985 tmp |= AMD_BIT(UDC_DEVINT_US);
2986 writel(tmp, &dev->regs->irqmsk);
2987 DBG(dev, "USB Disconnect (session valid low)\n");
2988 /* cleanup on disconnect */
2989 usb_disconnect(udc);
2997 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2998 static irqreturn_t udc_irq(int irq, void *pdev)
3000 struct udc *dev = pdev;
3004 irqreturn_t ret_val = IRQ_NONE;
3006 spin_lock(&dev->lock);
3008 /* check for ep irq */
3009 reg = readl(&dev->regs->ep_irqsts);
3011 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3012 ret_val |= udc_control_out_isr(dev);
3013 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3014 ret_val |= udc_control_in_isr(dev);
3020 for (i = 1; i < UDC_EP_NUM; i++) {
3022 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3025 /* clear irq status */
3026 writel(ep_irq, &dev->regs->ep_irqsts);
3028 /* irq for out ep ? */
3029 if (i > UDC_EPIN_NUM)
3030 ret_val |= udc_data_out_isr(dev, i);
3032 ret_val |= udc_data_in_isr(dev, i);
3038 /* check for dev irq */
3039 reg = readl(&dev->regs->irqsts);
3042 writel(reg, &dev->regs->irqsts);
3043 ret_val |= udc_dev_isr(dev, reg);
3047 spin_unlock(&dev->lock);
3051 /* Tears down device */
3052 static void gadget_release(struct device *pdev)
3054 struct amd5536udc *dev = dev_get_drvdata(pdev);
3058 /* Cleanup on device remove */
3059 static void udc_remove(struct udc *dev)
3063 if (timer_pending(&udc_timer))
3064 wait_for_completion(&on_exit);
3066 del_timer_sync(&udc_timer);
3067 /* remove pollstall timer */
3068 stop_pollstall_timer++;
3069 if (timer_pending(&udc_pollstall_timer))
3070 wait_for_completion(&on_pollstall_exit);
3071 if (udc_pollstall_timer.data)
3072 del_timer_sync(&udc_pollstall_timer);
3076 /* Reset all pci context */
3077 static void udc_pci_remove(struct pci_dev *pdev)
3081 dev = pci_get_drvdata(pdev);
3083 usb_del_gadget_udc(&udc->gadget);
3084 /* gadget driver must not be registered */
3085 BUG_ON(dev->driver != NULL);
3087 /* dma pool cleanup */
3088 if (dev->data_requests)
3089 pci_pool_destroy(dev->data_requests);
3091 if (dev->stp_requests) {
3092 /* cleanup DMA desc's for ep0in */
3093 pci_pool_free(dev->stp_requests,
3094 dev->ep[UDC_EP0OUT_IX].td_stp,
3095 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3096 pci_pool_free(dev->stp_requests,
3097 dev->ep[UDC_EP0OUT_IX].td,
3098 dev->ep[UDC_EP0OUT_IX].td_phys);
3100 pci_pool_destroy(dev->stp_requests);
3103 /* reset controller */
3104 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3105 if (dev->irq_registered)
3106 free_irq(pdev->irq, dev);
3109 if (dev->mem_region)
3110 release_mem_region(pci_resource_start(pdev, 0),
3111 pci_resource_len(pdev, 0));
3113 pci_disable_device(pdev);
3115 device_unregister(&dev->gadget.dev);
3116 pci_set_drvdata(pdev, NULL);
3121 /* create dma pools on init */
3122 static int init_dma_pools(struct udc *dev)
3124 struct udc_stp_dma *td_stp;
3125 struct udc_data_dma *td_data;
3128 /* consistent DMA mode setting ? */
3130 use_dma_bufferfill_mode = 0;
3133 use_dma_bufferfill_mode = 1;
3137 dev->data_requests = dma_pool_create("data_requests", NULL,
3138 sizeof(struct udc_data_dma), 0, 0);
3139 if (!dev->data_requests) {
3140 DBG(dev, "can't get request data pool\n");
3145 /* EP0 in dma regs = dev control regs */
3146 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3148 /* dma desc for setup data */
3149 dev->stp_requests = dma_pool_create("setup requests", NULL,
3150 sizeof(struct udc_stp_dma), 0, 0);
3151 if (!dev->stp_requests) {
3152 DBG(dev, "can't get stp request pool\n");
3157 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3158 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3159 if (td_stp == NULL) {
3163 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3165 /* data: 0 packets !? */
3166 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3167 &dev->ep[UDC_EP0OUT_IX].td_phys);
3168 if (td_data == NULL) {
3172 dev->ep[UDC_EP0OUT_IX].td = td_data;
3179 /* Called by pci bus driver to init pci context */
3180 static int udc_pci_probe(
3181 struct pci_dev *pdev,
3182 const struct pci_device_id *id
3186 unsigned long resource;
3192 dev_dbg(&pdev->dev, "already probed\n");
3197 dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3204 if (pci_enable_device(pdev) < 0) {
3212 /* PCI resource allocation */
3213 resource = pci_resource_start(pdev, 0);
3214 len = pci_resource_len(pdev, 0);
3216 if (!request_mem_region(resource, len, name)) {
3217 dev_dbg(&pdev->dev, "pci device used already\n");
3223 dev->mem_region = 1;
3225 dev->virt_addr = ioremap_nocache(resource, len);
3226 if (dev->virt_addr == NULL) {
3227 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
3235 dev_err(&dev->pdev->dev, "irq not set\n");
3242 spin_lock_init(&dev->lock);
3243 /* udc csr registers base */
3244 dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3245 /* dev registers base */
3246 dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3247 /* ep registers base */
3248 dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3250 dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3251 dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3253 if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
3254 dev_dbg(&dev->pdev->dev, "request_irq(%d) fail\n", pdev->irq);
3260 dev->irq_registered = 1;
3262 pci_set_drvdata(pdev, dev);
3264 /* chip revision for Hs AMD5536 */
3265 dev->chiprev = pdev->revision;
3267 pci_set_master(pdev);
3268 pci_try_set_mwi(pdev);
3270 /* init dma pools */
3272 retval = init_dma_pools(dev);
3277 dev->phys_addr = resource;
3278 dev->irq = pdev->irq;
3280 dev->gadget.dev.parent = &pdev->dev;
3281 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3283 /* general probing */
3284 if (udc_probe(dev) == 0)
3289 udc_pci_remove(pdev);
3294 static int udc_probe(struct udc *dev)
3300 /* mark timer as not initialized */
3302 udc_pollstall_timer.data = 0;
3304 /* device struct setup */
3305 dev->gadget.ops = &udc_ops;
3307 dev_set_name(&dev->gadget.dev, "gadget");
3308 dev->gadget.dev.release = gadget_release;
3309 dev->gadget.name = name;
3310 dev->gadget.max_speed = USB_SPEED_HIGH;
3312 /* init registers, interrupts, ... */
3313 startup_registers(dev);
3315 dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3317 snprintf(tmp, sizeof tmp, "%d", dev->irq);
3318 dev_info(&dev->pdev->dev,
3319 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3320 tmp, dev->phys_addr, dev->chiprev,
3321 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3322 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3323 if (dev->chiprev == UDC_HSA0_REV) {
3324 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3328 dev_info(&dev->pdev->dev,
3329 "driver version: %s(for Geode5536 B1)\n", tmp);
3332 retval = usb_add_gadget_udc(&udc->pdev->dev, &dev->gadget);
3336 retval = device_register(&dev->gadget.dev);
3338 usb_del_gadget_udc(&dev->gadget);
3339 put_device(&dev->gadget.dev);
3344 init_timer(&udc_timer);
3345 udc_timer.function = udc_timer_function;
3347 /* timer pollstall init */
3348 init_timer(&udc_pollstall_timer);
3349 udc_pollstall_timer.function = udc_pollstall_timer_function;
3350 udc_pollstall_timer.data = 1;
3353 reg = readl(&dev->regs->ctl);
3354 reg |= AMD_BIT(UDC_DEVCTL_SD);
3355 writel(reg, &dev->regs->ctl);
3357 /* print dev register info */
3366 /* Initiates a remote wakeup */
3367 static int udc_remote_wakeup(struct udc *dev)
3369 unsigned long flags;
3372 DBG(dev, "UDC initiates remote wakeup\n");
3374 spin_lock_irqsave(&dev->lock, flags);
3376 tmp = readl(&dev->regs->ctl);
3377 tmp |= AMD_BIT(UDC_DEVCTL_RES);
3378 writel(tmp, &dev->regs->ctl);
3379 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3380 writel(tmp, &dev->regs->ctl);
3382 spin_unlock_irqrestore(&dev->lock, flags);
3386 /* PCI device parameters */
3387 static DEFINE_PCI_DEVICE_TABLE(pci_id) = {
3389 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3390 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3391 .class_mask = 0xffffffff,
3395 MODULE_DEVICE_TABLE(pci, pci_id);
3398 static struct pci_driver udc_pci_driver = {
3399 .name = (char *) name,
3401 .probe = udc_pci_probe,
3402 .remove = udc_pci_remove,
3406 static int __init init(void)
3408 return pci_register_driver(&udc_pci_driver);
3413 static void __exit cleanup(void)
3415 pci_unregister_driver(&udc_pci_driver);
3417 module_exit(cleanup);
3419 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3420 MODULE_AUTHOR("Thomas Dahlmann");
3421 MODULE_LICENSE("GPL");