1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2015 Google, Inc
4 * Copyright (c) 2011 The Chromium OS Authors.
5 * Copyright (C) 2009 NVIDIA, Corporation
6 * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
17 #include <asm/unaligned.h>
18 #include <linux/delay.h>
19 #include <linux/mii.h>
20 #include "usb_ether.h"
22 /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
25 #define LED_GPIO_CFG (0x24)
26 #define LED_GPIO_CFG_SPD_LED (0x01000000)
27 #define LED_GPIO_CFG_LNK_LED (0x00100000)
28 #define LED_GPIO_CFG_FDX_LED (0x00010000)
30 /* Tx command words */
31 #define TX_CMD_A_FIRST_SEG_ 0x00002000
32 #define TX_CMD_A_LAST_SEG_ 0x00001000
35 #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
36 #define RX_STS_ES_ 0x00008000 /* Error Summary */
44 #define TX_CFG_ON_ 0x00000004
47 #define HW_CFG_BIR_ 0x00001000
48 #define HW_CFG_RXDOFF_ 0x00000600
49 #define HW_CFG_MEF_ 0x00000020
50 #define HW_CFG_BCE_ 0x00000002
51 #define HW_CFG_LRST_ 0x00000008
54 #define PM_CTL_PHY_RST_ 0x00000010
59 * Hi watermark = 15.5Kb (~10 mtu pkts)
60 * low watermark = 3k (~2 mtu pkts)
61 * backpressure duration = ~ 350us
62 * Apply FC on any frame.
64 #define AFC_CFG_DEFAULT 0x00F830A1
67 #define E2P_CMD_BUSY_ 0x80000000
68 #define E2P_CMD_READ_ 0x00000000
69 #define E2P_CMD_TIMEOUT_ 0x00000400
70 #define E2P_CMD_LOADED_ 0x00000200
71 #define E2P_CMD_ADDR_ 0x000001FF
75 #define BURST_CAP 0x38
77 #define INT_EP_CTL 0x68
78 #define INT_EP_CTL_PHY_INT_ 0x00008000
80 #define BULK_IN_DLY 0x6C
84 #define MAC_CR_MCPAS_ 0x00080000
85 #define MAC_CR_PRMS_ 0x00040000
86 #define MAC_CR_HPFILT_ 0x00002000
87 #define MAC_CR_TXEN_ 0x00000008
88 #define MAC_CR_RXEN_ 0x00000004
94 #define MII_ADDR 0x114
95 #define MII_WRITE_ 0x02
96 #define MII_BUSY_ 0x01
97 #define MII_READ_ 0x00 /* ~of MII Write bit */
99 #define MII_DATA 0x118
106 #define Tx_COE_EN_ 0x00010000
107 #define Rx_COE_EN_ 0x00000001
109 /* Vendor-specific PHY Definitions */
110 #define PHY_INT_SRC 29
112 #define PHY_INT_MASK 30
113 #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
114 #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
115 #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
116 PHY_INT_MASK_LINK_DOWN_)
118 /* USB Vendor Requests */
119 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
120 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
122 /* Some extra defines */
123 #define HS_USB_PKT_SIZE 512
124 #define FS_USB_PKT_SIZE 64
125 /* 5/33 is lower limit for BURST_CAP to work */
126 #define DEFAULT_HS_BURST_CAP_SIZE (5 * HS_USB_PKT_SIZE)
127 #define DEFAULT_FS_BURST_CAP_SIZE (33 * FS_USB_PKT_SIZE)
128 #define DEFAULT_BULK_IN_DELAY 0x00002000
129 #define MAX_SINGLE_PACKET_SIZE 2048
130 #define EEPROM_MAC_OFFSET 0x01
131 #define SMSC95XX_INTERNAL_PHY_ID 1
132 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
135 #define SMSC95XX_BASE_NAME "sms"
136 #define USB_CTRL_SET_TIMEOUT 5000
137 #define USB_CTRL_GET_TIMEOUT 5000
138 #define USB_BULK_SEND_TIMEOUT 5000
139 #define USB_BULK_RECV_TIMEOUT 5000
141 #define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE
142 #define PHY_CONNECT_TIMEOUT 5000
147 struct smsc95xx_private {
148 struct ueth_data ueth;
149 size_t rx_urb_size; /* maximum USB URB size */
150 u32 mac_cr; /* MAC control register value */
151 int have_hwaddr; /* 1 if we have a hardware MAC address */
155 * Smsc95xx infrastructure commands
157 static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
160 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
165 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
166 USB_VENDOR_REQUEST_WRITE_REGISTER,
167 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
168 0, index, tmpbuf, sizeof(data),
169 USB_CTRL_SET_TIMEOUT);
170 if (len != sizeof(data)) {
171 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
178 static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
181 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
183 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
184 USB_VENDOR_REQUEST_READ_REGISTER,
185 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
186 0, index, tmpbuf, sizeof(*data),
187 USB_CTRL_GET_TIMEOUT);
189 if (len != sizeof(*data)) {
190 debug("smsc95xx_read_reg failed: index=%d, len=%d",
199 /* Loop until the read is completed with timeout */
200 static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
202 unsigned long start_time = get_timer(0);
206 smsc95xx_read_reg(udev, MII_ADDR, &val);
207 if (!(val & MII_BUSY_))
209 } while (get_timer(start_time) < 1000);
214 static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
218 /* confirm MII not busy */
219 if (smsc95xx_phy_wait_not_busy(udev)) {
220 debug("MII is busy in smsc95xx_mdio_read\n");
224 /* set the address, index & direction (read from PHY) */
225 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
226 smsc95xx_write_reg(udev, MII_ADDR, addr);
228 if (smsc95xx_phy_wait_not_busy(udev)) {
229 debug("Timed out reading MII reg %02X\n", idx);
233 smsc95xx_read_reg(udev, MII_DATA, &val);
235 return (u16)(val & 0xFFFF);
238 static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
243 /* confirm MII not busy */
244 if (smsc95xx_phy_wait_not_busy(udev)) {
245 debug("MII is busy in smsc95xx_mdio_write\n");
250 smsc95xx_write_reg(udev, MII_DATA, val);
252 /* set the address, index & direction (write to PHY) */
253 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
254 smsc95xx_write_reg(udev, MII_ADDR, addr);
256 if (smsc95xx_phy_wait_not_busy(udev))
257 debug("Timed out writing MII reg %02X\n", idx);
260 static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
262 unsigned long start_time = get_timer(0);
266 smsc95xx_read_reg(udev, E2P_CMD, &val);
267 if (!(val & E2P_CMD_BUSY_))
270 } while (get_timer(start_time) < 1 * 1000 * 1000);
272 debug("EEPROM is busy\n");
276 static int smsc95xx_wait_eeprom(struct usb_device *udev)
278 unsigned long start_time = get_timer(0);
282 smsc95xx_read_reg(udev, E2P_CMD, &val);
283 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
286 } while (get_timer(start_time) < 1 * 1000 * 1000);
288 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
289 debug("EEPROM read operation timeout\n");
295 static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
301 ret = smsc95xx_eeprom_confirm_not_busy(udev);
305 for (i = 0; i < length; i++) {
306 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
307 smsc95xx_write_reg(udev, E2P_CMD, val);
309 ret = smsc95xx_wait_eeprom(udev);
313 smsc95xx_read_reg(udev, E2P_DATA, &val);
314 data[i] = val & 0xFF;
321 * mii_nway_restart - restart NWay (autonegotiation) for this interface
323 * Returns 0 on success, negative on error.
325 static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
330 /* if autoneg is off, it's an error */
331 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
333 if (bmcr & BMCR_ANENABLE) {
334 bmcr |= BMCR_ANRESTART;
335 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
341 static int smsc95xx_phy_initialize(struct usb_device *udev,
342 struct ueth_data *dev)
344 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
345 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
346 ADVERTISE_ALL | ADVERTISE_CSMA |
347 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
350 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
352 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
353 PHY_INT_MASK_DEFAULT_);
354 mii_nway_restart(udev, dev);
356 debug("phy initialised succesfully\n");
360 static int smsc95xx_init_mac_address(unsigned char *enetaddr,
361 struct usb_device *udev)
365 /* try reading mac address from EEPROM */
366 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
370 if (is_valid_ethaddr(enetaddr)) {
371 /* eeprom values are valid so use them */
372 debug("MAC address read from EEPROM\n");
377 * No eeprom, or eeprom values are invalid. Generating a random MAC
378 * address is not safe. Just return an error.
380 debug("Invalid MAC address read from EEPROM\n");
385 static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
386 struct smsc95xx_private *priv,
387 unsigned char *enetaddr)
389 u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
390 u32 addr_hi = get_unaligned_le16(&enetaddr[4]);
393 /* set hardware address */
394 debug("** %s()\n", __func__);
395 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
399 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
403 debug("MAC %pM\n", enetaddr);
404 priv->have_hwaddr = 1;
409 /* Enable or disable Tx & Rx checksum offload engines */
410 static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
414 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
419 read_buf |= Tx_COE_EN_;
421 read_buf &= ~Tx_COE_EN_;
424 read_buf |= Rx_COE_EN_;
426 read_buf &= ~Rx_COE_EN_;
428 ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
432 debug("COE_CR = 0x%08x\n", read_buf);
436 static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
438 /* No multicast in u-boot */
439 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
442 /* starts the TX path */
443 static void smsc95xx_start_tx_path(struct usb_device *udev,
444 struct smsc95xx_private *priv)
448 /* Enable Tx at MAC */
449 priv->mac_cr |= MAC_CR_TXEN_;
451 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
453 /* Enable Tx at SCSRs */
454 reg_val = TX_CFG_ON_;
455 smsc95xx_write_reg(udev, TX_CFG, reg_val);
458 /* Starts the Receive path */
459 static void smsc95xx_start_rx_path(struct usb_device *udev,
460 struct smsc95xx_private *priv)
462 priv->mac_cr |= MAC_CR_RXEN_;
463 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
466 static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
467 struct smsc95xx_private *priv,
468 unsigned char *enetaddr)
475 #define TIMEOUT_RESOLUTION 50 /* ms */
478 debug("** %s()\n", __func__);
479 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
481 write_buf = HW_CFG_LRST_;
482 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
488 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
493 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
495 if (timeout >= 100) {
496 debug("timeout waiting for completion of Lite Reset\n");
500 write_buf = PM_CTL_PHY_RST_;
501 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
507 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
512 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
513 if (timeout >= 100) {
514 debug("timeout waiting for PHY Reset\n");
517 if (!priv->have_hwaddr) {
518 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
519 return -EADDRNOTAVAIL;
521 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
526 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
527 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
528 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
530 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
531 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
535 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
537 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
539 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
543 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
546 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
548 read_buf = DEFAULT_BULK_IN_DELAY;
549 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
553 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
556 debug("Read Value from BULK_IN_DLY after writing: "
557 "0x%08x\n", read_buf);
559 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
562 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
565 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
567 read_buf &= ~HW_CFG_RXDOFF_;
569 #define NET_IP_ALIGN 0
570 read_buf |= NET_IP_ALIGN << 9;
572 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
576 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
579 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
581 write_buf = 0xFFFFFFFF;
582 ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
586 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
589 debug("ID_REV = 0x%08x\n", read_buf);
591 /* Configure GPIO pins as LED outputs */
592 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
593 LED_GPIO_CFG_FDX_LED;
594 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
597 debug("LED_GPIO_CFG set\n");
601 ret = smsc95xx_write_reg(udev, FLOW, write_buf);
605 read_buf = AFC_CFG_DEFAULT;
606 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
610 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
614 /* Init Rx. Set Vlan */
615 write_buf = (u32)ETH_P_8021Q;
616 ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
620 /* Disable checksum offload engines */
621 ret = smsc95xx_set_csums(udev, 0, 0);
623 debug("Failed to set csum offload: %d\n", ret);
626 smsc95xx_set_multicast(priv);
628 ret = smsc95xx_phy_initialize(udev, dev);
631 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
635 /* enable PHY interrupts */
636 read_buf |= INT_EP_CTL_PHY_INT_;
638 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
642 smsc95xx_start_tx_path(udev, priv);
643 smsc95xx_start_rx_path(udev, priv);
647 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
649 if (!link_detected) {
651 printf("Waiting for Ethernet connection... ");
652 udelay(TIMEOUT_RESOLUTION * 1000);
653 timeout += TIMEOUT_RESOLUTION;
655 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
660 printf("unable to connect.\n");
666 static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
672 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
673 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
675 debug("** %s(), len %d, buf %#x\n", __func__, length,
676 (unsigned int)(ulong)msg);
677 if (length > PKTSIZE)
680 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
681 tx_cmd_b = (u32)length;
682 cpu_to_le32s(&tx_cmd_a);
683 cpu_to_le32s(&tx_cmd_b);
685 /* prepend cmd_a and cmd_b */
686 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
687 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
688 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
690 err = usb_bulk_msg(dev->pusb_dev,
691 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
693 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
695 USB_BULK_SEND_TIMEOUT);
696 debug("Tx: len = %u, actual = %u, err = %d\n",
697 (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)),
698 (unsigned int)actual_len, err);
703 static int smsc95xx_eth_start(struct udevice *dev)
705 struct usb_device *udev = dev_get_parent_priv(dev);
706 struct smsc95xx_private *priv = dev_get_priv(dev);
707 struct eth_pdata *pdata = dev_get_plat(dev);
709 /* Driver-model Ethernet ensures we have this */
710 priv->have_hwaddr = 1;
712 return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
715 void smsc95xx_eth_stop(struct udevice *dev)
717 debug("** %s()\n", __func__);
720 int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
722 struct smsc95xx_private *priv = dev_get_priv(dev);
724 return smsc95xx_send_common(&priv->ueth, packet, length);
727 int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
729 struct smsc95xx_private *priv = dev_get_priv(dev);
730 struct ueth_data *ueth = &priv->ueth;
735 len = usb_ether_get_rx_bytes(ueth, &ptr);
736 debug("%s: first try, len=%d\n", __func__, len);
738 if (!(flags & ETH_RECV_CHECK_DEVICE))
740 ret = usb_ether_receive(ueth, RX_URB_SIZE);
744 len = usb_ether_get_rx_bytes(ueth, &ptr);
745 debug("%s: second try, len=%d\n", __func__, len);
749 * 1st 4 bytes contain the length of the actual data plus error info.
750 * Extract data length.
752 if (len < sizeof(packet_len)) {
753 debug("Rx: incomplete packet length\n");
756 memcpy(&packet_len, ptr, sizeof(packet_len));
757 le32_to_cpus(&packet_len);
758 if (packet_len & RX_STS_ES_) {
759 debug("Rx: Error header=%#x", packet_len);
762 packet_len = ((packet_len & RX_STS_FL_) >> 16);
764 if (packet_len > len - sizeof(packet_len)) {
765 debug("Rx: too large packet: %d\n", packet_len);
769 *packetp = ptr + sizeof(packet_len);
770 return packet_len - 4;
773 usb_ether_advance_rxbuf(ueth, -1);
777 static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
779 struct smsc95xx_private *priv = dev_get_priv(dev);
781 packet_len = ALIGN(packet_len + sizeof(u32), 4);
782 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
787 int smsc95xx_write_hwaddr(struct udevice *dev)
789 struct usb_device *udev = dev_get_parent_priv(dev);
790 struct eth_pdata *pdata = dev_get_plat(dev);
791 struct smsc95xx_private *priv = dev_get_priv(dev);
793 return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
796 int smsc95xx_read_rom_hwaddr(struct udevice *dev)
798 struct usb_device *udev = dev_get_parent_priv(dev);
799 struct eth_pdata *pdata = dev_get_plat(dev);
802 ret = smsc95xx_init_mac_address(pdata->enetaddr, udev);
804 memset(pdata->enetaddr, 0, 6);
809 static int smsc95xx_eth_probe(struct udevice *dev)
811 struct smsc95xx_private *priv = dev_get_priv(dev);
812 struct ueth_data *ueth = &priv->ueth;
814 return usb_ether_register(dev, ueth, RX_URB_SIZE);
817 static const struct eth_ops smsc95xx_eth_ops = {
818 .start = smsc95xx_eth_start,
819 .send = smsc95xx_eth_send,
820 .recv = smsc95xx_eth_recv,
821 .free_pkt = smsc95xx_free_pkt,
822 .stop = smsc95xx_eth_stop,
823 .write_hwaddr = smsc95xx_write_hwaddr,
824 .read_rom_hwaddr = smsc95xx_read_rom_hwaddr,
827 U_BOOT_DRIVER(smsc95xx_eth) = {
828 .name = "smsc95xx_eth",
830 .probe = smsc95xx_eth_probe,
831 .ops = &smsc95xx_eth_ops,
832 .priv_auto = sizeof(struct smsc95xx_private),
833 .plat_auto = sizeof(struct eth_pdata),
836 static const struct usb_device_id smsc95xx_eth_id_table[] = {
837 { USB_DEVICE(0x05ac, 0x1402) },
838 { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
839 { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
840 { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
841 { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
842 { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
843 { } /* Terminating entry */
846 U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);