1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
10 #include <linux/bitops.h>
11 #define R8152_BASE_NAME "r8152"
13 #define PLA_IDR 0xc000
14 #define PLA_RCR 0xc010
15 #define PLA_RMS 0xc016
16 #define PLA_RXFIFO_CTRL0 0xc0a0
17 #define PLA_RXFIFO_CTRL1 0xc0a4
18 #define PLA_RXFIFO_CTRL2 0xc0a8
19 #define PLA_DMY_REG0 0xc0b0
20 #define PLA_FMC 0xc0b4
21 #define PLA_CFG_WOL 0xc0b6
22 #define PLA_TEREDO_CFG 0xc0bc
23 #define PLA_MAR 0xcd00
24 #define PLA_BACKUP 0xd000
25 #define PLA_BDC_CR 0xd1a0
26 #define PLA_TEREDO_TIMER 0xd2cc
27 #define PLA_REALWOW_TIMER 0xd2e8
28 #define PLA_EXTRA_STATUS 0xd398
29 #define PLA_LEDSEL 0xdd90
30 #define PLA_LED_FEATURE 0xdd92
31 #define PLA_PHYAR 0xde00
32 #define PLA_BOOT_CTRL 0xe004
33 #define PLA_GPHY_INTR_IMR 0xe022
34 #define PLA_EEE_CR 0xe040
35 #define PLA_EEEP_CR 0xe080
36 #define PLA_MAC_PWR_CTRL 0xe0c0
37 #define PLA_MAC_PWR_CTRL2 0xe0ca
38 #define PLA_MAC_PWR_CTRL3 0xe0cc
39 #define PLA_MAC_PWR_CTRL4 0xe0ce
40 #define PLA_WDT6_CTRL 0xe428
41 #define PLA_TCR0 0xe610
42 #define PLA_TCR1 0xe612
43 #define PLA_MTPS 0xe615
44 #define PLA_TXFIFO_CTRL 0xe618
45 #define PLA_RSTTALLY 0xe800
46 #define BIST_CTRL 0xe810
48 #define PLA_CRWECR 0xe81c
49 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
50 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
51 #define PLA_CONFIG5 0xe822
52 #define PLA_PHY_PWR 0xe84c
53 #define PLA_OOB_CTRL 0xe84f
54 #define PLA_CPCR 0xe854
55 #define PLA_MISC_0 0xe858
56 #define PLA_MISC_1 0xe85a
57 #define PLA_OCP_GPHY_BASE 0xe86c
58 #define PLA_TALLYCNT 0xe890
59 #define PLA_SFF_STS_7 0xe8de
60 #define PLA_PHYSTATUS 0xe908
61 #define PLA_BP_BA 0xfc26
62 #define PLA_BP_0 0xfc28
63 #define PLA_BP_1 0xfc2a
64 #define PLA_BP_2 0xfc2c
65 #define PLA_BP_3 0xfc2e
66 #define PLA_BP_4 0xfc30
67 #define PLA_BP_5 0xfc32
68 #define PLA_BP_6 0xfc34
69 #define PLA_BP_7 0xfc36
70 #define PLA_BP_EN 0xfc38
72 #define USB_USB2PHY 0xb41e
73 #define USB_SSPHYLINK2 0xb428
74 #define USB_U2P3_CTRL 0xb460
75 #define USB_CSR_DUMMY1 0xb464
76 #define USB_CSR_DUMMY2 0xb466
77 #define USB_DEV_STAT 0xb808
78 #define USB_CONNECT_TIMER 0xcbf8
79 #define USB_BURST_SIZE 0xcfc0
80 #define USB_FW_FIX_EN1 0xcfcc
81 #define USB_USB_CTRL 0xd406
82 #define USB_PHY_CTRL 0xd408
83 #define USB_TX_AGG 0xd40a
84 #define USB_RX_BUF_TH 0xd40c
85 #define USB_USB_TIMER 0xd428
86 #define USB_RX_EARLY_TIMEOUT 0xd42c
87 #define USB_RX_EARLY_SIZE 0xd42e
88 #define USB_PM_CTRL_STATUS 0xd432
89 #define USB_TX_DMA 0xd434
90 #define USB_TOLERANCE 0xd490
91 #define USB_LPM_CTRL 0xd41a
92 #define USB_UPS_CTRL 0xd800
93 #define USB_MISC_0 0xd81a
94 #define USB_POWER_CUT 0xd80a
95 #define USB_AFE_CTRL2 0xd824
96 #define USB_WDT11_CTRL 0xe43c
97 #define USB_BP_BA 0xfc26
98 #define USB_BP_0 0xfc28
99 #define USB_BP_1 0xfc2a
100 #define USB_BP_2 0xfc2c
101 #define USB_BP_3 0xfc2e
102 #define USB_BP_4 0xfc30
103 #define USB_BP_5 0xfc32
104 #define USB_BP_6 0xfc34
105 #define USB_BP_7 0xfc36
106 #define USB_BP_EN 0xfc38
109 #define OCP_ALDPS_CONFIG 0x2010
110 #define OCP_EEE_CONFIG1 0x2080
111 #define OCP_EEE_CONFIG2 0x2092
112 #define OCP_EEE_CONFIG3 0x2094
113 #define OCP_BASE_MII 0xa400
114 #define OCP_EEE_AR 0xa41a
115 #define OCP_EEE_DATA 0xa41c
116 #define OCP_PHY_STATUS 0xa420
117 #define OCP_POWER_CFG 0xa430
118 #define OCP_EEE_CFG 0xa432
119 #define OCP_SRAM_ADDR 0xa436
120 #define OCP_SRAM_DATA 0xa438
121 #define OCP_DOWN_SPEED 0xa442
122 #define OCP_EEE_ABLE 0xa5c4
123 #define OCP_EEE_ADV 0xa5d0
124 #define OCP_EEE_LPABLE 0xa5d2
125 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
126 #define OCP_ADC_CFG 0xbc06
129 #define SRAM_LPF_CFG 0x8012
130 #define SRAM_10M_AMP1 0x8080
131 #define SRAM_10M_AMP2 0x8082
132 #define SRAM_IMPEDANCE 0x8084
135 #define RCR_AAP 0x00000001
136 #define RCR_APM 0x00000002
137 #define RCR_AM 0x00000004
138 #define RCR_AB 0x00000008
139 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
141 /* PLA_RXFIFO_CTRL0 */
142 #define RXFIFO_THR1_NORMAL 0x00080002
143 #define RXFIFO_THR1_OOB 0x01800003
145 /* PLA_RXFIFO_CTRL1 */
146 #define RXFIFO_THR2_FULL 0x00000060
147 #define RXFIFO_THR2_HIGH 0x00000038
148 #define RXFIFO_THR2_OOB 0x0000004a
149 #define RXFIFO_THR2_NORMAL 0x00a0
151 /* PLA_RXFIFO_CTRL2 */
152 #define RXFIFO_THR3_FULL 0x00000078
153 #define RXFIFO_THR3_HIGH 0x00000048
154 #define RXFIFO_THR3_OOB 0x0000005a
155 #define RXFIFO_THR3_NORMAL 0x0110
157 /* PLA_TXFIFO_CTRL */
158 #define TXFIFO_THR_NORMAL 0x00400008
159 #define TXFIFO_THR_NORMAL2 0x01000008
162 #define ECM_ALDPS 0x0002
165 #define FMC_FCR_MCU_EN 0x0001
168 #define EEEP_CR_EEEP_TX 0x0002
171 #define WDT6_SET_MODE 0x0010
174 #define TCR0_TX_EMPTY 0x0800
175 #define TCR0_AUTO_FIFO 0x0080
178 #define VERSION_MASK 0x7cf0
181 #define MTPS_JUMBO (12 * 1024 / 64)
182 #define MTPS_DEFAULT (6 * 1024 / 64)
185 #define TALLY_RESET 0x0001
188 #define PLA_CR_RST 0x10
189 #define PLA_CR_RE 0x08
190 #define PLA_CR_TE 0x04
193 #define BIST_CTRL_SW_RESET (0x10 << 24)
196 #define CRWECR_NORAML 0x00
197 #define CRWECR_CONFIG 0xc0
200 #define NOW_IS_OOB 0x80
201 #define TXFIFO_EMPTY 0x20
202 #define RXFIFO_EMPTY 0x10
203 #define LINK_LIST_READY 0x02
204 #define DIS_MCU_CLROOB 0x01
205 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
208 #define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24)
209 #define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24)
212 #define RXDY_GATED_EN 0x0008
215 #define RE_INIT_LL 0x8000
216 #define MCU_BORW_EN 0x4000
219 #define CPCR_RX_VLAN 0x0040
222 #define MAGIC_EN 0x0001
225 #define TEREDO_SEL 0x8000
226 #define TEREDO_WAKE_MASK 0x7f00
227 #define TEREDO_RS_EVENT_MASK 0x00fe
228 #define OOB_TEREDO_EN 0x0001
231 #define ALDPS_PROXY_MODE 0x0001
234 #define LINK_ON_WAKE_EN 0x0010
235 #define LINK_OFF_WAKE_EN 0x0008
238 #define BWF_EN 0x0040
239 #define MWF_EN 0x0020
240 #define UWF_EN 0x0010
241 #define LAN_WAKE_EN 0x0002
243 /* PLA_LED_FEATURE */
244 #define LED_MODE_MASK 0x0700
247 #define TX_10M_IDLE_EN 0x0080
248 #define PFM_PWM_SWITCH 0x0040
250 /* PLA_MAC_PWR_CTRL */
251 #define D3_CLK_GATED_EN 0x00004000
252 #define MCU_CLK_RATIO 0x07010f07
253 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
254 #define ALDPS_SPDWN_RATIO 0x0f87
256 /* PLA_MAC_PWR_CTRL2 */
257 #define EEE_SPDWN_RATIO 0x8007
259 /* PLA_MAC_PWR_CTRL3 */
260 #define PKT_AVAIL_SPDWN_EN 0x0100
261 #define SUSPEND_SPDWN_EN 0x0004
262 #define U1U2_SPDWN_EN 0x0002
263 #define L1_SPDWN_EN 0x0001
265 /* PLA_MAC_PWR_CTRL4 */
266 #define PWRSAVE_SPDWN_EN 0x1000
267 #define RXDV_SPDWN_EN 0x0800
268 #define TX10MIDLE_EN 0x0100
269 #define TP100_SPDWN_EN 0x0020
270 #define TP500_SPDWN_EN 0x0010
271 #define TP1000_SPDWN_EN 0x0008
272 #define EEE_SPDWN_EN 0x0001
274 /* PLA_GPHY_INTR_IMR */
275 #define GPHY_STS_MSK 0x0001
276 #define SPEED_DOWN_MSK 0x0002
277 #define SPDWN_RXDV_MSK 0x0004
278 #define SPDWN_LINKCHG_MSK 0x0008
281 #define PHYAR_FLAG 0x80000000
284 #define EEE_RX_EN 0x0001
285 #define EEE_TX_EN 0x0002
288 #define AUTOLOAD_DONE 0x0002
290 /* PLA_EXTRA_STATUS */
291 #define U3P3_CHECK_EN BIT(7)
294 #define USB2PHY_SUSPEND 0x0001
295 #define USB2PHY_L1 0x0002
298 #define pwd_dn_scale_mask 0x3ffe
299 #define pwd_dn_scale(x) ((x) << 1)
302 #define DYNAMIC_BURST 0x0001
305 #define EP4_FULL_FC 0x0001
308 #define STAT_SPEED_MASK 0x0006
309 #define STAT_SPEED_HIGH 0x0000
310 #define STAT_SPEED_FULL 0x0002
313 #define FW_IP_RESET_EN BIT(9)
316 #define TX_AGG_MAX_THRESHOLD 0x03
319 #define RX_THR_SUPPER 0x0c350180
320 #define RX_THR_HIGH 0x7a120180
321 #define RX_THR_SLOW 0xffff0180
324 #define TEST_MODE_DISABLE 0x00000001
325 #define TX_SIZE_ADJUST1 0x00000100
328 #define POWER_CUT 0x0100
330 /* USB_PM_CTRL_STATUS */
331 #define RESUME_INDICATE 0x0001
334 #define RX_AGG_DISABLE 0x0010
335 #define RX_ZERO_EN 0x0080
338 #define U2P3_ENABLE 0x0001
341 #define PWR_EN 0x0001
342 #define PHASE2_EN 0x0008
345 #define PCUT_STATUS 0x0001
347 /* USB_RX_EARLY_TIMEOUT */
348 #define COALESCE_SUPER 85000U
349 #define COALESCE_HIGH 250000U
350 #define COALESCE_SLOW 524280U
353 #define TIMER11_EN 0x0001
356 /* bit 4 ~ 5: fifo empty boundary */
357 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
358 /* bit 2 ~ 3: LMP timer */
359 #define LPM_TIMER_MASK 0x0c
360 #define LPM_TIMER_500MS 0x04 /* 500 ms */
361 #define LPM_TIMER_500US 0x0c /* 500 us */
362 #define ROK_EXIT_LPM 0x02
365 #define SEN_VAL_MASK 0xf800
366 #define SEN_VAL_NORMAL 0xa000
367 #define SEL_RXIDLE 0x0100
369 /* OCP_ALDPS_CONFIG */
370 #define ENPWRSAVE 0x8000
371 #define ENPDNPS 0x0200
372 #define LINKENA 0x0100
373 #define DIS_SDSAVE 0x0010
376 #define PHY_STAT_MASK 0x0007
377 #define PHY_STAT_LAN_ON 3
378 #define PHY_STAT_PWRDN 5
381 #define EEE_CLKDIV_EN 0x8000
382 #define EN_ALDPS 0x0004
383 #define EN_10M_PLLOFF 0x0001
385 /* OCP_EEE_CONFIG1 */
386 #define RG_TXLPI_MSK_HFDUP 0x8000
387 #define RG_MATCLR_EN 0x4000
388 #define EEE_10_CAP 0x2000
389 #define EEE_NWAY_EN 0x1000
390 #define TX_QUIET_EN 0x0200
391 #define RX_QUIET_EN 0x0100
392 #define sd_rise_time_mask 0x0070
393 #define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */
394 #define RG_RXLPI_MSK_HFDUP 0x0008
395 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
397 /* OCP_EEE_CONFIG2 */
398 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
399 #define RG_DACQUIET_EN 0x0400
400 #define RG_LDVQUIET_EN 0x0200
401 #define RG_CKRSEL 0x0020
402 #define RG_EEEPRG_EN 0x0010
404 /* OCP_EEE_CONFIG3 */
405 #define fast_snr_mask 0xff80
406 #define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */
407 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
408 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
411 /* bit[15:14] function */
412 #define FUN_ADDR 0x0000
413 #define FUN_DATA 0x4000
414 /* bit[4:0] device addr */
417 #define CTAP_SHORT_EN 0x0040
418 #define EEE10_EN 0x0010
421 #define EN_10M_BGOFF 0x0080
424 #define TXDIS_STATE 0x01
425 #define ABD_STATE 0x02
428 #define CKADSEL_L 0x0100
429 #define ADC_EN 0x0080
430 #define EN_EMI_L 0x0040
433 #define LPF_AUTO_TUNE 0x8000
436 #define GDAC_IB_UPALL 0x0008
439 #define AMP_DN 0x0200
442 #define RX_DRIVING_MASK 0x6000
444 #define RTL8152_MAX_TX 4
445 #define RTL8152_MAX_RX 10
451 #define INTR_LINK 0x0004
453 #define RTL8152_REQT_READ 0xc0
454 #define RTL8152_REQT_WRITE 0x40
455 #define RTL8152_REQ_GET_REGS 0x05
456 #define RTL8152_REQ_SET_REGS 0x05
458 #define BYTE_EN_DWORD 0xff
459 #define BYTE_EN_WORD 0x33
460 #define BYTE_EN_BYTE 0x11
461 #define BYTE_EN_SIX_BYTES 0x3f
462 #define BYTE_EN_START_MASK 0x0f
463 #define BYTE_EN_END_MASK 0xf0
465 #define RTL8152_ETH_FRAME_LEN 1514
466 #define RTL8152_AGG_BUF_SZ 2048
468 #define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
469 #define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
470 #define RTL8152_TX_TIMEOUT (5 * HZ)
472 #define MCU_TYPE_PLA 0x0100
473 #define MCU_TYPE_USB 0x0000
475 /* The forced speed, 10Mb, 100Mb, gigabit. */
477 #define SPEED_100 100
478 #define SPEED_1000 1000
480 #define SPEED_UNKNOWN -1
482 /* Duplex, half or full. */
483 #define DUPLEX_HALF 0x00
484 #define DUPLEX_FULL 0x01
485 #define DUPLEX_UNKNOWN 0xff
487 /* Enable or disable autonegotiation. */
488 #define AUTONEG_DISABLE 0x00
489 #define AUTONEG_ENABLE 0x01
491 /* Generic MII registers. */
492 #define MII_BMCR 0x00 /* Basic mode control register */
493 #define MII_BMSR 0x01 /* Basic mode status register */
494 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
495 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
496 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
497 #define MII_LPA 0x05 /* Link partner ability reg */
498 #define MII_EXPANSION 0x06 /* Expansion register */
499 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
500 #define MII_STAT1000 0x0a /* 1000BASE-T status */
501 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
502 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */
503 #define MII_ESTATUS 0x0f /* Extended Status */
504 #define MII_DCOUNTER 0x12 /* Disconnect counter */
505 #define MII_FCSCOUNTER 0x13 /* False carrier counter */
506 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
507 #define MII_RERRCOUNTER 0x15 /* Receive error counter */
508 #define MII_SREVISION 0x16 /* Silicon revision */
509 #define MII_RESV1 0x17 /* Reserved... */
510 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
511 #define MII_PHYADDR 0x19 /* PHY address */
512 #define MII_RESV2 0x1a /* Reserved... */
513 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
514 #define MII_NCONFIG 0x1c /* Network interface config */
516 #define TIMEOUT_RESOLUTION 50
517 #define PHY_CONNECT_TIMEOUT 5000
518 #define USB_BULK_SEND_TIMEOUT 5000
519 #define USB_BULK_RECV_TIMEOUT 5000
520 #define R8152_WAIT_TIMEOUT 2000
524 #define RD_CRC BIT(15)
525 #define RX_LEN_MASK 0x7fff
528 #define RD_UDP_CS BIT(23)
529 #define RD_TCP_CS BIT(22)
530 #define RD_IPV6_CS BIT(20)
531 #define RD_IPV4_CS BIT(19)
534 #define IPF BIT(23) /* IP checksum fail */
535 #define UDPF BIT(22) /* UDP checksum fail */
536 #define TCPF BIT(21) /* TCP checksum fail */
537 #define RX_VLAN_TAG BIT(16)
546 #define TX_FS BIT(31) /* First segment of a packet */
547 #define TX_LS BIT(30) /* Final segment of a packet */
548 #define LGSEND BIT(29)
549 #define GTSENDV4 BIT(28)
550 #define GTSENDV6 BIT(27)
551 #define GTTCPHO_SHIFT 18
552 #define GTTCPHO_MAX 0x7fU
553 #define TX_LEN_MAX 0x3ffffU
556 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
557 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
558 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
559 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
561 #define MSS_MAX 0x7ffU
562 #define TCPHO_SHIFT 17
563 #define TCPHO_MAX 0x7ffU
564 #define TX_VLAN_TAG BIT(16)
579 enum rtl_register_content {
588 struct usb_device *udev;
589 struct usb_interface *intf;
593 void (*init)(struct r8152 *);
594 int (*enable)(struct r8152 *);
595 void (*disable)(struct r8152 *);
596 void (*up)(struct r8152 *);
597 void (*down)(struct r8152 *);
598 void (*unload)(struct r8152 *);
607 struct ueth_data ueth;
611 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
612 u16 size, void *data, u16 type);
613 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
614 void *data, u16 type);
616 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
617 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
618 u16 size, void *data);
620 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
621 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
622 u16 size, void *data);
624 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index);
625 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data);
627 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index);
628 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data);
630 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index);
631 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data);
633 u16 ocp_reg_read(struct r8152 *tp, u16 addr);
634 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data);
636 void sram_write(struct r8152 *tp, u16 addr, u16 data);
638 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
639 const u32 mask, bool set, unsigned int timeout);
641 void r8152b_firmware(struct r8152 *tp);
642 void r8153_firmware(struct r8152 *tp);