1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
10 #include <linux/bitops.h>
11 #define R8152_BASE_NAME "r8152"
13 #define PLA_IDR 0xc000
14 #define PLA_RCR 0xc010
15 #define PLA_RMS 0xc016
16 #define PLA_RXFIFO_CTRL0 0xc0a0
17 #define PLA_RXFIFO_CTRL1 0xc0a4
18 #define PLA_RXFIFO_CTRL2 0xc0a8
19 #define PLA_DMY_REG0 0xc0b0
20 #define PLA_FMC 0xc0b4
21 #define PLA_CFG_WOL 0xc0b6
22 #define PLA_TEREDO_CFG 0xc0bc
23 #define PLA_MAR 0xcd00
24 #define PLA_BACKUP 0xd000
25 #define PLA_BDC_CR 0xd1a0
26 #define PLA_TEREDO_TIMER 0xd2cc
27 #define PLA_REALWOW_TIMER 0xd2e8
28 #define PLA_EXTRA_STATUS 0xd398
29 #define PLA_EFUSE_DATA 0xdd00
30 #define PLA_EFUSE_CMD 0xdd02
31 #define PLA_LEDSEL 0xdd90
32 #define PLA_LED_FEATURE 0xdd92
33 #define PLA_PHYAR 0xde00
34 #define PLA_BOOT_CTRL 0xe004
35 #define PLA_GPHY_INTR_IMR 0xe022
36 #define PLA_EEE_CR 0xe040
37 #define PLA_EEEP_CR 0xe080
38 #define PLA_MAC_PWR_CTRL 0xe0c0
39 #define PLA_MAC_PWR_CTRL2 0xe0ca
40 #define PLA_MAC_PWR_CTRL3 0xe0cc
41 #define PLA_MAC_PWR_CTRL4 0xe0ce
42 #define PLA_WDT6_CTRL 0xe428
43 #define PLA_TCR0 0xe610
44 #define PLA_TCR1 0xe612
45 #define PLA_MTPS 0xe615
46 #define PLA_TXFIFO_CTRL 0xe618
47 #define PLA_RSTTALLY 0xe800
48 #define BIST_CTRL 0xe810
50 #define PLA_CRWECR 0xe81c
51 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
52 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
53 #define PLA_CONFIG5 0xe822
54 #define PLA_PHY_PWR 0xe84c
55 #define PLA_OOB_CTRL 0xe84f
56 #define PLA_CPCR 0xe854
57 #define PLA_MISC_0 0xe858
58 #define PLA_MISC_1 0xe85a
59 #define PLA_OCP_GPHY_BASE 0xe86c
60 #define PLA_TALLYCNT 0xe890
61 #define PLA_SFF_STS_7 0xe8de
62 #define PLA_PHYSTATUS 0xe908
63 #define PLA_BP_BA 0xfc26
64 #define PLA_BP_0 0xfc28
65 #define PLA_BP_1 0xfc2a
66 #define PLA_BP_2 0xfc2c
67 #define PLA_BP_3 0xfc2e
68 #define PLA_BP_4 0xfc30
69 #define PLA_BP_5 0xfc32
70 #define PLA_BP_6 0xfc34
71 #define PLA_BP_7 0xfc36
72 #define PLA_BP_EN 0xfc38
74 #define USB_USB2PHY 0xb41e
75 #define USB_SSPHYLINK2 0xb428
76 #define USB_U2P3_CTRL 0xb460
77 #define USB_CSR_DUMMY1 0xb464
78 #define USB_CSR_DUMMY2 0xb466
79 #define USB_DEV_STAT 0xb808
80 #define USB_CONNECT_TIMER 0xcbf8
81 #define USB_MSC_TIMER 0xcbfc
82 #define USB_BURST_SIZE 0xcfc0
83 #define USB_FW_FIX_EN1 0xcfcc
84 #define USB_LPM_CONFIG 0xcfd8
85 #define USB_USB_CTRL 0xd406
86 #define USB_PHY_CTRL 0xd408
87 #define USB_TX_AGG 0xd40a
88 #define USB_RX_BUF_TH 0xd40c
89 #define USB_USB_TIMER 0xd428
90 #define USB_RX_EARLY_TIMEOUT 0xd42c
91 #define USB_RX_EARLY_SIZE 0xd42e
92 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
93 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
94 #define USB_TX_DMA 0xd434
95 #define USB_UPT_RXDMA_OWN 0xd437
96 #define USB_TOLERANCE 0xd490
97 #define USB_LPM_CTRL 0xd41a
98 #define USB_BMU_RESET 0xd4b0
99 #define USB_U1U2_TIMER 0xd4da
100 #define USB_UPS_CTRL 0xd800
101 #define USB_POWER_CUT 0xd80a
102 #define USB_MISC_0 0xd81a
103 #define USB_AFE_CTRL2 0xd824
104 #define USB_UPS_CFG 0xd842
105 #define USB_WDT11_CTRL 0xe43c
106 #define USB_BP_BA PLA_BP_BA
107 #define USB_BP(n) (0xfc28 + 2 * (n))
108 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
109 #define USB_BP2_EN 0xfc48
112 #define OCP_ALDPS_CONFIG 0x2010
113 #define OCP_EEE_CONFIG1 0x2080
114 #define OCP_EEE_CONFIG2 0x2092
115 #define OCP_EEE_CONFIG3 0x2094
116 #define OCP_BASE_MII 0xa400
117 #define OCP_EEE_AR 0xa41a
118 #define OCP_EEE_DATA 0xa41c
119 #define OCP_PHY_STATUS 0xa420
120 #define OCP_NCTL_CFG 0xa42c
121 #define OCP_POWER_CFG 0xa430
122 #define OCP_EEE_CFG 0xa432
123 #define OCP_SRAM_ADDR 0xa436
124 #define OCP_SRAM_DATA 0xa438
125 #define OCP_DOWN_SPEED 0xa442
126 #define OCP_EEE_ABLE 0xa5c4
127 #define OCP_EEE_ADV 0xa5d0
128 #define OCP_EEE_LPABLE 0xa5d2
129 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
130 #define OCP_ADC_IOFFSET 0xbcfc
131 #define OCP_ADC_CFG 0xbc06
134 #define SRAM_GREEN_CFG 0x8011
135 #define SRAM_LPF_CFG 0x8012
136 #define SRAM_10M_AMP1 0x8080
137 #define SRAM_10M_AMP2 0x8082
138 #define SRAM_IMPEDANCE 0x8084
141 #define RCR_AAP 0x00000001
142 #define RCR_APM 0x00000002
143 #define RCR_AM 0x00000004
144 #define RCR_AB 0x00000008
145 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
147 /* PLA_RXFIFO_CTRL0 */
148 #define RXFIFO_THR1_NORMAL 0x00080002
149 #define RXFIFO_THR1_OOB 0x01800003
151 /* PLA_RXFIFO_CTRL1 */
152 #define RXFIFO_THR2_FULL 0x00000060
153 #define RXFIFO_THR2_HIGH 0x00000038
154 #define RXFIFO_THR2_OOB 0x0000004a
155 #define RXFIFO_THR2_NORMAL 0x00a0
157 /* PLA_RXFIFO_CTRL2 */
158 #define RXFIFO_THR3_FULL 0x00000078
159 #define RXFIFO_THR3_HIGH 0x00000048
160 #define RXFIFO_THR3_OOB 0x0000005a
161 #define RXFIFO_THR3_NORMAL 0x0110
163 /* PLA_TXFIFO_CTRL */
164 #define TXFIFO_THR_NORMAL 0x00400008
165 #define TXFIFO_THR_NORMAL2 0x01000008
168 #define ECM_ALDPS 0x0002
171 #define FMC_FCR_MCU_EN 0x0001
174 #define EEEP_CR_EEEP_TX 0x0002
177 #define WDT6_SET_MODE 0x0010
180 #define TCR0_TX_EMPTY 0x0800
181 #define TCR0_AUTO_FIFO 0x0080
184 #define VERSION_MASK 0x7cf0
187 #define MTPS_JUMBO (12 * 1024 / 64)
188 #define MTPS_DEFAULT (6 * 1024 / 64)
191 #define TALLY_RESET 0x0001
194 #define PLA_CR_RST 0x10
195 #define PLA_CR_RE 0x08
196 #define PLA_CR_TE 0x04
199 #define BIST_CTRL_SW_RESET (0x10 << 24)
202 #define CRWECR_NORAML 0x00
203 #define CRWECR_CONFIG 0xc0
206 #define NOW_IS_OOB 0x80
207 #define TXFIFO_EMPTY 0x20
208 #define RXFIFO_EMPTY 0x10
209 #define LINK_LIST_READY 0x02
210 #define DIS_MCU_CLROOB 0x01
211 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
214 #define PLA_PHY_PWR_LLR (LINK_LIST_READY << 24)
215 #define PLA_PHY_PWR_TXEMP (TXFIFO_EMPTY << 24)
216 #define TEST_IO_OFF BIT(4)
219 #define RXDY_GATED_EN 0x0008
222 #define RE_INIT_LL 0x8000
223 #define MCU_BORW_EN 0x4000
226 #define CPCR_RX_VLAN 0x0040
229 #define MAGIC_EN 0x0001
232 #define TEREDO_SEL 0x8000
233 #define TEREDO_WAKE_MASK 0x7f00
234 #define TEREDO_RS_EVENT_MASK 0x00fe
235 #define OOB_TEREDO_EN 0x0001
238 #define ALDPS_PROXY_MODE 0x0001
241 #define EFUSE_READ_CMD BIT(15)
242 #define EFUSE_DATA_BIT16 BIT(7)
245 #define LINK_ON_WAKE_EN 0x0010
246 #define LINK_OFF_WAKE_EN 0x0008
249 #define BWF_EN 0x0040
250 #define MWF_EN 0x0020
251 #define UWF_EN 0x0010
252 #define LAN_WAKE_EN 0x0002
254 /* PLA_LED_FEATURE */
255 #define LED_MODE_MASK 0x0700
258 #define TX_10M_IDLE_EN 0x0080
259 #define PFM_PWM_SWITCH 0x0040
261 /* PLA_MAC_PWR_CTRL */
262 #define D3_CLK_GATED_EN 0x00004000
263 #define MCU_CLK_RATIO 0x07010f07
264 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
265 #define ALDPS_SPDWN_RATIO 0x0f87
267 /* PLA_MAC_PWR_CTRL2 */
268 #define EEE_SPDWN_RATIO 0x8007
269 #define MAC_CLK_SPDWN_EN BIT(15)
271 /* PLA_MAC_PWR_CTRL3 */
272 #define PLA_MCU_SPDWN_EN BIT(14)
273 #define PKT_AVAIL_SPDWN_EN 0x0100
274 #define SUSPEND_SPDWN_EN 0x0004
275 #define U1U2_SPDWN_EN 0x0002
276 #define L1_SPDWN_EN 0x0001
278 /* PLA_MAC_PWR_CTRL4 */
279 #define PWRSAVE_SPDWN_EN 0x1000
280 #define RXDV_SPDWN_EN 0x0800
281 #define TX10MIDLE_EN 0x0100
282 #define TP100_SPDWN_EN 0x0020
283 #define TP500_SPDWN_EN 0x0010
284 #define TP1000_SPDWN_EN 0x0008
285 #define EEE_SPDWN_EN 0x0001
287 /* PLA_GPHY_INTR_IMR */
288 #define GPHY_STS_MSK 0x0001
289 #define SPEED_DOWN_MSK 0x0002
290 #define SPDWN_RXDV_MSK 0x0004
291 #define SPDWN_LINKCHG_MSK 0x0008
294 #define PHYAR_FLAG 0x80000000
297 #define EEE_RX_EN 0x0001
298 #define EEE_TX_EN 0x0002
301 #define AUTOLOAD_DONE 0x0002
303 /* PLA_EXTRA_STATUS */
304 #define U3P3_CHECK_EN BIT(7)
307 #define USB2PHY_SUSPEND 0x0001
308 #define USB2PHY_L1 0x0002
311 #define pwd_dn_scale_mask 0x3ffe
312 #define pwd_dn_scale(x) ((x) << 1)
315 #define DYNAMIC_BURST 0x0001
318 #define EP4_FULL_FC 0x0001
321 #define STAT_SPEED_MASK 0x0006
322 #define STAT_SPEED_HIGH 0x0000
323 #define STAT_SPEED_FULL 0x0002
326 #define FW_IP_RESET_EN BIT(9)
329 #define LPM_U1U2_EN BIT(0)
332 #define TX_AGG_MAX_THRESHOLD 0x03
335 #define RX_THR_SUPPER 0x0c350180
336 #define RX_THR_HIGH 0x7a120180
337 #define RX_THR_SLOW 0xffff0180
339 /* USB_RX_EARLY_TIMEOUT */
340 #define RX_AUXILIARY_TIMER 1264
343 #define TEST_MODE_DISABLE 0x00000001
344 #define TX_SIZE_ADJUST1 0x00000100
347 #define BMU_RESET_EP_IN 0x01
348 #define BMU_RESET_EP_OUT 0x02
350 /* USB_UPT_RXDMA_OWN */
351 #define OWN_UPDATE BIT(0)
352 #define OWN_CLEAR BIT(1)
355 #define POWER_CUT 0x0100
357 /* USB_PM_CTRL_STATUS */
358 #define RESUME_INDICATE 0x0001
361 #define RX_AGG_DISABLE 0x0010
362 #define RX_ZERO_EN 0x0080
365 #define U2P3_ENABLE 0x0001
368 #define PWR_EN 0x0001
369 #define PHASE2_EN 0x0008
372 #define PCUT_STATUS 0x0001
374 /* USB_RX_EARLY_TIMEOUT */
375 #define COALESCE_SUPER 85000U
376 #define COALESCE_HIGH 250000U
377 #define COALESCE_SLOW 524280U
380 #define TIMER11_EN 0x0001
383 /* bit 4 ~ 5: fifo empty boundary */
384 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
385 /* bit 2 ~ 3: LMP timer */
386 #define LPM_TIMER_MASK 0x0c
387 #define LPM_TIMER_500MS 0x04 /* 500 ms */
388 #define LPM_TIMER_500US 0x0c /* 500 us */
389 #define ROK_EXIT_LPM 0x02
392 #define SEN_VAL_MASK 0xf800
393 #define SEN_VAL_NORMAL 0xa000
394 #define SEL_RXIDLE 0x0100
397 #define SAW_CNT_1MS_MASK 0x0fff
399 /* OCP_ALDPS_CONFIG */
400 #define ENPWRSAVE 0x8000
401 #define ENPDNPS 0x0200
402 #define LINKENA 0x0100
403 #define DIS_SDSAVE 0x0010
406 #define PHY_STAT_MASK 0x0007
407 #define PHY_STAT_LAN_ON 3
408 #define PHY_STAT_PWRDN 5
411 #define PGA_RETURN_EN BIT(1)
414 #define EEE_CLKDIV_EN 0x8000
415 #define EN_ALDPS 0x0004
416 #define EN_10M_PLLOFF 0x0001
418 /* OCP_EEE_CONFIG1 */
419 #define RG_TXLPI_MSK_HFDUP 0x8000
420 #define RG_MATCLR_EN 0x4000
421 #define EEE_10_CAP 0x2000
422 #define EEE_NWAY_EN 0x1000
423 #define TX_QUIET_EN 0x0200
424 #define RX_QUIET_EN 0x0100
425 #define sd_rise_time_mask 0x0070
426 #define sd_rise_time(x) (min((x), 7) << 4) /* bit 4 ~ 6 */
427 #define RG_RXLPI_MSK_HFDUP 0x0008
428 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
430 /* OCP_EEE_CONFIG2 */
431 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
432 #define RG_DACQUIET_EN 0x0400
433 #define RG_LDVQUIET_EN 0x0200
434 #define RG_CKRSEL 0x0020
435 #define RG_EEEPRG_EN 0x0010
437 /* OCP_EEE_CONFIG3 */
438 #define fast_snr_mask 0xff80
439 #define fast_snr(x) (min((x), 0x1ff) << 7) /* bit 7 ~ 15 */
440 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
441 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
444 /* bit[15:14] function */
445 #define FUN_ADDR 0x0000
446 #define FUN_DATA 0x4000
447 /* bit[4:0] device addr */
450 #define CTAP_SHORT_EN 0x0040
451 #define EEE10_EN 0x0010
454 #define EN_10M_BGOFF 0x0080
457 #define TXDIS_STATE 0x01
458 #define ABD_STATE 0x02
461 #define CKADSEL_L 0x0100
462 #define ADC_EN 0x0080
463 #define EN_EMI_L 0x0040
466 #define GREEN_ETH_EN BIT(15)
467 #define R_TUNE_EN BIT(11)
470 #define LPF_AUTO_TUNE 0x8000
473 #define GDAC_IB_UPALL 0x0008
476 #define AMP_DN 0x0200
479 #define RX_DRIVING_MASK 0x6000
481 #define RTL8152_MAX_TX 4
482 #define RTL8152_MAX_RX 10
488 #define INTR_LINK 0x0004
490 #define RTL8152_REQT_READ 0xc0
491 #define RTL8152_REQT_WRITE 0x40
492 #define RTL8152_REQ_GET_REGS 0x05
493 #define RTL8152_REQ_SET_REGS 0x05
495 #define BYTE_EN_DWORD 0xff
496 #define BYTE_EN_WORD 0x33
497 #define BYTE_EN_BYTE 0x11
498 #define BYTE_EN_SIX_BYTES 0x3f
499 #define BYTE_EN_START_MASK 0x0f
500 #define BYTE_EN_END_MASK 0xf0
502 #define RTL8152_ETH_FRAME_LEN 1514
503 #define RTL8152_AGG_BUF_SZ 2048
505 #define RTL8152_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
506 #define RTL8153_RMS (RTL8152_ETH_FRAME_LEN + CRC_SIZE)
507 #define RTL8152_TX_TIMEOUT (5 * HZ)
509 #define MCU_TYPE_PLA 0x0100
510 #define MCU_TYPE_USB 0x0000
512 /* The forced speed, 10Mb, 100Mb, gigabit. */
514 #define SPEED_100 100
515 #define SPEED_1000 1000
517 #define SPEED_UNKNOWN -1
519 /* Duplex, half or full. */
520 #define DUPLEX_HALF 0x00
521 #define DUPLEX_FULL 0x01
522 #define DUPLEX_UNKNOWN 0xff
524 /* Enable or disable autonegotiation. */
525 #define AUTONEG_DISABLE 0x00
526 #define AUTONEG_ENABLE 0x01
528 /* Generic MII registers. */
529 #define MII_BMCR 0x00 /* Basic mode control register */
530 #define MII_BMSR 0x01 /* Basic mode status register */
531 #define MII_PHYSID1 0x02 /* PHYS ID 1 */
532 #define MII_PHYSID2 0x03 /* PHYS ID 2 */
533 #define MII_ADVERTISE 0x04 /* Advertisement control reg */
534 #define MII_LPA 0x05 /* Link partner ability reg */
535 #define MII_EXPANSION 0x06 /* Expansion register */
536 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
537 #define MII_STAT1000 0x0a /* 1000BASE-T status */
538 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
539 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */
540 #define MII_ESTATUS 0x0f /* Extended Status */
541 #define MII_DCOUNTER 0x12 /* Disconnect counter */
542 #define MII_FCSCOUNTER 0x13 /* False carrier counter */
543 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
544 #define MII_RERRCOUNTER 0x15 /* Receive error counter */
545 #define MII_SREVISION 0x16 /* Silicon revision */
546 #define MII_RESV1 0x17 /* Reserved... */
547 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
548 #define MII_PHYADDR 0x19 /* PHY address */
549 #define MII_RESV2 0x1a /* Reserved... */
550 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
551 #define MII_NCONFIG 0x1c /* Network interface config */
553 #define TIMEOUT_RESOLUTION 50
554 #define PHY_CONNECT_TIMEOUT 5000
555 #define USB_BULK_SEND_TIMEOUT 5000
556 #define USB_BULK_RECV_TIMEOUT 5000
557 #define R8152_WAIT_TIMEOUT 2000
561 #define RD_CRC BIT(15)
562 #define RX_LEN_MASK 0x7fff
565 #define RD_UDP_CS BIT(23)
566 #define RD_TCP_CS BIT(22)
567 #define RD_IPV6_CS BIT(20)
568 #define RD_IPV4_CS BIT(19)
571 #define IPF BIT(23) /* IP checksum fail */
572 #define UDPF BIT(22) /* UDP checksum fail */
573 #define TCPF BIT(21) /* TCP checksum fail */
574 #define RX_VLAN_TAG BIT(16)
583 #define TX_FS BIT(31) /* First segment of a packet */
584 #define TX_LS BIT(30) /* Final segment of a packet */
585 #define LGSEND BIT(29)
586 #define GTSENDV4 BIT(28)
587 #define GTSENDV6 BIT(27)
588 #define GTTCPHO_SHIFT 18
589 #define GTTCPHO_MAX 0x7fU
590 #define TX_LEN_MAX 0x3ffffU
593 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
594 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
595 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
596 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
598 #define MSS_MAX 0x7ffU
599 #define TCPHO_SHIFT 17
600 #define TCPHO_MAX 0x7ffU
601 #define TX_VLAN_TAG BIT(16)
618 enum rtl_register_content {
627 struct usb_device *udev;
628 struct usb_interface *intf;
632 void (*init)(struct r8152 *);
633 int (*enable)(struct r8152 *);
634 void (*disable)(struct r8152 *);
635 void (*up)(struct r8152 *);
636 void (*down)(struct r8152 *);
637 void (*unload)(struct r8152 *);
645 struct ueth_data ueth;
648 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
649 u16 size, void *data, u16 type);
650 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
651 void *data, u16 type);
653 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
654 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
655 u16 size, void *data);
657 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data);
658 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
659 u16 size, void *data);
661 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index);
662 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data);
664 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index);
665 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data);
667 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index);
668 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data);
670 u16 ocp_reg_read(struct r8152 *tp, u16 addr);
671 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data);
673 void sram_write(struct r8152 *tp, u16 addr, u16 data);
675 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
676 const u32 mask, bool set, unsigned int timeout);
678 void r8152b_firmware(struct r8152 *tp);
679 void r8153_firmware(struct r8152 *tp);
680 void r8153b_firmware(struct r8152 *tp);