1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
15 #include <linux/delay.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include "usb_ether.h"
23 static int curr_eth_dev; /* index for name of next device detected */
26 unsigned short vendor;
27 unsigned short product;
30 static const struct r8152_dongle r8152_dongles[] = {
57 struct r8152_version {
59 unsigned short version;
63 static const struct r8152_version r8152_versions[] = {
64 { 0x4c00, RTL_VER_01, 0 },
65 { 0x4c10, RTL_VER_02, 0 },
66 { 0x5c00, RTL_VER_03, 1 },
67 { 0x5c10, RTL_VER_04, 1 },
68 { 0x5c20, RTL_VER_05, 1 },
69 { 0x5c30, RTL_VER_06, 1 },
70 { 0x4800, RTL_VER_07, 0 },
71 { 0x6000, RTL_VER_08, 1 },
72 { 0x6010, RTL_VER_09, 1 },
76 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
78 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
81 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
82 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
83 value, index, tmp, size, 500);
84 memcpy(data, tmp, size);
89 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
91 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
93 memcpy(tmp, data, size);
94 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
95 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
96 value, index, tmp, size, 500);
99 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
100 void *data, u16 type)
106 /* both size and index must be 4 bytes align */
107 if ((size & 3) || !size || (index & 3) || !data)
110 if (index + size > 0xffff)
114 txsize = min(size, burst_size);
115 ret = get_registers(tp, index, type, txsize, data);
127 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
128 u16 size, void *data, u16 type)
131 u16 byteen_start, byteen_end, byte_en_to_hw;
132 u16 burst_size = 512;
135 /* both size and index must be 4 bytes align */
136 if ((size & 3) || !size || (index & 3) || !data)
139 if (index + size > 0xffff)
142 byteen_start = byteen & BYTE_EN_START_MASK;
143 byteen_end = byteen & BYTE_EN_END_MASK;
145 byte_en_to_hw = byteen_start | (byteen_start << 4);
146 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
158 txsize = min(size, burst_size);
160 ret = set_registers(tp, index,
161 type | BYTE_EN_DWORD,
171 byte_en_to_hw = byteen_end | (byteen_end >> 4);
172 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
180 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
182 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
185 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
187 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
190 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
192 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
195 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
197 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
200 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
204 generic_ocp_read(tp, index, sizeof(data), &data, type);
206 return __le32_to_cpu(data);
209 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
211 __le32 tmp = __cpu_to_le32(data);
213 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
216 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
220 u8 shift = index & 2;
224 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
226 data = __le32_to_cpu(tmp);
227 data >>= (shift * 8);
233 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
237 u16 byen = BYTE_EN_WORD;
238 u8 shift = index & 2;
244 mask <<= (shift * 8);
245 data <<= (shift * 8);
249 tmp = __cpu_to_le32(data);
251 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
254 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
258 u8 shift = index & 3;
262 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
264 data = __le32_to_cpu(tmp);
265 data >>= (shift * 8);
271 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
275 u16 byen = BYTE_EN_BYTE;
276 u8 shift = index & 3;
282 mask <<= (shift * 8);
283 data <<= (shift * 8);
287 tmp = __cpu_to_le32(data);
289 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
292 u16 ocp_reg_read(struct r8152 *tp, u16 addr)
294 u16 ocp_base, ocp_index;
296 ocp_base = addr & 0xf000;
297 if (ocp_base != tp->ocp_base) {
298 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
299 tp->ocp_base = ocp_base;
302 ocp_index = (addr & 0x0fff) | 0xb000;
303 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
306 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
308 u16 ocp_base, ocp_index;
310 ocp_base = addr & 0xf000;
311 if (ocp_base != tp->ocp_base) {
312 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
313 tp->ocp_base = ocp_base;
316 ocp_index = (addr & 0x0fff) | 0xb000;
317 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
320 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
322 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
325 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
327 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
330 void sram_write(struct r8152 *tp, u16 addr, u16 data)
332 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
333 ocp_reg_write(tp, OCP_SRAM_DATA, data);
336 static u16 sram_read(struct r8152 *tp, u16 addr)
338 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
339 return ocp_reg_read(tp, OCP_SRAM_DATA);
342 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
343 const u32 mask, bool set, unsigned int timeout)
349 val = ocp_reg_read(tp, index);
351 val = ocp_read_dword(tp, type, index);
356 if ((val & mask) == mask)
362 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
363 __func__, index, mask, timeout);
368 static void r8152b_reset_packet_filter(struct r8152 *tp)
372 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
373 ocp_data &= ~FMC_FCR_MCU_EN;
374 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
375 ocp_data |= FMC_FCR_MCU_EN;
376 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
379 static void rtl8152_wait_fifo_empty(struct r8152 *tp)
383 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
384 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
386 debug("Timeout waiting for FIFO empty\n");
388 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
389 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
391 debug("Timeout waiting for TX empty\n");
394 static void rtl8152_nic_reset(struct r8152 *tp)
399 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
400 ocp_data |= BIST_CTRL_SW_RESET;
401 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
403 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
404 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
406 debug("Timeout waiting for NIC reset\n");
409 static u8 rtl8152_get_speed(struct r8152 *tp)
411 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
414 static void rtl_set_eee_plus(struct r8152 *tp)
418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
419 ocp_data &= ~EEEP_CR_EEEP_TX;
420 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
423 static void rxdy_gated_en(struct r8152 *tp, bool enable)
427 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
429 ocp_data |= RXDY_GATED_EN;
431 ocp_data &= ~RXDY_GATED_EN;
432 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
435 static void rtl8152_set_rx_mode(struct r8152 *tp)
443 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
445 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
446 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
447 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
450 static int rtl_enable(struct r8152 *tp)
454 r8152b_reset_packet_filter(tp);
456 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
457 ocp_data |= PLA_CR_RE | PLA_CR_TE;
458 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
460 rxdy_gated_en(tp, false);
462 rtl8152_set_rx_mode(tp);
467 static int rtl8152_enable(struct r8152 *tp)
469 rtl_set_eee_plus(tp);
471 return rtl_enable(tp);
474 static void r8153_set_rx_early_timeout(struct r8152 *tp)
476 u32 ocp_data = tp->coalesce / 8;
478 switch (tp->version) {
483 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
489 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
490 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 1264ns.
492 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
493 RX_AUXILIARY_TIMER / 8);
494 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
499 debug("** %s Invalid Device\n", __func__);
504 static void r8153_set_rx_early_size(struct r8152 *tp)
506 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS -
507 sizeof(struct rx_desc));
509 switch (tp->version) {
514 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
520 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
525 debug("** %s Invalid Device\n", __func__);
529 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
532 static int rtl8153_enable(struct r8152 *tp)
534 rtl_set_eee_plus(tp);
535 r8153_set_rx_early_timeout(tp);
536 r8153_set_rx_early_size(tp);
538 return rtl_enable(tp);
541 static void rtl_disable(struct r8152 *tp)
545 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
546 ocp_data &= ~RCR_ACPT_ALL;
547 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
549 rxdy_gated_en(tp, true);
551 rtl8152_wait_fifo_empty(tp);
552 rtl8152_nic_reset(tp);
555 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
559 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
561 ocp_data |= POWER_CUT;
563 ocp_data &= ~POWER_CUT;
564 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
566 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
567 ocp_data &= ~RESUME_INDICATE;
568 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
571 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
575 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
577 ocp_data |= CPCR_RX_VLAN;
579 ocp_data &= ~CPCR_RX_VLAN;
580 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
583 static void r8153_u1u2en(struct r8152 *tp, bool enable)
588 memset(u1u2, 0xff, sizeof(u1u2));
590 memset(u1u2, 0x00, sizeof(u1u2));
592 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
595 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
599 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
601 ocp_data |= LPM_U1U2_EN;
603 ocp_data &= ~LPM_U1U2_EN;
605 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
608 static void r8153_u2p3en(struct r8152 *tp, bool enable)
612 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
613 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
614 ocp_data |= U2P3_ENABLE;
616 ocp_data &= ~U2P3_ENABLE;
617 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
620 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
624 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
626 ocp_data |= PWR_EN | PHASE2_EN;
628 ocp_data &= ~(PWR_EN | PHASE2_EN);
629 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
631 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
632 ocp_data &= ~PCUT_STATUS;
633 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
636 static void rtl_reset_bmu(struct r8152 *tp)
640 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
641 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
642 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
643 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
644 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
647 static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
650 unsigned char enetaddr[8] = {0};
652 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
656 memcpy(macaddr, enetaddr, ETH_ALEN);
660 static void r8152b_disable_aldps(struct r8152 *tp)
662 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
666 static void r8152b_enable_aldps(struct r8152 *tp)
668 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
669 LINKENA | DIS_SDSAVE);
672 static void rtl8152_disable(struct r8152 *tp)
674 r8152b_disable_aldps(tp);
676 r8152b_enable_aldps(tp);
679 static void r8152b_hw_phy_cfg(struct r8152 *tp)
683 data = r8152_mdio_read(tp, MII_BMCR);
684 if (data & BMCR_PDOWN) {
686 r8152_mdio_write(tp, MII_BMCR, data);
692 static void rtl8152_reinit_ll(struct r8152 *tp)
697 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
698 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
700 debug("Timeout waiting for link list ready\n");
702 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
703 ocp_data |= RE_INIT_LL;
704 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
706 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
707 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
709 debug("Timeout waiting for link list ready\n");
712 static void r8152b_exit_oob(struct r8152 *tp)
716 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
717 ocp_data &= ~RCR_ACPT_ALL;
718 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
720 rxdy_gated_en(tp, true);
721 r8152b_hw_phy_cfg(tp);
723 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
724 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
726 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
727 ocp_data &= ~NOW_IS_OOB;
728 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
730 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
731 ocp_data &= ~MCU_BORW_EN;
732 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
734 rtl8152_reinit_ll(tp);
735 rtl8152_nic_reset(tp);
737 /* rx share fifo credit full threshold */
738 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
740 if (tp->udev->speed == USB_SPEED_FULL ||
741 tp->udev->speed == USB_SPEED_LOW) {
742 /* rx share fifo credit near full threshold */
743 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
745 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
748 /* rx share fifo credit near full threshold */
749 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
751 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
755 /* TX share fifo free credit full threshold */
756 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
758 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
759 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
760 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
761 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
763 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
765 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
766 ocp_data |= TCR0_AUTO_FIFO;
767 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
770 static void r8152b_enter_oob(struct r8152 *tp)
774 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
775 ocp_data &= ~NOW_IS_OOB;
776 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
778 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
779 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
780 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
784 rtl8152_reinit_ll(tp);
786 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
788 rtl_rx_vlan_en(tp, false);
790 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
791 ocp_data |= ALDPS_PROXY_MODE;
792 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
794 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
795 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
796 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
798 rxdy_gated_en(tp, false);
800 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
801 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
802 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
805 static void r8153_hw_phy_cfg(struct r8152 *tp)
810 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
811 tp->version == RTL_VER_05)
812 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
814 data = r8152_mdio_read(tp, MII_BMCR);
815 if (data & BMCR_PDOWN) {
817 r8152_mdio_write(tp, MII_BMCR, data);
822 if (tp->version == RTL_VER_03) {
823 data = ocp_reg_read(tp, OCP_EEE_CFG);
824 data &= ~CTAP_SHORT_EN;
825 ocp_reg_write(tp, OCP_EEE_CFG, data);
828 data = ocp_reg_read(tp, OCP_POWER_CFG);
829 data |= EEE_CLKDIV_EN;
830 ocp_reg_write(tp, OCP_POWER_CFG, data);
832 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
833 data |= EN_10M_BGOFF;
834 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
835 data = ocp_reg_read(tp, OCP_POWER_CFG);
836 data |= EN_10M_PLLOFF;
837 ocp_reg_write(tp, OCP_POWER_CFG, data);
838 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
840 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
841 ocp_data |= PFM_PWM_SWITCH;
842 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
844 /* Enable LPF corner auto tune */
845 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
847 /* Adjust 10M Amplitude */
848 sram_write(tp, SRAM_10M_AMP1, 0x00af);
849 sram_write(tp, SRAM_10M_AMP2, 0x0208);
852 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
856 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
857 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
858 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
859 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
864 static void r8153b_hw_phy_cfg(struct r8152 *tp)
869 data = r8152_mdio_read(tp, MII_BMCR);
870 if (data & BMCR_PDOWN) {
872 r8152_mdio_write(tp, MII_BMCR, data);
875 /* U1/U2/L1 idle timer. 500 us */
876 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
880 data = sram_read(tp, SRAM_GREEN_CFG);
882 sram_write(tp, SRAM_GREEN_CFG, data);
883 data = ocp_reg_read(tp, OCP_NCTL_CFG);
884 data |= PGA_RETURN_EN;
885 ocp_reg_write(tp, OCP_NCTL_CFG, data);
887 /* ADC Bias Calibration:
888 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
889 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
892 ocp_data = r8152_efuse_read(tp, 0x7d);
893 ocp_data = ((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7);
894 if (ocp_data != 0xffff)
895 ocp_reg_write(tp, OCP_ADC_IOFFSET, ocp_data);
897 /* ups mode tx-link-pulse timing adjustment:
898 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
899 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
901 ocp_data = ocp_reg_read(tp, 0xc426);
906 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
907 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
908 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
909 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
912 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
913 ocp_data |= PFM_PWM_SWITCH;
914 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
917 static void r8153_first_init(struct r8152 *tp)
921 rxdy_gated_en(tp, true);
923 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
924 ocp_data &= ~RCR_ACPT_ALL;
925 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
927 r8153_hw_phy_cfg(tp);
929 rtl8152_nic_reset(tp);
932 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
933 ocp_data &= ~NOW_IS_OOB;
934 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
936 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
937 ocp_data &= ~MCU_BORW_EN;
938 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
940 rtl8152_reinit_ll(tp);
942 rtl_rx_vlan_en(tp, false);
944 ocp_data = RTL8153_RMS;
945 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
946 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
948 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
949 ocp_data |= TCR0_AUTO_FIFO;
950 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
952 rtl8152_nic_reset(tp);
954 /* rx share fifo credit full threshold */
955 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
956 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
957 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
958 /* TX share fifo free credit full threshold */
959 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
962 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
964 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
965 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
968 static void r8153_enter_oob(struct r8152 *tp)
972 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
973 ocp_data &= ~NOW_IS_OOB;
974 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
979 rtl8152_reinit_ll(tp);
981 ocp_data = RTL8153_RMS;
982 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
984 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
985 ocp_data &= ~TEREDO_WAKE_MASK;
986 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
988 rtl_rx_vlan_en(tp, false);
990 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
991 ocp_data |= ALDPS_PROXY_MODE;
992 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
994 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
995 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
996 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
998 rxdy_gated_en(tp, false);
1000 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1001 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1002 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1005 static void r8153_disable_aldps(struct r8152 *tp)
1009 data = ocp_reg_read(tp, OCP_POWER_CFG);
1011 ocp_reg_write(tp, OCP_POWER_CFG, data);
1015 static void rtl8153_disable(struct r8152 *tp)
1017 r8153_disable_aldps(tp);
1022 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
1024 u16 bmcr, anar, gbcr;
1026 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1027 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1028 ADVERTISE_100HALF | ADVERTISE_100FULL);
1029 if (tp->supports_gmii) {
1030 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
1031 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1036 if (autoneg == AUTONEG_DISABLE) {
1037 if (speed == SPEED_10) {
1039 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1040 } else if (speed == SPEED_100) {
1041 bmcr = BMCR_SPEED100;
1042 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1043 } else if (speed == SPEED_1000 && tp->supports_gmii) {
1044 bmcr = BMCR_SPEED1000;
1045 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1050 if (duplex == DUPLEX_FULL)
1051 bmcr |= BMCR_FULLDPLX;
1053 if (speed == SPEED_10) {
1054 if (duplex == DUPLEX_FULL)
1055 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1057 anar |= ADVERTISE_10HALF;
1058 } else if (speed == SPEED_100) {
1059 if (duplex == DUPLEX_FULL) {
1060 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1061 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1063 anar |= ADVERTISE_10HALF;
1064 anar |= ADVERTISE_100HALF;
1066 } else if (speed == SPEED_1000 && tp->supports_gmii) {
1067 if (duplex == DUPLEX_FULL) {
1068 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1069 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1070 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1072 anar |= ADVERTISE_10HALF;
1073 anar |= ADVERTISE_100HALF;
1074 gbcr |= ADVERTISE_1000HALF;
1080 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1083 if (tp->supports_gmii)
1084 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
1086 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1087 r8152_mdio_write(tp, MII_BMCR, bmcr);
1092 static void rtl8152_up(struct r8152 *tp)
1094 r8152b_disable_aldps(tp);
1095 r8152b_exit_oob(tp);
1096 r8152b_enable_aldps(tp);
1099 static void rtl8152_down(struct r8152 *tp)
1101 r8152_power_cut_en(tp, false);
1102 r8152b_disable_aldps(tp);
1103 r8152b_enter_oob(tp);
1104 r8152b_enable_aldps(tp);
1107 static void rtl8153_up(struct r8152 *tp)
1109 r8153_u1u2en(tp, false);
1110 r8153_disable_aldps(tp);
1111 r8153_first_init(tp);
1112 r8153_u2p3en(tp, false);
1115 static void rtl8153_down(struct r8152 *tp)
1117 r8153_u1u2en(tp, false);
1118 r8153_u2p3en(tp, false);
1119 r8153_power_cut_en(tp, false);
1120 r8153_disable_aldps(tp);
1121 r8153_enter_oob(tp);
1124 static void rtl8153b_up(struct r8152 *tp)
1126 r8153_first_init(tp);
1129 static void rtl8153b_down(struct r8152 *tp)
1131 r8153_enter_oob(tp);
1134 static void r8152b_get_version(struct r8152 *tp)
1140 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
1141 tcr = (u16)(ocp_data & VERSION_MASK);
1143 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
1144 if (tcr == r8152_versions[i].tcr) {
1145 /* Found a supported version */
1146 tp->version = r8152_versions[i].version;
1147 tp->supports_gmii = r8152_versions[i].gmii;
1152 if (tp->version == RTL_VER_UNKNOWN)
1153 debug("r8152 Unknown tcr version 0x%04x\n", tcr);
1156 static void r8152b_enable_fc(struct r8152 *tp)
1159 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1160 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1161 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1164 static void rtl_tally_reset(struct r8152 *tp)
1168 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
1169 ocp_data |= TALLY_RESET;
1170 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
1173 static void r8152b_init(struct r8152 *tp)
1177 r8152b_disable_aldps(tp);
1179 if (tp->version == RTL_VER_01) {
1180 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1181 ocp_data &= ~LED_MODE_MASK;
1182 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1185 r8152_power_cut_en(tp, false);
1187 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1188 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1189 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1190 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1191 ocp_data &= ~MCU_CLK_RATIO_MASK;
1192 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1193 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1194 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1195 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1196 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1198 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
1199 ocp_data |= BIT(15);
1200 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1201 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
1202 ocp_data &= ~BIT(15);
1203 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1205 r8152b_enable_fc(tp);
1206 rtl_tally_reset(tp);
1208 /* enable rx aggregation */
1209 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1211 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1212 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1215 static void r8153_init(struct r8152 *tp)
1220 r8153_disable_aldps(tp);
1221 r8153_u1u2en(tp, false);
1223 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1224 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1226 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1227 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1228 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1234 r8153_u2p3en(tp, false);
1236 if (tp->version == RTL_VER_04) {
1237 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
1238 ocp_data &= ~pwd_dn_scale_mask;
1239 ocp_data |= pwd_dn_scale(96);
1240 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
1242 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
1243 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
1244 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
1245 } else if (tp->version == RTL_VER_05) {
1246 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
1247 ocp_data &= ~ECM_ALDPS;
1248 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
1250 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1251 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1252 ocp_data &= ~DYNAMIC_BURST;
1254 ocp_data |= DYNAMIC_BURST;
1255 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1256 } else if (tp->version == RTL_VER_06) {
1257 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1258 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1259 ocp_data &= ~DYNAMIC_BURST;
1261 ocp_data |= DYNAMIC_BURST;
1262 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1265 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
1266 ocp_data |= EP4_FULL_FC;
1267 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
1269 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
1270 ocp_data &= ~TIMER11_EN;
1271 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
1273 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1274 ocp_data &= ~LED_MODE_MASK;
1275 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1277 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
1278 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
1279 ocp_data |= LPM_TIMER_500MS;
1281 ocp_data |= LPM_TIMER_500US;
1282 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
1284 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
1285 ocp_data &= ~SEN_VAL_MASK;
1286 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
1287 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
1289 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1291 r8153_power_cut_en(tp, false);
1293 r8152b_enable_fc(tp);
1294 rtl_tally_reset(tp);
1297 static void r8153b_init(struct r8152 *tp)
1302 r8153_disable_aldps(tp);
1303 r8153b_u1u2en(tp, false);
1305 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1306 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1308 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1309 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1310 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1316 r8153_u2p3en(tp, false);
1318 /* MSC timer = 0xfff * 8ms = 32760 ms */
1319 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
1321 r8153_power_cut_en(tp, false);
1323 /* MAC clock speed down */
1324 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
1325 ocp_data |= MAC_CLK_SPDWN_EN;
1326 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
1328 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1329 ocp_data &= ~PLA_MCU_SPDWN_EN;
1330 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
1332 if (tp->version == RTL_VER_09) {
1333 /* Disable Test IO for 32QFN */
1334 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
1335 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1336 ocp_data |= TEST_IO_OFF;
1337 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1341 /* rx aggregation */
1342 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1343 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1344 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1346 rtl_tally_reset(tp);
1347 r8153b_hw_phy_cfg(tp);
1348 r8152b_enable_fc(tp);
1351 static void rtl8152_unload(struct r8152 *tp)
1353 if (tp->version != RTL_VER_01)
1354 r8152_power_cut_en(tp, true);
1357 static void rtl8153_unload(struct r8152 *tp)
1359 r8153_power_cut_en(tp, false);
1362 static int rtl_ops_init(struct r8152 *tp)
1364 struct rtl_ops *ops = &tp->rtl_ops;
1367 switch (tp->version) {
1371 ops->init = r8152b_init;
1372 ops->enable = rtl8152_enable;
1373 ops->disable = rtl8152_disable;
1374 ops->up = rtl8152_up;
1375 ops->down = rtl8152_down;
1376 ops->unload = rtl8152_unload;
1383 ops->init = r8153_init;
1384 ops->enable = rtl8153_enable;
1385 ops->disable = rtl8153_disable;
1386 ops->up = rtl8153_up;
1387 ops->down = rtl8153_down;
1388 ops->unload = rtl8153_unload;
1393 ops->init = r8153b_init;
1394 ops->enable = rtl8153_enable;
1395 ops->disable = rtl8153_disable;
1396 ops->up = rtl8153b_up;
1397 ops->down = rtl8153b_down;
1402 printf("r8152 Unknown Device\n");
1409 static int r8152_init_common(struct r8152 *tp)
1415 debug("** %s()\n", __func__);
1418 speed = rtl8152_get_speed(tp);
1420 link_detected = speed & LINK_STATUS;
1421 if (!link_detected) {
1423 printf("Waiting for Ethernet connection... ");
1424 mdelay(TIMEOUT_RESOLUTION);
1425 timeout += TIMEOUT_RESOLUTION;
1427 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
1428 if (link_detected) {
1429 tp->rtl_ops.enable(tp);
1434 printf("unable to connect.\n");
1440 static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
1442 struct usb_device *udev = ueth->pusb_dev;
1443 u32 opts1, opts2 = 0;
1446 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg,
1447 PKTSIZE + sizeof(struct tx_desc));
1448 struct tx_desc *tx_desc = (struct tx_desc *)msg;
1450 debug("** %s(), len %d\n", __func__, length);
1452 opts1 = length | TX_FS | TX_LS;
1454 tx_desc->opts2 = cpu_to_le32(opts2);
1455 tx_desc->opts1 = cpu_to_le32(opts1);
1457 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
1459 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out),
1460 (void *)msg, length + sizeof(struct tx_desc),
1461 &actual_len, USB_BULK_SEND_TIMEOUT);
1462 debug("Tx: len = %zu, actual = %u, err = %d\n",
1463 length + sizeof(struct tx_desc), actual_len, err);
1468 #ifndef CONFIG_DM_ETH
1469 static int r8152_init(struct eth_device *eth, struct bd_info *bd)
1471 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1472 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1474 return r8152_init_common(tp);
1477 static int r8152_send(struct eth_device *eth, void *packet, int length)
1479 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1481 return r8152_send_common(dev, packet, length);
1484 static int r8152_recv(struct eth_device *eth)
1486 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1488 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ);
1489 unsigned char *pkt_ptr;
1494 u32 bytes_process = 0;
1495 struct rx_desc *rx_desc;
1497 debug("** %s()\n", __func__);
1499 err = usb_bulk_msg(dev->pusb_dev,
1500 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
1504 USB_BULK_RECV_TIMEOUT);
1505 debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
1508 debug("Rx: failed to receive\n");
1511 if (actual_len > RTL8152_AGG_BUF_SZ) {
1512 debug("Rx: received too many bytes %d\n", actual_len);
1516 while (bytes_process < actual_len) {
1517 rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
1518 pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
1520 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1521 packet_len -= CRC_SIZE;
1523 net_process_received_packet(pkt_ptr, packet_len);
1526 (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
1528 if (bytes_process % 8)
1529 bytes_process = bytes_process + 8 - (bytes_process % 8);
1535 static void r8152_halt(struct eth_device *eth)
1537 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1538 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1540 debug("** %s()\n", __func__);
1542 tp->rtl_ops.disable(tp);
1545 static int r8152_write_hwaddr(struct eth_device *eth)
1547 struct ueth_data *dev = (struct ueth_data *)eth->priv;
1548 struct r8152 *tp = (struct r8152 *)dev->dev_priv;
1550 unsigned char enetaddr[8] = {0};
1552 memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
1554 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1555 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1556 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1558 debug("MAC %pM\n", eth->enetaddr);
1562 void r8152_eth_before_probe(void)
1567 /* Probe to see if a new device is actually an realtek device */
1568 int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
1569 struct ueth_data *ss)
1571 struct usb_interface *iface;
1572 struct usb_interface_descriptor *iface_desc;
1573 int ep_in_found = 0, ep_out_found = 0;
1577 /* let's examine the device now */
1578 iface = &dev->config.if_desc[ifnum];
1579 iface_desc = &dev->config.if_desc[ifnum].desc;
1581 for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
1582 if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
1583 dev->descriptor.idProduct == r8152_dongles[i].product)
1584 /* Found a supported dongle */
1588 if (i == ARRAY_SIZE(r8152_dongles))
1591 memset(ss, 0, sizeof(struct ueth_data));
1593 /* At this point, we know we've got a live one */
1594 debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
1595 dev->descriptor.idVendor, dev->descriptor.idProduct);
1597 /* Initialize the ueth_data structure with some useful info */
1600 ss->subclass = iface_desc->bInterfaceSubClass;
1601 ss->protocol = iface_desc->bInterfaceProtocol;
1603 /* alloc driver private */
1604 ss->dev_priv = calloc(1, sizeof(struct r8152));
1610 * We are expecting a minimum of 3 endpoints - in, out (bulk), and
1611 * int. We will ignore any others.
1613 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
1614 /* is it an BULK endpoint? */
1615 if ((iface->ep_desc[i].bmAttributes &
1616 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
1617 u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
1619 if (ep_addr & USB_DIR_IN) {
1621 ss->ep_in = ep_addr &
1622 USB_ENDPOINT_NUMBER_MASK;
1626 if (!ep_out_found) {
1627 ss->ep_out = ep_addr &
1628 USB_ENDPOINT_NUMBER_MASK;
1634 /* is it an interrupt endpoint? */
1635 if ((iface->ep_desc[i].bmAttributes &
1636 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
1637 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
1638 USB_ENDPOINT_NUMBER_MASK;
1639 ss->irqinterval = iface->ep_desc[i].bInterval;
1643 debug("Endpoints In %d Out %d Int %d\n",
1644 ss->ep_in, ss->ep_out, ss->ep_int);
1646 /* Do some basic sanity checks, and bail if we find a problem */
1647 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
1648 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
1649 debug("Problems with device\n");
1653 dev->privptr = (void *)ss;
1659 r8152b_get_version(tp);
1661 if (rtl_ops_init(tp))
1664 tp->rtl_ops.init(tp);
1667 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1668 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1674 int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
1675 struct eth_device *eth)
1678 debug("%s: missing parameter.\n", __func__);
1682 sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
1683 eth->init = r8152_init;
1684 eth->send = r8152_send;
1685 eth->recv = r8152_recv;
1686 eth->halt = r8152_halt;
1687 eth->write_hwaddr = r8152_write_hwaddr;
1690 /* Get the MAC address */
1691 if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
1694 debug("MAC %pM\n", eth->enetaddr);
1697 #endif /* !CONFIG_DM_ETH */
1699 #ifdef CONFIG_DM_ETH
1700 static int r8152_eth_start(struct udevice *dev)
1702 struct r8152 *tp = dev_get_priv(dev);
1704 debug("** %s (%d)\n", __func__, __LINE__);
1706 return r8152_init_common(tp);
1709 void r8152_eth_stop(struct udevice *dev)
1711 struct r8152 *tp = dev_get_priv(dev);
1713 debug("** %s (%d)\n", __func__, __LINE__);
1715 tp->rtl_ops.disable(tp);
1718 int r8152_eth_send(struct udevice *dev, void *packet, int length)
1720 struct r8152 *tp = dev_get_priv(dev);
1722 return r8152_send_common(&tp->ueth, packet, length);
1725 int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1727 struct r8152 *tp = dev_get_priv(dev);
1728 struct ueth_data *ueth = &tp->ueth;
1731 struct rx_desc *rx_desc;
1734 len = usb_ether_get_rx_bytes(ueth, &ptr);
1735 debug("%s: first try, len=%d\n", __func__, len);
1737 if (!(flags & ETH_RECV_CHECK_DEVICE))
1739 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ);
1743 len = usb_ether_get_rx_bytes(ueth, &ptr);
1744 debug("%s: second try, len=%d\n", __func__, len);
1747 rx_desc = (struct rx_desc *)ptr;
1748 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1749 packet_len -= CRC_SIZE;
1751 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) {
1752 debug("Rx: too large packet: %d\n", packet_len);
1756 *packetp = ptr + sizeof(struct rx_desc);
1760 usb_ether_advance_rxbuf(ueth, -1);
1764 static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1766 struct r8152 *tp = dev_get_priv(dev);
1768 packet_len += sizeof(struct rx_desc) + CRC_SIZE;
1769 packet_len = ALIGN(packet_len, 8);
1770 usb_ether_advance_rxbuf(&tp->ueth, packet_len);
1775 static int r8152_write_hwaddr(struct udevice *dev)
1777 struct eth_pdata *pdata = dev_get_platdata(dev);
1778 struct r8152 *tp = dev_get_priv(dev);
1780 unsigned char enetaddr[8] = { 0 };
1782 debug("** %s (%d)\n", __func__, __LINE__);
1783 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN);
1785 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1786 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1787 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1789 debug("MAC %pM\n", pdata->enetaddr);
1793 int r8152_read_rom_hwaddr(struct udevice *dev)
1795 struct eth_pdata *pdata = dev_get_platdata(dev);
1796 struct r8152 *tp = dev_get_priv(dev);
1798 debug("** %s (%d)\n", __func__, __LINE__);
1799 r8152_read_mac(tp, pdata->enetaddr);
1803 static int r8152_eth_probe(struct udevice *dev)
1805 struct usb_device *udev = dev_get_parent_priv(dev);
1806 struct eth_pdata *pdata = dev_get_platdata(dev);
1807 struct r8152 *tp = dev_get_priv(dev);
1808 struct ueth_data *ueth = &tp->ueth;
1812 r8152_read_mac(tp, pdata->enetaddr);
1814 r8152b_get_version(tp);
1816 ret = rtl_ops_init(tp);
1820 tp->rtl_ops.init(tp);
1823 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1824 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1827 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ);
1830 static const struct eth_ops r8152_eth_ops = {
1831 .start = r8152_eth_start,
1832 .send = r8152_eth_send,
1833 .recv = r8152_eth_recv,
1834 .free_pkt = r8152_free_pkt,
1835 .stop = r8152_eth_stop,
1836 .write_hwaddr = r8152_write_hwaddr,
1837 .read_rom_hwaddr = r8152_read_rom_hwaddr,
1840 U_BOOT_DRIVER(r8152_eth) = {
1841 .name = "r8152_eth",
1843 .probe = r8152_eth_probe,
1844 .ops = &r8152_eth_ops,
1845 .priv_auto = sizeof(struct r8152),
1846 .plat_auto = sizeof(struct eth_pdata),
1849 static const struct usb_device_id r8152_eth_id_table[] = {
1851 { USB_DEVICE(0x0bda, 0x8050) },
1852 { USB_DEVICE(0x0bda, 0x8152) },
1853 { USB_DEVICE(0x0bda, 0x8153) },
1856 { USB_DEVICE(0x04e8, 0xa101) },
1859 { USB_DEVICE(0x17ef, 0x304f) },
1860 { USB_DEVICE(0x17ef, 0x3052) },
1861 { USB_DEVICE(0x17ef, 0x3054) },
1862 { USB_DEVICE(0x17ef, 0x3057) },
1863 { USB_DEVICE(0x17ef, 0x7205) },
1864 { USB_DEVICE(0x17ef, 0x720a) },
1865 { USB_DEVICE(0x17ef, 0x720b) },
1866 { USB_DEVICE(0x17ef, 0x720c) },
1869 { USB_DEVICE(0x2357, 0x0601) },
1872 { USB_DEVICE(0x0955, 0x09ff) },
1874 { } /* Terminating entry */
1877 U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
1878 #endif /* CONFIG_DM_ETH */