1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
15 #include <linux/delay.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include "usb_ether.h"
21 struct r8152_version {
23 unsigned short version;
27 static const struct r8152_version r8152_versions[] = {
28 { 0x4c00, RTL_VER_01, 0 },
29 { 0x4c10, RTL_VER_02, 0 },
30 { 0x5c00, RTL_VER_03, 1 },
31 { 0x5c10, RTL_VER_04, 1 },
32 { 0x5c20, RTL_VER_05, 1 },
33 { 0x5c30, RTL_VER_06, 1 },
34 { 0x4800, RTL_VER_07, 0 },
35 { 0x6000, RTL_VER_08, 1 },
36 { 0x6010, RTL_VER_09, 1 },
40 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
42 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
45 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
46 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
47 value, index, tmp, size, 500);
48 memcpy(data, tmp, size);
53 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
55 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
57 memcpy(tmp, data, size);
58 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
59 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
60 value, index, tmp, size, 500);
63 int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
70 /* both size and index must be 4 bytes align */
71 if ((size & 3) || !size || (index & 3) || !data)
74 if (index + size > 0xffff)
78 txsize = min(size, burst_size);
79 ret = get_registers(tp, index, type, txsize, data);
91 int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
92 u16 size, void *data, u16 type)
95 u16 byteen_start, byteen_end, byte_en_to_hw;
99 /* both size and index must be 4 bytes align */
100 if ((size & 3) || !size || (index & 3) || !data)
103 if (index + size > 0xffff)
106 byteen_start = byteen & BYTE_EN_START_MASK;
107 byteen_end = byteen & BYTE_EN_END_MASK;
109 byte_en_to_hw = byteen_start | (byteen_start << 4);
110 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
122 txsize = min(size, burst_size);
124 ret = set_registers(tp, index,
125 type | BYTE_EN_DWORD,
135 byte_en_to_hw = byteen_end | (byteen_end >> 4);
136 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
144 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
146 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
149 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
151 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
154 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
156 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
159 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
161 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
164 u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
168 generic_ocp_read(tp, index, sizeof(data), &data, type);
170 return __le32_to_cpu(data);
173 void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
175 __le32 tmp = __cpu_to_le32(data);
177 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
180 u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
184 u8 shift = index & 2;
188 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
190 data = __le32_to_cpu(tmp);
191 data >>= (shift * 8);
197 void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
201 u16 byen = BYTE_EN_WORD;
202 u8 shift = index & 2;
208 mask <<= (shift * 8);
209 data <<= (shift * 8);
213 tmp = __cpu_to_le32(data);
215 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
218 u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
222 u8 shift = index & 3;
226 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
228 data = __le32_to_cpu(tmp);
229 data >>= (shift * 8);
235 void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
239 u16 byen = BYTE_EN_BYTE;
240 u8 shift = index & 3;
246 mask <<= (shift * 8);
247 data <<= (shift * 8);
251 tmp = __cpu_to_le32(data);
253 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
256 u16 ocp_reg_read(struct r8152 *tp, u16 addr)
258 u16 ocp_base, ocp_index;
260 ocp_base = addr & 0xf000;
261 if (ocp_base != tp->ocp_base) {
262 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
263 tp->ocp_base = ocp_base;
266 ocp_index = (addr & 0x0fff) | 0xb000;
267 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
270 void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
272 u16 ocp_base, ocp_index;
274 ocp_base = addr & 0xf000;
275 if (ocp_base != tp->ocp_base) {
276 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
277 tp->ocp_base = ocp_base;
280 ocp_index = (addr & 0x0fff) | 0xb000;
281 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
284 static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
286 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
289 static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
291 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
294 void sram_write(struct r8152 *tp, u16 addr, u16 data)
296 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
297 ocp_reg_write(tp, OCP_SRAM_DATA, data);
300 static u16 sram_read(struct r8152 *tp, u16 addr)
302 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
303 return ocp_reg_read(tp, OCP_SRAM_DATA);
306 int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
307 const u32 mask, bool set, unsigned int timeout)
313 val = ocp_reg_read(tp, index);
315 val = ocp_read_dword(tp, type, index);
320 if ((val & mask) == mask)
326 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
327 __func__, index, mask, timeout);
332 static void r8152b_reset_packet_filter(struct r8152 *tp)
336 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
337 ocp_data &= ~FMC_FCR_MCU_EN;
338 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
339 ocp_data |= FMC_FCR_MCU_EN;
340 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
343 static void rtl8152_wait_fifo_empty(struct r8152 *tp)
347 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
348 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
350 debug("Timeout waiting for FIFO empty\n");
352 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
353 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
355 debug("Timeout waiting for TX empty\n");
358 static void rtl8152_nic_reset(struct r8152 *tp)
363 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
364 ocp_data |= BIST_CTRL_SW_RESET;
365 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
367 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
368 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
370 debug("Timeout waiting for NIC reset\n");
373 static u8 rtl8152_get_speed(struct r8152 *tp)
375 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
378 static void rtl_set_eee_plus(struct r8152 *tp)
382 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
383 ocp_data &= ~EEEP_CR_EEEP_TX;
384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
387 static void rxdy_gated_en(struct r8152 *tp, bool enable)
391 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
393 ocp_data |= RXDY_GATED_EN;
395 ocp_data &= ~RXDY_GATED_EN;
396 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
399 static void rtl8152_set_rx_mode(struct r8152 *tp)
407 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
409 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
410 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
411 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
414 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
416 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
417 OWN_UPDATE | OWN_CLEAR);
420 static int rtl_enable(struct r8152 *tp)
424 r8152b_reset_packet_filter(tp);
426 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
427 ocp_data |= PLA_CR_RE | PLA_CR_TE;
428 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
430 switch (tp->version) {
433 r8153b_rx_agg_chg_indicate(tp);
439 rxdy_gated_en(tp, false);
441 rtl8152_set_rx_mode(tp);
446 static int rtl8152_enable(struct r8152 *tp)
448 rtl_set_eee_plus(tp);
450 return rtl_enable(tp);
453 static void r8153_set_rx_early_timeout(struct r8152 *tp)
455 u32 ocp_data = tp->coalesce / 8;
457 switch (tp->version) {
462 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
468 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
469 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 1264ns.
471 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
472 RX_AUXILIARY_TIMER / 8);
473 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
478 debug("** %s Invalid Device\n", __func__);
483 static void r8153_set_rx_early_size(struct r8152 *tp)
485 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS -
486 sizeof(struct rx_desc));
488 switch (tp->version) {
493 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
499 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
504 debug("** %s Invalid Device\n", __func__);
509 static int rtl8153_enable(struct r8152 *tp)
511 rtl_set_eee_plus(tp);
512 r8153_set_rx_early_timeout(tp);
513 r8153_set_rx_early_size(tp);
515 return rtl_enable(tp);
518 static void rtl_disable(struct r8152 *tp)
522 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
523 ocp_data &= ~RCR_ACPT_ALL;
524 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
526 rxdy_gated_en(tp, true);
528 rtl8152_wait_fifo_empty(tp);
529 rtl8152_nic_reset(tp);
532 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
536 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
538 ocp_data |= POWER_CUT;
540 ocp_data &= ~POWER_CUT;
541 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
543 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
544 ocp_data &= ~RESUME_INDICATE;
545 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
548 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
552 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
554 ocp_data |= CPCR_RX_VLAN;
556 ocp_data &= ~CPCR_RX_VLAN;
557 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
560 static void r8153_u1u2en(struct r8152 *tp, bool enable)
565 memset(u1u2, 0xff, sizeof(u1u2));
567 memset(u1u2, 0x00, sizeof(u1u2));
569 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
572 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
576 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
578 ocp_data |= LPM_U1U2_EN;
580 ocp_data &= ~LPM_U1U2_EN;
582 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
585 static void r8153_u2p3en(struct r8152 *tp, bool enable)
589 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
590 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
591 ocp_data |= U2P3_ENABLE;
593 ocp_data &= ~U2P3_ENABLE;
594 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
597 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
601 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
603 ocp_data |= PWR_EN | PHASE2_EN;
605 ocp_data &= ~(PWR_EN | PHASE2_EN);
606 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
608 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
609 ocp_data &= ~PCUT_STATUS;
610 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
613 static void rtl_reset_bmu(struct r8152 *tp)
617 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
618 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
619 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
620 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
621 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
624 static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
627 unsigned char enetaddr[8] = {0};
629 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
633 memcpy(macaddr, enetaddr, ETH_ALEN);
637 static void r8152b_disable_aldps(struct r8152 *tp)
639 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
643 static void r8152b_enable_aldps(struct r8152 *tp)
645 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
646 LINKENA | DIS_SDSAVE);
649 static void rtl8152_disable(struct r8152 *tp)
651 r8152b_disable_aldps(tp);
653 r8152b_enable_aldps(tp);
656 static void r8152b_hw_phy_cfg(struct r8152 *tp)
660 data = r8152_mdio_read(tp, MII_BMCR);
661 if (data & BMCR_PDOWN) {
663 r8152_mdio_write(tp, MII_BMCR, data);
669 static void rtl8152_reinit_ll(struct r8152 *tp)
674 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
675 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
677 debug("Timeout waiting for link list ready\n");
679 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
680 ocp_data |= RE_INIT_LL;
681 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
683 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
684 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
686 debug("Timeout waiting for link list ready\n");
689 static void r8152b_exit_oob(struct r8152 *tp)
693 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
694 ocp_data &= ~RCR_ACPT_ALL;
695 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
697 rxdy_gated_en(tp, true);
698 r8152b_hw_phy_cfg(tp);
700 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
701 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
703 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
704 ocp_data &= ~NOW_IS_OOB;
705 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
707 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
708 ocp_data &= ~MCU_BORW_EN;
709 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
711 rtl8152_reinit_ll(tp);
712 rtl8152_nic_reset(tp);
714 /* rx share fifo credit full threshold */
715 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
717 if (tp->udev->speed == USB_SPEED_FULL ||
718 tp->udev->speed == USB_SPEED_LOW) {
719 /* rx share fifo credit near full threshold */
720 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
722 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
725 /* rx share fifo credit near full threshold */
726 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
728 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
732 /* TX share fifo free credit full threshold */
733 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
735 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
736 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
737 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
738 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
740 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
742 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
743 ocp_data |= TCR0_AUTO_FIFO;
744 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
747 static void r8152b_enter_oob(struct r8152 *tp)
751 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
752 ocp_data &= ~NOW_IS_OOB;
753 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
755 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
756 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
757 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
761 rtl8152_reinit_ll(tp);
763 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
765 rtl_rx_vlan_en(tp, false);
767 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
768 ocp_data |= ALDPS_PROXY_MODE;
769 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
771 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
772 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
773 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
775 rxdy_gated_en(tp, false);
777 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
778 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
779 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
782 static void r8153_hw_phy_cfg(struct r8152 *tp)
787 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
788 tp->version == RTL_VER_05)
789 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
791 data = r8152_mdio_read(tp, MII_BMCR);
792 if (data & BMCR_PDOWN) {
794 r8152_mdio_write(tp, MII_BMCR, data);
799 if (tp->version == RTL_VER_03) {
800 data = ocp_reg_read(tp, OCP_EEE_CFG);
801 data &= ~CTAP_SHORT_EN;
802 ocp_reg_write(tp, OCP_EEE_CFG, data);
805 data = ocp_reg_read(tp, OCP_POWER_CFG);
806 data |= EEE_CLKDIV_EN;
807 ocp_reg_write(tp, OCP_POWER_CFG, data);
809 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
810 data |= EN_10M_BGOFF;
811 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
812 data = ocp_reg_read(tp, OCP_POWER_CFG);
813 data |= EN_10M_PLLOFF;
814 ocp_reg_write(tp, OCP_POWER_CFG, data);
815 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
817 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
818 ocp_data |= PFM_PWM_SWITCH;
819 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
821 /* Enable LPF corner auto tune */
822 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
824 /* Adjust 10M Amplitude */
825 sram_write(tp, SRAM_10M_AMP1, 0x00af);
826 sram_write(tp, SRAM_10M_AMP2, 0x0208);
829 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
833 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
834 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
835 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
836 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
841 static void r8153b_hw_phy_cfg(struct r8152 *tp)
846 data = r8152_mdio_read(tp, MII_BMCR);
847 if (data & BMCR_PDOWN) {
849 r8152_mdio_write(tp, MII_BMCR, data);
852 /* U1/U2/L1 idle timer. 500 us */
853 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
857 data = sram_read(tp, SRAM_GREEN_CFG);
859 sram_write(tp, SRAM_GREEN_CFG, data);
860 data = ocp_reg_read(tp, OCP_NCTL_CFG);
861 data |= PGA_RETURN_EN;
862 ocp_reg_write(tp, OCP_NCTL_CFG, data);
864 /* ADC Bias Calibration:
865 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
866 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
869 ocp_data = r8152_efuse_read(tp, 0x7d);
870 ocp_data = ((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7);
871 if (ocp_data != 0xffff)
872 ocp_reg_write(tp, OCP_ADC_IOFFSET, ocp_data);
874 /* ups mode tx-link-pulse timing adjustment:
875 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
876 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
878 ocp_data = ocp_reg_read(tp, 0xc426);
883 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
884 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
885 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
886 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
889 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
890 ocp_data |= PFM_PWM_SWITCH;
891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
894 static void r8153_first_init(struct r8152 *tp)
898 rxdy_gated_en(tp, true);
900 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
901 ocp_data &= ~RCR_ACPT_ALL;
902 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
904 r8153_hw_phy_cfg(tp);
906 rtl8152_nic_reset(tp);
909 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
910 ocp_data &= ~NOW_IS_OOB;
911 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
913 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
914 ocp_data &= ~MCU_BORW_EN;
915 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
917 rtl8152_reinit_ll(tp);
919 rtl_rx_vlan_en(tp, false);
921 ocp_data = RTL8153_RMS;
922 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
923 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
925 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
926 ocp_data |= TCR0_AUTO_FIFO;
927 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
929 rtl8152_nic_reset(tp);
931 /* rx share fifo credit full threshold */
932 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
934 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
935 /* TX share fifo free credit full threshold */
936 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
939 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
941 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
942 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
945 static void r8153_enter_oob(struct r8152 *tp)
949 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
950 ocp_data &= ~NOW_IS_OOB;
951 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
956 rtl8152_reinit_ll(tp);
958 ocp_data = RTL8153_RMS;
959 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
961 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
962 ocp_data &= ~TEREDO_WAKE_MASK;
963 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
965 rtl_rx_vlan_en(tp, false);
967 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
968 ocp_data |= ALDPS_PROXY_MODE;
969 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
971 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
972 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
973 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
975 rxdy_gated_en(tp, false);
977 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
978 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
979 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
982 static void r8153_disable_aldps(struct r8152 *tp)
986 data = ocp_reg_read(tp, OCP_POWER_CFG);
988 ocp_reg_write(tp, OCP_POWER_CFG, data);
992 static void rtl8153_disable(struct r8152 *tp)
994 r8153_disable_aldps(tp);
999 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
1001 u16 bmcr, anar, gbcr;
1003 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1004 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1005 ADVERTISE_100HALF | ADVERTISE_100FULL);
1006 if (tp->supports_gmii) {
1007 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
1008 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1013 if (autoneg == AUTONEG_DISABLE) {
1014 if (speed == SPEED_10) {
1016 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1017 } else if (speed == SPEED_100) {
1018 bmcr = BMCR_SPEED100;
1019 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1020 } else if (speed == SPEED_1000 && tp->supports_gmii) {
1021 bmcr = BMCR_SPEED1000;
1022 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1027 if (duplex == DUPLEX_FULL)
1028 bmcr |= BMCR_FULLDPLX;
1030 if (speed == SPEED_10) {
1031 if (duplex == DUPLEX_FULL)
1032 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1034 anar |= ADVERTISE_10HALF;
1035 } else if (speed == SPEED_100) {
1036 if (duplex == DUPLEX_FULL) {
1037 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1038 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1040 anar |= ADVERTISE_10HALF;
1041 anar |= ADVERTISE_100HALF;
1043 } else if (speed == SPEED_1000 && tp->supports_gmii) {
1044 if (duplex == DUPLEX_FULL) {
1045 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1046 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1047 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1049 anar |= ADVERTISE_10HALF;
1050 anar |= ADVERTISE_100HALF;
1051 gbcr |= ADVERTISE_1000HALF;
1057 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1060 if (tp->supports_gmii)
1061 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
1063 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1064 r8152_mdio_write(tp, MII_BMCR, bmcr);
1069 static void rtl8152_up(struct r8152 *tp)
1071 r8152b_disable_aldps(tp);
1072 r8152b_exit_oob(tp);
1073 r8152b_enable_aldps(tp);
1076 static void rtl8152_down(struct r8152 *tp)
1078 r8152_power_cut_en(tp, false);
1079 r8152b_disable_aldps(tp);
1080 r8152b_enter_oob(tp);
1081 r8152b_enable_aldps(tp);
1084 static void rtl8153_up(struct r8152 *tp)
1086 r8153_u1u2en(tp, false);
1087 r8153_disable_aldps(tp);
1088 r8153_first_init(tp);
1089 r8153_u2p3en(tp, false);
1092 static void rtl8153_down(struct r8152 *tp)
1094 r8153_u1u2en(tp, false);
1095 r8153_u2p3en(tp, false);
1096 r8153_power_cut_en(tp, false);
1097 r8153_disable_aldps(tp);
1098 r8153_enter_oob(tp);
1101 static void rtl8153b_up(struct r8152 *tp)
1103 r8153_first_init(tp);
1106 static void rtl8153b_down(struct r8152 *tp)
1108 r8153_enter_oob(tp);
1111 static void r8152b_get_version(struct r8152 *tp)
1117 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
1118 tcr = (u16)(ocp_data & VERSION_MASK);
1120 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
1121 if (tcr == r8152_versions[i].tcr) {
1122 /* Found a supported version */
1123 tp->version = r8152_versions[i].version;
1124 tp->supports_gmii = r8152_versions[i].gmii;
1129 if (tp->version == RTL_VER_UNKNOWN)
1130 debug("r8152 Unknown tcr version 0x%04x\n", tcr);
1133 static void r8152b_enable_fc(struct r8152 *tp)
1136 anar = r8152_mdio_read(tp, MII_ADVERTISE);
1137 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1138 r8152_mdio_write(tp, MII_ADVERTISE, anar);
1141 static void rtl_tally_reset(struct r8152 *tp)
1145 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
1146 ocp_data |= TALLY_RESET;
1147 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
1150 static void r8152b_init(struct r8152 *tp)
1154 r8152b_disable_aldps(tp);
1156 if (tp->version == RTL_VER_01) {
1157 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1158 ocp_data &= ~LED_MODE_MASK;
1159 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1162 r8152_power_cut_en(tp, false);
1164 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1165 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
1166 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1167 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
1168 ocp_data &= ~MCU_CLK_RATIO_MASK;
1169 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
1170 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
1171 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
1172 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
1173 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
1175 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
1176 ocp_data |= BIT(15);
1177 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1178 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
1179 ocp_data &= ~BIT(15);
1180 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
1182 r8152b_enable_fc(tp);
1183 rtl_tally_reset(tp);
1185 /* enable rx aggregation */
1186 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1188 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1189 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1192 static void r8153_init(struct r8152 *tp)
1197 r8153_disable_aldps(tp);
1198 r8153_u1u2en(tp, false);
1200 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1201 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1203 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1204 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1205 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1211 r8153_u2p3en(tp, false);
1213 if (tp->version == RTL_VER_04) {
1214 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
1215 ocp_data &= ~pwd_dn_scale_mask;
1216 ocp_data |= pwd_dn_scale(96);
1217 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
1219 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
1220 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
1221 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
1222 } else if (tp->version == RTL_VER_05) {
1223 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
1224 ocp_data &= ~ECM_ALDPS;
1225 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
1227 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1228 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1229 ocp_data &= ~DYNAMIC_BURST;
1231 ocp_data |= DYNAMIC_BURST;
1232 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1233 } else if (tp->version == RTL_VER_06) {
1234 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
1235 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
1236 ocp_data &= ~DYNAMIC_BURST;
1238 ocp_data |= DYNAMIC_BURST;
1239 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
1242 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
1243 ocp_data |= EP4_FULL_FC;
1244 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
1246 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
1247 ocp_data &= ~TIMER11_EN;
1248 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
1250 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
1251 ocp_data &= ~LED_MODE_MASK;
1252 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
1254 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
1255 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
1256 ocp_data |= LPM_TIMER_500MS;
1258 ocp_data |= LPM_TIMER_500US;
1259 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
1261 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
1262 ocp_data &= ~SEN_VAL_MASK;
1263 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
1264 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
1266 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1268 r8153_power_cut_en(tp, false);
1270 r8152b_enable_fc(tp);
1271 rtl_tally_reset(tp);
1274 static void r8153b_init(struct r8152 *tp)
1279 r8153_disable_aldps(tp);
1280 r8153b_u1u2en(tp, false);
1282 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
1283 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
1285 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
1286 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
1287 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
1293 r8153_u2p3en(tp, false);
1295 /* MSC timer = 0xfff * 8ms = 32760 ms */
1296 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
1298 r8153_power_cut_en(tp, false);
1300 /* MAC clock speed down */
1301 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
1302 ocp_data |= MAC_CLK_SPDWN_EN;
1303 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
1305 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1306 ocp_data &= ~PLA_MCU_SPDWN_EN;
1307 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
1309 if (tp->version == RTL_VER_09) {
1310 /* Disable Test IO for 32QFN */
1311 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
1312 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1313 ocp_data |= TEST_IO_OFF;
1314 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1318 /* rx aggregation */
1319 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1320 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1321 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1323 rtl_tally_reset(tp);
1324 r8153b_hw_phy_cfg(tp);
1325 r8152b_enable_fc(tp);
1328 static void rtl8152_unload(struct r8152 *tp)
1330 if (tp->version != RTL_VER_01)
1331 r8152_power_cut_en(tp, true);
1334 static void rtl8153_unload(struct r8152 *tp)
1336 r8153_power_cut_en(tp, false);
1339 static int rtl_ops_init(struct r8152 *tp)
1341 struct rtl_ops *ops = &tp->rtl_ops;
1344 switch (tp->version) {
1348 ops->init = r8152b_init;
1349 ops->enable = rtl8152_enable;
1350 ops->disable = rtl8152_disable;
1351 ops->up = rtl8152_up;
1352 ops->down = rtl8152_down;
1353 ops->unload = rtl8152_unload;
1360 ops->init = r8153_init;
1361 ops->enable = rtl8153_enable;
1362 ops->disable = rtl8153_disable;
1363 ops->up = rtl8153_up;
1364 ops->down = rtl8153_down;
1365 ops->unload = rtl8153_unload;
1370 ops->init = r8153b_init;
1371 ops->enable = rtl8153_enable;
1372 ops->disable = rtl8153_disable;
1373 ops->up = rtl8153b_up;
1374 ops->down = rtl8153b_down;
1379 printf("r8152 Unknown Device\n");
1386 static int r8152_init_common(struct r8152 *tp)
1392 debug("** %s()\n", __func__);
1395 speed = rtl8152_get_speed(tp);
1397 link_detected = speed & LINK_STATUS;
1398 if (!link_detected) {
1400 printf("Waiting for Ethernet connection... ");
1401 mdelay(TIMEOUT_RESOLUTION);
1402 timeout += TIMEOUT_RESOLUTION;
1404 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
1405 if (link_detected) {
1406 tp->rtl_ops.enable(tp);
1411 printf("unable to connect.\n");
1417 static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
1419 struct usb_device *udev = ueth->pusb_dev;
1420 u32 opts1, opts2 = 0;
1423 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg,
1424 PKTSIZE + sizeof(struct tx_desc));
1425 struct tx_desc *tx_desc = (struct tx_desc *)msg;
1427 debug("** %s(), len %d\n", __func__, length);
1429 opts1 = length | TX_FS | TX_LS;
1431 tx_desc->opts2 = cpu_to_le32(opts2);
1432 tx_desc->opts1 = cpu_to_le32(opts1);
1434 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
1436 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out),
1437 (void *)msg, length + sizeof(struct tx_desc),
1438 &actual_len, USB_BULK_SEND_TIMEOUT);
1439 debug("Tx: len = %zu, actual = %u, err = %d\n",
1440 length + sizeof(struct tx_desc), actual_len, err);
1445 static int r8152_eth_start(struct udevice *dev)
1447 struct r8152 *tp = dev_get_priv(dev);
1449 debug("** %s (%d)\n", __func__, __LINE__);
1451 return r8152_init_common(tp);
1454 void r8152_eth_stop(struct udevice *dev)
1456 struct r8152 *tp = dev_get_priv(dev);
1458 debug("** %s (%d)\n", __func__, __LINE__);
1460 tp->rtl_ops.disable(tp);
1463 int r8152_eth_send(struct udevice *dev, void *packet, int length)
1465 struct r8152 *tp = dev_get_priv(dev);
1467 return r8152_send_common(&tp->ueth, packet, length);
1470 int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1472 struct r8152 *tp = dev_get_priv(dev);
1473 struct ueth_data *ueth = &tp->ueth;
1476 struct rx_desc *rx_desc;
1479 len = usb_ether_get_rx_bytes(ueth, &ptr);
1480 debug("%s: first try, len=%d\n", __func__, len);
1482 if (!(flags & ETH_RECV_CHECK_DEVICE))
1484 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ);
1488 len = usb_ether_get_rx_bytes(ueth, &ptr);
1489 debug("%s: second try, len=%d\n", __func__, len);
1492 rx_desc = (struct rx_desc *)ptr;
1493 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1494 packet_len -= CRC_SIZE;
1496 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) {
1497 debug("Rx: too large packet: %d\n", packet_len);
1501 *packetp = ptr + sizeof(struct rx_desc);
1505 usb_ether_advance_rxbuf(ueth, -1);
1509 static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
1511 struct r8152 *tp = dev_get_priv(dev);
1513 packet_len += sizeof(struct rx_desc) + CRC_SIZE;
1514 packet_len = ALIGN(packet_len, 8);
1515 usb_ether_advance_rxbuf(&tp->ueth, packet_len);
1520 static int r8152_write_hwaddr(struct udevice *dev)
1522 struct eth_pdata *pdata = dev_get_plat(dev);
1523 struct r8152 *tp = dev_get_priv(dev);
1525 unsigned char enetaddr[8] = { 0 };
1527 debug("** %s (%d)\n", __func__, __LINE__);
1528 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN);
1530 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1531 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
1532 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1534 debug("MAC %pM\n", pdata->enetaddr);
1538 int r8152_read_rom_hwaddr(struct udevice *dev)
1540 struct eth_pdata *pdata = dev_get_plat(dev);
1541 struct r8152 *tp = dev_get_priv(dev);
1543 debug("** %s (%d)\n", __func__, __LINE__);
1544 r8152_read_mac(tp, pdata->enetaddr);
1548 static int r8152_eth_probe(struct udevice *dev)
1550 struct usb_device *udev = dev_get_parent_priv(dev);
1551 struct eth_pdata *pdata = dev_get_plat(dev);
1552 struct r8152 *tp = dev_get_priv(dev);
1553 struct ueth_data *ueth = &tp->ueth;
1557 r8152_read_mac(tp, pdata->enetaddr);
1559 r8152b_get_version(tp);
1561 ret = rtl_ops_init(tp);
1565 tp->rtl_ops.init(tp);
1568 rtl8152_set_speed(tp, AUTONEG_ENABLE,
1569 tp->supports_gmii ? SPEED_1000 : SPEED_100,
1572 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ);
1575 static const struct eth_ops r8152_eth_ops = {
1576 .start = r8152_eth_start,
1577 .send = r8152_eth_send,
1578 .recv = r8152_eth_recv,
1579 .free_pkt = r8152_free_pkt,
1580 .stop = r8152_eth_stop,
1581 .write_hwaddr = r8152_write_hwaddr,
1582 .read_rom_hwaddr = r8152_read_rom_hwaddr,
1585 U_BOOT_DRIVER(r8152_eth) = {
1586 .name = "r8152_eth",
1588 .probe = r8152_eth_probe,
1589 .ops = &r8152_eth_ops,
1590 .priv_auto = sizeof(struct r8152),
1591 .plat_auto = sizeof(struct eth_pdata),
1594 static const struct usb_device_id r8152_eth_id_table[] = {
1596 { USB_DEVICE(0x0bda, 0x8050) },
1597 { USB_DEVICE(0x0bda, 0x8152) },
1598 { USB_DEVICE(0x0bda, 0x8153) },
1601 { USB_DEVICE(0x04e8, 0xa101) },
1604 { USB_DEVICE(0x17ef, 0x304f) },
1605 { USB_DEVICE(0x17ef, 0x3052) },
1606 { USB_DEVICE(0x17ef, 0x3054) },
1607 { USB_DEVICE(0x17ef, 0x3057) },
1608 { USB_DEVICE(0x17ef, 0x7205) },
1609 { USB_DEVICE(0x17ef, 0x720a) },
1610 { USB_DEVICE(0x17ef, 0x720b) },
1611 { USB_DEVICE(0x17ef, 0x720c) },
1614 { USB_DEVICE(0x2357, 0x0601) },
1615 { USB_DEVICE(0x2357, 0x0602) },
1618 { USB_DEVICE(0x0955, 0x09ff) },
1620 { } /* Terminating entry */
1623 U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);