drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/gadget.c) and ported
  11  * to uboot.
  12  *
  13  * commit 8e74475b0e : usb: dwc3: gadget: use udc-core's reset notifier
  14  */
  15
  16 #include <cpu_func.h>
  17 #include <log.h>
  18 #include <malloc.h>
  19 #include <dm.h>
  20 #include <dm/device_compat.h>
  21 #include <dm/devres.h>
  22 #include <linux/bug.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/list.h>
  26 #include <linux/printk.h>
  27
  28 #include <linux/usb/ch9.h>
  29 #include <linux/usb/gadget.h>
  30
  31 #include "core.h"
  32 #include "gadget.h"
  33 #include "io.h"
  34
  35 #include "linux-compat.h"
  36
  37 /**
  38  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  39  * @dwc: pointer to our context structure
  40  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  41  *
  42  * Caller should take care of locking. This function will
  43  * return 0 on success or -EINVAL if wrong Test Selector
  44  * is passed
  45  */
  46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  47 {
  48         u32             reg;
  49
  50         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  51         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  52
  53         switch (mode) {
  54         case TEST_J:
  55         case TEST_K:
  56         case TEST_SE0_NAK:
  57         case TEST_PACKET:
  58         case TEST_FORCE_EN:
  59                 reg |= mode << 1;
  60                 break;
  61         default:
  62                 return -EINVAL;
  63         }
  64
  65         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  66
  67         return 0;
  68 }
  69
  70 /**
  71  * dwc3_gadget_get_link_state - Gets current state of USB Link
  72  * @dwc: pointer to our context structure
  73  *
  74  * Caller should take care of locking. This function will
  75  * return the link state on success (>= 0) or -ETIMEDOUT.
  76  */
  77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  78 {
  79         u32             reg;
  80
  81         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  82
  83         return DWC3_DSTS_USBLNKST(reg);
  84 }
  85
  86 /**
  87  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  88  * @dwc: pointer to our context structure
  89  * @state: the state to put link into
  90  *
  91  * Caller should take care of locking. This function will
  92  * return 0 on success or -ETIMEDOUT.
  93  */
  94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  95 {
  96         int             retries = 10000;
  97         u32             reg;
  98
  99         /*
 100          * Wait until device controller is ready. Only applies to 1.94a and
 101          * later RTL.
 102          */
 103         if (dwc->revision >= DWC3_REVISION_194A) {
 104                 while (--retries) {
 105                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 106                         if (reg & DWC3_DSTS_DCNRD)
 107                                 udelay(5);
 108                         else
 109                                 break;
 110                 }
 111
 112                 if (retries <= 0)
 113                         return -ETIMEDOUT;
 114         }
 115
 116         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 117         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 118
 119         /* set requested state */
 120         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 121         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 122
 123         /*
 124          * The following code is racy when called from dwc3_gadget_wakeup,
 125          * and is not needed, at least on newer versions
 126          */
 127         if (dwc->revision >= DWC3_REVISION_194A)
 128                 return 0;
 129
 130         /* wait for a change in DSTS */
 131         retries = 10000;
 132         while (--retries) {
 133                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 134
 135                 if (DWC3_DSTS_USBLNKST(reg) == state)
 136                         return 0;
 137
 138                 udelay(5);
 139         }
 140
 141         dev_vdbg(dwc->dev, "link state change request timed out\n");
 142
 143         return -ETIMEDOUT;
 144 }
 145
 146 /**
 147  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 148  * @dwc: pointer to our context structure
 149  *
 150  * This function will a best effort FIFO allocation in order
 151  * to improve FIFO usage and throughput, while still allowing
 152  * us to enable as many endpoints as possible.
 153  *
 154  * Keep in mind that this operation will be highly dependent
 155  * on the configured size for RAM1 - which contains TxFifo -,
 156  * the amount of endpoints enabled on coreConsultant tool, and
 157  * the width of the Master Bus.
 158  *
 159  * In the ideal world, we would always be able to satisfy the
 160  * following equation:
 161  *
 162  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 163  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 164  *
 165  * Unfortunately, due to many variables that's not always the case.
 166  */
 167 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 168 {
 169         int             last_fifo_depth = 0;
 170         int             fifo_size;
 171         int             mdwidth;
 172         int             num;
 173
 174         if (!dwc->needs_fifo_resize)
 175                 return 0;
 176
 177         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 178
 179         /* MDWIDTH is represented in bits, we need it in bytes */
 180         mdwidth >>= 3;
 181
 182         /*
 183          * FIXME For now we will only allocate 1 wMaxPacketSize space
 184          * for each enabled endpoint, later patches will come to
 185          * improve this algorithm so that we better use the internal
 186          * FIFO space
 187          */
 188         for (num = 0; num < dwc->num_in_eps; num++) {
 189                 /* bit0 indicates direction; 1 means IN ep */
 190                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 191                 int             mult = 1;
 192                 int             tmp;
 193
 194                 if (!(dep->flags & DWC3_EP_ENABLED))
 195                         continue;
 196
 197                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 198                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 199                         mult = 3;
 200
 201                 /*
 202                  * REVISIT: the following assumes we will always have enough
 203                  * space available on the FIFO RAM for all possible use cases.
 204                  * Make sure that's true somehow and change FIFO allocation
 205                  * accordingly.
 206                  *
 207                  * If we have Bulk or Isochronous endpoints, we want
 208                  * them to be able to be very, very fast. So we're giving
 209                  * those endpoints a fifo_size which is enough for 3 full
 210                  * packets
 211                  */
 212                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 213                 tmp += mdwidth;
 214
 215                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 216
 217                 fifo_size |= (last_fifo_depth << 16);
 218
 219                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 220                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 221
 222                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 223
 224                 last_fifo_depth += (fifo_size & 0xffff);
 225         }
 226
 227         return 0;
 228 }
 229
 230 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 231                 int status)
 232 {
 233         struct dwc3                     *dwc = dep->dwc;
 234
 235         if (req->queued) {
 236                 dep->busy_slot++;
 237                 /*
 238                  * Skip LINK TRB. We can't use req->trb and check for
 239                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 240                  * just completed (not the LINK TRB).
 241                  */
 242                 if (((dep->busy_slot & DWC3_TRB_MASK) ==
 243                         DWC3_TRB_NUM- 1) &&
 244                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 245                         dep->busy_slot++;
 246                 req->queued = false;
 247         }
 248
 249         list_del(&req->list);
 250         req->trb = NULL;
 251         if (req->request.dma && req->request.length)
 252                 dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
 253
 254         if (req->request.status == -EINPROGRESS)
 255                 req->request.status = status;
 256
 257         if (dwc->ep0_bounced && dep->number == 0)
 258                 dwc->ep0_bounced = false;
 259         else if (req->request.dma)
 260                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 261                                 req->direction);
 262
 263         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 264                         req, dep->name, req->request.actual,
 265                         req->request.length, status);
 266
 267         spin_unlock(&dwc->lock);
 268         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 269         spin_lock(&dwc->lock);
 270 }
 271
 272 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 273 {
 274         u32             timeout = 500;
 275         u32             reg;
 276
 277         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 278         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 279
 280         do {
 281                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 282                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 283                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 284                                         DWC3_DGCMD_STATUS(reg));
 285                         return 0;
 286                 }
 287
 288                 /*
 289                  * We can't sleep here, because it's also called from
 290                  * interrupt context.
 291                  */
 292                 timeout--;
 293                 if (!timeout)
 294                         return -ETIMEDOUT;
 295                 udelay(1);
 296         } while (1);
 297 }
 298
 299 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 300                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 301 {
 302         u32                     timeout = 500;
 303         u32                     saved_config = 0;
 304         u32                     reg;
 305
 306         int                     ret = -EINVAL;
 307
 308         /*
 309          * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
 310          * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
 311          * endpoint command.
 312          *
 313          * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
 314          * settings. Restore them after the command is completed.
 315          *
 316          * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
 317          */
 318         if (dwc->gadget.speed <= USB_SPEED_HIGH ||
 319             DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
 320                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 321                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 322                         saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
 323                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 324                 }
 325
 326                 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
 327                         saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 328                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 329                 }
 330
 331                 if (saved_config)
 332                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 333         }
 334
 335         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 336         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 337         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 338
 339         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 340         do {
 341                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 342                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 343                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 344                                         DWC3_DEPCMD_STATUS(reg));
 345                         ret = 0;
 346                         break;
 347                 }
 348
 349                 /*
 350                  * We can't sleep here, because it is also called from
 351                  * interrupt context.
 352                  */
 353                 timeout--;
 354                 if (!timeout) {
 355                         ret = -ETIMEDOUT;
 356                         break;
 357                 }
 358
 359                 udelay(1);
 360         } while (1);
 361
 362         if (saved_config) {
 363                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 364                 reg |= saved_config;
 365                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 366         }
 367
 368         return ret;
 369 }
 370
 371 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 372                 struct dwc3_trb *trb)
 373 {
 374         u32             offset = (char *) trb - (char *) dep->trb_pool;
 375
 376         return dep->trb_pool_dma + offset;
 377 }
 378
 379 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 380 {
 381         if (dep->trb_pool)
 382                 return 0;
 383
 384         if (dep->number == 0 || dep->number == 1)
 385                 return 0;
 386
 387         dep->trb_pool = dma_alloc_coherent(sizeof(struct dwc3_trb) *
 388                                            DWC3_TRB_NUM,
 389                                            (unsigned long *)&dep->trb_pool_dma);
 390         if (!dep->trb_pool) {
 391                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 392                                 dep->name);
 393                 return -ENOMEM;
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 400 {
 401         dma_free_coherent(dep->trb_pool);
 402
 403         dep->trb_pool = NULL;
 404         dep->trb_pool_dma = 0;
 405 }
 406
 407 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 408 {
 409         struct dwc3_gadget_ep_cmd_params params;
 410         u32                     cmd;
 411
 412         memset(&params, 0x00, sizeof(params));
 413
 414         if (dep->number != 1) {
 415                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 416                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 417                 if (dep->number > 1) {
 418                         if (dwc->start_config_issued)
 419                                 return 0;
 420                         dwc->start_config_issued = true;
 421                         cmd |= DWC3_DEPCMD_PARAM(2);
 422                 }
 423
 424                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 431                 const struct usb_endpoint_descriptor *desc,
 432                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 433                 bool ignore, bool restore)
 434 {
 435         struct dwc3_gadget_ep_cmd_params params;
 436
 437         memset(&params, 0x00, sizeof(params));
 438
 439         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 440                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 441
 442         /* Burst size is only needed in SuperSpeed mode */
 443         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 444                 u32 burst = dep->endpoint.maxburst - 1;
 445
 446                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 447         }
 448
 449         if (ignore)
 450                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 451
 452         if (restore) {
 453                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 454                 params.param2 |= dep->saved_state;
 455         }
 456
 457         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 458                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 459
 460         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 461                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 462                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 463                 dep->stream_capable = true;
 464         }
 465
 466         if (!usb_endpoint_xfer_control(desc))
 467                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 468
 469         /*
 470          * We are doing 1:1 mapping for endpoints, meaning
 471          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 472          * so on. We consider the direction bit as part of the physical
 473          * endpoint number. So USB endpoint 0x81 is 0x03.
 474          */
 475         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 476
 477         /*
 478          * We must use the lower 16 TX FIFOs even though
 479          * HW might have more
 480          */
 481         if (dep->direction)
 482                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 483
 484         if (desc->bInterval) {
 485                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 486                 dep->interval = 1 << (desc->bInterval - 1);
 487         }
 488
 489         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 490                         DWC3_DEPCMD_SETEPCONFIG, &params);
 491 }
 492
 493 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 494 {
 495         struct dwc3_gadget_ep_cmd_params params;
 496
 497         memset(&params, 0x00, sizeof(params));
 498
 499         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 500
 501         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 502                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 503 }
 504
 505 /**
 506  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 507  * @dep: endpoint to be initialized
 508  * @desc: USB Endpoint Descriptor
 509  *
 510  * Caller should take care of locking
 511  */
 512 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 513                 const struct usb_endpoint_descriptor *desc,
 514                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 515                 bool ignore, bool restore)
 516 {
 517         struct dwc3             *dwc = dep->dwc;
 518         u32                     reg;
 519         int                     ret;
 520
 521         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 522
 523         if (!(dep->flags & DWC3_EP_ENABLED)) {
 524                 ret = dwc3_gadget_start_config(dwc, dep);
 525                 if (ret)
 526                         return ret;
 527         }
 528
 529         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 530                         restore);
 531         if (ret)
 532                 return ret;
 533
 534         if (!(dep->flags & DWC3_EP_ENABLED)) {
 535                 struct dwc3_trb *trb_st_hw;
 536                 struct dwc3_trb *trb_link;
 537
 538                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 539                 if (ret)
 540                         return ret;
 541
 542                 dep->endpoint.desc = desc;
 543                 dep->comp_desc = comp_desc;
 544                 dep->type = usb_endpoint_type(desc);
 545                 dep->flags |= DWC3_EP_ENABLED;
 546
 547                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 548                 reg |= DWC3_DALEPENA_EP(dep->number);
 549                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 550
 551                 if (!usb_endpoint_xfer_isoc(desc))
 552                         return 0;
 553
 554                 /* Link TRB for ISOC. The HWO bit is never reset */
 555                 trb_st_hw = &dep->trb_pool[0];
 556
 557                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 558                 memset(trb_link, 0, sizeof(*trb_link));
 559
 560                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 561                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 562                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 563                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 564         }
 565
 566         return 0;
 567 }
 568
 569 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 570 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 571 {
 572         struct dwc3_request             *req;
 573
 574         if (!list_empty(&dep->req_queued)) {
 575                 dwc3_stop_active_transfer(dwc, dep->number, true);
 576
 577                 /* - giveback all requests to gadget driver */
 578                 while (!list_empty(&dep->req_queued)) {
 579                         req = next_request(&dep->req_queued);
 580
 581                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 582                 }
 583         }
 584
 585         while (!list_empty(&dep->request_list)) {
 586                 req = next_request(&dep->request_list);
 587
 588                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 589         }
 590 }
 591
 592 /**
 593  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 594  * @dep: the endpoint to disable
 595  *
 596  * This function also removes requests which are currently processed ny the
 597  * hardware and those which are not yet scheduled.
 598  * Caller should take care of locking.
 599  */
 600 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 601 {
 602         struct dwc3             *dwc = dep->dwc;
 603         u32                     reg;
 604
 605         dwc3_remove_requests(dwc, dep);
 606
 607         /* make sure HW endpoint isn't stalled */
 608         if (dep->flags & DWC3_EP_STALL)
 609                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 610
 611         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 612         reg &= ~DWC3_DALEPENA_EP(dep->number);
 613         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 614
 615         dep->stream_capable = false;
 616         dep->endpoint.desc = NULL;
 617         dep->comp_desc = NULL;
 618         dep->type = 0;
 619         dep->flags = 0;
 620
 621         return 0;
 622 }
 623
 624 /* -------------------------------------------------------------------------- */
 625
 626 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 627                 const struct usb_endpoint_descriptor *desc)
 628 {
 629         return -EINVAL;
 630 }
 631
 632 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 633 {
 634         return -EINVAL;
 635 }
 636
 637 /* -------------------------------------------------------------------------- */
 638
 639 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 640                 const struct usb_endpoint_descriptor *desc)
 641 {
 642         struct dwc3_ep                  *dep;
 643         unsigned long                   flags;
 644         int                             ret;
 645
 646         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 647                 pr_debug("dwc3: invalid parameters\n");
 648                 return -EINVAL;
 649         }
 650
 651         if (!desc->wMaxPacketSize) {
 652                 pr_debug("dwc3: missing wMaxPacketSize\n");
 653                 return -EINVAL;
 654         }
 655
 656         dep = to_dwc3_ep(ep);
 657
 658         if (dep->flags & DWC3_EP_ENABLED) {
 659                 WARN(true, "%s is already enabled\n",
 660                                 dep->name);
 661                 return 0;
 662         }
 663
 664         switch (usb_endpoint_type(desc)) {
 665         case USB_ENDPOINT_XFER_CONTROL:
 666                 strlcat(dep->name, "-control", sizeof(dep->name));
 667                 break;
 668         case USB_ENDPOINT_XFER_ISOC:
 669                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 670                 break;
 671         case USB_ENDPOINT_XFER_BULK:
 672                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 673                 break;
 674         case USB_ENDPOINT_XFER_INT:
 675                 strlcat(dep->name, "-int", sizeof(dep->name));
 676                 break;
 677         default:
 678                 dev_err(dep->dwc->dev, "invalid endpoint transfer type\n");
 679         }
 680
 681         spin_lock_irqsave(&dwc->lock, flags);
 682         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 683         spin_unlock_irqrestore(&dwc->lock, flags);
 684
 685         return ret;
 686 }
 687
 688 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 689 {
 690         struct dwc3_ep                  *dep;
 691         unsigned long                   flags;
 692         int                             ret;
 693
 694         if (!ep) {
 695                 pr_debug("dwc3: invalid parameters\n");
 696                 return -EINVAL;
 697         }
 698
 699         dep = to_dwc3_ep(ep);
 700
 701         if (!(dep->flags & DWC3_EP_ENABLED)) {
 702                 WARN(true, "%s is already disabled\n",
 703                                 dep->name);
 704                 return 0;
 705         }
 706
 707         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 708                         dep->number >> 1,
 709                         (dep->number & 1) ? "in" : "out");
 710
 711         spin_lock_irqsave(&dwc->lock, flags);
 712         ret = __dwc3_gadget_ep_disable(dep);
 713         spin_unlock_irqrestore(&dwc->lock, flags);
 714
 715         return ret;
 716 }
 717
 718 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 719         gfp_t gfp_flags)
 720 {
 721         struct dwc3_request             *req;
 722         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 723
 724         req = kzalloc(sizeof(*req), gfp_flags);
 725         if (!req)
 726                 return NULL;
 727
 728         req->epnum      = dep->number;
 729         req->dep        = dep;
 730
 731         return &req->request;
 732 }
 733
 734 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 735                 struct usb_request *request)
 736 {
 737         struct dwc3_request             *req = to_dwc3_request(request);
 738
 739         kfree(req);
 740 }
 741
 742 /**
 743  * dwc3_prepare_one_trb - setup one TRB from one request
 744  * @dep: endpoint for which this request is prepared
 745  * @req: dwc3_request pointer
 746  */
 747 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 748                 struct dwc3_request *req, dma_addr_t dma,
 749                 unsigned length, unsigned last, unsigned chain, unsigned node)
 750 {
 751         struct dwc3_trb         *trb;
 752
 753         dev_vdbg(dep->dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 754                  dep->name, req, (unsigned long long)dma,
 755                  length, last ? " last" : "", chain ? " chain" : "");
 756
 757         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 758
 759         if (!req->trb) {
 760                 dwc3_gadget_move_request_queued(req);
 761                 req->trb = trb;
 762                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 763                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 764         }
 765
 766         dep->free_slot++;
 767         /* Skip the LINK-TRB on ISOC */
 768         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 769                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 770                 dep->free_slot++;
 771
 772         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 773         trb->bpl = lower_32_bits(dma);
 774         trb->bph = upper_32_bits(dma);
 775
 776         switch (usb_endpoint_type(dep->endpoint.desc)) {
 777         case USB_ENDPOINT_XFER_CONTROL:
 778                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 779                 break;
 780
 781         case USB_ENDPOINT_XFER_ISOC:
 782                 if (!node)
 783                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 784                 else
 785                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 786                 break;
 787
 788         case USB_ENDPOINT_XFER_BULK:
 789         case USB_ENDPOINT_XFER_INT:
 790                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 791                 break;
 792         default:
 793                 /*
 794                  * This is only possible with faulty memory because we
 795                  * checked it already :)
 796                  */
 797                 BUG();
 798         }
 799
 800         if (!req->request.no_interrupt && !chain)
 801                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 802
 803         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 804                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 805                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 806         } else if (last) {
 807                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 808         }
 809
 810         if (chain)
 811                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 812
 813         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 814                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 815
 816         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 817
 818         dwc3_flush_cache((uintptr_t)dma, length);
 819         dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
 820 }
 821
 822 /*
 823  * dwc3_prepare_trbs - setup TRBs from requests
 824  * @dep: endpoint for which requests are being prepared
 825  * @starting: true if the endpoint is idle and no requests are queued.
 826  *
 827  * The function goes through the requests list and sets up TRBs for the
 828  * transfers. The function returns once there are no more TRBs available or
 829  * it runs out of requests.
 830  */
 831 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 832 {
 833         struct dwc3_request     *req, *n;
 834         u32                     trbs_left;
 835         u32                     max;
 836
 837         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 838
 839         /* the first request must not be queued */
 840         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 841
 842         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 843         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 844                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 845                 if (trbs_left > max)
 846                         trbs_left = max;
 847         }
 848
 849         /*
 850          * If busy & slot are equal than it is either full or empty. If we are
 851          * starting to process requests then we are empty. Otherwise we are
 852          * full and don't do anything
 853          */
 854         if (!trbs_left) {
 855                 if (!starting)
 856                         return;
 857                 trbs_left = DWC3_TRB_NUM;
 858                 /*
 859                  * In case we start from scratch, we queue the ISOC requests
 860                  * starting from slot 1. This is done because we use ring
 861                  * buffer and have no LST bit to stop us. Instead, we place
 862                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 863                  * after the first request so we start at slot 1 and have
 864                  * 7 requests proceed before we hit the first IOC.
 865                  * Other transfer types don't use the ring buffer and are
 866                  * processed from the first TRB until the last one. Since we
 867                  * don't wrap around we have to start at the beginning.
 868                  */
 869                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 870                         dep->busy_slot = 1;
 871                         dep->free_slot = 1;
 872                 } else {
 873                         dep->busy_slot = 0;
 874                         dep->free_slot = 0;
 875                 }
 876         }
 877
 878         /* The last TRB is a link TRB, not used for xfer */
 879         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 880                 return;
 881
 882         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 883                 unsigned        length;
 884                 dma_addr_t      dma;
 885
 886                 dma = req->request.dma;
 887                 length = req->request.length;
 888
 889                 dwc3_prepare_one_trb(dep, req, dma, length,
 890                                      true, false, 0);
 891
 892                 break;
 893         }
 894 }
 895
 896 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 897                 int start_new)
 898 {
 899         struct dwc3_gadget_ep_cmd_params params;
 900         struct dwc3_request             *req;
 901         struct dwc3                     *dwc = dep->dwc;
 902         int                             ret;
 903         u32                             cmd;
 904
 905         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 906                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 907                 return -EBUSY;
 908         }
 909         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 910
 911         /*
 912          * If we are getting here after a short-out-packet we don't enqueue any
 913          * new requests as we try to set the IOC bit only on the last request.
 914          */
 915         if (start_new) {
 916                 if (list_empty(&dep->req_queued))
 917                         dwc3_prepare_trbs(dep, start_new);
 918
 919                 /* req points to the first request which will be sent */
 920                 req = next_request(&dep->req_queued);
 921         } else {
 922                 dwc3_prepare_trbs(dep, start_new);
 923
 924                 /*
 925                  * req points to the first request where HWO changed from 0 to 1
 926                  */
 927                 req = next_request(&dep->req_queued);
 928         }
 929         if (!req) {
 930                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 931                 return 0;
 932         }
 933
 934         memset(&params, 0, sizeof(params));
 935
 936         if (start_new) {
 937                 params.param0 = upper_32_bits(req->trb_dma);
 938                 params.param1 = lower_32_bits(req->trb_dma);
 939                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 940         } else {
 941                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 942         }
 943
 944         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 945         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 946         if (ret < 0) {
 947                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 948
 949                 /*
 950                  * FIXME we need to iterate over the list of requests
 951                  * here and stop, unmap, free and del each of the linked
 952                  * requests instead of what we do now.
 953                  */
 954                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 955                                 req->direction);
 956                 list_del(&req->list);
 957                 return ret;
 958         }
 959
 960         dep->flags |= DWC3_EP_BUSY;
 961
 962         if (start_new) {
 963                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 964                                 dep->number);
 965                 WARN_ON_ONCE(!dep->resource_index);
 966         }
 967
 968         return 0;
 969 }
 970
 971 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
 972                 struct dwc3_ep *dep, u32 cur_uf)
 973 {
 974         u32 uf;
 975
 976         if (list_empty(&dep->request_list)) {
 977                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
 978                         dep->name);
 979                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 980                 return;
 981         }
 982
 983         /* 4 micro frames in the future */
 984         uf = cur_uf + dep->interval * 4;
 985
 986         __dwc3_gadget_kick_transfer(dep, uf, 1);
 987 }
 988
 989 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
 990                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
 991 {
 992         u32 cur_uf, mask;
 993
 994         mask = ~(dep->interval - 1);
 995         cur_uf = event->parameters & mask;
 996
 997         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
 998 }
 999
1000 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1001 {
1002         struct dwc3             *dwc = dep->dwc;
1003         int                     ret;
1004
1005         req->request.actual     = 0;
1006         req->request.status     = -EINPROGRESS;
1007         req->direction          = dep->direction;
1008         req->epnum              = dep->number;
1009
1010         /*
1011          * DWC3 hangs on OUT requests smaller than maxpacket size,
1012          * so HACK the request length
1013          */
1014         if (dep->direction == 0 &&
1015             req->request.length < dep->endpoint.maxpacket)
1016                 req->request.length = dep->endpoint.maxpacket;
1017
1018         /*
1019          * We only add to our list of requests now and
1020          * start consuming the list once we get XferNotReady
1021          * IRQ.
1022          *
1023          * That way, we avoid doing anything that we don't need
1024          * to do now and defer it until the point we receive a
1025          * particular token from the Host side.
1026          *
1027          * This will also avoid Host cancelling URBs due to too
1028          * many NAKs.
1029          */
1030         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1031                         dep->direction);
1032         if (ret)
1033                 return ret;
1034
1035         list_add_tail(&req->list, &dep->request_list);
1036
1037         /*
1038          * There are a few special cases:
1039          *
1040          * 1. XferNotReady with empty list of requests. We need to kick the
1041          *    transfer here in that situation, otherwise we will be NAKing
1042          *    forever. If we get XferNotReady before gadget driver has a
1043          *    chance to queue a request, we will ACK the IRQ but won't be
1044          *    able to receive the data until the next request is queued.
1045          *    The following code is handling exactly that.
1046          *
1047          */
1048         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1049                 /*
1050                  * If xfernotready is already elapsed and it is a case
1051                  * of isoc transfer, then issue END TRANSFER, so that
1052                  * you can receive xfernotready again and can have
1053                  * notion of current microframe.
1054                  */
1055                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1056                         if (list_empty(&dep->req_queued)) {
1057                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1058                                 dep->flags = DWC3_EP_ENABLED;
1059                         }
1060                         return 0;
1061                 }
1062
1063                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1064                 if (ret && ret != -EBUSY)
1065                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1066                                         dep->name);
1067                 return ret;
1068         }
1069
1070         /*
1071          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1072          *    kick the transfer here after queuing a request, otherwise the
1073          *    core may not see the modified TRB(s).
1074          */
1075         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1076                         (dep->flags & DWC3_EP_BUSY) &&
1077                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1078                 WARN_ON_ONCE(!dep->resource_index);
1079                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1080                                 false);
1081                 if (ret && ret != -EBUSY)
1082                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1083                                         dep->name);
1084                 return ret;
1085         }
1086
1087         /*
1088          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1089          * right away, otherwise host will not know we have streams to be
1090          * handled.
1091          */
1092         if (dep->stream_capable) {
1093                 int     ret;
1094
1095                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1096                 if (ret && ret != -EBUSY) {
1097                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1098                                         dep->name);
1099                 }
1100         }
1101
1102         return 0;
1103 }
1104
1105 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1106         gfp_t gfp_flags)
1107 {
1108         struct dwc3_request             *req = to_dwc3_request(request);
1109         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1110
1111         unsigned long                   flags;
1112
1113         int                             ret;
1114
1115         spin_lock_irqsave(&dwc->lock, flags);
1116         if (!dep->endpoint.desc) {
1117                 dev_dbg(dep->dwc->dev,
1118                         "trying to queue request %p to disabled %s\n", request,
1119                         ep->name);
1120                 ret = -ESHUTDOWN;
1121                 goto out;
1122         }
1123
1124         if (req->dep != dep) {
1125                 WARN(true, "request %p belongs to '%s'\n", request,
1126                      req->dep->name);
1127                 ret = -EINVAL;
1128                 goto out;
1129         }
1130
1131         dev_vdbg(dep->dwc->dev, "queing request %p to %s length %d\n",
1132                  request, ep->name, request->length);
1133
1134         ret = __dwc3_gadget_ep_queue(dep, req);
1135
1136 out:
1137         spin_unlock_irqrestore(&dwc->lock, flags);
1138
1139         return ret;
1140 }
1141
1142 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1143                 struct usb_request *request)
1144 {
1145         struct dwc3_request             *req = to_dwc3_request(request);
1146         struct dwc3_request             *r = NULL;
1147
1148         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1149         struct dwc3                     *dwc = dep->dwc;
1150
1151         unsigned long                   flags;
1152         int                             ret = 0;
1153
1154         spin_lock_irqsave(&dwc->lock, flags);
1155
1156         list_for_each_entry(r, &dep->request_list, list) {
1157                 if (r == req)
1158                         break;
1159         }
1160
1161         if (r != req) {
1162                 list_for_each_entry(r, &dep->req_queued, list) {
1163                         if (r == req)
1164                                 break;
1165                 }
1166                 if (r == req) {
1167                         /* wait until it is processed */
1168                         dwc3_stop_active_transfer(dwc, dep->number, true);
1169                         goto out1;
1170                 }
1171                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1172                                 request, ep->name);
1173                 ret = -EINVAL;
1174                 goto out0;
1175         }
1176
1177 out1:
1178         /* giveback the request */
1179         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1180
1181 out0:
1182         spin_unlock_irqrestore(&dwc->lock, flags);
1183
1184         return ret;
1185 }
1186
1187 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1188 {
1189         struct dwc3_gadget_ep_cmd_params        params;
1190         struct dwc3                             *dwc = dep->dwc;
1191         int                                     ret;
1192
1193         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1194                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1195                 return -EINVAL;
1196         }
1197
1198         memset(&params, 0x00, sizeof(params));
1199
1200         if (value) {
1201                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1202                                 (!list_empty(&dep->req_queued) ||
1203                                  !list_empty(&dep->request_list)))) {
1204                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1205                                         dep->name);
1206                         return -EAGAIN;
1207                 }
1208
1209                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1210                         DWC3_DEPCMD_SETSTALL, &params);
1211                 if (ret)
1212                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1213                                         dep->name);
1214                 else
1215                         dep->flags |= DWC3_EP_STALL;
1216         } else {
1217                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1218                         DWC3_DEPCMD_CLEARSTALL, &params);
1219                 if (ret)
1220                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1221                                         dep->name);
1222                 else
1223                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1224         }
1225
1226         return ret;
1227 }
1228
1229 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1230 {
1231         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1232
1233         unsigned long                   flags;
1234
1235         int                             ret;
1236
1237         spin_lock_irqsave(&dwc->lock, flags);
1238         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1239         spin_unlock_irqrestore(&dwc->lock, flags);
1240
1241         return ret;
1242 }
1243
1244 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1245 {
1246         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1247         unsigned long                   flags;
1248         int                             ret;
1249
1250         spin_lock_irqsave(&dwc->lock, flags);
1251         dep->flags |= DWC3_EP_WEDGE;
1252
1253         if (dep->number == 0 || dep->number == 1)
1254                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1255         else
1256                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1257         spin_unlock_irqrestore(&dwc->lock, flags);
1258
1259         return ret;
1260 }
1261
1262 /* -------------------------------------------------------------------------- */
1263
1264 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1265         .bLength        = USB_DT_ENDPOINT_SIZE,
1266         .bDescriptorType = USB_DT_ENDPOINT,
1267         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1268 };
1269
1270 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1271         .enable         = dwc3_gadget_ep0_enable,
1272         .disable        = dwc3_gadget_ep0_disable,
1273         .alloc_request  = dwc3_gadget_ep_alloc_request,
1274         .free_request   = dwc3_gadget_ep_free_request,
1275         .queue          = dwc3_gadget_ep0_queue,
1276         .dequeue        = dwc3_gadget_ep_dequeue,
1277         .set_halt       = dwc3_gadget_ep0_set_halt,
1278         .set_wedge      = dwc3_gadget_ep_set_wedge,
1279 };
1280
1281 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1282         .enable         = dwc3_gadget_ep_enable,
1283         .disable        = dwc3_gadget_ep_disable,
1284         .alloc_request  = dwc3_gadget_ep_alloc_request,
1285         .free_request   = dwc3_gadget_ep_free_request,
1286         .queue          = dwc3_gadget_ep_queue,
1287         .dequeue        = dwc3_gadget_ep_dequeue,
1288         .set_halt       = dwc3_gadget_ep_set_halt,
1289         .set_wedge      = dwc3_gadget_ep_set_wedge,
1290 };
1291
1292 /* -------------------------------------------------------------------------- */
1293
1294 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1295 {
1296         struct dwc3             *dwc = gadget_to_dwc(g);
1297         u32                     reg;
1298
1299         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1300         return DWC3_DSTS_SOFFN(reg);
1301 }
1302
1303 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1304 {
1305         struct dwc3             *dwc = gadget_to_dwc(g);
1306
1307         unsigned long           timeout;
1308         unsigned long           flags;
1309
1310         u32                     reg;
1311
1312         int                     ret = 0;
1313
1314         u8                      link_state;
1315         u8                      speed;
1316
1317         spin_lock_irqsave(&dwc->lock, flags);
1318
1319         /*
1320          * According to the Databook Remote wakeup request should
1321          * be issued only when the device is in early suspend state.
1322          *
1323          * We can check that via USB Link State bits in DSTS register.
1324          */
1325         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1326
1327         speed = reg & DWC3_DSTS_CONNECTSPD;
1328         if (speed == DWC3_DSTS_SUPERSPEED) {
1329                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1330                 ret = -EINVAL;
1331                 goto out;
1332         }
1333
1334         link_state = DWC3_DSTS_USBLNKST(reg);
1335
1336         switch (link_state) {
1337         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1338         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1339                 break;
1340         default:
1341                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1342                                 link_state);
1343                 ret = -EINVAL;
1344                 goto out;
1345         }
1346
1347         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1348         if (ret < 0) {
1349                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1350                 goto out;
1351         }
1352
1353         /* Recent versions do this automatically */
1354         if (dwc->revision < DWC3_REVISION_194A) {
1355                 /* write zeroes to Link Change Request */
1356                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1357                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1358                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1359         }
1360
1361         /* poll until Link State changes to ON */
1362         timeout = 1000;
1363
1364         while (timeout--) {
1365                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1366
1367                 /* in HS, means ON */
1368                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1369                         break;
1370         }
1371
1372         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1373                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1374                 ret = -EINVAL;
1375         }
1376
1377 out:
1378         spin_unlock_irqrestore(&dwc->lock, flags);
1379
1380         return ret;
1381 }
1382
1383 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1384                 int is_selfpowered)
1385 {
1386         struct dwc3             *dwc = gadget_to_dwc(g);
1387         unsigned long           flags;
1388
1389         spin_lock_irqsave(&dwc->lock, flags);
1390         dwc->is_selfpowered = !!is_selfpowered;
1391         spin_unlock_irqrestore(&dwc->lock, flags);
1392
1393         return 0;
1394 }
1395
1396 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1397 {
1398         u32                     reg;
1399         u32                     timeout = 500;
1400
1401         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1402         if (is_on) {
1403                 if (dwc->revision <= DWC3_REVISION_187A) {
1404                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1405                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1406                 }
1407
1408                 if (dwc->revision >= DWC3_REVISION_194A)
1409                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1410                 reg |= DWC3_DCTL_RUN_STOP;
1411
1412                 if (dwc->has_hibernation)
1413                         reg |= DWC3_DCTL_KEEP_CONNECT;
1414
1415                 dwc->pullups_connected = true;
1416         } else {
1417                 reg &= ~DWC3_DCTL_RUN_STOP;
1418
1419                 if (dwc->has_hibernation && !suspend)
1420                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1421
1422                 dwc->pullups_connected = false;
1423         }
1424
1425         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1426
1427         do {
1428                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1429                 if (is_on) {
1430                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1431                                 break;
1432                 } else {
1433                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1434                                 break;
1435                 }
1436                 timeout--;
1437                 if (!timeout)
1438                         return -ETIMEDOUT;
1439                 udelay(1);
1440         } while (1);
1441
1442         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1443                         dwc->gadget_driver
1444                         ? dwc->gadget_driver->function : "no-function",
1445                         is_on ? "connect" : "disconnect");
1446
1447         return 0;
1448 }
1449
1450 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1451 {
1452         struct dwc3             *dwc = gadget_to_dwc(g);
1453         unsigned long           flags;
1454         int                     ret;
1455
1456         is_on = !!is_on;
1457
1458         spin_lock_irqsave(&dwc->lock, flags);
1459         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1460         spin_unlock_irqrestore(&dwc->lock, flags);
1461
1462         return ret;
1463 }
1464
1465 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1466 {
1467         u32                     reg;
1468
1469         /* Enable all but Start and End of Frame IRQs */
1470         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1471                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1472                         DWC3_DEVTEN_CMDCMPLTEN |
1473                         DWC3_DEVTEN_ERRTICERREN |
1474                         DWC3_DEVTEN_WKUPEVTEN |
1475                         DWC3_DEVTEN_ULSTCNGEN |
1476                         DWC3_DEVTEN_CONNECTDONEEN |
1477                         DWC3_DEVTEN_USBRSTEN |
1478                         DWC3_DEVTEN_DISCONNEVTEN);
1479
1480         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1481 }
1482
1483 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1484 {
1485         /* mask all interrupts */
1486         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1487 }
1488
1489 static int dwc3_gadget_start(struct usb_gadget *g,
1490                 struct usb_gadget_driver *driver)
1491 {
1492         struct dwc3             *dwc = gadget_to_dwc(g);
1493         struct dwc3_ep          *dep;
1494         unsigned long           flags;
1495         int                     ret = 0;
1496         u32                     reg;
1497
1498         spin_lock_irqsave(&dwc->lock, flags);
1499
1500         if (dwc->gadget_driver) {
1501                 dev_err(dwc->dev, "%s is already bound to %s\n",
1502                                 dwc->gadget.name,
1503                                 dwc->gadget_driver->function);
1504                 ret = -EBUSY;
1505                 goto err1;
1506         }
1507
1508         dwc->gadget_driver      = driver;
1509
1510         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1511         reg &= ~(DWC3_DCFG_SPEED_MASK);
1512
1513         /**
1514          * WORKAROUND: DWC3 revision < 2.20a have an issue
1515          * which would cause metastability state on Run/Stop
1516          * bit if we try to force the IP to USB2-only mode.
1517          *
1518          * Because of that, we cannot configure the IP to any
1519          * speed other than the SuperSpeed
1520          *
1521          * Refers to:
1522          *
1523          * STAR#9000525659: Clock Domain Crossing on DCTL in
1524          * USB 2.0 Mode
1525          */
1526         if (dwc->revision < DWC3_REVISION_220A) {
1527                 reg |= DWC3_DCFG_SUPERSPEED;
1528         } else {
1529                 switch (dwc->maximum_speed) {
1530                 case USB_SPEED_LOW:
1531                         reg |= DWC3_DSTS_LOWSPEED;
1532                         break;
1533                 case USB_SPEED_FULL:
1534                         reg |= DWC3_DSTS_FULLSPEED1;
1535                         break;
1536                 case USB_SPEED_HIGH:
1537                         reg |= DWC3_DSTS_HIGHSPEED;
1538                         break;
1539                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1540                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1541                 default:
1542                         reg |= DWC3_DSTS_SUPERSPEED;
1543                 }
1544         }
1545         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1546
1547         dwc->start_config_issued = false;
1548
1549         /* Start with SuperSpeed Default */
1550         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1551
1552         dep = dwc->eps[0];
1553         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1554                         false);
1555         if (ret) {
1556                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1557                 goto err2;
1558         }
1559
1560         dep = dwc->eps[1];
1561         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1562                         false);
1563         if (ret) {
1564                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1565                 goto err3;
1566         }
1567
1568         /* begin to receive SETUP packets */
1569         dwc->ep0state = EP0_SETUP_PHASE;
1570         dwc3_ep0_out_start(dwc);
1571
1572         dwc3_gadget_enable_irq(dwc);
1573
1574         spin_unlock_irqrestore(&dwc->lock, flags);
1575
1576         return 0;
1577
1578 err3:
1579         __dwc3_gadget_ep_disable(dwc->eps[0]);
1580
1581 err2:
1582         dwc->gadget_driver = NULL;
1583
1584 err1:
1585         spin_unlock_irqrestore(&dwc->lock, flags);
1586
1587         return ret;
1588 }
1589
1590 static int dwc3_gadget_stop(struct usb_gadget *g)
1591 {
1592         struct dwc3             *dwc = gadget_to_dwc(g);
1593         unsigned long           flags;
1594
1595         spin_lock_irqsave(&dwc->lock, flags);
1596
1597         dwc3_gadget_disable_irq(dwc);
1598         __dwc3_gadget_ep_disable(dwc->eps[0]);
1599         __dwc3_gadget_ep_disable(dwc->eps[1]);
1600
1601         dwc->gadget_driver      = NULL;
1602
1603         spin_unlock_irqrestore(&dwc->lock, flags);
1604
1605         return 0;
1606 }
1607
1608 static struct usb_ep *dwc3_find_ep(struct usb_gadget *gadget, const char *name)
1609 {
1610         struct usb_ep *ep;
1611
1612         list_for_each_entry(ep, &gadget->ep_list, ep_list)
1613                 if (!strcmp(ep->name, name))
1614                         return ep;
1615
1616         return NULL;
1617 }
1618
1619 static struct
1620 usb_ep *dwc3_gadget_match_ep(struct usb_gadget *gadget,
1621                              struct usb_endpoint_descriptor *desc,
1622                              struct usb_ss_ep_comp_descriptor *comp_desc)
1623 {
1624         /*
1625          * First try standard, common configuration: ep1in-bulk,
1626          * ep2out-bulk, ep3in-int to match other udc drivers to avoid
1627          * confusion in already deployed software (endpoint numbers
1628          * hardcoded in userspace software/drivers)
1629          */
1630         if (usb_endpoint_is_bulk_in(desc))
1631                 return dwc3_find_ep(gadget, "ep1in");
1632         if (usb_endpoint_is_bulk_out(desc))
1633                 return dwc3_find_ep(gadget, "ep2out");
1634         if (usb_endpoint_is_int_in(desc))
1635                 return dwc3_find_ep(gadget, "ep3in");
1636
1637         return NULL;
1638 }
1639
1640 static const struct usb_gadget_ops dwc3_gadget_ops = {
1641         .get_frame              = dwc3_gadget_get_frame,
1642         .wakeup                 = dwc3_gadget_wakeup,
1643         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1644         .pullup                 = dwc3_gadget_pullup,
1645         .udc_start              = dwc3_gadget_start,
1646         .udc_stop               = dwc3_gadget_stop,
1647         .match_ep               = dwc3_gadget_match_ep,
1648 };
1649
1650 /* -------------------------------------------------------------------------- */
1651
1652 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1653                 u8 num, u32 direction)
1654 {
1655         struct dwc3_ep                  *dep;
1656         u8                              i;
1657
1658         for (i = 0; i < num; i++) {
1659                 u8 epnum = (i << 1) | (!!direction);
1660
1661                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1662                 if (!dep)
1663                         return -ENOMEM;
1664
1665                 dep->dwc = dwc;
1666                 dep->number = epnum;
1667                 dep->direction = !!direction;
1668                 dwc->eps[epnum] = dep;
1669
1670                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1671                                 (epnum & 1) ? "in" : "out");
1672
1673                 dep->endpoint.name = dep->name;
1674
1675                 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1676
1677                 if (epnum == 0 || epnum == 1) {
1678                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1679                         dep->endpoint.maxburst = 1;
1680                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1681                         if (!epnum)
1682                                 dwc->gadget.ep0 = &dep->endpoint;
1683                 } else {
1684                         int             ret;
1685
1686                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1687                         dep->endpoint.max_streams = 15;
1688                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1689                         list_add_tail(&dep->endpoint.ep_list,
1690                                         &dwc->gadget.ep_list);
1691
1692                         ret = dwc3_alloc_trb_pool(dep);
1693                         if (ret)
1694                                 return ret;
1695                 }
1696
1697                 INIT_LIST_HEAD(&dep->request_list);
1698                 INIT_LIST_HEAD(&dep->req_queued);
1699         }
1700
1701         return 0;
1702 }
1703
1704 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1705 {
1706         int                             ret;
1707
1708         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1709
1710         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1711         if (ret < 0) {
1712                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1713                 return ret;
1714         }
1715
1716         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1717         if (ret < 0) {
1718                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1719                 return ret;
1720         }
1721
1722         return 0;
1723 }
1724
1725 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1726 {
1727         struct dwc3_ep                  *dep;
1728         u8                              epnum;
1729
1730         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1731                 dep = dwc->eps[epnum];
1732                 if (!dep)
1733                         continue;
1734                 /*
1735                  * Physical endpoints 0 and 1 are special; they form the
1736                  * bi-directional USB endpoint 0.
1737                  *
1738                  * For those two physical endpoints, we don't allocate a TRB
1739                  * pool nor do we add them the endpoints list. Due to that, we
1740                  * shouldn't do these two operations otherwise we would end up
1741                  * with all sorts of bugs when removing dwc3.ko.
1742                  */
1743                 if (epnum != 0 && epnum != 1) {
1744                         dwc3_free_trb_pool(dep);
1745                         list_del(&dep->endpoint.ep_list);
1746                 }
1747
1748                 kfree(dep);
1749         }
1750 }
1751
1752 /* -------------------------------------------------------------------------- */
1753
1754 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1755                 struct dwc3_request *req, struct dwc3_trb *trb,
1756                 const struct dwc3_event_depevt *event, int status)
1757 {
1758         unsigned int            count;
1759         unsigned int            s_pkt = 0;
1760         unsigned int            trb_status;
1761
1762         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1763                 /*
1764                  * We continue despite the error. There is not much we
1765                  * can do. If we don't clean it up we loop forever. If
1766                  * we skip the TRB then it gets overwritten after a
1767                  * while since we use them in a ring buffer. A BUG()
1768                  * would help. Lets hope that if this occurs, someone
1769                  * fixes the root cause instead of looking away :)
1770                  */
1771                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1772                                 dep->name, trb);
1773         count = trb->size & DWC3_TRB_SIZE_MASK;
1774
1775         if (dep->direction) {
1776                 if (count) {
1777                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1778                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1779                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1780                                                 dep->name);
1781                                 /*
1782                                  * If missed isoc occurred and there is
1783                                  * no request queued then issue END
1784                                  * TRANSFER, so that core generates
1785                                  * next xfernotready and we will issue
1786                                  * a fresh START TRANSFER.
1787                                  * If there are still queued request
1788                                  * then wait, do not issue either END
1789                                  * or UPDATE TRANSFER, just attach next
1790                                  * request in request_list during
1791                                  * giveback.If any future queued request
1792                                  * is successfully transferred then we
1793                                  * will issue UPDATE TRANSFER for all
1794                                  * request in the request_list.
1795                                  */
1796                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1797                         } else {
1798                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1799                                                 dep->name);
1800                                 status = -ECONNRESET;
1801                         }
1802                 } else {
1803                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1804                 }
1805         } else {
1806                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1807                         s_pkt = 1;
1808         }
1809
1810         /*
1811          * We assume here we will always receive the entire data block
1812          * which we should receive. Meaning, if we program RX to
1813          * receive 4K but we receive only 2K, we assume that's all we
1814          * should receive and we simply bounce the request back to the
1815          * gadget driver for further processing.
1816          */
1817         req->request.actual += req->request.length - count;
1818         if (s_pkt)
1819                 return 1;
1820         if ((event->status & DEPEVT_STATUS_LST) &&
1821                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1822                                 DWC3_TRB_CTRL_HWO)))
1823                 return 1;
1824         if ((event->status & DEPEVT_STATUS_IOC) &&
1825                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1826                 return 1;
1827         return 0;
1828 }
1829
1830 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1831                 const struct dwc3_event_depevt *event, int status)
1832 {
1833         struct dwc3_request     *req;
1834         struct dwc3_trb         *trb;
1835         unsigned int            slot;
1836
1837         req = next_request(&dep->req_queued);
1838         if (!req) {
1839                 WARN_ON_ONCE(1);
1840                 return 1;
1841         }
1842
1843         slot = req->start_slot;
1844         if ((slot == DWC3_TRB_NUM - 1) &&
1845             usb_endpoint_xfer_isoc(dep->endpoint.desc))
1846                 slot++;
1847         slot %= DWC3_TRB_NUM;
1848         trb = &dep->trb_pool[slot];
1849
1850         dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
1851         __dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
1852         dwc3_gadget_giveback(dep, req, status);
1853
1854         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1855                         list_empty(&dep->req_queued)) {
1856                 if (list_empty(&dep->request_list)) {
1857                         /*
1858                          * If there is no entry in request list then do
1859                          * not issue END TRANSFER now. Just set PENDING
1860                          * flag, so that END TRANSFER is issued when an
1861                          * entry is added into request list.
1862                          */
1863                         dep->flags = DWC3_EP_PENDING_REQUEST;
1864                 } else {
1865                         dwc3_stop_active_transfer(dwc, dep->number, true);
1866                         dep->flags = DWC3_EP_ENABLED;
1867                 }
1868                 return 1;
1869         }
1870
1871         return 1;
1872 }
1873
1874 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1875                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1876 {
1877         unsigned                status = 0;
1878         int                     clean_busy;
1879
1880         if (event->status & DEPEVT_STATUS_BUSERR)
1881                 status = -ECONNRESET;
1882
1883         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1884         if (clean_busy)
1885                 dep->flags &= ~DWC3_EP_BUSY;
1886
1887         /*
1888          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1889          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1890          */
1891         if (dwc->revision < DWC3_REVISION_183A) {
1892                 u32             reg;
1893                 int             i;
1894
1895                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1896                         dep = dwc->eps[i];
1897
1898                         if (!(dep->flags & DWC3_EP_ENABLED))
1899                                 continue;
1900
1901                         if (!list_empty(&dep->req_queued))
1902                                 return;
1903                 }
1904
1905                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1906                 reg |= dwc->u1u2;
1907                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1908
1909                 dwc->u1u2 = 0;
1910         }
1911 }
1912
1913 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1914                 const struct dwc3_event_depevt *event)
1915 {
1916         struct dwc3_ep          *dep;
1917         u8                      epnum = event->endpoint_number;
1918
1919         dep = dwc->eps[epnum];
1920
1921         if (!(dep->flags & DWC3_EP_ENABLED))
1922                 return;
1923
1924         if (epnum == 0 || epnum == 1) {
1925                 dwc3_ep0_interrupt(dwc, event);
1926                 return;
1927         }
1928
1929         switch (event->endpoint_event) {
1930         case DWC3_DEPEVT_XFERCOMPLETE:
1931                 dep->resource_index = 0;
1932
1933                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1934                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1935                                         dep->name);
1936                         return;
1937                 }
1938
1939                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1940                 break;
1941         case DWC3_DEPEVT_XFERINPROGRESS:
1942                 dwc3_endpoint_transfer_complete(dwc, dep, event);
1943                 break;
1944         case DWC3_DEPEVT_XFERNOTREADY:
1945                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1946                         dwc3_gadget_start_isoc(dwc, dep, event);
1947                 } else {
1948                         int ret;
1949
1950                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1951                                         dep->name, event->status &
1952                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1953                                         ? "Transfer Active"
1954                                         : "Transfer Not Active");
1955
1956                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1957                         if (!ret || ret == -EBUSY)
1958                                 return;
1959
1960                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1961                                         dep->name);
1962                 }
1963
1964                 break;
1965         case DWC3_DEPEVT_STREAMEVT:
1966                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1967                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1968                                         dep->name);
1969                         return;
1970                 }
1971
1972                 switch (event->status) {
1973                 case DEPEVT_STREAMEVT_FOUND:
1974                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1975                                         event->parameters);
1976
1977                         break;
1978                 case DEPEVT_STREAMEVT_NOTFOUND:
1979                         /* FALLTHROUGH */
1980                 default:
1981                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1982                 }
1983                 break;
1984         case DWC3_DEPEVT_RXTXFIFOEVT:
1985                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1986                 break;
1987         case DWC3_DEPEVT_EPCMDCMPLT:
1988                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1989                 break;
1990         }
1991 }
1992
1993 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1994 {
1995         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1996                 spin_unlock(&dwc->lock);
1997                 dwc->gadget_driver->disconnect(&dwc->gadget);
1998                 spin_lock(&dwc->lock);
1999         }
2000 }
2001
2002 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2003 {
2004         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2005                 spin_unlock(&dwc->lock);
2006                 dwc->gadget_driver->suspend(&dwc->gadget);
2007                 spin_lock(&dwc->lock);
2008         }
2009 }
2010
2011 static void dwc3_resume_gadget(struct dwc3 *dwc)
2012 {
2013         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2014                 spin_unlock(&dwc->lock);
2015                 dwc->gadget_driver->resume(&dwc->gadget);
2016         }
2017 }
2018
2019 static void dwc3_reset_gadget(struct dwc3 *dwc)
2020 {
2021         if (!dwc->gadget_driver)
2022                 return;
2023
2024         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2025                 spin_unlock(&dwc->lock);
2026                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2027                 spin_lock(&dwc->lock);
2028         }
2029 }
2030
2031 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2032 {
2033         struct dwc3_ep *dep;
2034         struct dwc3_gadget_ep_cmd_params params;
2035         u32 cmd;
2036         int ret;
2037
2038         dep = dwc->eps[epnum];
2039
2040         if (!dep->resource_index)
2041                 return;
2042
2043         /*
2044          * NOTICE: We are violating what the Databook says about the
2045          * EndTransfer command. Ideally we would _always_ wait for the
2046          * EndTransfer Command Completion IRQ, but that's causing too
2047          * much trouble synchronizing between us and gadget driver.
2048          *
2049          * We have discussed this with the IP Provider and it was
2050          * suggested to giveback all requests here, but give HW some
2051          * extra time to synchronize with the interconnect. We're using
2052          * an arbitraty 100us delay for that.
2053          *
2054          * Note also that a similar handling was tested by Synopsys
2055          * (thanks a lot Paul) and nothing bad has come out of it.
2056          * In short, what we're doing is:
2057          *
2058          * - Issue EndTransfer WITH CMDIOC bit set
2059          * - Wait 100us
2060          */
2061
2062         cmd = DWC3_DEPCMD_ENDTRANSFER;
2063         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2064         cmd |= DWC3_DEPCMD_CMDIOC;
2065         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2066         memset(&params, 0, sizeof(params));
2067         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2068         WARN_ON_ONCE(ret);
2069         dep->resource_index = 0;
2070         dep->flags &= ~DWC3_EP_BUSY;
2071         udelay(100);
2072 }
2073
2074 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2075 {
2076         u32 epnum;
2077
2078         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2079                 struct dwc3_ep *dep;
2080
2081                 dep = dwc->eps[epnum];
2082                 if (!dep)
2083                         continue;
2084
2085                 if (!(dep->flags & DWC3_EP_ENABLED))
2086                         continue;
2087
2088                 dwc3_remove_requests(dwc, dep);
2089         }
2090 }
2091
2092 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2093 {
2094         u32 epnum;
2095
2096         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2097                 struct dwc3_ep *dep;
2098                 struct dwc3_gadget_ep_cmd_params params;
2099                 int ret;
2100
2101                 dep = dwc->eps[epnum];
2102                 if (!dep)
2103                         continue;
2104
2105                 if (!(dep->flags & DWC3_EP_STALL))
2106                         continue;
2107
2108                 dep->flags &= ~DWC3_EP_STALL;
2109
2110                 memset(&params, 0, sizeof(params));
2111                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2112                                 DWC3_DEPCMD_CLEARSTALL, &params);
2113                 WARN_ON_ONCE(ret);
2114         }
2115 }
2116
2117 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2118 {
2119         int                     reg;
2120
2121         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2122         reg &= ~DWC3_DCTL_INITU1ENA;
2123         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2124
2125         reg &= ~DWC3_DCTL_INITU2ENA;
2126         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2127
2128         dwc3_disconnect_gadget(dwc);
2129         dwc->start_config_issued = false;
2130
2131         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2132         dwc->setup_packet_pending = false;
2133         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2134 }
2135
2136 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2137 {
2138         u32                     reg;
2139
2140         /*
2141          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2142          * would cause a missing Disconnect Event if there's a
2143          * pending Setup Packet in the FIFO.
2144          *
2145          * There's no suggested workaround on the official Bug
2146          * report, which states that "unless the driver/application
2147          * is doing any special handling of a disconnect event,
2148          * there is no functional issue".
2149          *
2150          * Unfortunately, it turns out that we _do_ some special
2151          * handling of a disconnect event, namely complete all
2152          * pending transfers, notify gadget driver of the
2153          * disconnection, and so on.
2154          *
2155          * Our suggested workaround is to follow the Disconnect
2156          * Event steps here, instead, based on a setup_packet_pending
2157          * flag. Such flag gets set whenever we have a XferNotReady
2158          * event on EP0 and gets cleared on XferComplete for the
2159          * same endpoint.
2160          *
2161          * Refers to:
2162          *
2163          * STAR#9000466709: RTL: Device : Disconnect event not
2164          * generated if setup packet pending in FIFO
2165          */
2166         if (dwc->revision < DWC3_REVISION_188A) {
2167                 if (dwc->setup_packet_pending)
2168                         dwc3_gadget_disconnect_interrupt(dwc);
2169         }
2170
2171         dwc3_reset_gadget(dwc);
2172
2173         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2174         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2175         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2176         dwc->test_mode = false;
2177
2178         dwc3_stop_active_transfers(dwc);
2179         dwc3_clear_stall_all_ep(dwc);
2180         dwc->start_config_issued = false;
2181
2182         /* Reset device address to zero */
2183         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2184         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2185         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2186 }
2187
2188 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2189 {
2190         u32 reg;
2191         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2192
2193         /*
2194          * We change the clock only at SS but I dunno why I would want to do
2195          * this. Maybe it becomes part of the power saving plan.
2196          */
2197
2198         if (speed != DWC3_DSTS_SUPERSPEED)
2199                 return;
2200
2201         /*
2202          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2203          * each time on Connect Done.
2204          */
2205         if (!usb30_clock)
2206                 return;
2207
2208         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2209         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2210         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2211 }
2212
2213 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2214 {
2215         struct dwc3_ep          *dep;
2216         int                     ret;
2217         u32                     reg;
2218         u8                      speed;
2219
2220         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2221         speed = reg & DWC3_DSTS_CONNECTSPD;
2222         dwc->speed = speed;
2223
2224         dwc3_update_ram_clk_sel(dwc, speed);
2225
2226         switch (speed) {
2227         case DWC3_DCFG_SUPERSPEED:
2228                 /*
2229                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2230                  * would cause a missing USB3 Reset event.
2231                  *
2232                  * In such situations, we should force a USB3 Reset
2233                  * event by calling our dwc3_gadget_reset_interrupt()
2234                  * routine.
2235                  *
2236                  * Refers to:
2237                  *
2238                  * STAR#9000483510: RTL: SS : USB3 reset event may
2239                  * not be generated always when the link enters poll
2240                  */
2241                 if (dwc->revision < DWC3_REVISION_190A)
2242                         dwc3_gadget_reset_interrupt(dwc);
2243
2244                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2245                 dwc->gadget.ep0->maxpacket = 512;
2246                 dwc->gadget.speed = USB_SPEED_SUPER;
2247                 break;
2248         case DWC3_DCFG_HIGHSPEED:
2249                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2250                 dwc->gadget.ep0->maxpacket = 64;
2251                 dwc->gadget.speed = USB_SPEED_HIGH;
2252                 break;
2253         case DWC3_DCFG_FULLSPEED2:
2254         case DWC3_DCFG_FULLSPEED1:
2255                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2256                 dwc->gadget.ep0->maxpacket = 64;
2257                 dwc->gadget.speed = USB_SPEED_FULL;
2258                 break;
2259         case DWC3_DCFG_LOWSPEED:
2260                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2261                 dwc->gadget.ep0->maxpacket = 8;
2262                 dwc->gadget.speed = USB_SPEED_LOW;
2263                 break;
2264         }
2265
2266         /* Enable USB2 LPM Capability */
2267
2268         if ((dwc->revision > DWC3_REVISION_194A)
2269                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2270                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2271                 reg |= DWC3_DCFG_LPM_CAP;
2272                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2273
2274                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2275                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2276
2277                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2278
2279                 /*
2280                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2281                  * DCFG.LPMCap is set, core responses with an ACK and the
2282                  * BESL value in the LPM token is less than or equal to LPM
2283                  * NYET threshold.
2284                  */
2285                 if (dwc->revision < DWC3_REVISION_240A  && dwc->has_lpm_erratum)
2286                         WARN(true, "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2287
2288                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2289                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2290
2291                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2292         } else {
2293                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2294                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2295                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2296         }
2297
2298         dep = dwc->eps[0];
2299         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2300                         false);
2301         if (ret) {
2302                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2303                 return;
2304         }
2305
2306         dep = dwc->eps[1];
2307         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2308                         false);
2309         if (ret) {
2310                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2311                 return;
2312         }
2313
2314         /*
2315          * Configure PHY via GUSB3PIPECTLn if required.
2316          *
2317          * Update GTXFIFOSIZn
2318          *
2319          * In both cases reset values should be sufficient.
2320          */
2321 }
2322
2323 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2324 {
2325         /*
2326          * TODO take core out of low power mode when that's
2327          * implemented.
2328          */
2329
2330         dwc->gadget_driver->resume(&dwc->gadget);
2331 }
2332
2333 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2334                 unsigned int evtinfo)
2335 {
2336         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2337         unsigned int            pwropt;
2338
2339         /*
2340          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2341          * Hibernation mode enabled which would show up when device detects
2342          * host-initiated U3 exit.
2343          *
2344          * In that case, device will generate a Link State Change Interrupt
2345          * from U3 to RESUME which is only necessary if Hibernation is
2346          * configured in.
2347          *
2348          * There are no functional changes due to such spurious event and we
2349          * just need to ignore it.
2350          *
2351          * Refers to:
2352          *
2353          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2354          * operational mode
2355          */
2356         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2357         if ((dwc->revision < DWC3_REVISION_250A) &&
2358                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2359                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2360                                 (next == DWC3_LINK_STATE_RESUME)) {
2361                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2362                         return;
2363                 }
2364         }
2365
2366         /*
2367          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2368          * on the link partner, the USB session might do multiple entry/exit
2369          * of low power states before a transfer takes place.
2370          *
2371          * Due to this problem, we might experience lower throughput. The
2372          * suggested workaround is to disable DCTL[12:9] bits if we're
2373          * transitioning from U1/U2 to U0 and enable those bits again
2374          * after a transfer completes and there are no pending transfers
2375          * on any of the enabled endpoints.
2376          *
2377          * This is the first half of that workaround.
2378          *
2379          * Refers to:
2380          *
2381          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2382          * core send LGO_Ux entering U0
2383          */
2384         if (dwc->revision < DWC3_REVISION_183A) {
2385                 if (next == DWC3_LINK_STATE_U0) {
2386                         u32     u1u2;
2387                         u32     reg;
2388
2389                         switch (dwc->link_state) {
2390                         case DWC3_LINK_STATE_U1:
2391                         case DWC3_LINK_STATE_U2:
2392                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2393                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2394                                                 | DWC3_DCTL_ACCEPTU2ENA
2395                                                 | DWC3_DCTL_INITU1ENA
2396                                                 | DWC3_DCTL_ACCEPTU1ENA);
2397
2398                                 if (!dwc->u1u2)
2399                                         dwc->u1u2 = reg & u1u2;
2400
2401                                 reg &= ~u1u2;
2402
2403                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2404                                 break;
2405                         default:
2406                                 /* do nothing */
2407                                 break;
2408                         }
2409                 }
2410         }
2411
2412         switch (next) {
2413         case DWC3_LINK_STATE_U1:
2414                 if (dwc->speed == USB_SPEED_SUPER)
2415                         dwc3_suspend_gadget(dwc);
2416                 break;
2417         case DWC3_LINK_STATE_U2:
2418         case DWC3_LINK_STATE_U3:
2419                 dwc3_suspend_gadget(dwc);
2420                 break;
2421         case DWC3_LINK_STATE_RESUME:
2422                 dwc3_resume_gadget(dwc);
2423                 break;
2424         default:
2425                 /* do nothing */
2426                 break;
2427         }
2428
2429         dwc->link_state = next;
2430 }
2431
2432 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2433                 unsigned int evtinfo)
2434 {
2435         unsigned int is_ss = evtinfo & (1UL << 4);
2436
2437         /**
2438          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2439          * have a known issue which can cause USB CV TD.9.23 to fail
2440          * randomly.
2441          *
2442          * Because of this issue, core could generate bogus hibernation
2443          * events which SW needs to ignore.
2444          *
2445          * Refers to:
2446          *
2447          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2448          * Device Fallback from SuperSpeed
2449          */
2450         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2451                 return;
2452
2453         /* enter hibernation here */
2454 }
2455
2456 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2457                 const struct dwc3_event_devt *event)
2458 {
2459         switch (event->type) {
2460         case DWC3_DEVICE_EVENT_DISCONNECT:
2461                 dwc3_gadget_disconnect_interrupt(dwc);
2462                 break;
2463         case DWC3_DEVICE_EVENT_RESET:
2464                 dwc3_gadget_reset_interrupt(dwc);
2465                 break;
2466         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2467                 dwc3_gadget_conndone_interrupt(dwc);
2468                 break;
2469         case DWC3_DEVICE_EVENT_WAKEUP:
2470                 dwc3_gadget_wakeup_interrupt(dwc);
2471                 break;
2472         case DWC3_DEVICE_EVENT_HIBER_REQ:
2473                 if (!dwc->has_hibernation) {
2474                         WARN(1 ,"unexpected hibernation event\n");
2475                         break;
2476                 }
2477                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2478                 break;
2479         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2480                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2481                 break;
2482         case DWC3_DEVICE_EVENT_EOPF:
2483                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2484                 break;
2485         case DWC3_DEVICE_EVENT_SOF:
2486                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2487                 break;
2488         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2489                 dev_vdbg(dwc->dev, "Erratic Error\n");
2490                 break;
2491         case DWC3_DEVICE_EVENT_CMD_CMPL:
2492                 dev_vdbg(dwc->dev, "Command Complete\n");
2493                 break;
2494         case DWC3_DEVICE_EVENT_OVERFLOW:
2495                 dev_vdbg(dwc->dev, "Overflow\n");
2496                 break;
2497         default:
2498                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2499         }
2500 }
2501
2502 static void dwc3_process_event_entry(struct dwc3 *dwc,
2503                 const union dwc3_event *event)
2504 {
2505         /* Endpoint IRQ, handle it and return early */
2506         if (event->type.is_devspec == 0) {
2507                 /* depevt */
2508                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2509         }
2510
2511         switch (event->type.type) {
2512         case DWC3_EVENT_TYPE_DEV:
2513                 dwc3_gadget_interrupt(dwc, &event->devt);
2514                 break;
2515         /* REVISIT what to do with Carkit and I2C events ? */
2516         default:
2517                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2518         }
2519 }
2520
2521 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2522 {
2523         struct dwc3_event_buffer *evt;
2524         irqreturn_t ret = IRQ_NONE;
2525         int left;
2526         u32 reg;
2527
2528         evt = dwc->ev_buffs[buf];
2529         left = evt->count;
2530
2531         if (!(evt->flags & DWC3_EVENT_PENDING))
2532                 return IRQ_NONE;
2533
2534         while (left > 0) {
2535                 union dwc3_event event;
2536
2537                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2538
2539                 dwc3_process_event_entry(dwc, &event);
2540
2541                 /*
2542                  * FIXME we wrap around correctly to the next entry as
2543                  * almost all entries are 4 bytes in size. There is one
2544                  * entry which has 12 bytes which is a regular entry
2545                  * followed by 8 bytes data. ATM I don't know how
2546                  * things are organized if we get next to the a
2547                  * boundary so I worry about that once we try to handle
2548                  * that.
2549                  */
2550                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2551                 left -= 4;
2552
2553                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2554         }
2555
2556         evt->count = 0;
2557         evt->flags &= ~DWC3_EVENT_PENDING;
2558         ret = IRQ_HANDLED;
2559
2560         /* Unmask interrupt */
2561         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2562         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2563         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2564
2565         return ret;
2566 }
2567
2568 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2569 {
2570         struct dwc3 *dwc = _dwc;
2571         unsigned long flags;
2572         irqreturn_t ret = IRQ_NONE;
2573         int i;
2574
2575         spin_lock_irqsave(&dwc->lock, flags);
2576
2577         for (i = 0; i < dwc->num_event_buffers; i++)
2578                 ret |= dwc3_process_event_buf(dwc, i);
2579
2580         spin_unlock_irqrestore(&dwc->lock, flags);
2581
2582         return ret;
2583 }
2584
2585 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2586 {
2587         struct dwc3_event_buffer *evt;
2588         u32 count;
2589         u32 reg;
2590
2591         evt = dwc->ev_buffs[buf];
2592
2593         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2594         count &= DWC3_GEVNTCOUNT_MASK;
2595         if (!count)
2596                 return IRQ_NONE;
2597
2598         evt->count = count;
2599         evt->flags |= DWC3_EVENT_PENDING;
2600
2601         /* Mask interrupt */
2602         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2603         reg |= DWC3_GEVNTSIZ_INTMASK;
2604         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2605
2606         return IRQ_WAKE_THREAD;
2607 }
2608
2609 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2610 {
2611         struct dwc3                     *dwc = _dwc;
2612         int                             i;
2613         irqreturn_t                     ret = IRQ_NONE;
2614
2615         spin_lock(&dwc->lock);
2616
2617         for (i = 0; i < dwc->num_event_buffers; i++) {
2618                 irqreturn_t status;
2619
2620                 status = dwc3_check_event_buf(dwc, i);
2621                 if (status == IRQ_WAKE_THREAD)
2622                         ret = status;
2623         }
2624
2625         spin_unlock(&dwc->lock);
2626
2627         return ret;
2628 }
2629
2630 /**
2631  * dwc3_gadget_init - Initializes gadget related registers
2632  * @dwc: pointer to our controller context structure
2633  *
2634  * Returns 0 on success otherwise negative errno.
2635  */
2636 int dwc3_gadget_init(struct dwc3 *dwc)
2637 {
2638         int                                     ret;
2639
2640         dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
2641                                         (unsigned long *)&dwc->ctrl_req_addr);
2642         if (!dwc->ctrl_req) {
2643                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2644                 ret = -ENOMEM;
2645                 goto err0;
2646         }
2647
2648         dwc->ep0_trb = dma_alloc_coherent(sizeof(*dwc->ep0_trb) * 2,
2649                                           (unsigned long *)&dwc->ep0_trb_addr);
2650         if (!dwc->ep0_trb) {
2651                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2652                 ret = -ENOMEM;
2653                 goto err1;
2654         }
2655
2656         dwc->setup_buf = memalign(CONFIG_SYS_CACHELINE_SIZE,
2657                                   DWC3_EP0_BOUNCE_SIZE);
2658         if (!dwc->setup_buf) {
2659                 ret = -ENOMEM;
2660                 goto err2;
2661         }
2662
2663         dwc->ep0_bounce = dma_alloc_coherent(DWC3_EP0_BOUNCE_SIZE,
2664                                         (unsigned long *)&dwc->ep0_bounce_addr);
2665         if (!dwc->ep0_bounce) {
2666                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2667                 ret = -ENOMEM;
2668                 goto err3;
2669         }
2670
2671         dwc->gadget.ops                 = &dwc3_gadget_ops;
2672         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2673         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2674         dwc->gadget.name                = "dwc3-gadget";
2675
2676         /*
2677          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2678          * on ep out.
2679          */
2680         dwc->gadget.quirk_ep_out_aligned_size = true;
2681
2682         /*
2683          * REVISIT: Here we should clear all pending IRQs to be
2684          * sure we're starting from a well known location.
2685          */
2686
2687         ret = dwc3_gadget_init_endpoints(dwc);
2688         if (ret)
2689                 goto err4;
2690
2691         ret = usb_add_gadget_udc((struct device *)dwc->dev, &dwc->gadget);
2692         if (ret) {
2693                 dev_err(dwc->dev, "failed to register udc\n");
2694                 goto err4;
2695         }
2696
2697         return 0;
2698
2699 err4:
2700         dwc3_gadget_free_endpoints(dwc);
2701         dma_free_coherent(dwc->ep0_bounce);
2702
2703 err3:
2704         kfree(dwc->setup_buf);
2705
2706 err2:
2707         dma_free_coherent(dwc->ep0_trb);
2708
2709 err1:
2710         dma_free_coherent(dwc->ctrl_req);
2711
2712 err0:
2713         return ret;
2714 }
2715
2716 /* -------------------------------------------------------------------------- */
2717
2718 void dwc3_gadget_exit(struct dwc3 *dwc)
2719 {
2720         usb_del_gadget_udc(&dwc->gadget);
2721
2722         dwc3_gadget_free_endpoints(dwc);
2723
2724         dma_free_coherent(dwc->ep0_bounce);
2725
2726         kfree(dwc->setup_buf);
2727
2728         dma_free_coherent(dwc->ep0_trb);
2729
2730         dma_free_coherent(dwc->ctrl_req);
2731 }
2732
2733 /**
2734  * dwc3_gadget_uboot_handle_interrupt - handle dwc3 gadget interrupt
2735  * @dwc: struct dwce *
2736  *
2737  * Handles ep0 and gadget interrupt
2738  *
2739  * Should be called from dwc3 core.
2740  */
2741 void dwc3_gadget_uboot_handle_interrupt(struct dwc3 *dwc)
2742 {
2743         int ret = dwc3_interrupt(0, dwc);
2744
2745         if (ret == IRQ_WAKE_THREAD) {
2746                 int i;
2747                 struct dwc3_event_buffer *evt;
2748
2749                 dwc3_thread_interrupt(0, dwc);
2750
2751                 /* Clean + Invalidate the buffers after touching them */
2752                 for (i = 0; i < dwc->num_event_buffers; i++) {
2753                         evt = dwc->ev_buffs[i];
2754                         dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
2755                 }
2756         }
2757 }