1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
51 case USB_TEST_SE0_NAK:
53 case USB_TEST_FORCE_ENABLE:
60 dwc3_gadget_dctl_write_safe(dwc, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
128 /* wait for a change in DSTS */
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
133 if (DWC3_DSTS_USBLNKST(reg) == state)
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
150 static void dwc3_ep_inc_trb(u8 *index)
153 if (*index == (DWC3_TRB_NUM - 1))
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
163 dwc3_ep_inc_trb(&dep->trb_enqueue);
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
172 dwc3_ep_inc_trb(&dep->trb_dequeue);
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176 struct dwc3_request *req, int status)
178 struct dwc3 *dwc = dep->dwc;
180 list_del(&req->list);
182 req->needs_extra_trb = false;
184 if (req->request.status == -EINPROGRESS)
185 req->request.status = status;
188 usb_gadget_unmap_request_by_dev(dwc->sysdev,
189 &req->request, req->direction);
192 trace_dwc3_gadget_giveback(req);
195 pm_runtime_put(dwc->dev);
199 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200 * @dep: The endpoint to whom the request belongs to
201 * @req: The request we're giving back
202 * @status: completion code for the request
204 * Must be called with controller's lock held and interrupts disabled. This
205 * function will unmap @req and call its ->complete() callback to notify upper
206 * layers that it has completed.
208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
211 struct dwc3 *dwc = dep->dwc;
213 dwc3_gadget_del_and_unmap_request(dep, req, status);
214 req->status = DWC3_REQUEST_STATUS_COMPLETED;
216 spin_unlock(&dwc->lock);
217 usb_gadget_giveback_request(&dep->endpoint, &req->request);
218 spin_lock(&dwc->lock);
222 * dwc3_send_gadget_generic_command - issue a generic command for the controller
223 * @dwc: pointer to the controller context
224 * @cmd: the command to be issued
225 * @param: command parameter
227 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228 * and wait for its completion.
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
238 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
239 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
242 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
243 if (!(reg & DWC3_DGCMD_CMDACT)) {
244 status = DWC3_DGCMD_STATUS(reg);
256 trace_dwc3_gadget_generic_cmd(cmd, param, status);
261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
264 * dwc3_send_gadget_ep_cmd - issue an endpoint command
265 * @dep: the endpoint to which the command is going to be issued
266 * @cmd: the command to be issued
267 * @params: parameters to the command
269 * Caller should handle locking. This function will issue @cmd with given
270 * @params to @dep and wait for its completion.
272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
273 struct dwc3_gadget_ep_cmd_params *params)
275 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
276 struct dwc3 *dwc = dep->dwc;
278 u32 saved_config = 0;
285 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
286 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
289 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
290 * settings. Restore them after the command is completed.
292 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
294 if (dwc->gadget->speed <= USB_SPEED_HIGH) {
295 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
296 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
297 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
298 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
301 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
302 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
303 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
307 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
310 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
314 * Initiate remote wakeup if the link state is in U3 when
315 * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
316 * link state is in U1/U2, no remote wakeup is needed. The Start
317 * Transfer command will initiate the link recovery.
319 link_state = dwc3_gadget_get_link_state(dwc);
320 switch (link_state) {
321 case DWC3_LINK_STATE_U2:
322 if (dwc->gadget->speed >= USB_SPEED_SUPER)
326 case DWC3_LINK_STATE_U3:
327 ret = __dwc3_gadget_wakeup(dwc);
328 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
334 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
335 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
336 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
339 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
340 * not relying on XferNotReady, we can make use of a special "No
341 * Response Update Transfer" command where we should clear both CmdAct
344 * With this, we don't need to wait for command completion and can
345 * straight away issue further commands to the endpoint.
347 * NOTICE: We're making an assumption that control endpoints will never
348 * make use of Update Transfer command. This is a safe assumption
349 * because we can never have more than one request at a time with
350 * Control Endpoints. If anybody changes that assumption, this chunk
351 * needs to be updated accordingly.
353 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
354 !usb_endpoint_xfer_isoc(desc))
355 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
357 cmd |= DWC3_DEPCMD_CMDACT;
359 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
361 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
362 if (!(reg & DWC3_DEPCMD_CMDACT)) {
363 cmd_status = DWC3_DEPCMD_STATUS(reg);
365 switch (cmd_status) {
369 case DEPEVT_TRANSFER_NO_RESOURCE:
370 dev_WARN(dwc->dev, "No resource for %s\n",
374 case DEPEVT_TRANSFER_BUS_EXPIRY:
376 * SW issues START TRANSFER command to
377 * isochronous ep with future frame interval. If
378 * future interval time has already passed when
379 * core receives the command, it will respond
380 * with an error status of 'Bus Expiry'.
382 * Instead of always returning -EINVAL, let's
383 * give a hint to the gadget driver that this is
384 * the case by returning -EAGAIN.
389 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
398 cmd_status = -ETIMEDOUT;
401 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
403 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
405 dep->flags |= DWC3_EP_TRANSFER_STARTED;
407 if (ret != -ETIMEDOUT)
408 dwc3_gadget_ep_get_transfer_index(dep);
412 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
414 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
420 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
422 struct dwc3 *dwc = dep->dwc;
423 struct dwc3_gadget_ep_cmd_params params;
424 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
427 * As of core revision 2.60a the recommended programming model
428 * is to set the ClearPendIN bit when issuing a Clear Stall EP
429 * command for IN endpoints. This is to prevent an issue where
430 * some (non-compliant) hosts may not send ACK TPs for pending
431 * IN transfers due to a mishandled error condition. Synopsys
434 if (dep->direction &&
435 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
436 (dwc->gadget->speed >= USB_SPEED_SUPER))
437 cmd |= DWC3_DEPCMD_CLEARPENDIN;
439 memset(¶ms, 0, sizeof(params));
441 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
444 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
445 struct dwc3_trb *trb)
447 u32 offset = (char *) trb - (char *) dep->trb_pool;
449 return dep->trb_pool_dma + offset;
452 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
454 struct dwc3 *dwc = dep->dwc;
459 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
460 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
461 &dep->trb_pool_dma, GFP_KERNEL);
462 if (!dep->trb_pool) {
463 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
471 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
473 struct dwc3 *dwc = dep->dwc;
475 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
476 dep->trb_pool, dep->trb_pool_dma);
478 dep->trb_pool = NULL;
479 dep->trb_pool_dma = 0;
482 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
484 struct dwc3_gadget_ep_cmd_params params;
486 memset(¶ms, 0x00, sizeof(params));
488 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
490 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
495 * dwc3_gadget_start_config - configure ep resources
496 * @dep: endpoint that is being enabled
498 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
499 * completion, it will set Transfer Resource for all available endpoints.
501 * The assignment of transfer resources cannot perfectly follow the data book
502 * due to the fact that the controller driver does not have all knowledge of the
503 * configuration in advance. It is given this information piecemeal by the
504 * composite gadget framework after every SET_CONFIGURATION and
505 * SET_INTERFACE. Trying to follow the databook programming model in this
506 * scenario can cause errors. For two reasons:
508 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
509 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
510 * incorrect in the scenario of multiple interfaces.
512 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
513 * endpoint on alt setting (8.1.6).
515 * The following simplified method is used instead:
517 * All hardware endpoints can be assigned a transfer resource and this setting
518 * will stay persistent until either a core reset or hibernation. So whenever we
519 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
520 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
521 * guaranteed that there are as many transfer resources as endpoints.
523 * This function is called for each endpoint when it is being enabled but is
524 * triggered only when called for EP0-out, which always happens first, and which
525 * should only happen in one of the above conditions.
527 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
529 struct dwc3_gadget_ep_cmd_params params;
538 memset(¶ms, 0x00, sizeof(params));
539 cmd = DWC3_DEPCMD_DEPSTARTCFG;
542 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
546 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
547 struct dwc3_ep *dep = dwc->eps[i];
552 ret = dwc3_gadget_set_xfer_resource(dep);
560 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
562 const struct usb_ss_ep_comp_descriptor *comp_desc;
563 const struct usb_endpoint_descriptor *desc;
564 struct dwc3_gadget_ep_cmd_params params;
565 struct dwc3 *dwc = dep->dwc;
567 comp_desc = dep->endpoint.comp_desc;
568 desc = dep->endpoint.desc;
570 memset(¶ms, 0x00, sizeof(params));
572 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
573 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
575 /* Burst size is only needed in SuperSpeed mode */
576 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
577 u32 burst = dep->endpoint.maxburst;
579 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
582 params.param0 |= action;
583 if (action == DWC3_DEPCFG_ACTION_RESTORE)
584 params.param2 |= dep->saved_state;
586 if (usb_endpoint_xfer_control(desc))
587 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
589 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
590 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
592 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
593 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
594 | DWC3_DEPCFG_XFER_COMPLETE_EN
595 | DWC3_DEPCFG_STREAM_EVENT_EN;
596 dep->stream_capable = true;
599 if (!usb_endpoint_xfer_control(desc))
600 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
603 * We are doing 1:1 mapping for endpoints, meaning
604 * Physical Endpoints 2 maps to Logical Endpoint 2 and
605 * so on. We consider the direction bit as part of the physical
606 * endpoint number. So USB endpoint 0x81 is 0x03.
608 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
611 * We must use the lower 16 TX FIFOs even though
615 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
617 if (desc->bInterval) {
621 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
623 * NOTE: The programming guide incorrectly stated bInterval_m1
624 * must be set to 0 when operating in fullspeed. Internally the
625 * controller does not have this limitation. See DWC_usb3x
626 * programming guide section 3.2.2.1.
628 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
630 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
631 dwc->gadget->speed == USB_SPEED_FULL)
632 dep->interval = desc->bInterval;
634 dep->interval = 1 << (desc->bInterval - 1);
636 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
639 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
642 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
646 * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
647 * @dwc: pointer to the DWC3 context
648 * @nfifos: number of fifos to calculate for
650 * Calculates the size value based on the equation below:
652 * DWC3 revision 280A and prior:
653 * fifo_size = mult * (max_packet / mdwidth) + 1;
655 * DWC3 revision 290A and onwards:
656 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
658 * The max packet size is set to 1024, as the txfifo requirements mainly apply
659 * to super speed USB use cases. However, it is safe to overestimate the fifo
660 * allocations for other scenarios, i.e. high speed USB.
662 static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
664 int max_packet = 1024;
668 mdwidth = dwc3_mdwidth(dwc);
670 /* MDWIDTH is represented in bits, we need it in bytes */
673 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
674 fifo_size = mult * (max_packet / mdwidth) + 1;
676 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
681 * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation
682 * @dwc: pointer to the DWC3 context
684 * Iterates through all the endpoint registers and clears the previous txfifo
687 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
694 if (!dwc->do_fifo_resize)
697 /* Read ep0IN related TXFIFO size */
699 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
700 if (DWC3_IP_IS(DWC3))
701 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
703 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
705 dwc->last_fifo_depth = fifo_depth;
706 /* Clear existing TXFIFO for all IN eps except ep0 */
707 for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
710 /* Don't change TXFRAMNUM on usb31 version */
711 size = DWC3_IP_IS(DWC3) ? 0 :
712 dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
713 DWC31_GTXFIFOSIZ_TXFRAMNUM;
715 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
716 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
718 dwc->num_ep_resized = 0;
722 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
723 * @dwc: pointer to our context structure
725 * This function will a best effort FIFO allocation in order
726 * to improve FIFO usage and throughput, while still allowing
727 * us to enable as many endpoints as possible.
729 * Keep in mind that this operation will be highly dependent
730 * on the configured size for RAM1 - which contains TxFifo -,
731 * the amount of endpoints enabled on coreConsultant tool, and
732 * the width of the Master Bus.
734 * In general, FIFO depths are represented with the following equation:
736 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
738 * In conjunction with dwc3_gadget_check_config(), this resizing logic will
739 * ensure that all endpoints will have enough internal memory for one max
740 * packet per endpoint.
742 static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
744 struct dwc3 *dwc = dep->dwc;
755 if (!dwc->do_fifo_resize)
758 /* resize IN endpoints except ep0 */
759 if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
762 /* bail if already resized */
763 if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
766 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
768 if ((dep->endpoint.maxburst > 1 &&
769 usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
770 usb_endpoint_xfer_isoc(dep->endpoint.desc))
773 if (dep->endpoint.maxburst > 6 &&
774 usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
775 num_fifos = dwc->tx_fifo_resize_max_num;
777 /* FIFO size for a single buffer */
778 fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
780 /* Calculate the number of remaining EPs w/o any FIFO */
781 num_in_ep = dwc->max_cfg_eps;
782 num_in_ep -= dwc->num_ep_resized;
784 /* Reserve at least one FIFO for the number of IN EPs */
785 min_depth = num_in_ep * (fifo + 1);
786 remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
787 remaining = max_t(int, 0, remaining);
789 * We've already reserved 1 FIFO per EP, so check what we can fit in
790 * addition to it. If there is not enough remaining space, allocate
791 * all the remaining space to the EP.
793 fifo_size = (num_fifos - 1) * fifo;
794 if (remaining < fifo_size)
795 fifo_size = remaining;
798 /* Last increment according to the TX FIFO size equation */
801 /* Check if TXFIFOs start at non-zero addr */
802 tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
803 fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
805 fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
806 if (DWC3_IP_IS(DWC3))
807 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
809 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
811 /* Check fifo size allocation doesn't exceed available RAM size. */
812 if (dwc->last_fifo_depth >= ram1_depth) {
813 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
814 dwc->last_fifo_depth, ram1_depth,
815 dep->endpoint.name, fifo_size);
816 if (DWC3_IP_IS(DWC3))
817 fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
819 fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
821 dwc->last_fifo_depth -= fifo_size;
825 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
826 dep->flags |= DWC3_EP_TXFIFO_RESIZED;
827 dwc->num_ep_resized++;
833 * __dwc3_gadget_ep_enable - initializes a hw endpoint
834 * @dep: endpoint to be initialized
835 * @action: one of INIT, MODIFY or RESTORE
837 * Caller should take care of locking. Execute all necessary commands to
838 * initialize a HW endpoint so it can be used by a gadget driver.
840 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
842 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
843 struct dwc3 *dwc = dep->dwc;
848 if (!(dep->flags & DWC3_EP_ENABLED)) {
849 ret = dwc3_gadget_resize_tx_fifos(dep);
853 ret = dwc3_gadget_start_config(dep);
858 ret = dwc3_gadget_set_ep_config(dep, action);
862 if (!(dep->flags & DWC3_EP_ENABLED)) {
863 struct dwc3_trb *trb_st_hw;
864 struct dwc3_trb *trb_link;
866 dep->type = usb_endpoint_type(desc);
867 dep->flags |= DWC3_EP_ENABLED;
869 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
870 reg |= DWC3_DALEPENA_EP(dep->number);
871 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
873 if (usb_endpoint_xfer_control(desc))
876 /* Initialize the TRB ring */
877 dep->trb_dequeue = 0;
878 dep->trb_enqueue = 0;
879 memset(dep->trb_pool, 0,
880 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
882 /* Link TRB. The HWO bit is never reset */
883 trb_st_hw = &dep->trb_pool[0];
885 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
886 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
887 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
888 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
889 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
893 * Issue StartTransfer here with no-op TRB so we can always rely on No
894 * Response Update Transfer command.
896 if (usb_endpoint_xfer_bulk(desc) ||
897 usb_endpoint_xfer_int(desc)) {
898 struct dwc3_gadget_ep_cmd_params params;
899 struct dwc3_trb *trb;
903 memset(¶ms, 0, sizeof(params));
904 trb = &dep->trb_pool[0];
905 trb_dma = dwc3_trb_dma_offset(dep, trb);
907 params.param0 = upper_32_bits(trb_dma);
908 params.param1 = lower_32_bits(trb_dma);
910 cmd = DWC3_DEPCMD_STARTTRANSFER;
912 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
916 if (dep->stream_capable) {
918 * For streams, at start, there maybe a race where the
919 * host primes the endpoint before the function driver
920 * queues a request to initiate a stream. In that case,
921 * the controller will not see the prime to generate the
922 * ERDY and start stream. To workaround this, issue a
923 * no-op TRB as normal, but end it immediately. As a
924 * result, when the function driver queues the request,
925 * the next START_TRANSFER command will cause the
926 * controller to generate an ERDY to initiate the
929 dwc3_stop_active_transfer(dep, true, true);
932 * All stream eps will reinitiate stream on NoStream
933 * rejection until we can determine that the host can
934 * prime after the first transfer.
936 * However, if the controller is capable of
937 * TXF_FLUSH_BYPASS, then IN direction endpoints will
938 * automatically restart the stream without the driver
941 if (!dep->direction ||
942 !(dwc->hwparams.hwparams9 &
943 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
944 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
949 trace_dwc3_gadget_ep_enable(dep);
954 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
956 struct dwc3_request *req;
958 dwc3_stop_active_transfer(dep, true, false);
960 /* - giveback all requests to gadget driver */
961 while (!list_empty(&dep->started_list)) {
962 req = next_request(&dep->started_list);
964 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
967 while (!list_empty(&dep->pending_list)) {
968 req = next_request(&dep->pending_list);
970 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
973 while (!list_empty(&dep->cancelled_list)) {
974 req = next_request(&dep->cancelled_list);
976 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
981 * __dwc3_gadget_ep_disable - disables a hw endpoint
982 * @dep: the endpoint to disable
984 * This function undoes what __dwc3_gadget_ep_enable did and also removes
985 * requests which are currently being processed by the hardware and those which
986 * are not yet scheduled.
988 * Caller should take care of locking.
990 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
992 struct dwc3 *dwc = dep->dwc;
995 trace_dwc3_gadget_ep_disable(dep);
997 /* make sure HW endpoint isn't stalled */
998 if (dep->flags & DWC3_EP_STALL)
999 __dwc3_gadget_ep_set_halt(dep, 0, false);
1001 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1002 reg &= ~DWC3_DALEPENA_EP(dep->number);
1003 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1005 /* Clear out the ep descriptors for non-ep0 */
1006 if (dep->number > 1) {
1007 dep->endpoint.comp_desc = NULL;
1008 dep->endpoint.desc = NULL;
1011 dwc3_remove_requests(dwc, dep);
1013 dep->stream_capable = false;
1015 dep->flags &= DWC3_EP_TXFIFO_RESIZED;
1020 /* -------------------------------------------------------------------------- */
1022 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1023 const struct usb_endpoint_descriptor *desc)
1028 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1033 /* -------------------------------------------------------------------------- */
1035 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1036 const struct usb_endpoint_descriptor *desc)
1038 struct dwc3_ep *dep;
1040 unsigned long flags;
1043 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1044 pr_debug("dwc3: invalid parameters\n");
1048 if (!desc->wMaxPacketSize) {
1049 pr_debug("dwc3: missing wMaxPacketSize\n");
1053 dep = to_dwc3_ep(ep);
1056 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1057 "%s is already enabled\n",
1061 spin_lock_irqsave(&dwc->lock, flags);
1062 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1063 spin_unlock_irqrestore(&dwc->lock, flags);
1068 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1070 struct dwc3_ep *dep;
1072 unsigned long flags;
1076 pr_debug("dwc3: invalid parameters\n");
1080 dep = to_dwc3_ep(ep);
1083 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1084 "%s is already disabled\n",
1088 spin_lock_irqsave(&dwc->lock, flags);
1089 ret = __dwc3_gadget_ep_disable(dep);
1090 spin_unlock_irqrestore(&dwc->lock, flags);
1095 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1098 struct dwc3_request *req;
1099 struct dwc3_ep *dep = to_dwc3_ep(ep);
1101 req = kzalloc(sizeof(*req), gfp_flags);
1105 req->direction = dep->direction;
1106 req->epnum = dep->number;
1108 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
1110 trace_dwc3_alloc_request(req);
1112 return &req->request;
1115 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1116 struct usb_request *request)
1118 struct dwc3_request *req = to_dwc3_request(request);
1120 trace_dwc3_free_request(req);
1125 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1126 * @dep: The endpoint with the TRB ring
1127 * @index: The index of the current TRB in the ring
1129 * Returns the TRB prior to the one pointed to by the index. If the
1130 * index is 0, we will wrap backwards, skip the link TRB, and return
1131 * the one just before that.
1133 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1138 tmp = DWC3_TRB_NUM - 1;
1140 return &dep->trb_pool[tmp - 1];
1143 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1148 * If the enqueue & dequeue are equal then the TRB ring is either full
1149 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1150 * pending to be processed by the driver.
1152 if (dep->trb_enqueue == dep->trb_dequeue) {
1154 * If there is any request remained in the started_list at
1155 * this point, that means there is no TRB available.
1157 if (!list_empty(&dep->started_list))
1160 return DWC3_TRB_NUM - 1;
1163 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1164 trbs_left &= (DWC3_TRB_NUM - 1);
1166 if (dep->trb_dequeue < dep->trb_enqueue)
1172 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
1173 dma_addr_t dma, unsigned int length, unsigned int chain,
1174 unsigned int node, unsigned int stream_id,
1175 unsigned int short_not_ok, unsigned int no_interrupt,
1176 unsigned int is_last, bool must_interrupt)
1178 struct dwc3 *dwc = dep->dwc;
1179 struct usb_gadget *gadget = dwc->gadget;
1180 enum usb_device_speed speed = gadget->speed;
1182 trb->size = DWC3_TRB_SIZE_LENGTH(length);
1183 trb->bpl = lower_32_bits(dma);
1184 trb->bph = upper_32_bits(dma);
1186 switch (usb_endpoint_type(dep->endpoint.desc)) {
1187 case USB_ENDPOINT_XFER_CONTROL:
1188 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1191 case USB_ENDPOINT_XFER_ISOC:
1193 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1196 * USB Specification 2.0 Section 5.9.2 states that: "If
1197 * there is only a single transaction in the microframe,
1198 * only a DATA0 data packet PID is used. If there are
1199 * two transactions per microframe, DATA1 is used for
1200 * the first transaction data packet and DATA0 is used
1201 * for the second transaction data packet. If there are
1202 * three transactions per microframe, DATA2 is used for
1203 * the first transaction data packet, DATA1 is used for
1204 * the second, and DATA0 is used for the third."
1206 * IOW, we should satisfy the following cases:
1208 * 1) length <= maxpacket
1211 * 2) maxpacket < length <= (2 * maxpacket)
1214 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1215 * - DATA2, DATA1, DATA0
1217 if (speed == USB_SPEED_HIGH) {
1218 struct usb_ep *ep = &dep->endpoint;
1219 unsigned int mult = 2;
1220 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1222 if (length <= (2 * maxp))
1228 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1231 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1234 /* always enable Interrupt on Missed ISOC */
1235 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1238 case USB_ENDPOINT_XFER_BULK:
1239 case USB_ENDPOINT_XFER_INT:
1240 trb->ctrl = DWC3_TRBCTL_NORMAL;
1244 * This is only possible with faulty memory because we
1245 * checked it already :)
1247 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1248 usb_endpoint_type(dep->endpoint.desc));
1252 * Enable Continue on Short Packet
1253 * when endpoint is not a stream capable
1255 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1256 if (!dep->stream_capable)
1257 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1260 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1263 if ((!no_interrupt && !chain) || must_interrupt)
1264 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1267 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1268 else if (dep->stream_capable && is_last)
1269 trb->ctrl |= DWC3_TRB_CTRL_LST;
1271 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1272 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1275 * As per data book 4.2.3.2TRB Control Bit Rules section
1277 * The controller autonomously checks the HWO field of a TRB to determine if the
1278 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1279 * is valid before setting the HWO field to '1'. In most systems, this means that
1280 * software must update the fourth DWORD of a TRB last.
1282 * However there is a possibility of CPU re-ordering here which can cause
1283 * controller to observe the HWO bit set prematurely.
1284 * Add a write memory barrier to prevent CPU re-ordering.
1287 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1289 dwc3_ep_inc_enq(dep);
1291 trace_dwc3_prepare_trb(dep, trb);
1295 * dwc3_prepare_one_trb - setup one TRB from one request
1296 * @dep: endpoint for which this request is prepared
1297 * @req: dwc3_request pointer
1298 * @trb_length: buffer size of the TRB
1299 * @chain: should this TRB be chained to the next?
1300 * @node: only for isochronous endpoints. First TRB needs different type.
1301 * @use_bounce_buffer: set to use bounce buffer
1302 * @must_interrupt: set to interrupt on TRB completion
1304 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1305 struct dwc3_request *req, unsigned int trb_length,
1306 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1307 bool must_interrupt)
1309 struct dwc3_trb *trb;
1311 unsigned int stream_id = req->request.stream_id;
1312 unsigned int short_not_ok = req->request.short_not_ok;
1313 unsigned int no_interrupt = req->request.no_interrupt;
1314 unsigned int is_last = req->request.is_last;
1316 if (use_bounce_buffer)
1317 dma = dep->dwc->bounce_addr;
1318 else if (req->request.num_sgs > 0)
1319 dma = sg_dma_address(req->start_sg);
1321 dma = req->request.dma;
1323 trb = &dep->trb_pool[dep->trb_enqueue];
1326 dwc3_gadget_move_started_request(req);
1328 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1333 __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1334 stream_id, short_not_ok, no_interrupt, is_last,
1338 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1340 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1341 unsigned int rem = req->request.length % maxp;
1343 if ((req->request.length && req->request.zero && !rem &&
1344 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1345 (!req->direction && rem))
1352 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1353 * @dep: The endpoint that the request belongs to
1354 * @req: The request to prepare
1355 * @entry_length: The last SG entry size
1356 * @node: Indicates whether this is not the first entry (for isoc only)
1358 * Return the number of TRBs prepared.
1360 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1361 struct dwc3_request *req, unsigned int entry_length,
1364 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1365 unsigned int rem = req->request.length % maxp;
1366 unsigned int num_trbs = 1;
1368 if (dwc3_needs_extra_trb(dep, req))
1371 if (dwc3_calc_trbs_left(dep) < num_trbs)
1374 req->needs_extra_trb = num_trbs > 1;
1376 /* Prepare a normal TRB */
1377 if (req->direction || req->request.length)
1378 dwc3_prepare_one_trb(dep, req, entry_length,
1379 req->needs_extra_trb, node, false, false);
1381 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1382 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1383 dwc3_prepare_one_trb(dep, req,
1384 req->direction ? 0 : maxp - rem,
1385 false, 1, true, false);
1390 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1391 struct dwc3_request *req)
1393 struct scatterlist *sg = req->start_sg;
1394 struct scatterlist *s;
1396 unsigned int length = req->request.length;
1397 unsigned int remaining = req->request.num_mapped_sgs
1398 - req->num_queued_sgs;
1399 unsigned int num_trbs = req->num_trbs;
1400 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1403 * If we resume preparing the request, then get the remaining length of
1404 * the request and resume where we left off.
1406 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1407 length -= sg_dma_len(s);
1409 for_each_sg(sg, s, remaining, i) {
1410 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1411 unsigned int trb_length;
1412 bool must_interrupt = false;
1413 bool last_sg = false;
1415 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1417 length -= trb_length;
1420 * IOMMU driver is coalescing the list of sgs which shares a
1421 * page boundary into one and giving it to USB driver. With
1422 * this the number of sgs mapped is not equal to the number of
1423 * sgs passed. So mark the chain bit to false if it isthe last
1426 if ((i == remaining - 1) || !length)
1433 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1437 * Look ahead to check if we have enough TRBs for the
1438 * next SG entry. If not, set interrupt on this TRB to
1439 * resume preparing the next SG entry when more TRBs are
1442 if (num_trbs_left == 1 || (needs_extra_trb &&
1443 num_trbs_left <= 2 &&
1444 sg_dma_len(sg_next(s)) >= length))
1445 must_interrupt = true;
1447 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1452 * There can be a situation where all sgs in sglist are not
1453 * queued because of insufficient trb number. To handle this
1454 * case, update start_sg to next sg to be queued, so that
1455 * we have free trbs we can continue queuing from where we
1456 * previously stopped
1459 req->start_sg = sg_next(s);
1461 req->num_queued_sgs++;
1462 req->num_pending_sgs--;
1465 * The number of pending SG entries may not correspond to the
1466 * number of mapped SG entries. If all the data are queued, then
1467 * don't include unused SG entries.
1470 req->num_pending_sgs = 0;
1478 return req->num_trbs - num_trbs;
1481 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1482 struct dwc3_request *req)
1484 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1488 * dwc3_prepare_trbs - setup TRBs from requests
1489 * @dep: endpoint for which requests are being prepared
1491 * The function goes through the requests list and sets up TRBs for the
1492 * transfers. The function returns once there are no more TRBs available or
1493 * it runs out of requests.
1495 * Returns the number of TRBs prepared or negative errno.
1497 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1499 struct dwc3_request *req, *n;
1502 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1505 * We can get in a situation where there's a request in the started list
1506 * but there weren't enough TRBs to fully kick it in the first time
1507 * around, so it has been waiting for more TRBs to be freed up.
1509 * In that case, we should check if we have a request with pending_sgs
1510 * in the started list and prepare TRBs for that request first,
1511 * otherwise we will prepare TRBs completely out of order and that will
1514 list_for_each_entry(req, &dep->started_list, list) {
1515 if (req->num_pending_sgs > 0) {
1516 ret = dwc3_prepare_trbs_sg(dep, req);
1517 if (!ret || req->num_pending_sgs)
1521 if (!dwc3_calc_trbs_left(dep))
1525 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1526 * burst capability may try to read and use TRBs beyond the
1527 * active transfer instead of stopping.
1529 if (dep->stream_capable && req->request.is_last)
1533 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1534 struct dwc3 *dwc = dep->dwc;
1536 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1541 req->sg = req->request.sg;
1542 req->start_sg = req->sg;
1543 req->num_queued_sgs = 0;
1544 req->num_pending_sgs = req->request.num_mapped_sgs;
1546 if (req->num_pending_sgs > 0) {
1547 ret = dwc3_prepare_trbs_sg(dep, req);
1548 if (req->num_pending_sgs)
1551 ret = dwc3_prepare_trbs_linear(dep, req);
1554 if (!ret || !dwc3_calc_trbs_left(dep))
1558 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1559 * burst capability may try to read and use TRBs beyond the
1560 * active transfer instead of stopping.
1562 if (dep->stream_capable && req->request.is_last)
1569 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1571 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1573 struct dwc3_gadget_ep_cmd_params params;
1574 struct dwc3_request *req;
1580 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1581 * This happens when we need to stop and restart a transfer such as in
1582 * the case of reinitiating a stream or retrying an isoc transfer.
1584 ret = dwc3_prepare_trbs(dep);
1588 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1591 * If there's no new TRB prepared and we don't need to restart a
1592 * transfer, there's no need to update the transfer.
1594 if (!ret && !starting)
1597 req = next_request(&dep->started_list);
1599 dep->flags |= DWC3_EP_PENDING_REQUEST;
1603 memset(¶ms, 0, sizeof(params));
1606 params.param0 = upper_32_bits(req->trb_dma);
1607 params.param1 = lower_32_bits(req->trb_dma);
1608 cmd = DWC3_DEPCMD_STARTTRANSFER;
1610 if (dep->stream_capable)
1611 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1613 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1614 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1616 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1617 DWC3_DEPCMD_PARAM(dep->resource_index);
1620 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1622 struct dwc3_request *tmp;
1627 dwc3_stop_active_transfer(dep, true, true);
1629 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1630 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1632 /* If ep isn't started, then there's no end transfer pending */
1633 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1634 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1639 if (dep->stream_capable && req->request.is_last)
1640 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1645 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1649 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1650 return DWC3_DSTS_SOFFN(reg);
1654 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1655 * @dep: isoc endpoint
1657 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1658 * microframe number reported by the XferNotReady event for the future frame
1659 * number to start the isoc transfer.
1661 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1662 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1663 * XferNotReady event are invalid. The driver uses this number to schedule the
1664 * isochronous transfer and passes it to the START TRANSFER command. Because
1665 * this number is invalid, the command may fail. If BIT[15:14] matches the
1666 * internal 16-bit microframe, the START TRANSFER command will pass and the
1667 * transfer will start at the scheduled time, if it is off by 1, the command
1668 * will still pass, but the transfer will start 2 seconds in the future. For all
1669 * other conditions, the START TRANSFER command will fail with bus-expiry.
1671 * In order to workaround this issue, we can test for the correct combination of
1672 * BIT[15:14] by sending START TRANSFER commands with different values of
1673 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1674 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1675 * As the result, within the 4 possible combinations for BIT[15:14], there will
1676 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1677 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1678 * value is the correct combination.
1680 * Since there are only 4 outcomes and the results are ordered, we can simply
1681 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1682 * deduce the smaller successful combination.
1684 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1685 * of BIT[15:14]. The correct combination is as follow:
1687 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1688 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1689 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1690 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1692 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1695 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1701 while (dep->combo_num < 2) {
1702 struct dwc3_gadget_ep_cmd_params params;
1703 u32 test_frame_number;
1707 * Check if we can start isoc transfer on the next interval or
1708 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1710 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1711 test_frame_number |= dep->combo_num << 14;
1712 test_frame_number += max_t(u32, 4, dep->interval);
1714 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1715 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1717 cmd = DWC3_DEPCMD_STARTTRANSFER;
1718 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1719 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1721 /* Redo if some other failure beside bus-expiry is received */
1722 if (cmd_status && cmd_status != -EAGAIN) {
1723 dep->start_cmd_status = 0;
1728 /* Store the first test status */
1729 if (dep->combo_num == 0)
1730 dep->start_cmd_status = cmd_status;
1735 * End the transfer if the START_TRANSFER command is successful
1736 * to wait for the next XferNotReady to test the command again
1738 if (cmd_status == 0) {
1739 dwc3_stop_active_transfer(dep, true, true);
1744 /* test0 and test1 are both completed at this point */
1745 test0 = (dep->start_cmd_status == 0);
1746 test1 = (cmd_status == 0);
1748 if (!test0 && test1)
1750 else if (!test0 && !test1)
1752 else if (test0 && !test1)
1754 else if (test0 && test1)
1757 dep->frame_number &= DWC3_FRNUMBER_MASK;
1758 dep->frame_number |= dep->combo_num << 14;
1759 dep->frame_number += max_t(u32, 4, dep->interval);
1761 /* Reinitialize test variables */
1762 dep->start_cmd_status = 0;
1765 return __dwc3_gadget_kick_transfer(dep);
1768 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1770 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1771 struct dwc3 *dwc = dep->dwc;
1775 if (list_empty(&dep->pending_list) &&
1776 list_empty(&dep->started_list)) {
1777 dep->flags |= DWC3_EP_PENDING_REQUEST;
1781 if (!dwc->dis_start_transfer_quirk &&
1782 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1783 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1784 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1785 return dwc3_gadget_start_isoc_quirk(dep);
1788 if (desc->bInterval <= 14 &&
1789 dwc->gadget->speed >= USB_SPEED_HIGH) {
1790 u32 frame = __dwc3_gadget_get_frame(dwc);
1791 bool rollover = frame <
1792 (dep->frame_number & DWC3_FRNUMBER_MASK);
1795 * frame_number is set from XferNotReady and may be already
1796 * out of date. DSTS only provides the lower 14 bit of the
1797 * current frame number. So add the upper two bits of
1798 * frame_number and handle a possible rollover.
1799 * This will provide the correct frame_number unless more than
1800 * rollover has happened since XferNotReady.
1803 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1806 dep->frame_number += BIT(14);
1809 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1810 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1812 ret = __dwc3_gadget_kick_transfer(dep);
1818 * After a number of unsuccessful start attempts due to bus-expiry
1819 * status, issue END_TRANSFER command and retry on the next XferNotReady
1822 if (ret == -EAGAIN) {
1823 struct dwc3_gadget_ep_cmd_params params;
1826 cmd = DWC3_DEPCMD_ENDTRANSFER |
1827 DWC3_DEPCMD_CMDIOC |
1828 DWC3_DEPCMD_PARAM(dep->resource_index);
1830 dep->resource_index = 0;
1831 memset(¶ms, 0, sizeof(params));
1833 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1835 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1841 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1843 struct dwc3 *dwc = dep->dwc;
1845 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1846 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1851 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1852 &req->request, req->dep->name))
1855 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1856 "%s: request %pK already in flight\n",
1857 dep->name, &req->request))
1860 pm_runtime_get(dwc->dev);
1862 req->request.actual = 0;
1863 req->request.status = -EINPROGRESS;
1865 trace_dwc3_ep_queue(req);
1867 list_add_tail(&req->list, &dep->pending_list);
1868 req->status = DWC3_REQUEST_STATUS_QUEUED;
1870 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1874 * Start the transfer only after the END_TRANSFER is completed
1875 * and endpoint STALL is cleared.
1877 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1878 (dep->flags & DWC3_EP_WEDGE) ||
1879 (dep->flags & DWC3_EP_STALL)) {
1880 dep->flags |= DWC3_EP_DELAY_START;
1885 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1886 * wait for a XferNotReady event so we will know what's the current
1887 * (micro-)frame number.
1889 * Without this trick, we are very, very likely gonna get Bus Expiry
1890 * errors which will force us issue EndTransfer command.
1892 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1893 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1894 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1897 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1898 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1899 return __dwc3_gadget_start_isoc(dep);
1903 __dwc3_gadget_kick_transfer(dep);
1908 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1911 struct dwc3_request *req = to_dwc3_request(request);
1912 struct dwc3_ep *dep = to_dwc3_ep(ep);
1913 struct dwc3 *dwc = dep->dwc;
1915 unsigned long flags;
1919 spin_lock_irqsave(&dwc->lock, flags);
1920 ret = __dwc3_gadget_ep_queue(dep, req);
1921 spin_unlock_irqrestore(&dwc->lock, flags);
1926 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1930 /* If req->trb is not set, then the request has not started */
1935 * If request was already started, this means we had to
1936 * stop the transfer. With that we also need to ignore
1937 * all TRBs used by the request, however TRBs can only
1938 * be modified after completion of END_TRANSFER
1939 * command. So what we do here is that we wait for
1940 * END_TRANSFER completion and only after that, we jump
1941 * over TRBs by clearing HWO and incrementing dequeue
1944 for (i = 0; i < req->num_trbs; i++) {
1945 struct dwc3_trb *trb;
1947 trb = &dep->trb_pool[dep->trb_dequeue];
1948 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1949 dwc3_ep_inc_deq(dep);
1955 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1957 struct dwc3_request *req;
1958 struct dwc3 *dwc = dep->dwc;
1960 while (!list_empty(&dep->cancelled_list)) {
1961 req = next_request(&dep->cancelled_list);
1962 dwc3_gadget_ep_skip_trbs(dep, req);
1963 switch (req->status) {
1964 case DWC3_REQUEST_STATUS_DISCONNECTED:
1965 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1967 case DWC3_REQUEST_STATUS_DEQUEUED:
1968 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1970 case DWC3_REQUEST_STATUS_STALLED:
1971 dwc3_gadget_giveback(dep, req, -EPIPE);
1974 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
1975 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1979 * The endpoint is disabled, let the dwc3_remove_requests()
1980 * handle the cleanup.
1982 if (!dep->endpoint.desc)
1987 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1988 struct usb_request *request)
1990 struct dwc3_request *req = to_dwc3_request(request);
1991 struct dwc3_request *r = NULL;
1993 struct dwc3_ep *dep = to_dwc3_ep(ep);
1994 struct dwc3 *dwc = dep->dwc;
1996 unsigned long flags;
1999 trace_dwc3_ep_dequeue(req);
2001 spin_lock_irqsave(&dwc->lock, flags);
2003 list_for_each_entry(r, &dep->cancelled_list, list) {
2008 list_for_each_entry(r, &dep->pending_list, list) {
2010 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2015 list_for_each_entry(r, &dep->started_list, list) {
2017 struct dwc3_request *t;
2019 /* wait until it is processed */
2020 dwc3_stop_active_transfer(dep, true, true);
2023 * Remove any started request if the transfer is
2026 list_for_each_entry_safe(r, t, &dep->started_list, list)
2027 dwc3_gadget_move_cancelled_request(r,
2028 DWC3_REQUEST_STATUS_DEQUEUED);
2030 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2036 dev_err(dwc->dev, "request %pK was not queued to %s\n",
2040 spin_unlock_irqrestore(&dwc->lock, flags);
2045 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2047 struct dwc3_gadget_ep_cmd_params params;
2048 struct dwc3 *dwc = dep->dwc;
2049 struct dwc3_request *req;
2050 struct dwc3_request *tmp;
2053 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2054 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2058 memset(¶ms, 0x00, sizeof(params));
2061 struct dwc3_trb *trb;
2063 unsigned int transfer_in_flight;
2064 unsigned int started;
2066 if (dep->number > 1)
2067 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2069 trb = &dwc->ep0_trb[dep->trb_enqueue];
2071 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2072 started = !list_empty(&dep->started_list);
2074 if (!protocol && ((dep->direction && transfer_in_flight) ||
2075 (!dep->direction && started))) {
2079 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2082 dev_err(dwc->dev, "failed to set STALL on %s\n",
2085 dep->flags |= DWC3_EP_STALL;
2088 * Don't issue CLEAR_STALL command to control endpoints. The
2089 * controller automatically clears the STALL when it receives
2092 if (dep->number <= 1) {
2093 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2097 dwc3_stop_active_transfer(dep, true, true);
2099 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2100 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2102 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
2103 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2107 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2109 ret = dwc3_send_clear_stall_ep_cmd(dep);
2111 dev_err(dwc->dev, "failed to clear STALL on %s\n",
2116 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2118 if ((dep->flags & DWC3_EP_DELAY_START) &&
2119 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2120 __dwc3_gadget_kick_transfer(dep);
2122 dep->flags &= ~DWC3_EP_DELAY_START;
2128 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2130 struct dwc3_ep *dep = to_dwc3_ep(ep);
2131 struct dwc3 *dwc = dep->dwc;
2133 unsigned long flags;
2137 spin_lock_irqsave(&dwc->lock, flags);
2138 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2139 spin_unlock_irqrestore(&dwc->lock, flags);
2144 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2146 struct dwc3_ep *dep = to_dwc3_ep(ep);
2147 struct dwc3 *dwc = dep->dwc;
2148 unsigned long flags;
2151 spin_lock_irqsave(&dwc->lock, flags);
2152 dep->flags |= DWC3_EP_WEDGE;
2154 if (dep->number == 0 || dep->number == 1)
2155 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2157 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2158 spin_unlock_irqrestore(&dwc->lock, flags);
2163 /* -------------------------------------------------------------------------- */
2165 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2166 .bLength = USB_DT_ENDPOINT_SIZE,
2167 .bDescriptorType = USB_DT_ENDPOINT,
2168 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
2171 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2172 .enable = dwc3_gadget_ep0_enable,
2173 .disable = dwc3_gadget_ep0_disable,
2174 .alloc_request = dwc3_gadget_ep_alloc_request,
2175 .free_request = dwc3_gadget_ep_free_request,
2176 .queue = dwc3_gadget_ep0_queue,
2177 .dequeue = dwc3_gadget_ep_dequeue,
2178 .set_halt = dwc3_gadget_ep0_set_halt,
2179 .set_wedge = dwc3_gadget_ep_set_wedge,
2182 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2183 .enable = dwc3_gadget_ep_enable,
2184 .disable = dwc3_gadget_ep_disable,
2185 .alloc_request = dwc3_gadget_ep_alloc_request,
2186 .free_request = dwc3_gadget_ep_free_request,
2187 .queue = dwc3_gadget_ep_queue,
2188 .dequeue = dwc3_gadget_ep_dequeue,
2189 .set_halt = dwc3_gadget_ep_set_halt,
2190 .set_wedge = dwc3_gadget_ep_set_wedge,
2193 /* -------------------------------------------------------------------------- */
2195 static int dwc3_gadget_get_frame(struct usb_gadget *g)
2197 struct dwc3 *dwc = gadget_to_dwc(g);
2199 return __dwc3_gadget_get_frame(dwc);
2202 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
2212 * According to the Databook Remote wakeup request should
2213 * be issued only when the device is in early suspend state.
2215 * We can check that via USB Link State bits in DSTS register.
2217 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2219 link_state = DWC3_DSTS_USBLNKST(reg);
2221 switch (link_state) {
2222 case DWC3_LINK_STATE_RESET:
2223 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2224 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2225 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2226 case DWC3_LINK_STATE_U1:
2227 case DWC3_LINK_STATE_RESUME:
2233 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2235 dev_err(dwc->dev, "failed to put link in Recovery\n");
2239 /* Recent versions do this automatically */
2240 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2241 /* write zeroes to Link Change Request */
2242 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2243 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2244 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2247 /* poll until Link State changes to ON */
2251 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2253 /* in HS, means ON */
2254 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2258 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2259 dev_err(dwc->dev, "failed to send remote wakeup\n");
2266 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2268 struct dwc3 *dwc = gadget_to_dwc(g);
2269 unsigned long flags;
2272 spin_lock_irqsave(&dwc->lock, flags);
2273 ret = __dwc3_gadget_wakeup(dwc);
2274 spin_unlock_irqrestore(&dwc->lock, flags);
2279 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2282 struct dwc3 *dwc = gadget_to_dwc(g);
2283 unsigned long flags;
2285 spin_lock_irqsave(&dwc->lock, flags);
2286 g->is_selfpowered = !!is_selfpowered;
2287 spin_unlock_irqrestore(&dwc->lock, flags);
2292 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2296 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2297 struct dwc3_ep *dep;
2299 dep = dwc->eps[epnum];
2303 dwc3_remove_requests(dwc, dep);
2307 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2309 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2312 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2313 ssp_rate = dwc->max_ssp_rate;
2315 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2316 reg &= ~DWC3_DCFG_SPEED_MASK;
2317 reg &= ~DWC3_DCFG_NUMLANES(~0);
2319 if (ssp_rate == USB_SSP_GEN_1x2)
2320 reg |= DWC3_DCFG_SUPERSPEED;
2321 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2322 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2324 if (ssp_rate != USB_SSP_GEN_2x1 &&
2325 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2326 reg |= DWC3_DCFG_NUMLANES(1);
2328 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2331 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2333 enum usb_device_speed speed;
2336 speed = dwc->gadget_max_speed;
2337 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2338 speed = dwc->maximum_speed;
2340 if (speed == USB_SPEED_SUPER_PLUS &&
2341 DWC3_IP_IS(DWC32)) {
2342 __dwc3_gadget_set_ssp_rate(dwc);
2346 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2347 reg &= ~(DWC3_DCFG_SPEED_MASK);
2350 * WORKAROUND: DWC3 revision < 2.20a have an issue
2351 * which would cause metastability state on Run/Stop
2352 * bit if we try to force the IP to USB2-only mode.
2354 * Because of that, we cannot configure the IP to any
2355 * speed other than the SuperSpeed
2359 * STAR#9000525659: Clock Domain Crossing on DCTL in
2362 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2363 !dwc->dis_metastability_quirk) {
2364 reg |= DWC3_DCFG_SUPERSPEED;
2367 case USB_SPEED_FULL:
2368 reg |= DWC3_DCFG_FULLSPEED;
2370 case USB_SPEED_HIGH:
2371 reg |= DWC3_DCFG_HIGHSPEED;
2373 case USB_SPEED_SUPER:
2374 reg |= DWC3_DCFG_SUPERSPEED;
2376 case USB_SPEED_SUPER_PLUS:
2377 if (DWC3_IP_IS(DWC3))
2378 reg |= DWC3_DCFG_SUPERSPEED;
2380 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2383 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2385 if (DWC3_IP_IS(DWC3))
2386 reg |= DWC3_DCFG_SUPERSPEED;
2388 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2392 if (DWC3_IP_IS(DWC32) &&
2393 speed > USB_SPEED_UNKNOWN &&
2394 speed < USB_SPEED_SUPER_PLUS)
2395 reg &= ~DWC3_DCFG_NUMLANES(~0);
2397 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2400 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2405 if (pm_runtime_suspended(dwc->dev))
2408 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2410 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2411 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2412 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2415 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2416 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2417 reg |= DWC3_DCTL_RUN_STOP;
2419 if (dwc->has_hibernation)
2420 reg |= DWC3_DCTL_KEEP_CONNECT;
2422 __dwc3_gadget_set_speed(dwc);
2423 dwc->pullups_connected = true;
2425 reg &= ~DWC3_DCTL_RUN_STOP;
2427 if (dwc->has_hibernation && !suspend)
2428 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2430 dwc->pullups_connected = false;
2433 dwc3_gadget_dctl_write_safe(dwc, reg);
2436 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2437 reg &= DWC3_DSTS_DEVCTRLHLT;
2438 } while (--timeout && !(!is_on ^ !reg));
2446 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2447 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2448 static int __dwc3_gadget_start(struct dwc3 *dwc);
2450 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2452 struct dwc3 *dwc = gadget_to_dwc(g);
2453 unsigned long flags;
2459 * Per databook, when we want to stop the gadget, if a control transfer
2460 * is still in process, complete it and get the core into setup phase.
2462 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2463 reinit_completion(&dwc->ep0_in_setup);
2465 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2466 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2468 dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
2472 * Avoid issuing a runtime resume if the device is already in the
2473 * suspended state during gadget disconnect. DWC3 gadget was already
2474 * halted/stopped during runtime suspend.
2477 pm_runtime_barrier(dwc->dev);
2478 if (pm_runtime_suspended(dwc->dev))
2483 * Check the return value for successful resume, or error. For a
2484 * successful resume, the DWC3 runtime PM resume routine will handle
2485 * the run stop sequence, so avoid duplicate operations here.
2487 ret = pm_runtime_get_sync(dwc->dev);
2488 if (!ret || ret < 0) {
2489 pm_runtime_put(dwc->dev);
2494 * Synchronize and disable any further event handling while controller
2495 * is being enabled/disabled.
2497 disable_irq(dwc->irq_gadget);
2499 spin_lock_irqsave(&dwc->lock, flags);
2504 dwc->connected = false;
2506 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2507 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2508 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2509 * command for any active transfers" before clearing the RunStop
2512 dwc3_stop_active_transfers(dwc);
2513 __dwc3_gadget_stop(dwc);
2516 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2517 * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2518 * "software needs to acknowledge the events that are generated
2519 * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2520 * to be set to '1'."
2522 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2523 count &= DWC3_GEVNTCOUNT_MASK;
2525 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2526 dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
2527 dwc->ev_buf->length;
2530 __dwc3_gadget_start(dwc);
2533 ret = dwc3_gadget_run_stop(dwc, is_on, false);
2534 spin_unlock_irqrestore(&dwc->lock, flags);
2535 enable_irq(dwc->irq_gadget);
2537 pm_runtime_put(dwc->dev);
2542 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2546 /* Enable all but Start and End of Frame IRQs */
2547 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2548 DWC3_DEVTEN_CMDCMPLTEN |
2549 DWC3_DEVTEN_ERRTICERREN |
2550 DWC3_DEVTEN_WKUPEVTEN |
2551 DWC3_DEVTEN_CONNECTDONEEN |
2552 DWC3_DEVTEN_USBRSTEN |
2553 DWC3_DEVTEN_DISCONNEVTEN);
2555 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2556 reg |= DWC3_DEVTEN_ULSTCNGEN;
2558 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2559 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2560 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2562 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2565 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2567 /* mask all interrupts */
2568 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2571 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2572 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2575 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2576 * @dwc: pointer to our context structure
2578 * The following looks like complex but it's actually very simple. In order to
2579 * calculate the number of packets we can burst at once on OUT transfers, we're
2580 * gonna use RxFIFO size.
2582 * To calculate RxFIFO size we need two numbers:
2583 * MDWIDTH = size, in bits, of the internal memory bus
2584 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2586 * Given these two numbers, the formula is simple:
2588 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2590 * 24 bytes is for 3x SETUP packets
2591 * 16 bytes is a clock domain crossing tolerance
2593 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2595 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2602 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2603 mdwidth = dwc3_mdwidth(dwc);
2605 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2606 nump = min_t(u32, nump, 16);
2609 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2610 reg &= ~DWC3_DCFG_NUMP_MASK;
2611 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2612 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2615 static int __dwc3_gadget_start(struct dwc3 *dwc)
2617 struct dwc3_ep *dep;
2622 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2623 * the core supports IMOD, disable it.
2625 if (dwc->imod_interval) {
2626 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2627 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2628 } else if (dwc3_has_imod(dwc)) {
2629 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2633 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2634 * field instead of letting dwc3 itself calculate that automatically.
2636 * This way, we maximize the chances that we'll be able to get several
2637 * bursts of data without going through any sort of endpoint throttling.
2639 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2640 if (DWC3_IP_IS(DWC3))
2641 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2643 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2645 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2647 dwc3_gadget_setup_nump(dwc);
2650 * Currently the controller handles single stream only. So, Ignore
2651 * Packet Pending bit for stream selection and don't search for another
2652 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2653 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2654 * the stream performance.
2656 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2657 reg |= DWC3_DCFG_IGNSTRMPP;
2658 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2660 /* Start with SuperSpeed Default */
2661 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2664 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2666 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2671 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2673 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2677 /* begin to receive SETUP packets */
2678 dwc->ep0state = EP0_SETUP_PHASE;
2679 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2680 dwc->delayed_status = false;
2681 dwc3_ep0_out_start(dwc);
2683 dwc3_gadget_enable_irq(dwc);
2688 __dwc3_gadget_ep_disable(dwc->eps[0]);
2694 static int dwc3_gadget_start(struct usb_gadget *g,
2695 struct usb_gadget_driver *driver)
2697 struct dwc3 *dwc = gadget_to_dwc(g);
2698 unsigned long flags;
2702 irq = dwc->irq_gadget;
2703 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2704 IRQF_SHARED, "dwc3", dwc->ev_buf);
2706 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2711 spin_lock_irqsave(&dwc->lock, flags);
2712 dwc->gadget_driver = driver;
2713 spin_unlock_irqrestore(&dwc->lock, flags);
2718 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2720 dwc3_gadget_disable_irq(dwc);
2721 __dwc3_gadget_ep_disable(dwc->eps[0]);
2722 __dwc3_gadget_ep_disable(dwc->eps[1]);
2725 static int dwc3_gadget_stop(struct usb_gadget *g)
2727 struct dwc3 *dwc = gadget_to_dwc(g);
2728 unsigned long flags;
2730 spin_lock_irqsave(&dwc->lock, flags);
2731 dwc->gadget_driver = NULL;
2732 dwc->max_cfg_eps = 0;
2733 spin_unlock_irqrestore(&dwc->lock, flags);
2735 free_irq(dwc->irq_gadget, dwc->ev_buf);
2740 static void dwc3_gadget_config_params(struct usb_gadget *g,
2741 struct usb_dcd_config_params *params)
2743 struct dwc3 *dwc = gadget_to_dwc(g);
2745 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2746 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2748 /* Recommended BESL */
2749 if (!dwc->dis_enblslpm_quirk) {
2751 * If the recommended BESL baseline is 0 or if the BESL deep is
2752 * less than 2, Microsoft's Windows 10 host usb stack will issue
2753 * a usb reset immediately after it receives the extended BOS
2754 * descriptor and the enumeration will fail. To maintain
2755 * compatibility with the Windows' usb stack, let's set the
2756 * recommended BESL baseline to 1 and clamp the BESL deep to be
2759 params->besl_baseline = 1;
2760 if (dwc->is_utmi_l1_suspend)
2762 clamp_t(u8, dwc->hird_threshold, 2, 15);
2765 /* U1 Device exit Latency */
2766 if (dwc->dis_u1_entry_quirk)
2767 params->bU1devExitLat = 0;
2769 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2771 /* U2 Device exit Latency */
2772 if (dwc->dis_u2_entry_quirk)
2773 params->bU2DevExitLat = 0;
2775 params->bU2DevExitLat =
2776 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2779 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2780 enum usb_device_speed speed)
2782 struct dwc3 *dwc = gadget_to_dwc(g);
2783 unsigned long flags;
2785 spin_lock_irqsave(&dwc->lock, flags);
2786 dwc->gadget_max_speed = speed;
2787 spin_unlock_irqrestore(&dwc->lock, flags);
2790 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2791 enum usb_ssp_rate rate)
2793 struct dwc3 *dwc = gadget_to_dwc(g);
2794 unsigned long flags;
2796 spin_lock_irqsave(&dwc->lock, flags);
2797 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2798 dwc->gadget_ssp_rate = rate;
2799 spin_unlock_irqrestore(&dwc->lock, flags);
2802 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2804 struct dwc3 *dwc = gadget_to_dwc(g);
2805 union power_supply_propval val = {0};
2809 return usb_phy_set_power(dwc->usb2_phy, mA);
2814 val.intval = 1000 * mA;
2815 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2821 * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
2822 * @g: pointer to the USB gadget
2824 * Used to record the maximum number of endpoints being used in a USB composite
2825 * device. (across all configurations) This is to be used in the calculation
2826 * of the TXFIFO sizes when resizing internal memory for individual endpoints.
2827 * It will help ensured that the resizing logic reserves enough space for at
2828 * least one max packet.
2830 static int dwc3_gadget_check_config(struct usb_gadget *g)
2832 struct dwc3 *dwc = gadget_to_dwc(g);
2838 if (!dwc->do_fifo_resize)
2841 list_for_each_entry(ep, &g->ep_list, ep_list) {
2842 /* Only interested in the IN endpoints */
2843 if (ep->claimed && (ep->address & USB_DIR_IN))
2847 if (ep_num <= dwc->max_cfg_eps)
2850 /* Update the max number of eps in the composition */
2851 dwc->max_cfg_eps = ep_num;
2853 fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
2854 /* Based on the equation, increment by one for every ep */
2855 fifo_size += dwc->max_cfg_eps;
2857 /* Check if we can fit a single fifo per endpoint */
2858 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
2859 if (fifo_size > ram1_depth)
2865 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
2867 struct dwc3 *dwc = gadget_to_dwc(g);
2868 unsigned long flags;
2870 spin_lock_irqsave(&dwc->lock, flags);
2871 dwc->async_callbacks = enable;
2872 spin_unlock_irqrestore(&dwc->lock, flags);
2875 static const struct usb_gadget_ops dwc3_gadget_ops = {
2876 .get_frame = dwc3_gadget_get_frame,
2877 .wakeup = dwc3_gadget_wakeup,
2878 .set_selfpowered = dwc3_gadget_set_selfpowered,
2879 .pullup = dwc3_gadget_pullup,
2880 .udc_start = dwc3_gadget_start,
2881 .udc_stop = dwc3_gadget_stop,
2882 .udc_set_speed = dwc3_gadget_set_speed,
2883 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
2884 .get_config_params = dwc3_gadget_config_params,
2885 .vbus_draw = dwc3_gadget_vbus_draw,
2886 .check_config = dwc3_gadget_check_config,
2887 .udc_async_callbacks = dwc3_gadget_async_callbacks,
2890 /* -------------------------------------------------------------------------- */
2892 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2894 struct dwc3 *dwc = dep->dwc;
2896 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2897 dep->endpoint.maxburst = 1;
2898 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2899 if (!dep->direction)
2900 dwc->gadget->ep0 = &dep->endpoint;
2902 dep->endpoint.caps.type_control = true;
2907 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2909 struct dwc3 *dwc = dep->dwc;
2913 mdwidth = dwc3_mdwidth(dwc);
2915 /* MDWIDTH is represented in bits, we need it in bytes */
2918 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2919 if (DWC3_IP_IS(DWC3))
2920 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2922 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2924 /* FIFO Depth is in MDWDITH bytes. Multiply */
2928 * To meet performance requirement, a minimum TxFIFO size of 3x
2929 * MaxPacketSize is recommended for endpoints that support burst and a
2930 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2931 * support burst. Use those numbers and we can calculate the max packet
2934 if (dwc->maximum_speed >= USB_SPEED_SUPER)
2939 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2941 dep->endpoint.max_streams = 16;
2942 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2943 list_add_tail(&dep->endpoint.ep_list,
2944 &dwc->gadget->ep_list);
2945 dep->endpoint.caps.type_iso = true;
2946 dep->endpoint.caps.type_bulk = true;
2947 dep->endpoint.caps.type_int = true;
2949 return dwc3_alloc_trb_pool(dep);
2952 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2954 struct dwc3 *dwc = dep->dwc;
2958 mdwidth = dwc3_mdwidth(dwc);
2960 /* MDWIDTH is represented in bits, convert to bytes */
2963 /* All OUT endpoints share a single RxFIFO space */
2964 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2965 if (DWC3_IP_IS(DWC3))
2966 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2968 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2970 /* FIFO depth is in MDWDITH bytes */
2974 * To meet performance requirement, a minimum recommended RxFIFO size
2975 * is defined as follow:
2976 * RxFIFO size >= (3 x MaxPacketSize) +
2977 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2979 * Then calculate the max packet limit as below.
2981 size -= (3 * 8) + 16;
2987 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2988 dep->endpoint.max_streams = 16;
2989 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2990 list_add_tail(&dep->endpoint.ep_list,
2991 &dwc->gadget->ep_list);
2992 dep->endpoint.caps.type_iso = true;
2993 dep->endpoint.caps.type_bulk = true;
2994 dep->endpoint.caps.type_int = true;
2996 return dwc3_alloc_trb_pool(dep);
2999 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3001 struct dwc3_ep *dep;
3002 bool direction = epnum & 1;
3004 u8 num = epnum >> 1;
3006 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3011 dep->number = epnum;
3012 dep->direction = direction;
3013 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3014 dwc->eps[epnum] = dep;
3016 dep->start_cmd_status = 0;
3018 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3019 direction ? "in" : "out");
3021 dep->endpoint.name = dep->name;
3023 if (!(dep->number > 1)) {
3024 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3025 dep->endpoint.comp_desc = NULL;
3029 ret = dwc3_gadget_init_control_endpoint(dep);
3031 ret = dwc3_gadget_init_in_endpoint(dep);
3033 ret = dwc3_gadget_init_out_endpoint(dep);
3038 dep->endpoint.caps.dir_in = direction;
3039 dep->endpoint.caps.dir_out = !direction;
3041 INIT_LIST_HEAD(&dep->pending_list);
3042 INIT_LIST_HEAD(&dep->started_list);
3043 INIT_LIST_HEAD(&dep->cancelled_list);
3045 dwc3_debugfs_create_endpoint_dir(dep);
3050 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3054 INIT_LIST_HEAD(&dwc->gadget->ep_list);
3056 for (epnum = 0; epnum < total; epnum++) {
3059 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3067 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3069 struct dwc3_ep *dep;
3072 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3073 dep = dwc->eps[epnum];
3077 * Physical endpoints 0 and 1 are special; they form the
3078 * bi-directional USB endpoint 0.
3080 * For those two physical endpoints, we don't allocate a TRB
3081 * pool nor do we add them the endpoints list. Due to that, we
3082 * shouldn't do these two operations otherwise we would end up
3083 * with all sorts of bugs when removing dwc3.ko.
3085 if (epnum != 0 && epnum != 1) {
3086 dwc3_free_trb_pool(dep);
3087 list_del(&dep->endpoint.ep_list);
3090 debugfs_remove_recursive(debugfs_lookup(dep->name,
3091 debugfs_lookup(dev_name(dep->dwc->dev),
3097 /* -------------------------------------------------------------------------- */
3099 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3100 struct dwc3_request *req, struct dwc3_trb *trb,
3101 const struct dwc3_event_depevt *event, int status, int chain)
3105 dwc3_ep_inc_deq(dep);
3107 trace_dwc3_complete_trb(dep, trb);
3111 * If we're in the middle of series of chained TRBs and we
3112 * receive a short transfer along the way, DWC3 will skip
3113 * through all TRBs including the last TRB in the chain (the
3114 * where CHN bit is zero. DWC3 will also avoid clearing HWO
3115 * bit and SW has to do it manually.
3117 * We're going to do that here to avoid problems of HW trying
3118 * to use bogus TRBs for transfers.
3120 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3121 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3124 * For isochronous transfers, the first TRB in a service interval must
3125 * have the Isoc-First type. Track and report its interval frame number.
3127 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3128 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3129 unsigned int frame_number;
3131 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3132 frame_number &= ~(dep->interval - 1);
3133 req->request.frame_number = frame_number;
3137 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3138 * this TRB points to the bounce buffer address, it's a MPS alignment
3139 * TRB. Don't add it to req->remaining calculation.
3141 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3142 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3143 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3147 count = trb->size & DWC3_TRB_SIZE_MASK;
3148 req->remaining += count;
3150 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3153 if (event->status & DEPEVT_STATUS_SHORT && !chain)
3156 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3157 (trb->ctrl & DWC3_TRB_CTRL_LST))
3163 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3164 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3167 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3168 struct scatterlist *sg = req->sg;
3169 struct scatterlist *s;
3170 unsigned int num_queued = req->num_queued_sgs;
3174 for_each_sg(sg, s, num_queued, i) {
3175 trb = &dep->trb_pool[dep->trb_dequeue];
3177 req->sg = sg_next(s);
3178 req->num_queued_sgs--;
3180 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3181 trb, event, status, true);
3189 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3190 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3193 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3195 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3196 event, status, false);
3199 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3201 return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3204 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3205 const struct dwc3_event_depevt *event,
3206 struct dwc3_request *req, int status)
3211 if (req->request.num_mapped_sgs)
3212 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3215 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3218 req->request.actual = req->request.length - req->remaining;
3220 if (!dwc3_gadget_ep_request_completed(req))
3223 if (req->needs_extra_trb) {
3224 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3226 req->needs_extra_trb = false;
3230 * The event status only reflects the status of the TRB with IOC set.
3231 * For the requests that don't set interrupt on completion, the driver
3232 * needs to check and return the status of the completed TRBs associated
3233 * with the request. Use the status of the last TRB of the request.
3235 if (req->request.no_interrupt) {
3236 struct dwc3_trb *trb;
3238 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3239 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
3240 case DWC3_TRBSTS_MISSED_ISOC:
3241 /* Isoc endpoint only */
3242 request_status = -EXDEV;
3244 case DWC3_TRB_STS_XFER_IN_PROG:
3245 /* Applicable when End Transfer with ForceRM=0 */
3246 case DWC3_TRBSTS_SETUP_PENDING:
3247 /* Control endpoint only */
3248 case DWC3_TRBSTS_OK:
3254 request_status = status;
3257 dwc3_gadget_giveback(dep, req, request_status);
3263 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3264 const struct dwc3_event_depevt *event, int status)
3266 struct dwc3_request *req;
3268 while (!list_empty(&dep->started_list)) {
3271 req = next_request(&dep->started_list);
3272 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3277 * The endpoint is disabled, let the dwc3_remove_requests()
3278 * handle the cleanup.
3280 if (!dep->endpoint.desc)
3285 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3287 struct dwc3_request *req;
3288 struct dwc3 *dwc = dep->dwc;
3290 if (!dep->endpoint.desc || !dwc->pullups_connected ||
3294 if (!list_empty(&dep->pending_list))
3298 * We only need to check the first entry of the started list. We can
3299 * assume the completed requests are removed from the started list.
3301 req = next_request(&dep->started_list);
3305 return !dwc3_gadget_ep_request_completed(req);
3308 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3309 const struct dwc3_event_depevt *event)
3311 dep->frame_number = event->parameters;
3314 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3315 const struct dwc3_event_depevt *event, int status)
3317 struct dwc3 *dwc = dep->dwc;
3318 bool no_started_trb = true;
3320 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3322 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3325 if (!dep->endpoint.desc)
3326 return no_started_trb;
3328 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3329 list_empty(&dep->started_list) &&
3330 (list_empty(&dep->pending_list) || status == -EXDEV))
3331 dwc3_stop_active_transfer(dep, true, true);
3332 else if (dwc3_gadget_ep_should_continue(dep))
3333 if (__dwc3_gadget_kick_transfer(dep) == 0)
3334 no_started_trb = false;
3338 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3339 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3341 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3345 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3348 if (!(dep->flags & DWC3_EP_ENABLED))
3351 if (!list_empty(&dep->started_list))
3352 return no_started_trb;
3355 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3357 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3362 return no_started_trb;
3365 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3366 const struct dwc3_event_depevt *event)
3370 if (!dep->endpoint.desc)
3373 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3374 dwc3_gadget_endpoint_frame_from_event(dep, event);
3376 if (event->status & DEPEVT_STATUS_BUSERR)
3377 status = -ECONNRESET;
3379 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3382 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3385 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3386 const struct dwc3_event_depevt *event)
3390 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3392 if (event->status & DEPEVT_STATUS_BUSERR)
3393 status = -ECONNRESET;
3395 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3396 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3399 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3400 const struct dwc3_event_depevt *event)
3402 dwc3_gadget_endpoint_frame_from_event(dep, event);
3405 * The XferNotReady event is generated only once before the endpoint
3406 * starts. It will be generated again when END_TRANSFER command is
3407 * issued. For some controller versions, the XferNotReady event may be
3408 * generated while the END_TRANSFER command is still in process. Ignore
3409 * it and wait for the next XferNotReady event after the command is
3412 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3415 (void) __dwc3_gadget_start_isoc(dep);
3418 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3419 const struct dwc3_event_depevt *event)
3421 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3423 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3427 * The END_TRANSFER command will cause the controller to generate a
3428 * NoStream Event, and it's not due to the host DP NoStream rejection.
3429 * Ignore the next NoStream event.
3431 if (dep->stream_capable)
3432 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3434 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3435 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3436 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3438 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3439 struct dwc3 *dwc = dep->dwc;
3441 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3442 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3443 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3445 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3446 if (dwc->delayed_status)
3447 __dwc3_gadget_ep0_set_halt(ep0, 1);
3451 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3452 if (dwc->delayed_status)
3453 dwc3_ep0_send_delayed_status(dwc);
3456 if ((dep->flags & DWC3_EP_DELAY_START) &&
3457 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3458 __dwc3_gadget_kick_transfer(dep);
3460 dep->flags &= ~DWC3_EP_DELAY_START;
3463 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3464 const struct dwc3_event_depevt *event)
3466 struct dwc3 *dwc = dep->dwc;
3468 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3469 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3473 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3474 switch (event->parameters) {
3475 case DEPEVT_STREAM_PRIME:
3477 * If the host can properly transition the endpoint state from
3478 * idle to prime after a NoStream rejection, there's no need to
3479 * force restarting the endpoint to reinitiate the stream. To
3480 * simplify the check, assume the host follows the USB spec if
3481 * it primed the endpoint more than once.
3483 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3484 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3485 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3487 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3491 case DEPEVT_STREAM_NOSTREAM:
3492 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3493 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3494 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
3498 * If the host rejects a stream due to no active stream, by the
3499 * USB and xHCI spec, the endpoint will be put back to idle
3500 * state. When the host is ready (buffer added/updated), it will
3501 * prime the endpoint to inform the usb device controller. This
3502 * triggers the device controller to issue ERDY to restart the
3503 * stream. However, some hosts don't follow this and keep the
3504 * endpoint in the idle state. No prime will come despite host
3505 * streams are updated, and the device controller will not be
3506 * triggered to generate ERDY to move the next stream data. To
3507 * workaround this and maintain compatibility with various
3508 * hosts, force to reinitate the stream until the host is ready
3509 * instead of waiting for the host to prime the endpoint.
3511 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3512 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3514 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3516 dep->flags |= DWC3_EP_DELAY_START;
3517 dwc3_stop_active_transfer(dep, true, true);
3524 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3527 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3528 const struct dwc3_event_depevt *event)
3530 struct dwc3_ep *dep;
3531 u8 epnum = event->endpoint_number;
3533 dep = dwc->eps[epnum];
3535 if (!(dep->flags & DWC3_EP_ENABLED)) {
3536 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3539 /* Handle only EPCMDCMPLT when EP disabled */
3540 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3544 if (epnum == 0 || epnum == 1) {
3545 dwc3_ep0_interrupt(dwc, event);
3549 switch (event->endpoint_event) {
3550 case DWC3_DEPEVT_XFERINPROGRESS:
3551 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3553 case DWC3_DEPEVT_XFERNOTREADY:
3554 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3556 case DWC3_DEPEVT_EPCMDCMPLT:
3557 dwc3_gadget_endpoint_command_complete(dep, event);
3559 case DWC3_DEPEVT_XFERCOMPLETE:
3560 dwc3_gadget_endpoint_transfer_complete(dep, event);
3562 case DWC3_DEPEVT_STREAMEVT:
3563 dwc3_gadget_endpoint_stream_event(dep, event);
3565 case DWC3_DEPEVT_RXTXFIFOEVT:
3570 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3572 if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3573 spin_unlock(&dwc->lock);
3574 dwc->gadget_driver->disconnect(dwc->gadget);
3575 spin_lock(&dwc->lock);
3579 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3581 if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3582 spin_unlock(&dwc->lock);
3583 dwc->gadget_driver->suspend(dwc->gadget);
3584 spin_lock(&dwc->lock);
3588 static void dwc3_resume_gadget(struct dwc3 *dwc)
3590 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3591 spin_unlock(&dwc->lock);
3592 dwc->gadget_driver->resume(dwc->gadget);
3593 spin_lock(&dwc->lock);
3597 static void dwc3_reset_gadget(struct dwc3 *dwc)
3599 if (!dwc->gadget_driver)
3602 if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3603 spin_unlock(&dwc->lock);
3604 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3605 spin_lock(&dwc->lock);
3609 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3612 struct dwc3_gadget_ep_cmd_params params;
3616 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3617 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3621 * NOTICE: We are violating what the Databook says about the
3622 * EndTransfer command. Ideally we would _always_ wait for the
3623 * EndTransfer Command Completion IRQ, but that's causing too
3624 * much trouble synchronizing between us and gadget driver.
3626 * We have discussed this with the IP Provider and it was
3627 * suggested to giveback all requests here.
3629 * Note also that a similar handling was tested by Synopsys
3630 * (thanks a lot Paul) and nothing bad has come out of it.
3631 * In short, what we're doing is issuing EndTransfer with
3632 * CMDIOC bit set and delay kicking transfer until the
3633 * EndTransfer command had completed.
3635 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3636 * supports a mode to work around the above limitation. The
3637 * software can poll the CMDACT bit in the DEPCMD register
3638 * after issuing a EndTransfer command. This mode is enabled
3639 * by writing GUCTL2[14]. This polling is already done in the
3640 * dwc3_send_gadget_ep_cmd() function so if the mode is
3641 * enabled, the EndTransfer command will have completed upon
3642 * returning from this function.
3644 * This mode is NOT available on the DWC_usb31 IP.
3647 cmd = DWC3_DEPCMD_ENDTRANSFER;
3648 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3649 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3650 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3651 memset(¶ms, 0, sizeof(params));
3652 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
3654 dep->resource_index = 0;
3657 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3659 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3662 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3666 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3667 struct dwc3_ep *dep;
3670 dep = dwc->eps[epnum];
3674 if (!(dep->flags & DWC3_EP_STALL))
3677 dep->flags &= ~DWC3_EP_STALL;
3679 ret = dwc3_send_clear_stall_ep_cmd(dep);
3684 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3688 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3690 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3691 reg &= ~DWC3_DCTL_INITU1ENA;
3692 reg &= ~DWC3_DCTL_INITU2ENA;
3693 dwc3_gadget_dctl_write_safe(dwc, reg);
3695 dwc3_disconnect_gadget(dwc);
3697 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3698 dwc->setup_packet_pending = false;
3699 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3701 dwc->connected = false;
3704 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3709 * Ideally, dwc3_reset_gadget() would trigger the function
3710 * drivers to stop any active transfers through ep disable.
3711 * However, for functions which defer ep disable, such as mass
3712 * storage, we will need to rely on the call to stop active
3713 * transfers here, and avoid allowing of request queuing.
3715 dwc->connected = false;
3718 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3719 * would cause a missing Disconnect Event if there's a
3720 * pending Setup Packet in the FIFO.
3722 * There's no suggested workaround on the official Bug
3723 * report, which states that "unless the driver/application
3724 * is doing any special handling of a disconnect event,
3725 * there is no functional issue".
3727 * Unfortunately, it turns out that we _do_ some special
3728 * handling of a disconnect event, namely complete all
3729 * pending transfers, notify gadget driver of the
3730 * disconnection, and so on.
3732 * Our suggested workaround is to follow the Disconnect
3733 * Event steps here, instead, based on a setup_packet_pending
3734 * flag. Such flag gets set whenever we have a SETUP_PENDING
3735 * status for EP0 TRBs and gets cleared on XferComplete for the
3740 * STAR#9000466709: RTL: Device : Disconnect event not
3741 * generated if setup packet pending in FIFO
3743 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3744 if (dwc->setup_packet_pending)
3745 dwc3_gadget_disconnect_interrupt(dwc);
3748 dwc3_reset_gadget(dwc);
3750 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3751 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3752 * needs to ensure that it sends "a DEPENDXFER command for any active
3755 dwc3_stop_active_transfers(dwc);
3756 dwc->connected = true;
3758 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3759 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3760 dwc3_gadget_dctl_write_safe(dwc, reg);
3761 dwc->test_mode = false;
3762 dwc3_clear_stall_all_ep(dwc);
3764 /* Reset device address to zero */
3765 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3766 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3767 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3770 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3772 struct dwc3_ep *dep;
3778 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3779 speed = reg & DWC3_DSTS_CONNECTSPD;
3782 if (DWC3_IP_IS(DWC32))
3783 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3785 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3788 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3789 * each time on Connect Done.
3791 * Currently we always use the reset value. If any platform
3792 * wants to set this to a different value, we need to add a
3793 * setting and update GCTL.RAMCLKSEL here.
3797 case DWC3_DSTS_SUPERSPEED_PLUS:
3798 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3799 dwc->gadget->ep0->maxpacket = 512;
3800 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3803 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3805 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3807 case DWC3_DSTS_SUPERSPEED:
3809 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3810 * would cause a missing USB3 Reset event.
3812 * In such situations, we should force a USB3 Reset
3813 * event by calling our dwc3_gadget_reset_interrupt()
3818 * STAR#9000483510: RTL: SS : USB3 reset event may
3819 * not be generated always when the link enters poll
3821 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3822 dwc3_gadget_reset_interrupt(dwc);
3824 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3825 dwc->gadget->ep0->maxpacket = 512;
3826 dwc->gadget->speed = USB_SPEED_SUPER;
3829 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3830 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3833 case DWC3_DSTS_HIGHSPEED:
3834 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3835 dwc->gadget->ep0->maxpacket = 64;
3836 dwc->gadget->speed = USB_SPEED_HIGH;
3838 case DWC3_DSTS_FULLSPEED:
3839 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3840 dwc->gadget->ep0->maxpacket = 64;
3841 dwc->gadget->speed = USB_SPEED_FULL;
3845 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3847 /* Enable USB2 LPM Capability */
3849 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3850 !dwc->usb2_gadget_lpm_disable &&
3851 (speed != DWC3_DSTS_SUPERSPEED) &&
3852 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3853 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3854 reg |= DWC3_DCFG_LPM_CAP;
3855 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3857 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3858 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3860 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3861 (dwc->is_utmi_l1_suspend << 4));
3864 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3865 * DCFG.LPMCap is set, core responses with an ACK and the
3866 * BESL value in the LPM token is less than or equal to LPM
3869 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3870 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3872 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3873 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3875 dwc3_gadget_dctl_write_safe(dwc, reg);
3877 if (dwc->usb2_gadget_lpm_disable) {
3878 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3879 reg &= ~DWC3_DCFG_LPM_CAP;
3880 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3883 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3884 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3885 dwc3_gadget_dctl_write_safe(dwc, reg);
3889 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3891 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3896 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3898 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3903 * Configure PHY via GUSB3PIPECTLn if required.
3905 * Update GTXFIFOSIZn
3907 * In both cases reset values should be sufficient.
3911 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3914 * TODO take core out of low power mode when that's
3918 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3919 spin_unlock(&dwc->lock);
3920 dwc->gadget_driver->resume(dwc->gadget);
3921 spin_lock(&dwc->lock);
3925 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3926 unsigned int evtinfo)
3928 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3929 unsigned int pwropt;
3932 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3933 * Hibernation mode enabled which would show up when device detects
3934 * host-initiated U3 exit.
3936 * In that case, device will generate a Link State Change Interrupt
3937 * from U3 to RESUME which is only necessary if Hibernation is
3940 * There are no functional changes due to such spurious event and we
3941 * just need to ignore it.
3945 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3948 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3949 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3950 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3951 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3952 (next == DWC3_LINK_STATE_RESUME)) {
3958 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3959 * on the link partner, the USB session might do multiple entry/exit
3960 * of low power states before a transfer takes place.
3962 * Due to this problem, we might experience lower throughput. The
3963 * suggested workaround is to disable DCTL[12:9] bits if we're
3964 * transitioning from U1/U2 to U0 and enable those bits again
3965 * after a transfer completes and there are no pending transfers
3966 * on any of the enabled endpoints.
3968 * This is the first half of that workaround.
3972 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3973 * core send LGO_Ux entering U0
3975 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3976 if (next == DWC3_LINK_STATE_U0) {
3980 switch (dwc->link_state) {
3981 case DWC3_LINK_STATE_U1:
3982 case DWC3_LINK_STATE_U2:
3983 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3984 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3985 | DWC3_DCTL_ACCEPTU2ENA
3986 | DWC3_DCTL_INITU1ENA
3987 | DWC3_DCTL_ACCEPTU1ENA);
3990 dwc->u1u2 = reg & u1u2;
3994 dwc3_gadget_dctl_write_safe(dwc, reg);
4004 case DWC3_LINK_STATE_U1:
4005 if (dwc->speed == USB_SPEED_SUPER)
4006 dwc3_suspend_gadget(dwc);
4008 case DWC3_LINK_STATE_U2:
4009 case DWC3_LINK_STATE_U3:
4010 dwc3_suspend_gadget(dwc);
4012 case DWC3_LINK_STATE_RESUME:
4013 dwc3_resume_gadget(dwc);
4020 dwc->link_state = next;
4023 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4024 unsigned int evtinfo)
4026 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4028 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
4029 dwc3_suspend_gadget(dwc);
4031 dwc->link_state = next;
4034 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
4035 unsigned int evtinfo)
4037 unsigned int is_ss = evtinfo & BIT(4);
4040 * WORKAROUND: DWC3 revison 2.20a with hibernation support
4041 * have a known issue which can cause USB CV TD.9.23 to fail
4044 * Because of this issue, core could generate bogus hibernation
4045 * events which SW needs to ignore.
4049 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
4050 * Device Fallback from SuperSpeed
4052 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
4055 /* enter hibernation here */
4058 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4059 const struct dwc3_event_devt *event)
4061 switch (event->type) {
4062 case DWC3_DEVICE_EVENT_DISCONNECT:
4063 dwc3_gadget_disconnect_interrupt(dwc);
4065 case DWC3_DEVICE_EVENT_RESET:
4066 dwc3_gadget_reset_interrupt(dwc);
4068 case DWC3_DEVICE_EVENT_CONNECT_DONE:
4069 dwc3_gadget_conndone_interrupt(dwc);
4071 case DWC3_DEVICE_EVENT_WAKEUP:
4072 dwc3_gadget_wakeup_interrupt(dwc);
4074 case DWC3_DEVICE_EVENT_HIBER_REQ:
4075 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
4076 "unexpected hibernation event\n"))
4079 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
4081 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4082 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4084 case DWC3_DEVICE_EVENT_SUSPEND:
4085 /* It changed to be suspend event for version 2.30a and above */
4086 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
4088 * Ignore suspend event until the gadget enters into
4089 * USB_STATE_CONFIGURED state.
4091 if (dwc->gadget->state >= USB_STATE_CONFIGURED)
4092 dwc3_gadget_suspend_interrupt(dwc,
4096 case DWC3_DEVICE_EVENT_SOF:
4097 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4098 case DWC3_DEVICE_EVENT_CMD_CMPL:
4099 case DWC3_DEVICE_EVENT_OVERFLOW:
4102 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4106 static void dwc3_process_event_entry(struct dwc3 *dwc,
4107 const union dwc3_event *event)
4109 trace_dwc3_event(event->raw, dwc);
4111 if (!event->type.is_devspec)
4112 dwc3_endpoint_interrupt(dwc, &event->depevt);
4113 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4114 dwc3_gadget_interrupt(dwc, &event->devt);
4116 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4119 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4121 struct dwc3 *dwc = evt->dwc;
4122 irqreturn_t ret = IRQ_NONE;
4128 if (!(evt->flags & DWC3_EVENT_PENDING))
4132 union dwc3_event event;
4134 event.raw = *(u32 *) (evt->cache + evt->lpos);
4136 dwc3_process_event_entry(dwc, &event);
4139 * FIXME we wrap around correctly to the next entry as
4140 * almost all entries are 4 bytes in size. There is one
4141 * entry which has 12 bytes which is a regular entry
4142 * followed by 8 bytes data. ATM I don't know how
4143 * things are organized if we get next to the a
4144 * boundary so I worry about that once we try to handle
4147 evt->lpos = (evt->lpos + 4) % evt->length;
4152 evt->flags &= ~DWC3_EVENT_PENDING;
4155 /* Unmask interrupt */
4156 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
4157 reg &= ~DWC3_GEVNTSIZ_INTMASK;
4158 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
4160 if (dwc->imod_interval) {
4161 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4162 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4168 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4170 struct dwc3_event_buffer *evt = _evt;
4171 struct dwc3 *dwc = evt->dwc;
4172 unsigned long flags;
4173 irqreturn_t ret = IRQ_NONE;
4176 spin_lock_irqsave(&dwc->lock, flags);
4177 ret = dwc3_process_event_buf(evt);
4178 spin_unlock_irqrestore(&dwc->lock, flags);
4184 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4186 struct dwc3 *dwc = evt->dwc;
4191 if (pm_runtime_suspended(dwc->dev)) {
4192 pm_runtime_get(dwc->dev);
4193 disable_irq_nosync(dwc->irq_gadget);
4194 dwc->pending_events = true;
4199 * With PCIe legacy interrupt, test shows that top-half irq handler can
4200 * be called again after HW interrupt deassertion. Check if bottom-half
4201 * irq event handler completes before caching new event to prevent
4204 if (evt->flags & DWC3_EVENT_PENDING)
4207 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4208 count &= DWC3_GEVNTCOUNT_MASK;
4213 evt->flags |= DWC3_EVENT_PENDING;
4215 /* Mask interrupt */
4216 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
4217 reg |= DWC3_GEVNTSIZ_INTMASK;
4218 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
4220 amount = min(count, evt->length - evt->lpos);
4221 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4224 memcpy(evt->cache, evt->buf, count - amount);
4226 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4228 return IRQ_WAKE_THREAD;
4231 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4233 struct dwc3_event_buffer *evt = _evt;
4235 return dwc3_check_event_buf(evt);
4238 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4240 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4243 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4247 if (irq == -EPROBE_DEFER)
4250 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4254 if (irq == -EPROBE_DEFER)
4257 irq = platform_get_irq(dwc3_pdev, 0);
4268 static void dwc_gadget_release(struct device *dev)
4270 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4276 * dwc3_gadget_init - initializes gadget related registers
4277 * @dwc: pointer to our controller context structure
4279 * Returns 0 on success otherwise negative errno.
4281 int dwc3_gadget_init(struct dwc3 *dwc)
4287 irq = dwc3_gadget_get_irq(dwc);
4293 dwc->irq_gadget = irq;
4295 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4296 sizeof(*dwc->ep0_trb) * 2,
4297 &dwc->ep0_trb_addr, GFP_KERNEL);
4298 if (!dwc->ep0_trb) {
4299 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4304 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4305 if (!dwc->setup_buf) {
4310 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4311 &dwc->bounce_addr, GFP_KERNEL);
4317 init_completion(&dwc->ep0_in_setup);
4318 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4325 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4326 dev = &dwc->gadget->dev;
4327 dev->platform_data = dwc;
4328 dwc->gadget->ops = &dwc3_gadget_ops;
4329 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4330 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4331 dwc->gadget->sg_supported = true;
4332 dwc->gadget->name = "dwc3-gadget";
4333 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
4336 * FIXME We might be setting max_speed to <SUPER, however versions
4337 * <2.20a of dwc3 have an issue with metastability (documented
4338 * elsewhere in this driver) which tells us we can't set max speed to
4339 * anything lower than SUPER.
4341 * Because gadget.max_speed is only used by composite.c and function
4342 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4343 * to happen so we avoid sending SuperSpeed Capability descriptor
4344 * together with our BOS descriptor as that could confuse host into
4345 * thinking we can handle super speed.
4347 * Note that, in fact, we won't even support GetBOS requests when speed
4348 * is less than super speed because we don't have means, yet, to tell
4349 * composite.c that we are USB 2.0 + LPM ECN.
4351 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4352 !dwc->dis_metastability_quirk)
4353 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4356 dwc->gadget->max_speed = dwc->maximum_speed;
4357 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4360 * REVISIT: Here we should clear all pending IRQs to be
4361 * sure we're starting from a well known location.
4364 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4368 ret = usb_add_gadget(dwc->gadget);
4370 dev_err(dwc->dev, "failed to add gadget\n");
4374 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4375 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4377 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4382 dwc3_gadget_free_endpoints(dwc);
4384 usb_put_gadget(dwc->gadget);
4387 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4391 kfree(dwc->setup_buf);
4394 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4395 dwc->ep0_trb, dwc->ep0_trb_addr);
4401 /* -------------------------------------------------------------------------- */
4403 void dwc3_gadget_exit(struct dwc3 *dwc)
4408 usb_del_gadget(dwc->gadget);
4409 dwc3_gadget_free_endpoints(dwc);
4410 usb_put_gadget(dwc->gadget);
4411 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4413 kfree(dwc->setup_buf);
4414 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4415 dwc->ep0_trb, dwc->ep0_trb_addr);
4418 int dwc3_gadget_suspend(struct dwc3 *dwc)
4420 if (!dwc->gadget_driver)
4423 dwc3_gadget_run_stop(dwc, false, false);
4424 dwc3_disconnect_gadget(dwc);
4425 __dwc3_gadget_stop(dwc);
4430 int dwc3_gadget_resume(struct dwc3 *dwc)
4434 if (!dwc->gadget_driver)
4437 ret = __dwc3_gadget_start(dwc);
4441 ret = dwc3_gadget_run_stop(dwc, true, false);
4448 __dwc3_gadget_stop(dwc);
4454 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4456 if (dwc->pending_events) {
4457 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4458 dwc->pending_events = false;
4459 enable_irq(dwc->irq_gadget);