1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d) (((d)->frame_number + (d)->interval) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (dwc->revision >= DWC3_REVISION_194A) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
122 if (dwc->revision >= DWC3_REVISION_194A)
125 /* wait for a change in DSTS */
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
130 if (DWC3_DSTS_USBLNKST(reg) == state)
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
147 static void dwc3_ep_inc_trb(u8 *index)
150 if (*index == (DWC3_TRB_NUM - 1))
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
158 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
167 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
172 void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
175 struct dwc3 *dwc = dep->dwc;
177 req->started = false;
178 list_del(&req->list);
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
185 usb_gadget_unmap_request_by_dev(dwc->sysdev,
186 &req->request, req->direction);
189 trace_dwc3_gadget_giveback(req);
192 pm_runtime_put(dwc->dev);
196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197 * @dep: The endpoint to whom the request belongs to
198 * @req: The request we're giving back
199 * @status: completion code for the request
201 * Must be called with controller's lock held and interrupts disabled. This
202 * function will unmap @req and call its ->complete() callback to notify upper
203 * layers that it has completed.
205 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
208 struct dwc3 *dwc = dep->dwc;
210 dwc3_gadget_del_and_unmap_request(dep, req, status);
212 spin_unlock(&dwc->lock);
213 usb_gadget_giveback_request(&dep->endpoint, &req->request);
214 spin_lock(&dwc->lock);
218 * dwc3_send_gadget_generic_command - issue a generic command for the controller
219 * @dwc: pointer to the controller context
220 * @cmd: the command to be issued
221 * @param: command parameter
223 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
224 * and wait for its completion.
226 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
233 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
234 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
237 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
238 if (!(reg & DWC3_DGCMD_CMDACT)) {
239 status = DWC3_DGCMD_STATUS(reg);
251 trace_dwc3_gadget_generic_cmd(cmd, param, status);
256 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
259 * dwc3_send_gadget_ep_cmd - issue an endpoint command
260 * @dep: the endpoint to which the command is going to be issued
261 * @cmd: the command to be issued
262 * @params: parameters to the command
264 * Caller should handle locking. This function will issue @cmd with given
265 * @params to @dep and wait for its completion.
267 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
268 struct dwc3_gadget_ep_cmd_params *params)
270 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
271 struct dwc3 *dwc = dep->dwc;
280 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
281 * we're issuing an endpoint command, we must check if
282 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
284 * We will also set SUSPHY bit to what it was before returning as stated
285 * by the same section on Synopsys databook.
287 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
288 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
289 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
291 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
292 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
296 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
299 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
300 dwc->link_state == DWC3_LINK_STATE_U2 ||
301 dwc->link_state == DWC3_LINK_STATE_U3);
303 if (unlikely(needs_wakeup)) {
304 ret = __dwc3_gadget_wakeup(dwc);
305 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
310 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
311 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
312 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
315 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
316 * not relying on XferNotReady, we can make use of a special "No
317 * Response Update Transfer" command where we should clear both CmdAct
320 * With this, we don't need to wait for command completion and can
321 * straight away issue further commands to the endpoint.
323 * NOTICE: We're making an assumption that control endpoints will never
324 * make use of Update Transfer command. This is a safe assumption
325 * because we can never have more than one request at a time with
326 * Control Endpoints. If anybody changes that assumption, this chunk
327 * needs to be updated accordingly.
329 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
330 !usb_endpoint_xfer_isoc(desc))
331 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
333 cmd |= DWC3_DEPCMD_CMDACT;
335 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
337 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
338 if (!(reg & DWC3_DEPCMD_CMDACT)) {
339 cmd_status = DWC3_DEPCMD_STATUS(reg);
341 switch (cmd_status) {
345 case DEPEVT_TRANSFER_NO_RESOURCE:
348 case DEPEVT_TRANSFER_BUS_EXPIRY:
350 * SW issues START TRANSFER command to
351 * isochronous ep with future frame interval. If
352 * future interval time has already passed when
353 * core receives the command, it will respond
354 * with an error status of 'Bus Expiry'.
356 * Instead of always returning -EINVAL, let's
357 * give a hint to the gadget driver that this is
358 * the case by returning -EAGAIN.
363 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
372 cmd_status = -ETIMEDOUT;
375 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
378 switch (DWC3_DEPCMD_CMD(cmd)) {
379 case DWC3_DEPCMD_STARTTRANSFER:
380 dep->flags |= DWC3_EP_TRANSFER_STARTED;
382 case DWC3_DEPCMD_ENDTRANSFER:
383 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
391 if (unlikely(susphy)) {
392 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
393 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
394 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
400 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
402 struct dwc3 *dwc = dep->dwc;
403 struct dwc3_gadget_ep_cmd_params params;
404 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
407 * As of core revision 2.60a the recommended programming model
408 * is to set the ClearPendIN bit when issuing a Clear Stall EP
409 * command for IN endpoints. This is to prevent an issue where
410 * some (non-compliant) hosts may not send ACK TPs for pending
411 * IN transfers due to a mishandled error condition. Synopsys
414 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
415 (dwc->gadget.speed >= USB_SPEED_SUPER))
416 cmd |= DWC3_DEPCMD_CLEARPENDIN;
418 memset(¶ms, 0, sizeof(params));
420 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
423 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
424 struct dwc3_trb *trb)
426 u32 offset = (char *) trb - (char *) dep->trb_pool;
428 return dep->trb_pool_dma + offset;
431 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
433 struct dwc3 *dwc = dep->dwc;
438 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
439 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
440 &dep->trb_pool_dma, GFP_KERNEL);
441 if (!dep->trb_pool) {
442 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
450 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
452 struct dwc3 *dwc = dep->dwc;
454 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
455 dep->trb_pool, dep->trb_pool_dma);
457 dep->trb_pool = NULL;
458 dep->trb_pool_dma = 0;
461 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
463 struct dwc3_gadget_ep_cmd_params params;
465 memset(¶ms, 0x00, sizeof(params));
467 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
469 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
474 * dwc3_gadget_start_config - configure ep resources
475 * @dwc: pointer to our controller context structure
476 * @dep: endpoint that is being enabled
478 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
479 * completion, it will set Transfer Resource for all available endpoints.
481 * The assignment of transfer resources cannot perfectly follow the data book
482 * due to the fact that the controller driver does not have all knowledge of the
483 * configuration in advance. It is given this information piecemeal by the
484 * composite gadget framework after every SET_CONFIGURATION and
485 * SET_INTERFACE. Trying to follow the databook programming model in this
486 * scenario can cause errors. For two reasons:
488 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
489 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
490 * incorrect in the scenario of multiple interfaces.
492 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
493 * endpoint on alt setting (8.1.6).
495 * The following simplified method is used instead:
497 * All hardware endpoints can be assigned a transfer resource and this setting
498 * will stay persistent until either a core reset or hibernation. So whenever we
499 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
500 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
501 * guaranteed that there are as many transfer resources as endpoints.
503 * This function is called for each endpoint when it is being enabled but is
504 * triggered only when called for EP0-out, which always happens first, and which
505 * should only happen in one of the above conditions.
507 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
509 struct dwc3_gadget_ep_cmd_params params;
518 memset(¶ms, 0x00, sizeof(params));
519 cmd = DWC3_DEPCMD_DEPSTARTCFG;
522 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
526 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
527 struct dwc3_ep *dep = dwc->eps[i];
532 ret = dwc3_gadget_set_xfer_resource(dep);
540 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
542 const struct usb_ss_ep_comp_descriptor *comp_desc;
543 const struct usb_endpoint_descriptor *desc;
544 struct dwc3_gadget_ep_cmd_params params;
545 struct dwc3 *dwc = dep->dwc;
547 comp_desc = dep->endpoint.comp_desc;
548 desc = dep->endpoint.desc;
550 memset(¶ms, 0x00, sizeof(params));
552 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
553 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
555 /* Burst size is only needed in SuperSpeed mode */
556 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
557 u32 burst = dep->endpoint.maxburst;
558 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
561 params.param0 |= action;
562 if (action == DWC3_DEPCFG_ACTION_RESTORE)
563 params.param2 |= dep->saved_state;
565 if (usb_endpoint_xfer_control(desc))
566 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
568 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
569 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
571 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
572 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
573 | DWC3_DEPCFG_STREAM_EVENT_EN;
574 dep->stream_capable = true;
577 if (!usb_endpoint_xfer_control(desc))
578 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
581 * We are doing 1:1 mapping for endpoints, meaning
582 * Physical Endpoints 2 maps to Logical Endpoint 2 and
583 * so on. We consider the direction bit as part of the physical
584 * endpoint number. So USB endpoint 0x81 is 0x03.
586 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
589 * We must use the lower 16 TX FIFOs even though
593 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
595 if (desc->bInterval) {
596 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
597 dep->interval = 1 << (desc->bInterval - 1);
600 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
604 * __dwc3_gadget_ep_enable - initializes a hw endpoint
605 * @dep: endpoint to be initialized
606 * @action: one of INIT, MODIFY or RESTORE
608 * Caller should take care of locking. Execute all necessary commands to
609 * initialize a HW endpoint so it can be used by a gadget driver.
611 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
613 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
614 struct dwc3 *dwc = dep->dwc;
619 if (!(dep->flags & DWC3_EP_ENABLED)) {
620 ret = dwc3_gadget_start_config(dep);
625 ret = dwc3_gadget_set_ep_config(dep, action);
629 if (!(dep->flags & DWC3_EP_ENABLED)) {
630 struct dwc3_trb *trb_st_hw;
631 struct dwc3_trb *trb_link;
633 dep->type = usb_endpoint_type(desc);
634 dep->flags |= DWC3_EP_ENABLED;
635 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
637 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
638 reg |= DWC3_DALEPENA_EP(dep->number);
639 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
641 init_waitqueue_head(&dep->wait_end_transfer);
643 if (usb_endpoint_xfer_control(desc))
646 /* Initialize the TRB ring */
647 dep->trb_dequeue = 0;
648 dep->trb_enqueue = 0;
649 memset(dep->trb_pool, 0,
650 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
652 /* Link TRB. The HWO bit is never reset */
653 trb_st_hw = &dep->trb_pool[0];
655 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
656 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
657 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
658 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
659 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
663 * Issue StartTransfer here with no-op TRB so we can always rely on No
664 * Response Update Transfer command.
666 if (usb_endpoint_xfer_bulk(desc) ||
667 usb_endpoint_xfer_int(desc)) {
668 struct dwc3_gadget_ep_cmd_params params;
669 struct dwc3_trb *trb;
673 memset(¶ms, 0, sizeof(params));
674 trb = &dep->trb_pool[0];
675 trb_dma = dwc3_trb_dma_offset(dep, trb);
677 params.param0 = upper_32_bits(trb_dma);
678 params.param1 = lower_32_bits(trb_dma);
680 cmd = DWC3_DEPCMD_STARTTRANSFER;
682 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
686 dwc3_gadget_ep_get_transfer_index(dep);
690 trace_dwc3_gadget_ep_enable(dep);
695 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force);
696 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
698 struct dwc3_request *req;
700 dwc3_stop_active_transfer(dep, true);
702 /* - giveback all requests to gadget driver */
703 while (!list_empty(&dep->started_list)) {
704 req = next_request(&dep->started_list);
706 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
709 while (!list_empty(&dep->pending_list)) {
710 req = next_request(&dep->pending_list);
712 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
717 * __dwc3_gadget_ep_disable - disables a hw endpoint
718 * @dep: the endpoint to disable
720 * This function undoes what __dwc3_gadget_ep_enable did and also removes
721 * requests which are currently being processed by the hardware and those which
722 * are not yet scheduled.
724 * Caller should take care of locking.
726 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
728 struct dwc3 *dwc = dep->dwc;
731 trace_dwc3_gadget_ep_disable(dep);
733 dwc3_remove_requests(dwc, dep);
735 /* make sure HW endpoint isn't stalled */
736 if (dep->flags & DWC3_EP_STALL)
737 __dwc3_gadget_ep_set_halt(dep, 0, false);
739 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
740 reg &= ~DWC3_DALEPENA_EP(dep->number);
741 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
743 dep->stream_capable = false;
745 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
747 /* Clear out the ep descriptors for non-ep0 */
748 if (dep->number > 1) {
749 dep->endpoint.comp_desc = NULL;
750 dep->endpoint.desc = NULL;
756 /* -------------------------------------------------------------------------- */
758 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
759 const struct usb_endpoint_descriptor *desc)
764 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
769 /* -------------------------------------------------------------------------- */
771 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
772 const struct usb_endpoint_descriptor *desc)
779 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
780 pr_debug("dwc3: invalid parameters\n");
784 if (!desc->wMaxPacketSize) {
785 pr_debug("dwc3: missing wMaxPacketSize\n");
789 dep = to_dwc3_ep(ep);
792 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
793 "%s is already enabled\n",
797 spin_lock_irqsave(&dwc->lock, flags);
798 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
799 spin_unlock_irqrestore(&dwc->lock, flags);
804 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
812 pr_debug("dwc3: invalid parameters\n");
816 dep = to_dwc3_ep(ep);
819 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
820 "%s is already disabled\n",
824 spin_lock_irqsave(&dwc->lock, flags);
825 ret = __dwc3_gadget_ep_disable(dep);
826 spin_unlock_irqrestore(&dwc->lock, flags);
831 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
834 struct dwc3_request *req;
835 struct dwc3_ep *dep = to_dwc3_ep(ep);
837 req = kzalloc(sizeof(*req), gfp_flags);
841 req->epnum = dep->number;
844 trace_dwc3_alloc_request(req);
846 return &req->request;
849 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
850 struct usb_request *request)
852 struct dwc3_request *req = to_dwc3_request(request);
854 trace_dwc3_free_request(req);
859 * dwc3_ep_prev_trb - returns the previous TRB in the ring
860 * @dep: The endpoint with the TRB ring
861 * @index: The index of the current TRB in the ring
863 * Returns the TRB prior to the one pointed to by the index. If the
864 * index is 0, we will wrap backwards, skip the link TRB, and return
865 * the one just before that.
867 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
872 tmp = DWC3_TRB_NUM - 1;
874 return &dep->trb_pool[tmp - 1];
877 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
879 struct dwc3_trb *tmp;
883 * If enqueue & dequeue are equal than it is either full or empty.
885 * One way to know for sure is if the TRB right before us has HWO bit
886 * set or not. If it has, then we're definitely full and can't fit any
887 * more transfers in our ring.
889 if (dep->trb_enqueue == dep->trb_dequeue) {
890 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
891 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
894 return DWC3_TRB_NUM - 1;
897 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
898 trbs_left &= (DWC3_TRB_NUM - 1);
900 if (dep->trb_dequeue < dep->trb_enqueue)
906 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
907 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
908 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
910 struct dwc3 *dwc = dep->dwc;
911 struct usb_gadget *gadget = &dwc->gadget;
912 enum usb_device_speed speed = gadget->speed;
914 dwc3_ep_inc_enq(dep);
916 trb->size = DWC3_TRB_SIZE_LENGTH(length);
917 trb->bpl = lower_32_bits(dma);
918 trb->bph = upper_32_bits(dma);
920 switch (usb_endpoint_type(dep->endpoint.desc)) {
921 case USB_ENDPOINT_XFER_CONTROL:
922 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
925 case USB_ENDPOINT_XFER_ISOC:
927 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
930 * USB Specification 2.0 Section 5.9.2 states that: "If
931 * there is only a single transaction in the microframe,
932 * only a DATA0 data packet PID is used. If there are
933 * two transactions per microframe, DATA1 is used for
934 * the first transaction data packet and DATA0 is used
935 * for the second transaction data packet. If there are
936 * three transactions per microframe, DATA2 is used for
937 * the first transaction data packet, DATA1 is used for
938 * the second, and DATA0 is used for the third."
940 * IOW, we should satisfy the following cases:
942 * 1) length <= maxpacket
945 * 2) maxpacket < length <= (2 * maxpacket)
948 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
949 * - DATA2, DATA1, DATA0
951 if (speed == USB_SPEED_HIGH) {
952 struct usb_ep *ep = &dep->endpoint;
953 unsigned int mult = 2;
954 unsigned int maxp = usb_endpoint_maxp(ep->desc);
956 if (length <= (2 * maxp))
962 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
965 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
968 /* always enable Interrupt on Missed ISOC */
969 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
972 case USB_ENDPOINT_XFER_BULK:
973 case USB_ENDPOINT_XFER_INT:
974 trb->ctrl = DWC3_TRBCTL_NORMAL;
978 * This is only possible with faulty memory because we
979 * checked it already :)
981 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
982 usb_endpoint_type(dep->endpoint.desc));
985 /* always enable Continue on Short Packet */
986 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
987 trb->ctrl |= DWC3_TRB_CTRL_CSP;
990 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
993 if ((!no_interrupt && !chain) ||
994 (dwc3_calc_trbs_left(dep) == 0))
995 trb->ctrl |= DWC3_TRB_CTRL_IOC;
998 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1000 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1001 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1003 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1005 trace_dwc3_prepare_trb(dep, trb);
1009 * dwc3_prepare_one_trb - setup one TRB from one request
1010 * @dep: endpoint for which this request is prepared
1011 * @req: dwc3_request pointer
1012 * @chain: should this TRB be chained to the next?
1013 * @node: only for isochronous endpoints. First TRB needs different type.
1015 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1016 struct dwc3_request *req, unsigned chain, unsigned node)
1018 struct dwc3_trb *trb;
1019 unsigned int length;
1021 unsigned stream_id = req->request.stream_id;
1022 unsigned short_not_ok = req->request.short_not_ok;
1023 unsigned no_interrupt = req->request.no_interrupt;
1025 if (req->request.num_sgs > 0) {
1026 length = sg_dma_len(req->start_sg);
1027 dma = sg_dma_address(req->start_sg);
1029 length = req->request.length;
1030 dma = req->request.dma;
1033 trb = &dep->trb_pool[dep->trb_enqueue];
1036 dwc3_gadget_move_started_request(req);
1038 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1041 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1042 stream_id, short_not_ok, no_interrupt);
1045 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1046 struct dwc3_request *req)
1048 struct scatterlist *sg = req->start_sg;
1049 struct scatterlist *s;
1052 unsigned int remaining = req->request.num_mapped_sgs
1053 - req->num_queued_sgs;
1055 for_each_sg(sg, s, remaining, i) {
1056 unsigned int length = req->request.length;
1057 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1058 unsigned int rem = length % maxp;
1059 unsigned chain = true;
1064 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1065 struct dwc3 *dwc = dep->dwc;
1066 struct dwc3_trb *trb;
1068 req->unaligned = true;
1070 /* prepare normal TRB */
1071 dwc3_prepare_one_trb(dep, req, true, i);
1073 /* Now prepare one extra TRB to align transfer size */
1074 trb = &dep->trb_pool[dep->trb_enqueue];
1075 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1076 maxp - rem, false, 0,
1077 req->request.stream_id,
1078 req->request.short_not_ok,
1079 req->request.no_interrupt);
1081 dwc3_prepare_one_trb(dep, req, chain, i);
1085 * There can be a situation where all sgs in sglist are not
1086 * queued because of insufficient trb number. To handle this
1087 * case, update start_sg to next sg to be queued, so that
1088 * we have free trbs we can continue queuing from where we
1089 * previously stopped
1092 req->start_sg = sg_next(s);
1094 req->num_queued_sgs++;
1096 if (!dwc3_calc_trbs_left(dep))
1101 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1102 struct dwc3_request *req)
1104 unsigned int length = req->request.length;
1105 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1106 unsigned int rem = length % maxp;
1108 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1109 struct dwc3 *dwc = dep->dwc;
1110 struct dwc3_trb *trb;
1112 req->unaligned = true;
1114 /* prepare normal TRB */
1115 dwc3_prepare_one_trb(dep, req, true, 0);
1117 /* Now prepare one extra TRB to align transfer size */
1118 trb = &dep->trb_pool[dep->trb_enqueue];
1119 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1120 false, 0, req->request.stream_id,
1121 req->request.short_not_ok,
1122 req->request.no_interrupt);
1123 } else if (req->request.zero && req->request.length &&
1124 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1125 struct dwc3 *dwc = dep->dwc;
1126 struct dwc3_trb *trb;
1130 /* prepare normal TRB */
1131 dwc3_prepare_one_trb(dep, req, true, 0);
1133 /* Now prepare one extra TRB to handle ZLP */
1134 trb = &dep->trb_pool[dep->trb_enqueue];
1135 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1136 false, 0, req->request.stream_id,
1137 req->request.short_not_ok,
1138 req->request.no_interrupt);
1140 dwc3_prepare_one_trb(dep, req, false, 0);
1145 * dwc3_prepare_trbs - setup TRBs from requests
1146 * @dep: endpoint for which requests are being prepared
1148 * The function goes through the requests list and sets up TRBs for the
1149 * transfers. The function returns once there are no more TRBs available or
1150 * it runs out of requests.
1152 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1154 struct dwc3_request *req, *n;
1156 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1159 * We can get in a situation where there's a request in the started list
1160 * but there weren't enough TRBs to fully kick it in the first time
1161 * around, so it has been waiting for more TRBs to be freed up.
1163 * In that case, we should check if we have a request with pending_sgs
1164 * in the started list and prepare TRBs for that request first,
1165 * otherwise we will prepare TRBs completely out of order and that will
1168 list_for_each_entry(req, &dep->started_list, list) {
1169 if (req->num_pending_sgs > 0)
1170 dwc3_prepare_one_trb_sg(dep, req);
1172 if (!dwc3_calc_trbs_left(dep))
1176 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1177 struct dwc3 *dwc = dep->dwc;
1180 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1185 req->sg = req->request.sg;
1186 req->start_sg = req->sg;
1187 req->num_queued_sgs = 0;
1188 req->num_pending_sgs = req->request.num_mapped_sgs;
1190 if (req->num_pending_sgs > 0)
1191 dwc3_prepare_one_trb_sg(dep, req);
1193 dwc3_prepare_one_trb_linear(dep, req);
1195 if (!dwc3_calc_trbs_left(dep))
1200 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1202 struct dwc3_gadget_ep_cmd_params params;
1203 struct dwc3_request *req;
1208 if (!dwc3_calc_trbs_left(dep))
1211 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1213 dwc3_prepare_trbs(dep);
1214 req = next_request(&dep->started_list);
1216 dep->flags |= DWC3_EP_PENDING_REQUEST;
1220 memset(¶ms, 0, sizeof(params));
1223 params.param0 = upper_32_bits(req->trb_dma);
1224 params.param1 = lower_32_bits(req->trb_dma);
1225 cmd = DWC3_DEPCMD_STARTTRANSFER;
1227 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1228 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1230 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1231 DWC3_DEPCMD_PARAM(dep->resource_index);
1234 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1237 * FIXME we need to iterate over the list of requests
1238 * here and stop, unmap, free and del each of the linked
1239 * requests instead of what we do now.
1242 memset(req->trb, 0, sizeof(struct dwc3_trb));
1243 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1248 dwc3_gadget_ep_get_transfer_index(dep);
1253 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1257 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1258 return DWC3_DSTS_SOFFN(reg);
1261 static void __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1263 if (list_empty(&dep->pending_list)) {
1264 dev_info(dep->dwc->dev, "%s: ran out of requests\n",
1266 dep->flags |= DWC3_EP_PENDING_REQUEST;
1270 dep->frame_number = DWC3_ALIGN_FRAME(dep);
1271 __dwc3_gadget_kick_transfer(dep);
1274 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1276 struct dwc3 *dwc = dep->dwc;
1278 if (!dep->endpoint.desc) {
1279 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1284 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1285 &req->request, req->dep->name))
1288 pm_runtime_get(dwc->dev);
1290 req->request.actual = 0;
1291 req->request.status = -EINPROGRESS;
1292 req->direction = dep->direction;
1293 req->epnum = dep->number;
1295 trace_dwc3_ep_queue(req);
1297 list_add_tail(&req->list, &dep->pending_list);
1300 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1301 * wait for a XferNotReady event so we will know what's the current
1302 * (micro-)frame number.
1304 * Without this trick, we are very, very likely gonna get Bus Expiry
1305 * errors which will force us issue EndTransfer command.
1307 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1308 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1309 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1312 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1313 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1314 __dwc3_gadget_start_isoc(dep);
1320 return __dwc3_gadget_kick_transfer(dep);
1323 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1326 struct dwc3_request *req = to_dwc3_request(request);
1327 struct dwc3_ep *dep = to_dwc3_ep(ep);
1328 struct dwc3 *dwc = dep->dwc;
1330 unsigned long flags;
1334 spin_lock_irqsave(&dwc->lock, flags);
1335 ret = __dwc3_gadget_ep_queue(dep, req);
1336 spin_unlock_irqrestore(&dwc->lock, flags);
1341 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1342 struct usb_request *request)
1344 struct dwc3_request *req = to_dwc3_request(request);
1345 struct dwc3_request *r = NULL;
1347 struct dwc3_ep *dep = to_dwc3_ep(ep);
1348 struct dwc3 *dwc = dep->dwc;
1350 unsigned long flags;
1353 trace_dwc3_ep_dequeue(req);
1355 spin_lock_irqsave(&dwc->lock, flags);
1357 list_for_each_entry(r, &dep->pending_list, list) {
1363 list_for_each_entry(r, &dep->started_list, list) {
1368 /* wait until it is processed */
1369 dwc3_stop_active_transfer(dep, true);
1372 * If request was already started, this means we had to
1373 * stop the transfer. With that we also need to ignore
1374 * all TRBs used by the request, however TRBs can only
1375 * be modified after completion of END_TRANSFER
1376 * command. So what we do here is that we wait for
1377 * END_TRANSFER completion and only after that, we jump
1378 * over TRBs by clearing HWO and incrementing dequeue
1381 * Note that we have 2 possible types of transfers here:
1383 * i) Linear buffer request
1384 * ii) SG-list based request
1386 * SG-list based requests will have r->num_pending_sgs
1387 * set to a valid number (> 0). Linear requests,
1388 * normally use a single TRB.
1390 * For each of these two cases, if r->unaligned flag is
1391 * set, one extra TRB has been used to align transfer
1392 * size to wMaxPacketSize.
1394 * All of these cases need to be taken into
1395 * consideration so we don't mess up our TRB ring
1398 wait_event_lock_irq(dep->wait_end_transfer,
1399 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1405 if (r->num_pending_sgs) {
1406 struct dwc3_trb *trb;
1409 for (i = 0; i < r->num_pending_sgs; i++) {
1411 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1412 dwc3_ep_inc_deq(dep);
1415 if (r->unaligned || r->zero) {
1416 trb = r->trb + r->num_pending_sgs + 1;
1417 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1418 dwc3_ep_inc_deq(dep);
1421 struct dwc3_trb *trb = r->trb;
1423 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1424 dwc3_ep_inc_deq(dep);
1426 if (r->unaligned || r->zero) {
1428 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1429 dwc3_ep_inc_deq(dep);
1434 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1441 /* giveback the request */
1443 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1446 spin_unlock_irqrestore(&dwc->lock, flags);
1451 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1453 struct dwc3_gadget_ep_cmd_params params;
1454 struct dwc3 *dwc = dep->dwc;
1457 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1458 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1462 memset(¶ms, 0x00, sizeof(params));
1465 struct dwc3_trb *trb;
1467 unsigned transfer_in_flight;
1470 if (dep->flags & DWC3_EP_STALL)
1473 if (dep->number > 1)
1474 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1476 trb = &dwc->ep0_trb[dep->trb_enqueue];
1478 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1479 started = !list_empty(&dep->started_list);
1481 if (!protocol && ((dep->direction && transfer_in_flight) ||
1482 (!dep->direction && started))) {
1486 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1489 dev_err(dwc->dev, "failed to set STALL on %s\n",
1492 dep->flags |= DWC3_EP_STALL;
1494 if (!(dep->flags & DWC3_EP_STALL))
1497 ret = dwc3_send_clear_stall_ep_cmd(dep);
1499 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1502 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1508 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1510 struct dwc3_ep *dep = to_dwc3_ep(ep);
1511 struct dwc3 *dwc = dep->dwc;
1513 unsigned long flags;
1517 spin_lock_irqsave(&dwc->lock, flags);
1518 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1519 spin_unlock_irqrestore(&dwc->lock, flags);
1524 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1526 struct dwc3_ep *dep = to_dwc3_ep(ep);
1527 struct dwc3 *dwc = dep->dwc;
1528 unsigned long flags;
1531 spin_lock_irqsave(&dwc->lock, flags);
1532 dep->flags |= DWC3_EP_WEDGE;
1534 if (dep->number == 0 || dep->number == 1)
1535 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1537 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1538 spin_unlock_irqrestore(&dwc->lock, flags);
1543 /* -------------------------------------------------------------------------- */
1545 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1546 .bLength = USB_DT_ENDPOINT_SIZE,
1547 .bDescriptorType = USB_DT_ENDPOINT,
1548 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1551 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1552 .enable = dwc3_gadget_ep0_enable,
1553 .disable = dwc3_gadget_ep0_disable,
1554 .alloc_request = dwc3_gadget_ep_alloc_request,
1555 .free_request = dwc3_gadget_ep_free_request,
1556 .queue = dwc3_gadget_ep0_queue,
1557 .dequeue = dwc3_gadget_ep_dequeue,
1558 .set_halt = dwc3_gadget_ep0_set_halt,
1559 .set_wedge = dwc3_gadget_ep_set_wedge,
1562 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1563 .enable = dwc3_gadget_ep_enable,
1564 .disable = dwc3_gadget_ep_disable,
1565 .alloc_request = dwc3_gadget_ep_alloc_request,
1566 .free_request = dwc3_gadget_ep_free_request,
1567 .queue = dwc3_gadget_ep_queue,
1568 .dequeue = dwc3_gadget_ep_dequeue,
1569 .set_halt = dwc3_gadget_ep_set_halt,
1570 .set_wedge = dwc3_gadget_ep_set_wedge,
1573 /* -------------------------------------------------------------------------- */
1575 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1577 struct dwc3 *dwc = gadget_to_dwc(g);
1579 return __dwc3_gadget_get_frame(dwc);
1582 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1593 * According to the Databook Remote wakeup request should
1594 * be issued only when the device is in early suspend state.
1596 * We can check that via USB Link State bits in DSTS register.
1598 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1600 speed = reg & DWC3_DSTS_CONNECTSPD;
1601 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1602 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1605 link_state = DWC3_DSTS_USBLNKST(reg);
1607 switch (link_state) {
1608 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1609 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1615 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1617 dev_err(dwc->dev, "failed to put link in Recovery\n");
1621 /* Recent versions do this automatically */
1622 if (dwc->revision < DWC3_REVISION_194A) {
1623 /* write zeroes to Link Change Request */
1624 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1625 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1626 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1629 /* poll until Link State changes to ON */
1633 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1635 /* in HS, means ON */
1636 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1640 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1641 dev_err(dwc->dev, "failed to send remote wakeup\n");
1648 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1650 struct dwc3 *dwc = gadget_to_dwc(g);
1651 unsigned long flags;
1654 spin_lock_irqsave(&dwc->lock, flags);
1655 ret = __dwc3_gadget_wakeup(dwc);
1656 spin_unlock_irqrestore(&dwc->lock, flags);
1661 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1664 struct dwc3 *dwc = gadget_to_dwc(g);
1665 unsigned long flags;
1667 spin_lock_irqsave(&dwc->lock, flags);
1668 g->is_selfpowered = !!is_selfpowered;
1669 spin_unlock_irqrestore(&dwc->lock, flags);
1674 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1679 if (pm_runtime_suspended(dwc->dev))
1682 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1684 if (dwc->revision <= DWC3_REVISION_187A) {
1685 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1686 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1689 if (dwc->revision >= DWC3_REVISION_194A)
1690 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1691 reg |= DWC3_DCTL_RUN_STOP;
1693 if (dwc->has_hibernation)
1694 reg |= DWC3_DCTL_KEEP_CONNECT;
1696 dwc->pullups_connected = true;
1698 reg &= ~DWC3_DCTL_RUN_STOP;
1700 if (dwc->has_hibernation && !suspend)
1701 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1703 dwc->pullups_connected = false;
1706 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1709 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1710 reg &= DWC3_DSTS_DEVCTRLHLT;
1711 } while (--timeout && !(!is_on ^ !reg));
1719 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1721 struct dwc3 *dwc = gadget_to_dwc(g);
1722 unsigned long flags;
1728 * Per databook, when we want to stop the gadget, if a control transfer
1729 * is still in process, complete it and get the core into setup phase.
1731 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1732 reinit_completion(&dwc->ep0_in_setup);
1734 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1735 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1737 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1742 spin_lock_irqsave(&dwc->lock, flags);
1743 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1744 spin_unlock_irqrestore(&dwc->lock, flags);
1749 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1753 /* Enable all but Start and End of Frame IRQs */
1754 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1755 DWC3_DEVTEN_EVNTOVERFLOWEN |
1756 DWC3_DEVTEN_CMDCMPLTEN |
1757 DWC3_DEVTEN_ERRTICERREN |
1758 DWC3_DEVTEN_WKUPEVTEN |
1759 DWC3_DEVTEN_CONNECTDONEEN |
1760 DWC3_DEVTEN_USBRSTEN |
1761 DWC3_DEVTEN_DISCONNEVTEN);
1763 if (dwc->revision < DWC3_REVISION_250A)
1764 reg |= DWC3_DEVTEN_ULSTCNGEN;
1766 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1769 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1771 /* mask all interrupts */
1772 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1775 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1776 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1779 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1780 * @dwc: pointer to our context structure
1782 * The following looks like complex but it's actually very simple. In order to
1783 * calculate the number of packets we can burst at once on OUT transfers, we're
1784 * gonna use RxFIFO size.
1786 * To calculate RxFIFO size we need two numbers:
1787 * MDWIDTH = size, in bits, of the internal memory bus
1788 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1790 * Given these two numbers, the formula is simple:
1792 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1794 * 24 bytes is for 3x SETUP packets
1795 * 16 bytes is a clock domain crossing tolerance
1797 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1799 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1806 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1807 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1809 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1810 nump = min_t(u32, nump, 16);
1813 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1814 reg &= ~DWC3_DCFG_NUMP_MASK;
1815 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1816 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1819 static int __dwc3_gadget_start(struct dwc3 *dwc)
1821 struct dwc3_ep *dep;
1826 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1827 * the core supports IMOD, disable it.
1829 if (dwc->imod_interval) {
1830 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1831 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1832 } else if (dwc3_has_imod(dwc)) {
1833 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1837 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1838 * field instead of letting dwc3 itself calculate that automatically.
1840 * This way, we maximize the chances that we'll be able to get several
1841 * bursts of data without going through any sort of endpoint throttling.
1843 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1844 if (dwc3_is_usb31(dwc))
1845 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1847 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1849 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1851 dwc3_gadget_setup_nump(dwc);
1853 /* Start with SuperSpeed Default */
1854 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1857 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1859 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1864 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1866 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1870 /* begin to receive SETUP packets */
1871 dwc->ep0state = EP0_SETUP_PHASE;
1872 dwc3_ep0_out_start(dwc);
1874 dwc3_gadget_enable_irq(dwc);
1879 __dwc3_gadget_ep_disable(dwc->eps[0]);
1885 static int dwc3_gadget_start(struct usb_gadget *g,
1886 struct usb_gadget_driver *driver)
1888 struct dwc3 *dwc = gadget_to_dwc(g);
1889 unsigned long flags;
1893 irq = dwc->irq_gadget;
1894 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1895 IRQF_SHARED, "dwc3", dwc->ev_buf);
1897 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1902 spin_lock_irqsave(&dwc->lock, flags);
1903 if (dwc->gadget_driver) {
1904 dev_err(dwc->dev, "%s is already bound to %s\n",
1906 dwc->gadget_driver->driver.name);
1911 dwc->gadget_driver = driver;
1913 if (pm_runtime_active(dwc->dev))
1914 __dwc3_gadget_start(dwc);
1916 spin_unlock_irqrestore(&dwc->lock, flags);
1921 spin_unlock_irqrestore(&dwc->lock, flags);
1928 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1930 dwc3_gadget_disable_irq(dwc);
1931 __dwc3_gadget_ep_disable(dwc->eps[0]);
1932 __dwc3_gadget_ep_disable(dwc->eps[1]);
1935 static int dwc3_gadget_stop(struct usb_gadget *g)
1937 struct dwc3 *dwc = gadget_to_dwc(g);
1938 unsigned long flags;
1942 spin_lock_irqsave(&dwc->lock, flags);
1944 if (pm_runtime_suspended(dwc->dev))
1947 __dwc3_gadget_stop(dwc);
1949 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1950 struct dwc3_ep *dep = dwc->eps[epnum];
1956 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1959 ret = wait_event_interruptible_lock_irq_timeout(dep->wait_end_transfer,
1960 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1961 dwc->lock, msecs_to_jiffies(5));
1964 /* Timed out or interrupted! There's nothing much
1965 * we can do so we just log here and print which
1966 * endpoints timed out at the end.
1968 tmo_eps |= 1 << epnum;
1969 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
1975 "end transfer timed out on endpoints 0x%x [bitmap]\n",
1980 dwc->gadget_driver = NULL;
1981 spin_unlock_irqrestore(&dwc->lock, flags);
1983 free_irq(dwc->irq_gadget, dwc->ev_buf);
1988 static void dwc3_gadget_set_speed(struct usb_gadget *g,
1989 enum usb_device_speed speed)
1991 struct dwc3 *dwc = gadget_to_dwc(g);
1992 unsigned long flags;
1995 spin_lock_irqsave(&dwc->lock, flags);
1996 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1997 reg &= ~(DWC3_DCFG_SPEED_MASK);
2000 * WORKAROUND: DWC3 revision < 2.20a have an issue
2001 * which would cause metastability state on Run/Stop
2002 * bit if we try to force the IP to USB2-only mode.
2004 * Because of that, we cannot configure the IP to any
2005 * speed other than the SuperSpeed
2009 * STAR#9000525659: Clock Domain Crossing on DCTL in
2012 if (dwc->revision < DWC3_REVISION_220A &&
2013 !dwc->dis_metastability_quirk) {
2014 reg |= DWC3_DCFG_SUPERSPEED;
2018 reg |= DWC3_DCFG_LOWSPEED;
2020 case USB_SPEED_FULL:
2021 reg |= DWC3_DCFG_FULLSPEED;
2023 case USB_SPEED_HIGH:
2024 reg |= DWC3_DCFG_HIGHSPEED;
2026 case USB_SPEED_SUPER:
2027 reg |= DWC3_DCFG_SUPERSPEED;
2029 case USB_SPEED_SUPER_PLUS:
2030 if (dwc3_is_usb31(dwc))
2031 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2033 reg |= DWC3_DCFG_SUPERSPEED;
2036 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2038 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2039 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2041 reg |= DWC3_DCFG_SUPERSPEED;
2044 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2046 spin_unlock_irqrestore(&dwc->lock, flags);
2049 static const struct usb_gadget_ops dwc3_gadget_ops = {
2050 .get_frame = dwc3_gadget_get_frame,
2051 .wakeup = dwc3_gadget_wakeup,
2052 .set_selfpowered = dwc3_gadget_set_selfpowered,
2053 .pullup = dwc3_gadget_pullup,
2054 .udc_start = dwc3_gadget_start,
2055 .udc_stop = dwc3_gadget_stop,
2056 .udc_set_speed = dwc3_gadget_set_speed,
2059 /* -------------------------------------------------------------------------- */
2061 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2063 struct dwc3 *dwc = dep->dwc;
2065 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2066 dep->endpoint.maxburst = 1;
2067 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2068 if (!dep->direction)
2069 dwc->gadget.ep0 = &dep->endpoint;
2071 dep->endpoint.caps.type_control = true;
2076 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2078 struct dwc3 *dwc = dep->dwc;
2083 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2084 /* MDWIDTH is represented in bits, we need it in bytes */
2087 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2088 if (dwc3_is_usb31(dwc))
2089 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2091 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2093 /* FIFO Depth is in MDWDITH bytes. Multiply */
2096 kbytes = size / 1024;
2101 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2102 * internal overhead. We don't really know how these are used,
2103 * but documentation say it exists.
2105 size -= mdwidth * (kbytes + 1);
2108 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2110 dep->endpoint.max_streams = 15;
2111 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2112 list_add_tail(&dep->endpoint.ep_list,
2113 &dwc->gadget.ep_list);
2114 dep->endpoint.caps.type_iso = true;
2115 dep->endpoint.caps.type_bulk = true;
2116 dep->endpoint.caps.type_int = true;
2118 return dwc3_alloc_trb_pool(dep);
2121 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2123 struct dwc3 *dwc = dep->dwc;
2125 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2126 dep->endpoint.max_streams = 15;
2127 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2128 list_add_tail(&dep->endpoint.ep_list,
2129 &dwc->gadget.ep_list);
2130 dep->endpoint.caps.type_iso = true;
2131 dep->endpoint.caps.type_bulk = true;
2132 dep->endpoint.caps.type_int = true;
2134 return dwc3_alloc_trb_pool(dep);
2137 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2139 struct dwc3_ep *dep;
2140 bool direction = epnum & 1;
2142 u8 num = epnum >> 1;
2144 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2149 dep->number = epnum;
2150 dep->direction = direction;
2151 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2152 dwc->eps[epnum] = dep;
2154 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2155 direction ? "in" : "out");
2157 dep->endpoint.name = dep->name;
2159 if (!(dep->number > 1)) {
2160 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2161 dep->endpoint.comp_desc = NULL;
2164 spin_lock_init(&dep->lock);
2167 ret = dwc3_gadget_init_control_endpoint(dep);
2169 ret = dwc3_gadget_init_in_endpoint(dep);
2171 ret = dwc3_gadget_init_out_endpoint(dep);
2176 dep->endpoint.caps.dir_in = direction;
2177 dep->endpoint.caps.dir_out = !direction;
2179 INIT_LIST_HEAD(&dep->pending_list);
2180 INIT_LIST_HEAD(&dep->started_list);
2185 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2189 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2191 for (epnum = 0; epnum < total; epnum++) {
2194 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2202 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2204 struct dwc3_ep *dep;
2207 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2208 dep = dwc->eps[epnum];
2212 * Physical endpoints 0 and 1 are special; they form the
2213 * bi-directional USB endpoint 0.
2215 * For those two physical endpoints, we don't allocate a TRB
2216 * pool nor do we add them the endpoints list. Due to that, we
2217 * shouldn't do these two operations otherwise we would end up
2218 * with all sorts of bugs when removing dwc3.ko.
2220 if (epnum != 0 && epnum != 1) {
2221 dwc3_free_trb_pool(dep);
2222 list_del(&dep->endpoint.ep_list);
2229 /* -------------------------------------------------------------------------- */
2231 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2232 struct dwc3_request *req, struct dwc3_trb *trb,
2233 const struct dwc3_event_depevt *event, int status, int chain)
2237 dwc3_ep_inc_deq(dep);
2239 trace_dwc3_complete_trb(dep, trb);
2242 * If we're in the middle of series of chained TRBs and we
2243 * receive a short transfer along the way, DWC3 will skip
2244 * through all TRBs including the last TRB in the chain (the
2245 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2246 * bit and SW has to do it manually.
2248 * We're going to do that here to avoid problems of HW trying
2249 * to use bogus TRBs for transfers.
2251 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2252 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2255 * If we're dealing with unaligned size OUT transfer, we will be left
2256 * with one TRB pending in the ring. We need to manually clear HWO bit
2259 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2260 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2264 count = trb->size & DWC3_TRB_SIZE_MASK;
2265 req->remaining += count;
2267 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2270 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2273 if (event->status & DEPEVT_STATUS_IOC)
2279 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2280 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2283 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2284 struct scatterlist *sg = req->sg;
2285 struct scatterlist *s;
2286 unsigned int pending = req->num_pending_sgs;
2290 for_each_sg(sg, s, pending, i) {
2291 trb = &dep->trb_pool[dep->trb_dequeue];
2293 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2296 req->sg = sg_next(s);
2297 req->num_pending_sgs--;
2299 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2300 trb, event, status, true);
2308 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2309 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2312 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2314 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2315 event, status, false);
2318 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2320 return req->request.actual == req->request.length;
2323 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2324 const struct dwc3_event_depevt *event,
2325 struct dwc3_request *req, int status)
2329 if (req->num_pending_sgs)
2330 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2333 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2336 if (req->unaligned || req->zero) {
2337 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2339 req->unaligned = false;
2343 req->request.actual = req->request.length - req->remaining;
2345 if (!dwc3_gadget_ep_request_completed(req) &&
2346 req->num_pending_sgs) {
2347 __dwc3_gadget_kick_transfer(dep);
2351 dwc3_gadget_giveback(dep, req, status);
2357 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2358 const struct dwc3_event_depevt *event, int status)
2360 struct dwc3_request *req;
2361 struct dwc3_request *tmp;
2363 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2366 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2373 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2374 const struct dwc3_event_depevt *event)
2376 dep->frame_number = event->parameters;
2379 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2380 const struct dwc3_event_depevt *event)
2382 struct dwc3 *dwc = dep->dwc;
2383 unsigned status = 0;
2386 dwc3_gadget_endpoint_frame_from_event(dep, event);
2388 if (event->status & DEPEVT_STATUS_BUSERR)
2389 status = -ECONNRESET;
2391 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2394 if (list_empty(&dep->started_list))
2398 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2401 dwc3_stop_active_transfer(dep, true);
2402 dep->flags = DWC3_EP_ENABLED;
2406 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2407 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2409 if (dwc->revision < DWC3_REVISION_183A) {
2413 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2416 if (!(dep->flags & DWC3_EP_ENABLED))
2419 if (!list_empty(&dep->started_list))
2423 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2425 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2431 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2432 const struct dwc3_event_depevt *event)
2434 dwc3_gadget_endpoint_frame_from_event(dep, event);
2435 __dwc3_gadget_start_isoc(dep);
2438 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2439 const struct dwc3_event_depevt *event)
2441 struct dwc3_ep *dep;
2442 u8 epnum = event->endpoint_number;
2445 dep = dwc->eps[epnum];
2447 if (!(dep->flags & DWC3_EP_ENABLED)) {
2448 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2451 /* Handle only EPCMDCMPLT when EP disabled */
2452 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2456 if (epnum == 0 || epnum == 1) {
2457 dwc3_ep0_interrupt(dwc, event);
2461 switch (event->endpoint_event) {
2462 case DWC3_DEPEVT_XFERINPROGRESS:
2463 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2465 case DWC3_DEPEVT_XFERNOTREADY:
2466 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2468 case DWC3_DEPEVT_EPCMDCMPLT:
2469 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2471 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2472 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2473 wake_up(&dep->wait_end_transfer);
2476 case DWC3_DEPEVT_STREAMEVT:
2477 case DWC3_DEPEVT_XFERCOMPLETE:
2478 case DWC3_DEPEVT_RXTXFIFOEVT:
2483 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2485 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2486 spin_unlock(&dwc->lock);
2487 dwc->gadget_driver->disconnect(&dwc->gadget);
2488 spin_lock(&dwc->lock);
2492 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2494 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2495 spin_unlock(&dwc->lock);
2496 dwc->gadget_driver->suspend(&dwc->gadget);
2497 spin_lock(&dwc->lock);
2501 static void dwc3_resume_gadget(struct dwc3 *dwc)
2503 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2504 spin_unlock(&dwc->lock);
2505 dwc->gadget_driver->resume(&dwc->gadget);
2506 spin_lock(&dwc->lock);
2510 static void dwc3_reset_gadget(struct dwc3 *dwc)
2512 if (!dwc->gadget_driver)
2515 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2516 spin_unlock(&dwc->lock);
2517 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2518 spin_lock(&dwc->lock);
2522 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force)
2524 struct dwc3 *dwc = dep->dwc;
2525 struct dwc3_gadget_ep_cmd_params params;
2529 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2530 !dep->resource_index)
2534 * NOTICE: We are violating what the Databook says about the
2535 * EndTransfer command. Ideally we would _always_ wait for the
2536 * EndTransfer Command Completion IRQ, but that's causing too
2537 * much trouble synchronizing between us and gadget driver.
2539 * We have discussed this with the IP Provider and it was
2540 * suggested to giveback all requests here, but give HW some
2541 * extra time to synchronize with the interconnect. We're using
2542 * an arbitrary 100us delay for that.
2544 * Note also that a similar handling was tested by Synopsys
2545 * (thanks a lot Paul) and nothing bad has come out of it.
2546 * In short, what we're doing is:
2548 * - Issue EndTransfer WITH CMDIOC bit set
2551 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2552 * supports a mode to work around the above limitation. The
2553 * software can poll the CMDACT bit in the DEPCMD register
2554 * after issuing a EndTransfer command. This mode is enabled
2555 * by writing GUCTL2[14]. This polling is already done in the
2556 * dwc3_send_gadget_ep_cmd() function so if the mode is
2557 * enabled, the EndTransfer command will have completed upon
2558 * returning from this function and we don't need to delay for
2561 * This mode is NOT available on the DWC_usb31 IP.
2564 cmd = DWC3_DEPCMD_ENDTRANSFER;
2565 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2566 cmd |= DWC3_DEPCMD_CMDIOC;
2567 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2568 memset(¶ms, 0, sizeof(params));
2569 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2571 dep->resource_index = 0;
2573 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2574 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2579 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2583 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2584 struct dwc3_ep *dep;
2587 dep = dwc->eps[epnum];
2591 if (!(dep->flags & DWC3_EP_STALL))
2594 dep->flags &= ~DWC3_EP_STALL;
2596 ret = dwc3_send_clear_stall_ep_cmd(dep);
2601 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2605 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2606 reg &= ~DWC3_DCTL_INITU1ENA;
2607 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2609 reg &= ~DWC3_DCTL_INITU2ENA;
2610 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2612 dwc3_disconnect_gadget(dwc);
2614 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2615 dwc->setup_packet_pending = false;
2616 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2618 dwc->connected = false;
2621 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2625 dwc->connected = true;
2628 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2629 * would cause a missing Disconnect Event if there's a
2630 * pending Setup Packet in the FIFO.
2632 * There's no suggested workaround on the official Bug
2633 * report, which states that "unless the driver/application
2634 * is doing any special handling of a disconnect event,
2635 * there is no functional issue".
2637 * Unfortunately, it turns out that we _do_ some special
2638 * handling of a disconnect event, namely complete all
2639 * pending transfers, notify gadget driver of the
2640 * disconnection, and so on.
2642 * Our suggested workaround is to follow the Disconnect
2643 * Event steps here, instead, based on a setup_packet_pending
2644 * flag. Such flag gets set whenever we have a SETUP_PENDING
2645 * status for EP0 TRBs and gets cleared on XferComplete for the
2650 * STAR#9000466709: RTL: Device : Disconnect event not
2651 * generated if setup packet pending in FIFO
2653 if (dwc->revision < DWC3_REVISION_188A) {
2654 if (dwc->setup_packet_pending)
2655 dwc3_gadget_disconnect_interrupt(dwc);
2658 dwc3_reset_gadget(dwc);
2660 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2661 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2662 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2663 dwc->test_mode = false;
2664 dwc3_clear_stall_all_ep(dwc);
2666 /* Reset device address to zero */
2667 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2668 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2669 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2672 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2674 struct dwc3_ep *dep;
2679 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2680 speed = reg & DWC3_DSTS_CONNECTSPD;
2684 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2685 * each time on Connect Done.
2687 * Currently we always use the reset value. If any platform
2688 * wants to set this to a different value, we need to add a
2689 * setting and update GCTL.RAMCLKSEL here.
2693 case DWC3_DSTS_SUPERSPEED_PLUS:
2694 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2695 dwc->gadget.ep0->maxpacket = 512;
2696 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2698 case DWC3_DSTS_SUPERSPEED:
2700 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2701 * would cause a missing USB3 Reset event.
2703 * In such situations, we should force a USB3 Reset
2704 * event by calling our dwc3_gadget_reset_interrupt()
2709 * STAR#9000483510: RTL: SS : USB3 reset event may
2710 * not be generated always when the link enters poll
2712 if (dwc->revision < DWC3_REVISION_190A)
2713 dwc3_gadget_reset_interrupt(dwc);
2715 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2716 dwc->gadget.ep0->maxpacket = 512;
2717 dwc->gadget.speed = USB_SPEED_SUPER;
2719 case DWC3_DSTS_HIGHSPEED:
2720 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2721 dwc->gadget.ep0->maxpacket = 64;
2722 dwc->gadget.speed = USB_SPEED_HIGH;
2724 case DWC3_DSTS_FULLSPEED:
2725 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2726 dwc->gadget.ep0->maxpacket = 64;
2727 dwc->gadget.speed = USB_SPEED_FULL;
2729 case DWC3_DSTS_LOWSPEED:
2730 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2731 dwc->gadget.ep0->maxpacket = 8;
2732 dwc->gadget.speed = USB_SPEED_LOW;
2736 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2738 /* Enable USB2 LPM Capability */
2740 if ((dwc->revision > DWC3_REVISION_194A) &&
2741 (speed != DWC3_DSTS_SUPERSPEED) &&
2742 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2743 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2744 reg |= DWC3_DCFG_LPM_CAP;
2745 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2747 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2748 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2750 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2753 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2754 * DCFG.LPMCap is set, core responses with an ACK and the
2755 * BESL value in the LPM token is less than or equal to LPM
2758 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2759 && dwc->has_lpm_erratum,
2760 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2762 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2763 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2765 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2767 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2768 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2769 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2773 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2775 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2780 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2782 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2787 * Configure PHY via GUSB3PIPECTLn if required.
2789 * Update GTXFIFOSIZn
2791 * In both cases reset values should be sufficient.
2795 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2798 * TODO take core out of low power mode when that's
2802 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2803 spin_unlock(&dwc->lock);
2804 dwc->gadget_driver->resume(&dwc->gadget);
2805 spin_lock(&dwc->lock);
2809 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2810 unsigned int evtinfo)
2812 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2813 unsigned int pwropt;
2816 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2817 * Hibernation mode enabled which would show up when device detects
2818 * host-initiated U3 exit.
2820 * In that case, device will generate a Link State Change Interrupt
2821 * from U3 to RESUME which is only necessary if Hibernation is
2824 * There are no functional changes due to such spurious event and we
2825 * just need to ignore it.
2829 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2832 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2833 if ((dwc->revision < DWC3_REVISION_250A) &&
2834 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2835 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2836 (next == DWC3_LINK_STATE_RESUME)) {
2842 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2843 * on the link partner, the USB session might do multiple entry/exit
2844 * of low power states before a transfer takes place.
2846 * Due to this problem, we might experience lower throughput. The
2847 * suggested workaround is to disable DCTL[12:9] bits if we're
2848 * transitioning from U1/U2 to U0 and enable those bits again
2849 * after a transfer completes and there are no pending transfers
2850 * on any of the enabled endpoints.
2852 * This is the first half of that workaround.
2856 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2857 * core send LGO_Ux entering U0
2859 if (dwc->revision < DWC3_REVISION_183A) {
2860 if (next == DWC3_LINK_STATE_U0) {
2864 switch (dwc->link_state) {
2865 case DWC3_LINK_STATE_U1:
2866 case DWC3_LINK_STATE_U2:
2867 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2868 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2869 | DWC3_DCTL_ACCEPTU2ENA
2870 | DWC3_DCTL_INITU1ENA
2871 | DWC3_DCTL_ACCEPTU1ENA);
2874 dwc->u1u2 = reg & u1u2;
2878 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2888 case DWC3_LINK_STATE_U1:
2889 if (dwc->speed == USB_SPEED_SUPER)
2890 dwc3_suspend_gadget(dwc);
2892 case DWC3_LINK_STATE_U2:
2893 case DWC3_LINK_STATE_U3:
2894 dwc3_suspend_gadget(dwc);
2896 case DWC3_LINK_STATE_RESUME:
2897 dwc3_resume_gadget(dwc);
2904 dwc->link_state = next;
2907 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2908 unsigned int evtinfo)
2910 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2912 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2913 dwc3_suspend_gadget(dwc);
2915 dwc->link_state = next;
2918 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2919 unsigned int evtinfo)
2921 unsigned int is_ss = evtinfo & BIT(4);
2924 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2925 * have a known issue which can cause USB CV TD.9.23 to fail
2928 * Because of this issue, core could generate bogus hibernation
2929 * events which SW needs to ignore.
2933 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2934 * Device Fallback from SuperSpeed
2936 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2939 /* enter hibernation here */
2942 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2943 const struct dwc3_event_devt *event)
2945 switch (event->type) {
2946 case DWC3_DEVICE_EVENT_DISCONNECT:
2947 dwc3_gadget_disconnect_interrupt(dwc);
2949 case DWC3_DEVICE_EVENT_RESET:
2950 dwc3_gadget_reset_interrupt(dwc);
2952 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2953 dwc3_gadget_conndone_interrupt(dwc);
2955 case DWC3_DEVICE_EVENT_WAKEUP:
2956 dwc3_gadget_wakeup_interrupt(dwc);
2958 case DWC3_DEVICE_EVENT_HIBER_REQ:
2959 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2960 "unexpected hibernation event\n"))
2963 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2965 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2966 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2968 case DWC3_DEVICE_EVENT_EOPF:
2969 /* It changed to be suspend event for version 2.30a and above */
2970 if (dwc->revision >= DWC3_REVISION_230A) {
2972 * Ignore suspend event until the gadget enters into
2973 * USB_STATE_CONFIGURED state.
2975 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2976 dwc3_gadget_suspend_interrupt(dwc,
2980 case DWC3_DEVICE_EVENT_SOF:
2981 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2982 case DWC3_DEVICE_EVENT_CMD_CMPL:
2983 case DWC3_DEVICE_EVENT_OVERFLOW:
2986 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2990 static void dwc3_process_event_entry(struct dwc3 *dwc,
2991 const union dwc3_event *event)
2993 trace_dwc3_event(event->raw, dwc);
2995 if (!event->type.is_devspec)
2996 dwc3_endpoint_interrupt(dwc, &event->depevt);
2997 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
2998 dwc3_gadget_interrupt(dwc, &event->devt);
3000 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3003 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3005 struct dwc3 *dwc = evt->dwc;
3006 irqreturn_t ret = IRQ_NONE;
3012 if (!(evt->flags & DWC3_EVENT_PENDING))
3016 union dwc3_event event;
3018 event.raw = *(u32 *) (evt->cache + evt->lpos);
3020 dwc3_process_event_entry(dwc, &event);
3023 * FIXME we wrap around correctly to the next entry as
3024 * almost all entries are 4 bytes in size. There is one
3025 * entry which has 12 bytes which is a regular entry
3026 * followed by 8 bytes data. ATM I don't know how
3027 * things are organized if we get next to the a
3028 * boundary so I worry about that once we try to handle
3031 evt->lpos = (evt->lpos + 4) % evt->length;
3036 evt->flags &= ~DWC3_EVENT_PENDING;
3039 /* Unmask interrupt */
3040 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3041 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3042 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3044 if (dwc->imod_interval) {
3045 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3046 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3052 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3054 struct dwc3_event_buffer *evt = _evt;
3055 struct dwc3 *dwc = evt->dwc;
3056 unsigned long flags;
3057 irqreturn_t ret = IRQ_NONE;
3059 spin_lock_irqsave(&dwc->lock, flags);
3060 ret = dwc3_process_event_buf(evt);
3061 spin_unlock_irqrestore(&dwc->lock, flags);
3066 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3068 struct dwc3 *dwc = evt->dwc;
3073 if (pm_runtime_suspended(dwc->dev)) {
3074 pm_runtime_get(dwc->dev);
3075 disable_irq_nosync(dwc->irq_gadget);
3076 dwc->pending_events = true;
3081 * With PCIe legacy interrupt, test shows that top-half irq handler can
3082 * be called again after HW interrupt deassertion. Check if bottom-half
3083 * irq event handler completes before caching new event to prevent
3086 if (evt->flags & DWC3_EVENT_PENDING)
3089 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3090 count &= DWC3_GEVNTCOUNT_MASK;
3095 evt->flags |= DWC3_EVENT_PENDING;
3097 /* Mask interrupt */
3098 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3099 reg |= DWC3_GEVNTSIZ_INTMASK;
3100 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3102 amount = min(count, evt->length - evt->lpos);
3103 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3106 memcpy(evt->cache, evt->buf, count - amount);
3108 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3110 return IRQ_WAKE_THREAD;
3113 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3115 struct dwc3_event_buffer *evt = _evt;
3117 return dwc3_check_event_buf(evt);
3120 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3122 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3125 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3129 if (irq == -EPROBE_DEFER)
3132 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3136 if (irq == -EPROBE_DEFER)
3139 irq = platform_get_irq(dwc3_pdev, 0);
3143 if (irq != -EPROBE_DEFER)
3144 dev_err(dwc->dev, "missing peripheral IRQ\n");
3154 * dwc3_gadget_init - initializes gadget related registers
3155 * @dwc: pointer to our controller context structure
3157 * Returns 0 on success otherwise negative errno.
3159 int dwc3_gadget_init(struct dwc3 *dwc)
3164 irq = dwc3_gadget_get_irq(dwc);
3170 dwc->irq_gadget = irq;
3172 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3173 sizeof(*dwc->ep0_trb) * 2,
3174 &dwc->ep0_trb_addr, GFP_KERNEL);
3175 if (!dwc->ep0_trb) {
3176 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3181 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3182 if (!dwc->setup_buf) {
3187 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3188 &dwc->bounce_addr, GFP_KERNEL);
3194 init_completion(&dwc->ep0_in_setup);
3196 dwc->gadget.ops = &dwc3_gadget_ops;
3197 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3198 dwc->gadget.sg_supported = true;
3199 dwc->gadget.name = "dwc3-gadget";
3200 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3203 * FIXME We might be setting max_speed to <SUPER, however versions
3204 * <2.20a of dwc3 have an issue with metastability (documented
3205 * elsewhere in this driver) which tells us we can't set max speed to
3206 * anything lower than SUPER.
3208 * Because gadget.max_speed is only used by composite.c and function
3209 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3210 * to happen so we avoid sending SuperSpeed Capability descriptor
3211 * together with our BOS descriptor as that could confuse host into
3212 * thinking we can handle super speed.
3214 * Note that, in fact, we won't even support GetBOS requests when speed
3215 * is less than super speed because we don't have means, yet, to tell
3216 * composite.c that we are USB 2.0 + LPM ECN.
3218 if (dwc->revision < DWC3_REVISION_220A &&
3219 !dwc->dis_metastability_quirk)
3220 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3223 dwc->gadget.max_speed = dwc->maximum_speed;
3226 * REVISIT: Here we should clear all pending IRQs to be
3227 * sure we're starting from a well known location.
3230 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3234 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3236 dev_err(dwc->dev, "failed to register udc\n");
3243 dwc3_gadget_free_endpoints(dwc);
3246 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3250 kfree(dwc->setup_buf);
3253 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3254 dwc->ep0_trb, dwc->ep0_trb_addr);
3260 /* -------------------------------------------------------------------------- */
3262 void dwc3_gadget_exit(struct dwc3 *dwc)
3264 usb_del_gadget_udc(&dwc->gadget);
3265 dwc3_gadget_free_endpoints(dwc);
3266 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3268 kfree(dwc->setup_buf);
3269 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3270 dwc->ep0_trb, dwc->ep0_trb_addr);
3273 int dwc3_gadget_suspend(struct dwc3 *dwc)
3275 if (!dwc->gadget_driver)
3278 dwc3_gadget_run_stop(dwc, false, false);
3279 dwc3_disconnect_gadget(dwc);
3280 __dwc3_gadget_stop(dwc);
3285 int dwc3_gadget_resume(struct dwc3 *dwc)
3289 if (!dwc->gadget_driver)
3292 ret = __dwc3_gadget_start(dwc);
3296 ret = dwc3_gadget_run_stop(dwc, true, false);
3303 __dwc3_gadget_stop(dwc);
3309 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3311 if (dwc->pending_events) {
3312 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3313 dwc->pending_events = false;
3314 enable_irq(dwc->irq_gadget);