1 // SPDX-License-Identifier: GPL-2.0
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/interrupt.h>
18 #include <linux/list.h>
19 #include <linux/dma-mapping.h>
21 #include <linux/usb/ch9.h>
22 #include <linux/usb/gadget.h>
23 #include <linux/usb/composite.h>
30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
35 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
41 trb = &dwc->ep0_trb[dep->trb_enqueue];
46 trb->bpl = lower_32_bits(buf_dma);
47 trb->bph = upper_32_bits(buf_dma);
51 trb->ctrl |= (DWC3_TRB_CTRL_HWO
52 | DWC3_TRB_CTRL_ISP_IMI);
55 trb->ctrl |= DWC3_TRB_CTRL_CHN;
57 trb->ctrl |= (DWC3_TRB_CTRL_IOC
60 trace_dwc3_prepare_trb(dep, trb);
63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
65 struct dwc3_gadget_ep_cmd_params params;
69 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
74 memset(¶ms, 0, sizeof(params));
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
82 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
88 struct dwc3_request *req)
90 struct dwc3 *dwc = dep->dwc;
92 req->request.actual = 0;
93 req->request.status = -EINPROGRESS;
94 req->epnum = dep->number;
96 list_add_tail(&req->list, &dep->pending_list);
99 * Gadget driver might not be quick enough to queue a request
100 * before we get a Transfer Not Ready event on this endpoint.
102 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
103 * flag is set, it's telling us that as soon as Gadget queues the
104 * required request, we should kick the transfer here because the
105 * IRQ we were waiting for is long gone.
107 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
108 unsigned int direction;
110 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
112 if (dwc->ep0state != EP0_DATA_PHASE) {
113 dev_WARN(dwc->dev, "Unexpected pending request\n");
117 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
119 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
126 * In case gadget driver asked us to delay the STATUS phase,
129 if (dwc->delayed_status) {
130 unsigned int direction;
132 direction = !dwc->ep0_expect_in;
133 dwc->delayed_status = false;
134 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
136 if (dwc->ep0state == EP0_STATUS_PHASE)
137 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
143 * Unfortunately we have uncovered a limitation wrt the Data Phase.
145 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
146 * come before issueing Start Transfer command, but if we do, we will
147 * miss situations where the host starts another SETUP phase instead of
148 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
149 * Layer Compliance Suite.
151 * The problem surfaces due to the fact that in case of back-to-back
152 * SETUP packets there will be no XferNotReady(DATA) generated and we
153 * will be stuck waiting for XferNotReady(DATA) forever.
155 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
156 * it tells us to start Data Phase right away. It also mentions that if
157 * we receive a SETUP phase instead of the DATA phase, core will issue
158 * XferComplete for the DATA phase, before actually initiating it in
159 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
160 * can only be used to print some debugging logs, as the core expects
161 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
162 * just so it completes right away, without transferring anything and,
163 * only then, we can go back to the SETUP phase.
165 * Because of this scenario, SNPS decided to change the programming
166 * model of control transfers and support on-demand transfers only for
167 * the STATUS phase. To fix the issue we have now, we will always wait
168 * for gadget driver to queue the DATA phase's struct usb_request, then
169 * start it right away.
171 * If we're actually in a 2-stage transfer, we will wait for
172 * XferNotReady(STATUS).
174 if (dwc->three_stage_setup) {
175 unsigned int direction;
177 direction = dwc->ep0_expect_in;
178 dwc->ep0state = EP0_DATA_PHASE;
180 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
182 dep->flags &= ~DWC3_EP0_DIR_IN;
188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
191 struct dwc3_request *req = to_dwc3_request(request);
192 struct dwc3_ep *dep = to_dwc3_ep(ep);
193 struct dwc3 *dwc = dep->dwc;
199 spin_lock_irqsave(&dwc->lock, flags);
200 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
201 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
207 /* we share one TRB for ep0/1 */
208 if (!list_empty(&dep->pending_list)) {
213 ret = __dwc3_gadget_ep0_queue(dep, req);
216 spin_unlock_irqrestore(&dwc->lock, flags);
221 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
225 /* reinitialize physical ep1 */
227 dep->flags = DWC3_EP_ENABLED;
229 /* stall is always issued on EP0 */
231 __dwc3_gadget_ep_set_halt(dep, 1, false);
232 dep->flags = DWC3_EP_ENABLED;
233 dwc->delayed_status = false;
235 if (!list_empty(&dep->pending_list)) {
236 struct dwc3_request *req;
238 req = next_request(&dep->pending_list);
239 dwc3_gadget_giveback(dep, req, -ECONNRESET);
242 dwc->eps[0]->trb_enqueue = 0;
243 dwc->eps[1]->trb_enqueue = 0;
244 dwc->ep0state = EP0_SETUP_PHASE;
245 dwc3_ep0_out_start(dwc);
248 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
250 struct dwc3_ep *dep = to_dwc3_ep(ep);
251 struct dwc3 *dwc = dep->dwc;
253 dwc3_ep0_stall_and_restart(dwc);
258 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
260 struct dwc3_ep *dep = to_dwc3_ep(ep);
261 struct dwc3 *dwc = dep->dwc;
265 spin_lock_irqsave(&dwc->lock, flags);
266 ret = __dwc3_gadget_ep0_set_halt(ep, value);
267 spin_unlock_irqrestore(&dwc->lock, flags);
272 void dwc3_ep0_out_start(struct dwc3 *dwc)
278 complete(&dwc->ep0_in_setup);
281 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
282 DWC3_TRBCTL_CONTROL_SETUP, false);
283 ret = dwc3_ep0_start_trans(dep);
285 for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
286 struct dwc3_ep *dwc3_ep;
288 dwc3_ep = dwc->eps[i];
292 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
295 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
296 dwc3_stop_active_transfer(dwc3_ep, true, true);
300 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
303 u32 windex = le16_to_cpu(wIndex_le);
306 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
307 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
310 dep = dwc->eps[epnum];
314 if (dep->flags & DWC3_EP_ENABLED)
320 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
326 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
327 struct usb_ctrlrequest *ctrl)
334 __le16 *response_pkt;
336 /* We don't support PTM_STATUS */
337 value = le16_to_cpu(ctrl->wValue);
341 recip = ctrl->bRequestType & USB_RECIP_MASK;
343 case USB_RECIP_DEVICE:
345 * LTM will be set once we know how to set this in HW.
347 usb_status |= dwc->gadget->is_selfpowered;
349 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
350 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
351 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
352 if (reg & DWC3_DCTL_INITU1ENA)
353 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
354 if (reg & DWC3_DCTL_INITU2ENA)
355 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
360 case USB_RECIP_INTERFACE:
362 * Function Remote Wake Capable D0
363 * Function Remote Wakeup D1
367 case USB_RECIP_ENDPOINT:
368 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
372 if (dep->flags & DWC3_EP_STALL)
373 usb_status = 1 << USB_ENDPOINT_HALT;
379 response_pkt = (__le16 *) dwc->setup_buf;
380 *response_pkt = cpu_to_le16(usb_status);
383 dwc->ep0_usb_req.dep = dep;
384 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
385 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
386 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
388 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
391 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
396 if (state != USB_STATE_CONFIGURED)
398 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
399 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
401 if (set && dwc->dis_u1_entry_quirk)
404 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
406 reg |= DWC3_DCTL_INITU1ENA;
408 reg &= ~DWC3_DCTL_INITU1ENA;
409 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
414 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
420 if (state != USB_STATE_CONFIGURED)
422 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
423 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
425 if (set && dwc->dis_u2_entry_quirk)
428 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
430 reg |= DWC3_DCTL_INITU2ENA;
432 reg &= ~DWC3_DCTL_INITU2ENA;
433 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
438 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
441 if ((wIndex & 0xff) != 0)
446 switch (wIndex >> 8) {
449 case USB_TEST_SE0_NAK:
450 case USB_TEST_PACKET:
451 case USB_TEST_FORCE_ENABLE:
452 dwc->test_mode_nr = wIndex >> 8;
453 dwc->test_mode = true;
462 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
463 struct usb_ctrlrequest *ctrl, int set)
465 enum usb_device_state state;
470 wValue = le16_to_cpu(ctrl->wValue);
471 wIndex = le16_to_cpu(ctrl->wIndex);
472 state = dwc->gadget->state;
475 case USB_DEVICE_REMOTE_WAKEUP:
478 * 9.4.1 says only for SS, in AddressState only for
479 * default control pipe
481 case USB_DEVICE_U1_ENABLE:
482 ret = dwc3_ep0_handle_u1(dwc, state, set);
484 case USB_DEVICE_U2_ENABLE:
485 ret = dwc3_ep0_handle_u2(dwc, state, set);
487 case USB_DEVICE_LTM_ENABLE:
490 case USB_DEVICE_TEST_MODE:
491 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
500 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
501 struct usb_ctrlrequest *ctrl, int set)
506 wValue = le16_to_cpu(ctrl->wValue);
509 case USB_INTRF_FUNC_SUSPEND:
511 * REVISIT: Ideally we would enable some low power mode here,
512 * however it's unclear what we should be doing here.
514 * For now, we're not doing anything, just making sure we return
515 * 0 so USB Command Verifier tests pass without any errors.
525 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
526 struct usb_ctrlrequest *ctrl, int set)
532 wValue = le16_to_cpu(ctrl->wValue);
535 case USB_ENDPOINT_HALT:
536 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
540 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
543 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
547 /* ClearFeature(Halt) may need delayed status */
548 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
549 return USB_GADGET_DELAYED_STATUS;
559 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
560 struct usb_ctrlrequest *ctrl, int set)
565 recip = ctrl->bRequestType & USB_RECIP_MASK;
568 case USB_RECIP_DEVICE:
569 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
571 case USB_RECIP_INTERFACE:
572 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
574 case USB_RECIP_ENDPOINT:
575 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
584 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
586 enum usb_device_state state = dwc->gadget->state;
590 addr = le16_to_cpu(ctrl->wValue);
592 dev_err(dwc->dev, "invalid device address %d\n", addr);
596 if (state == USB_STATE_CONFIGURED) {
597 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
601 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
602 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
603 reg |= DWC3_DCFG_DEVADDR(addr);
604 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
607 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
609 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
614 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
618 if (dwc->async_callbacks) {
619 spin_unlock(&dwc->lock);
620 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
621 spin_lock(&dwc->lock);
626 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
628 enum usb_device_state state = dwc->gadget->state;
633 cfg = le16_to_cpu(ctrl->wValue);
636 case USB_STATE_DEFAULT:
639 case USB_STATE_ADDRESS:
640 dwc3_gadget_clear_tx_fifos(dwc);
642 ret = dwc3_ep0_delegate_req(dwc, ctrl);
643 /* if the cfg matches and the cfg is non zero */
644 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
647 * only change state if set_config has already
648 * been processed. If gadget driver returns
649 * USB_GADGET_DELAYED_STATUS, we will wait
650 * to change the state on the next usb_ep_queue()
653 usb_gadget_set_state(dwc->gadget,
654 USB_STATE_CONFIGURED);
657 * Enable transition to U1/U2 state when
658 * nothing is pending from application.
660 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
661 if (!dwc->dis_u1_entry_quirk)
662 reg |= DWC3_DCTL_ACCEPTU1ENA;
663 if (!dwc->dis_u2_entry_quirk)
664 reg |= DWC3_DCTL_ACCEPTU2ENA;
665 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
669 case USB_STATE_CONFIGURED:
670 ret = dwc3_ep0_delegate_req(dwc, ctrl);
672 usb_gadget_set_state(dwc->gadget,
681 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
683 struct dwc3_ep *dep = to_dwc3_ep(ep);
684 struct dwc3 *dwc = dep->dwc;
698 memcpy(&timing, req->buf, sizeof(timing));
700 dwc->u1sel = timing.u1sel;
701 dwc->u1pel = timing.u1pel;
702 dwc->u2sel = le16_to_cpu(timing.u2sel);
703 dwc->u2pel = le16_to_cpu(timing.u2pel);
705 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
706 if (reg & DWC3_DCTL_INITU2ENA)
708 if (reg & DWC3_DCTL_INITU1ENA)
712 * According to Synopsys Databook, if parameter is
713 * greater than 125, a value of zero should be
714 * programmed in the register.
719 /* now that we have the time, issue DGCMD Set Sel */
720 ret = dwc3_send_gadget_generic_command(dwc,
721 DWC3_DGCMD_SET_PERIODIC_PAR, param);
725 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
728 enum usb_device_state state = dwc->gadget->state;
731 if (state == USB_STATE_DEFAULT)
734 wLength = le16_to_cpu(ctrl->wLength);
737 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
743 * To handle Set SEL we need to receive 6 bytes from Host. So let's
744 * queue a usb_request for 6 bytes.
746 * Remember, though, this controller can't handle non-wMaxPacketSize
747 * aligned transfers on the OUT direction, so we queue a request for
748 * wMaxPacketSize instead.
751 dwc->ep0_usb_req.dep = dep;
752 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
753 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
754 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
756 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
759 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
765 wValue = le16_to_cpu(ctrl->wValue);
766 wLength = le16_to_cpu(ctrl->wLength);
767 wIndex = le16_to_cpu(ctrl->wIndex);
769 if (wIndex || wLength)
772 dwc->gadget->isoch_delay = wValue;
777 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
781 switch (ctrl->bRequest) {
782 case USB_REQ_GET_STATUS:
783 ret = dwc3_ep0_handle_status(dwc, ctrl);
785 case USB_REQ_CLEAR_FEATURE:
786 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
788 case USB_REQ_SET_FEATURE:
789 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
791 case USB_REQ_SET_ADDRESS:
792 ret = dwc3_ep0_set_address(dwc, ctrl);
794 case USB_REQ_SET_CONFIGURATION:
795 ret = dwc3_ep0_set_config(dwc, ctrl);
797 case USB_REQ_SET_SEL:
798 ret = dwc3_ep0_set_sel(dwc, ctrl);
800 case USB_REQ_SET_ISOCH_DELAY:
801 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
804 ret = dwc3_ep0_delegate_req(dwc, ctrl);
811 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
812 const struct dwc3_event_depevt *event)
814 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
818 if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected)
821 trace_dwc3_ctrl_req(ctrl);
823 len = le16_to_cpu(ctrl->wLength);
825 dwc->three_stage_setup = false;
826 dwc->ep0_expect_in = false;
827 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
829 dwc->three_stage_setup = true;
830 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
831 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
834 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
835 ret = dwc3_ep0_std_request(dwc, ctrl);
837 ret = dwc3_ep0_delegate_req(dwc, ctrl);
839 if (ret == USB_GADGET_DELAYED_STATUS)
840 dwc->delayed_status = true;
844 dwc3_ep0_stall_and_restart(dwc);
847 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
848 const struct dwc3_event_depevt *event)
850 struct dwc3_request *r;
851 struct usb_request *ur;
852 struct dwc3_trb *trb;
859 epnum = event->endpoint_number;
862 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
864 trace_dwc3_complete_trb(ep0, trb);
866 r = next_request(&ep0->pending_list);
870 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
871 if (status == DWC3_TRBSTS_SETUP_PENDING) {
872 dwc->setup_packet_pending = true;
874 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
881 length = trb->size & DWC3_TRB_SIZE_MASK;
882 transferred = ur->length - length;
883 ur->actual += transferred;
885 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
886 ur->length && ur->zero) || dwc->ep0_bounced) {
888 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
889 trace_dwc3_complete_trb(ep0, trb);
892 dwc->eps[1]->trb_enqueue = 0;
894 dwc->eps[0]->trb_enqueue = 0;
896 dwc->ep0_bounced = false;
899 if ((epnum & 1) && ur->actual < ur->length)
900 dwc3_ep0_stall_and_restart(dwc);
902 dwc3_gadget_giveback(ep0, r, 0);
905 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
906 const struct dwc3_event_depevt *event)
908 struct dwc3_request *r;
910 struct dwc3_trb *trb;
916 trace_dwc3_complete_trb(dep, trb);
918 if (!list_empty(&dep->pending_list)) {
919 r = next_request(&dep->pending_list);
921 dwc3_gadget_giveback(dep, r, 0);
924 if (dwc->test_mode) {
927 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
929 dev_err(dwc->dev, "invalid test #%d\n",
931 dwc3_ep0_stall_and_restart(dwc);
936 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
937 if (status == DWC3_TRBSTS_SETUP_PENDING)
938 dwc->setup_packet_pending = true;
940 dwc->ep0state = EP0_SETUP_PHASE;
941 dwc3_ep0_out_start(dwc);
944 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
945 const struct dwc3_event_depevt *event)
947 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
949 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
950 dep->resource_index = 0;
951 dwc->setup_packet_pending = false;
953 switch (dwc->ep0state) {
954 case EP0_SETUP_PHASE:
955 dwc3_ep0_inspect_setup(dwc, event);
959 dwc3_ep0_complete_data(dwc, event);
962 case EP0_STATUS_PHASE:
963 dwc3_ep0_complete_status(dwc, event);
966 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
970 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
971 struct dwc3_ep *dep, struct dwc3_request *req)
973 unsigned int trb_length = 0;
976 req->direction = !!dep->number;
978 if (req->request.length == 0) {
980 trb_length = dep->endpoint.maxpacket;
982 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
983 DWC3_TRBCTL_CONTROL_DATA, false);
984 ret = dwc3_ep0_start_trans(dep);
985 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
986 && (dep->number == 0)) {
990 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
991 &req->request, dep->number);
995 maxpacket = dep->endpoint.maxpacket;
996 rem = req->request.length % maxpacket;
997 dwc->ep0_bounced = true;
999 /* prepare normal TRB */
1000 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1001 req->request.length,
1002 DWC3_TRBCTL_CONTROL_DATA,
1005 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1007 /* Now prepare one extra TRB to align transfer size */
1008 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1010 DWC3_TRBCTL_CONTROL_DATA,
1012 ret = dwc3_ep0_start_trans(dep);
1013 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1014 req->request.length && req->request.zero) {
1016 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1017 &req->request, dep->number);
1021 /* prepare normal TRB */
1022 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1023 req->request.length,
1024 DWC3_TRBCTL_CONTROL_DATA,
1027 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1029 if (!req->direction)
1030 trb_length = dep->endpoint.maxpacket;
1032 /* Now prepare one extra TRB to align transfer size */
1033 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1034 trb_length, DWC3_TRBCTL_CONTROL_DATA,
1036 ret = dwc3_ep0_start_trans(dep);
1038 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1039 &req->request, dep->number);
1043 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1044 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1047 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1049 ret = dwc3_ep0_start_trans(dep);
1055 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1057 struct dwc3 *dwc = dep->dwc;
1060 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1061 : DWC3_TRBCTL_CONTROL_STATUS2;
1063 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1064 return dwc3_ep0_start_trans(dep);
1067 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1069 WARN_ON(dwc3_ep0_start_control_status(dep));
1072 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1073 const struct dwc3_event_depevt *event)
1075 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1077 __dwc3_ep0_do_control_status(dwc, dep);
1080 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1082 unsigned int direction = !dwc->ep0_expect_in;
1084 dwc->delayed_status = false;
1085 dwc->clear_stall_protocol = 0;
1087 if (dwc->ep0state != EP0_STATUS_PHASE)
1090 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1093 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1095 struct dwc3_gadget_ep_cmd_params params;
1100 * For status/DATA OUT stage, TRB will be queued on ep0 out
1101 * endpoint for which resource index is zero. Hence allow
1102 * queuing ENDXFER command for ep0 out endpoint.
1104 if (!dep->resource_index && dep->number)
1107 cmd = DWC3_DEPCMD_ENDTRANSFER;
1108 cmd |= DWC3_DEPCMD_CMDIOC;
1109 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1110 memset(¶ms, 0, sizeof(params));
1111 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1113 dep->resource_index = 0;
1116 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1117 const struct dwc3_event_depevt *event)
1119 switch (event->status) {
1120 case DEPEVT_STATUS_CONTROL_DATA:
1121 if (!dwc->softconnect || !dwc->connected)
1124 * We already have a DATA transfer in the controller's cache,
1125 * if we receive a XferNotReady(DATA) we will ignore it, unless
1126 * it's for the wrong direction.
1128 * In that case, we must issue END_TRANSFER command to the Data
1129 * Phase we already have started and issue SetStall on the
1132 if (dwc->ep0_expect_in != event->endpoint_number) {
1133 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1135 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1136 dwc3_ep0_end_control_data(dwc, dep);
1137 dwc3_ep0_stall_and_restart(dwc);
1143 case DEPEVT_STATUS_CONTROL_STATUS:
1144 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1147 if (dwc->setup_packet_pending) {
1148 dwc3_ep0_stall_and_restart(dwc);
1152 dwc->ep0state = EP0_STATUS_PHASE;
1154 if (dwc->delayed_status) {
1155 struct dwc3_ep *dep = dwc->eps[0];
1157 WARN_ON_ONCE(event->endpoint_number != 1);
1159 * We should handle the delay STATUS phase here if the
1160 * request for handling delay STATUS has been queued
1163 if (!list_empty(&dep->pending_list)) {
1164 dwc->delayed_status = false;
1165 usb_gadget_set_state(dwc->gadget,
1166 USB_STATE_CONFIGURED);
1167 dwc3_ep0_do_control_status(dwc, event);
1173 dwc3_ep0_do_control_status(dwc, event);
1177 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1178 const struct dwc3_event_depevt *event)
1180 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1183 switch (event->endpoint_event) {
1184 case DWC3_DEPEVT_XFERCOMPLETE:
1185 dwc3_ep0_xfer_complete(dwc, event);
1188 case DWC3_DEPEVT_XFERNOTREADY:
1189 dwc3_ep0_xfernotready(dwc, event);
1192 case DWC3_DEPEVT_XFERINPROGRESS:
1193 case DWC3_DEPEVT_RXTXFIFOEVT:
1194 case DWC3_DEPEVT_STREAMEVT:
1196 case DWC3_DEPEVT_EPCMDCMPLT:
1197 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1199 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1200 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1201 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;