drivers/usb/dwc3/dwc3-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dwc3-pci.c - PCI Specific glue layer
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/slab.h>
  14 #include <linux/pci.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/gpio/machine.h>
  20 #include <linux/acpi.h>
  21 #include <linux/delay.h>
  22
  23 #define PCI_DEVICE_ID_INTEL_BYT                 0x0f37
  24 #define PCI_DEVICE_ID_INTEL_MRFLD               0x119e
  25 #define PCI_DEVICE_ID_INTEL_BSW                 0x22b7
  26 #define PCI_DEVICE_ID_INTEL_SPTLP               0x9d30
  27 #define PCI_DEVICE_ID_INTEL_SPTH                0xa130
  28 #define PCI_DEVICE_ID_INTEL_BXT                 0x0aaa
  29 #define PCI_DEVICE_ID_INTEL_BXT_M               0x1aaa
  30 #define PCI_DEVICE_ID_INTEL_APL                 0x5aaa
  31 #define PCI_DEVICE_ID_INTEL_KBP                 0xa2b0
  32 #define PCI_DEVICE_ID_INTEL_CMLLP               0x02ee
  33 #define PCI_DEVICE_ID_INTEL_CMLH                0x06ee
  34 #define PCI_DEVICE_ID_INTEL_GLK                 0x31aa
  35 #define PCI_DEVICE_ID_INTEL_CNPLP               0x9dee
  36 #define PCI_DEVICE_ID_INTEL_CNPH                0xa36e
  37 #define PCI_DEVICE_ID_INTEL_CNPV                0xa3b0
  38 #define PCI_DEVICE_ID_INTEL_ICLLP               0x34ee
  39 #define PCI_DEVICE_ID_INTEL_EHL                 0x4b7e
  40 #define PCI_DEVICE_ID_INTEL_TGPLP               0xa0ee
  41 #define PCI_DEVICE_ID_INTEL_TGPH                0x43ee
  42 #define PCI_DEVICE_ID_INTEL_JSP                 0x4dee
  43 #define PCI_DEVICE_ID_INTEL_ADLP                0x51ee
  44 #define PCI_DEVICE_ID_INTEL_ADLM                0x54ee
  45 #define PCI_DEVICE_ID_INTEL_ADLS                0x7ae1
  46 #define PCI_DEVICE_ID_INTEL_TGL                 0x9a15
  47 #define PCI_DEVICE_ID_AMD_MR                    0x163a
  48
  49 #define PCI_INTEL_BXT_DSM_GUID          "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  50 #define PCI_INTEL_BXT_FUNC_PMU_PWR      4
  51 #define PCI_INTEL_BXT_STATE_D0          0
  52 #define PCI_INTEL_BXT_STATE_D3          3
  53
  54 #define GP_RWBAR                        1
  55 #define GP_RWREG1                       0xa0
  56 #define GP_RWREG1_ULPI_REFCLK_DISABLE   (1 << 17)
  57
  58 /**
  59  * struct dwc3_pci - Driver private structure
  60  * @dwc3: child dwc3 platform_device
  61  * @pci: our link to PCI bus
  62  * @guid: _DSM GUID
  63  * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  64  * @wakeup_work: work for asynchronous resume
  65  */
  66 struct dwc3_pci {
  67         struct platform_device *dwc3;
  68         struct pci_dev *pci;
  69
  70         guid_t guid;
  71
  72         unsigned int has_dsm_for_pm:1;
  73         struct work_struct wakeup_work;
  74 };
  75
  76 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  77 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  78
  79 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  80         { "reset-gpios", &reset_gpios, 1 },
  81         { "cs-gpios", &cs_gpios, 1 },
  82         { },
  83 };
  84
  85 static struct gpiod_lookup_table platform_bytcr_gpios = {
  86         .dev_id         = "0000:00:16.0",
  87         .table          = {
  88                 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
  89                 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
  90                 {}
  91         },
  92 };
  93
  94 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
  95 {
  96         void __iomem    *reg;
  97         u32             value;
  98
  99         reg = pcim_iomap(pci, GP_RWBAR, 0);
 100         if (!reg)
 101                 return -ENOMEM;
 102
 103         value = readl(reg + GP_RWREG1);
 104         if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
 105                 goto unmap; /* ULPI refclk already enabled */
 106
 107         value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
 108         writel(value, reg + GP_RWREG1);
 109         /* This comes from the Intel Android x86 tree w/o any explanation */
 110         msleep(100);
 111 unmap:
 112         pcim_iounmap(pci, reg);
 113         return 0;
 114 }
 115
 116 static const struct property_entry dwc3_pci_intel_properties[] = {
 117         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 118         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 119         {}
 120 };
 121
 122 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = {
 123         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 124         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 125         PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
 126         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 127         {}
 128 };
 129
 130 static const struct property_entry dwc3_pci_mrfld_properties[] = {
 131         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 132         PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
 133         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 134         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 135         PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
 136         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 137         {}
 138 };
 139
 140 static const struct property_entry dwc3_pci_amd_properties[] = {
 141         PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
 142         PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
 143         PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
 144         PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
 145         PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
 146         PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
 147         PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
 148         PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
 149         PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
 150         PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
 151         PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
 152         /* FIXME these quirks should be removed when AMD NL tapes out */
 153         PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
 154         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 155         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 156         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 157         {}
 158 };
 159
 160 static const struct property_entry dwc3_pci_mr_properties[] = {
 161         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 162         PROPERTY_ENTRY_BOOL("usb-role-switch"),
 163         PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
 164         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 165         {}
 166 };
 167
 168 static const struct software_node dwc3_pci_intel_swnode = {
 169         .properties = dwc3_pci_intel_properties,
 170 };
 171
 172 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = {
 173         .properties = dwc3_pci_intel_phy_charger_detect_properties,
 174 };
 175
 176 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
 177         .properties = dwc3_pci_mrfld_properties,
 178 };
 179
 180 static const struct software_node dwc3_pci_amd_swnode = {
 181         .properties = dwc3_pci_amd_properties,
 182 };
 183
 184 static const struct software_node dwc3_pci_amd_mr_swnode = {
 185         .properties = dwc3_pci_mr_properties,
 186 };
 187
 188 static int dwc3_pci_quirks(struct dwc3_pci *dwc,
 189                            const struct software_node *swnode)
 190 {
 191         struct pci_dev                  *pdev = dwc->pci;
 192
 193         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 194                 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
 195                     pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
 196                     pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
 197                         guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
 198                         dwc->has_dsm_for_pm = true;
 199                 }
 200
 201                 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
 202                         struct gpio_desc *gpio;
 203                         int ret;
 204
 205                         /* On BYT the FW does not always enable the refclock */
 206                         ret = dwc3_byt_enable_ulpi_refclock(pdev);
 207                         if (ret)
 208                                 return ret;
 209
 210                         ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
 211                                         acpi_dwc3_byt_gpios);
 212                         if (ret)
 213                                 dev_dbg(&pdev->dev, "failed to add mapping table\n");
 214
 215                         /*
 216                          * A lot of BYT devices lack ACPI resource entries for
 217                          * the GPIOs, add a fallback mapping to the reference
 218                          * design GPIOs which all boards seem to use.
 219                          */
 220                         gpiod_add_lookup_table(&platform_bytcr_gpios);
 221
 222                         /*
 223                          * These GPIOs will turn on the USB2 PHY. Note that we have to
 224                          * put the gpio descriptors again here because the phy driver
 225                          * might want to grab them, too.
 226                          */
 227                         gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
 228                         if (IS_ERR(gpio))
 229                                 return PTR_ERR(gpio);
 230
 231                         gpiod_set_value_cansleep(gpio, 1);
 232                         gpiod_put(gpio);
 233
 234                         gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
 235                         if (IS_ERR(gpio))
 236                                 return PTR_ERR(gpio);
 237
 238                         if (gpio) {
 239                                 gpiod_set_value_cansleep(gpio, 1);
 240                                 gpiod_put(gpio);
 241                                 usleep_range(10000, 11000);
 242                         }
 243
 244                         /*
 245                          * Make the pdev name predictable (only 1 DWC3 on BYT)
 246                          * and patch the phy dev-name into the lookup table so
 247                          * that the phy-driver can get the GPIOs.
 248                          */
 249                         dwc->dwc3->id = PLATFORM_DEVID_NONE;
 250                         platform_bytcr_gpios.dev_id = "dwc3.ulpi";
 251
 252                         /*
 253                          * Some Android tablets with a Crystal Cove PMIC
 254                          * (INT33FD), rely on the TUSB1211 phy for charger
 255                          * detection. These can be identified by them _not_
 256                          * using the standard ACPI battery and ac drivers.
 257                          */
 258                         if (acpi_dev_present("INT33FD", "1", 2) &&
 259                             acpi_quirk_skip_acpi_ac_and_battery()) {
 260                                 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n");
 261                                 swnode = &dwc3_pci_intel_phy_charger_detect_swnode;
 262                         }
 263                 }
 264         }
 265
 266         return device_add_software_node(&dwc->dwc3->dev, swnode);
 267 }
 268
 269 #ifdef CONFIG_PM
 270 static void dwc3_pci_resume_work(struct work_struct *work)
 271 {
 272         struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
 273         struct platform_device *dwc3 = dwc->dwc3;
 274         int ret;
 275
 276         ret = pm_runtime_get_sync(&dwc3->dev);
 277         if (ret) {
 278                 pm_runtime_put_sync_autosuspend(&dwc3->dev);
 279                 return;
 280         }
 281
 282         pm_runtime_mark_last_busy(&dwc3->dev);
 283         pm_runtime_put_sync_autosuspend(&dwc3->dev);
 284 }
 285 #endif
 286
 287 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
 288 {
 289         struct dwc3_pci         *dwc;
 290         struct resource         res[2];
 291         int                     ret;
 292         struct device           *dev = &pci->dev;
 293
 294         ret = pcim_enable_device(pci);
 295         if (ret) {
 296                 dev_err(dev, "failed to enable pci device\n");
 297                 return -ENODEV;
 298         }
 299
 300         pci_set_master(pci);
 301
 302         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
 303         if (!dwc)
 304                 return -ENOMEM;
 305
 306         dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
 307         if (!dwc->dwc3)
 308                 return -ENOMEM;
 309
 310         memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
 311
 312         res[0].start    = pci_resource_start(pci, 0);
 313         res[0].end      = pci_resource_end(pci, 0);
 314         res[0].name     = "dwc_usb3";
 315         res[0].flags    = IORESOURCE_MEM;
 316
 317         res[1].start    = pci->irq;
 318         res[1].name     = "dwc_usb3";
 319         res[1].flags    = IORESOURCE_IRQ;
 320
 321         ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
 322         if (ret) {
 323                 dev_err(dev, "couldn't add resources to dwc3 device\n");
 324                 goto err;
 325         }
 326
 327         dwc->pci = pci;
 328         dwc->dwc3->dev.parent = dev;
 329         ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
 330
 331         ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
 332         if (ret)
 333                 goto err;
 334
 335         ret = platform_device_add(dwc->dwc3);
 336         if (ret) {
 337                 dev_err(dev, "failed to register dwc3 device\n");
 338                 goto err;
 339         }
 340
 341         device_init_wakeup(dev, true);
 342         pci_set_drvdata(pci, dwc);
 343         pm_runtime_put(dev);
 344 #ifdef CONFIG_PM
 345         INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
 346 #endif
 347
 348         return 0;
 349 err:
 350         device_remove_software_node(&dwc->dwc3->dev);
 351         platform_device_put(dwc->dwc3);
 352         return ret;
 353 }
 354
 355 static void dwc3_pci_remove(struct pci_dev *pci)
 356 {
 357         struct dwc3_pci         *dwc = pci_get_drvdata(pci);
 358         struct pci_dev          *pdev = dwc->pci;
 359
 360         if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
 361                 gpiod_remove_lookup_table(&platform_bytcr_gpios);
 362 #ifdef CONFIG_PM
 363         cancel_work_sync(&dwc->wakeup_work);
 364 #endif
 365         device_init_wakeup(&pci->dev, false);
 366         pm_runtime_get(&pci->dev);
 367         device_remove_software_node(&dwc->dwc3->dev);
 368         platform_device_unregister(dwc->dwc3);
 369 }
 370
 371 static const struct pci_device_id dwc3_pci_id_table[] = {
 372         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
 373           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 374
 375         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
 376           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 377
 378         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
 379           (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
 380
 381         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
 382           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 383
 384         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
 385           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 386
 387         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
 388           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 389
 390         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
 391           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 392
 393         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
 394           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 395
 396         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
 397           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 398
 399         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
 400           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 401
 402         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
 403           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 404
 405         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
 406           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 407
 408         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
 409           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 410
 411         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
 412           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 413
 414         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
 415           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 416
 417         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
 418           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 419
 420         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL),
 421           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 422
 423         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
 424           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 425
 426         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
 427           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 428
 429         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
 430           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 431
 432         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP),
 433           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 434
 435         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM),
 436           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 437
 438         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
 439           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 440
 441         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
 442           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 443
 444         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
 445           (kernel_ulong_t) &dwc3_pci_amd_swnode, },
 446
 447         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR),
 448           (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, },
 449
 450         {  }    /* Terminating Entry */
 451 };
 452 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
 453
 454 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
 455 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
 456 {
 457         union acpi_object *obj;
 458         union acpi_object tmp;
 459         union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
 460
 461         if (!dwc->has_dsm_for_pm)
 462                 return 0;
 463
 464         tmp.type = ACPI_TYPE_INTEGER;
 465         tmp.integer.value = param;
 466
 467         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
 468                         1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
 469         if (!obj) {
 470                 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
 471                 return -EIO;
 472         }
 473
 474         ACPI_FREE(obj);
 475
 476         return 0;
 477 }
 478 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
 479
 480 #ifdef CONFIG_PM
 481 static int dwc3_pci_runtime_suspend(struct device *dev)
 482 {
 483         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 484
 485         if (device_can_wakeup(dev))
 486                 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 487
 488         return -EBUSY;
 489 }
 490
 491 static int dwc3_pci_runtime_resume(struct device *dev)
 492 {
 493         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 494         int                     ret;
 495
 496         ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 497         if (ret)
 498                 return ret;
 499
 500         queue_work(pm_wq, &dwc->wakeup_work);
 501
 502         return 0;
 503 }
 504 #endif /* CONFIG_PM */
 505
 506 #ifdef CONFIG_PM_SLEEP
 507 static int dwc3_pci_suspend(struct device *dev)
 508 {
 509         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 510
 511         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 512 }
 513
 514 static int dwc3_pci_resume(struct device *dev)
 515 {
 516         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 517
 518         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 519 }
 520 #endif /* CONFIG_PM_SLEEP */
 521
 522 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
 523         SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
 524         SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
 525                 NULL)
 526 };
 527
 528 static struct pci_driver dwc3_pci_driver = {
 529         .name           = "dwc3-pci",
 530         .id_table       = dwc3_pci_id_table,
 531         .probe          = dwc3_pci_probe,
 532         .remove         = dwc3_pci_remove,
 533         .driver         = {
 534                 .pm     = &dwc3_pci_dev_pm_ops,
 535         }
 536 };
 537
 538 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 539 MODULE_LICENSE("GPL v2");
 540 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
 541
 542 module_pci_driver(dwc3_pci_driver);