drivers/usb/dwc3/dwc3-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dwc3-pci.c - PCI Specific glue layer
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/slab.h>
  14 #include <linux/pci.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/gpio/machine.h>
  20 #include <linux/acpi.h>
  21 #include <linux/delay.h>
  22
  23 #define PCI_DEVICE_ID_INTEL_BYT                 0x0f37
  24 #define PCI_DEVICE_ID_INTEL_MRFLD               0x119e
  25 #define PCI_DEVICE_ID_INTEL_BSW                 0x22b7
  26 #define PCI_DEVICE_ID_INTEL_SPTLP               0x9d30
  27 #define PCI_DEVICE_ID_INTEL_SPTH                0xa130
  28 #define PCI_DEVICE_ID_INTEL_BXT                 0x0aaa
  29 #define PCI_DEVICE_ID_INTEL_BXT_M               0x1aaa
  30 #define PCI_DEVICE_ID_INTEL_APL                 0x5aaa
  31 #define PCI_DEVICE_ID_INTEL_KBP                 0xa2b0
  32 #define PCI_DEVICE_ID_INTEL_CMLLP               0x02ee
  33 #define PCI_DEVICE_ID_INTEL_CMLH                0x06ee
  34 #define PCI_DEVICE_ID_INTEL_GLK                 0x31aa
  35 #define PCI_DEVICE_ID_INTEL_CNPLP               0x9dee
  36 #define PCI_DEVICE_ID_INTEL_CNPH                0xa36e
  37 #define PCI_DEVICE_ID_INTEL_CNPV                0xa3b0
  38 #define PCI_DEVICE_ID_INTEL_ICLLP               0x34ee
  39 #define PCI_DEVICE_ID_INTEL_EHL                 0x4b7e
  40 #define PCI_DEVICE_ID_INTEL_TGPLP               0xa0ee
  41 #define PCI_DEVICE_ID_INTEL_TGPH                0x43ee
  42 #define PCI_DEVICE_ID_INTEL_JSP                 0x4dee
  43 #define PCI_DEVICE_ID_INTEL_ADLP                0x51ee
  44 #define PCI_DEVICE_ID_INTEL_ADLM                0x54ee
  45 #define PCI_DEVICE_ID_INTEL_ADLS                0x7ae1
  46 #define PCI_DEVICE_ID_INTEL_RPLS                0x7a61
  47 #define PCI_DEVICE_ID_INTEL_TGL                 0x9a15
  48 #define PCI_DEVICE_ID_AMD_MR                    0x163a
  49
  50 #define PCI_INTEL_BXT_DSM_GUID          "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  51 #define PCI_INTEL_BXT_FUNC_PMU_PWR      4
  52 #define PCI_INTEL_BXT_STATE_D0          0
  53 #define PCI_INTEL_BXT_STATE_D3          3
  54
  55 #define GP_RWBAR                        1
  56 #define GP_RWREG1                       0xa0
  57 #define GP_RWREG1_ULPI_REFCLK_DISABLE   (1 << 17)
  58
  59 /**
  60  * struct dwc3_pci - Driver private structure
  61  * @dwc3: child dwc3 platform_device
  62  * @pci: our link to PCI bus
  63  * @guid: _DSM GUID
  64  * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  65  * @wakeup_work: work for asynchronous resume
  66  */
  67 struct dwc3_pci {
  68         struct platform_device *dwc3;
  69         struct pci_dev *pci;
  70
  71         guid_t guid;
  72
  73         unsigned int has_dsm_for_pm:1;
  74         struct work_struct wakeup_work;
  75 };
  76
  77 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  78 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  79
  80 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  81         { "reset-gpios", &reset_gpios, 1 },
  82         { "cs-gpios", &cs_gpios, 1 },
  83         { },
  84 };
  85
  86 static struct gpiod_lookup_table platform_bytcr_gpios = {
  87         .dev_id         = "0000:00:16.0",
  88         .table          = {
  89                 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
  90                 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
  91                 {}
  92         },
  93 };
  94
  95 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
  96 {
  97         void __iomem    *reg;
  98         u32             value;
  99
 100         reg = pcim_iomap(pci, GP_RWBAR, 0);
 101         if (!reg)
 102                 return -ENOMEM;
 103
 104         value = readl(reg + GP_RWREG1);
 105         if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
 106                 goto unmap; /* ULPI refclk already enabled */
 107
 108         value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
 109         writel(value, reg + GP_RWREG1);
 110         /* This comes from the Intel Android x86 tree w/o any explanation */
 111         msleep(100);
 112 unmap:
 113         pcim_iounmap(pci, reg);
 114         return 0;
 115 }
 116
 117 static const struct property_entry dwc3_pci_intel_properties[] = {
 118         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 119         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 120         {}
 121 };
 122
 123 static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = {
 124         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 125         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 126         PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"),
 127         {}
 128 };
 129
 130 static const struct property_entry dwc3_pci_intel_byt_properties[] = {
 131         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 132         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 133         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 134         {}
 135 };
 136
 137 static const struct property_entry dwc3_pci_mrfld_properties[] = {
 138         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 139         PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
 140         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 141         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 142         PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
 143         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 144         {}
 145 };
 146
 147 static const struct property_entry dwc3_pci_amd_properties[] = {
 148         PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
 149         PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
 150         PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
 151         PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
 152         PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
 153         PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
 154         PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
 155         PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
 156         PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
 157         PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
 158         PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
 159         /* FIXME these quirks should be removed when AMD NL tapes out */
 160         PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
 161         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 162         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 163         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 164         {}
 165 };
 166
 167 static const struct property_entry dwc3_pci_mr_properties[] = {
 168         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 169         PROPERTY_ENTRY_BOOL("usb-role-switch"),
 170         PROPERTY_ENTRY_STRING("role-switch-default-mode", "host"),
 171         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 172         {}
 173 };
 174
 175 static const struct software_node dwc3_pci_intel_swnode = {
 176         .properties = dwc3_pci_intel_properties,
 177 };
 178
 179 static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = {
 180         .properties = dwc3_pci_intel_phy_charger_detect_properties,
 181 };
 182
 183 static const struct software_node dwc3_pci_intel_byt_swnode = {
 184         .properties = dwc3_pci_intel_byt_properties,
 185 };
 186
 187 static const struct software_node dwc3_pci_intel_mrfld_swnode = {
 188         .properties = dwc3_pci_mrfld_properties,
 189 };
 190
 191 static const struct software_node dwc3_pci_amd_swnode = {
 192         .properties = dwc3_pci_amd_properties,
 193 };
 194
 195 static const struct software_node dwc3_pci_amd_mr_swnode = {
 196         .properties = dwc3_pci_mr_properties,
 197 };
 198
 199 static int dwc3_pci_quirks(struct dwc3_pci *dwc,
 200                            const struct software_node *swnode)
 201 {
 202         struct pci_dev                  *pdev = dwc->pci;
 203
 204         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 205                 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
 206                     pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
 207                     pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
 208                         guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
 209                         dwc->has_dsm_for_pm = true;
 210                 }
 211
 212                 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
 213                         struct gpio_desc *gpio;
 214                         int ret;
 215
 216                         /* On BYT the FW does not always enable the refclock */
 217                         ret = dwc3_byt_enable_ulpi_refclock(pdev);
 218                         if (ret)
 219                                 return ret;
 220
 221                         ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
 222                                         acpi_dwc3_byt_gpios);
 223                         if (ret)
 224                                 dev_dbg(&pdev->dev, "failed to add mapping table\n");
 225
 226                         /*
 227                          * A lot of BYT devices lack ACPI resource entries for
 228                          * the GPIOs, add a fallback mapping to the reference
 229                          * design GPIOs which all boards seem to use.
 230                          */
 231                         gpiod_add_lookup_table(&platform_bytcr_gpios);
 232
 233                         /*
 234                          * These GPIOs will turn on the USB2 PHY. Note that we have to
 235                          * put the gpio descriptors again here because the phy driver
 236                          * might want to grab them, too.
 237                          */
 238                         gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
 239                         if (IS_ERR(gpio))
 240                                 return PTR_ERR(gpio);
 241
 242                         gpiod_set_value_cansleep(gpio, 1);
 243                         gpiod_put(gpio);
 244
 245                         gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
 246                         if (IS_ERR(gpio))
 247                                 return PTR_ERR(gpio);
 248
 249                         if (gpio) {
 250                                 gpiod_set_value_cansleep(gpio, 1);
 251                                 gpiod_put(gpio);
 252                                 usleep_range(10000, 11000);
 253                         }
 254
 255                         /*
 256                          * Make the pdev name predictable (only 1 DWC3 on BYT)
 257                          * and patch the phy dev-name into the lookup table so
 258                          * that the phy-driver can get the GPIOs.
 259                          */
 260                         dwc->dwc3->id = PLATFORM_DEVID_NONE;
 261                         platform_bytcr_gpios.dev_id = "dwc3.ulpi";
 262
 263                         /*
 264                          * Some Android tablets with a Crystal Cove PMIC
 265                          * (INT33FD), rely on the TUSB1211 phy for charger
 266                          * detection. These can be identified by them _not_
 267                          * using the standard ACPI battery and ac drivers.
 268                          */
 269                         if (acpi_dev_present("INT33FD", "1", 2) &&
 270                             acpi_quirk_skip_acpi_ac_and_battery()) {
 271                                 dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n");
 272                                 swnode = &dwc3_pci_intel_phy_charger_detect_swnode;
 273                         }
 274                 }
 275         }
 276
 277         return device_add_software_node(&dwc->dwc3->dev, swnode);
 278 }
 279
 280 #ifdef CONFIG_PM
 281 static void dwc3_pci_resume_work(struct work_struct *work)
 282 {
 283         struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
 284         struct platform_device *dwc3 = dwc->dwc3;
 285         int ret;
 286
 287         ret = pm_runtime_get_sync(&dwc3->dev);
 288         if (ret) {
 289                 pm_runtime_put_sync_autosuspend(&dwc3->dev);
 290                 return;
 291         }
 292
 293         pm_runtime_mark_last_busy(&dwc3->dev);
 294         pm_runtime_put_sync_autosuspend(&dwc3->dev);
 295 }
 296 #endif
 297
 298 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
 299 {
 300         struct dwc3_pci         *dwc;
 301         struct resource         res[2];
 302         int                     ret;
 303         struct device           *dev = &pci->dev;
 304
 305         ret = pcim_enable_device(pci);
 306         if (ret) {
 307                 dev_err(dev, "failed to enable pci device\n");
 308                 return -ENODEV;
 309         }
 310
 311         pci_set_master(pci);
 312
 313         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
 314         if (!dwc)
 315                 return -ENOMEM;
 316
 317         dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
 318         if (!dwc->dwc3)
 319                 return -ENOMEM;
 320
 321         memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
 322
 323         res[0].start    = pci_resource_start(pci, 0);
 324         res[0].end      = pci_resource_end(pci, 0);
 325         res[0].name     = "dwc_usb3";
 326         res[0].flags    = IORESOURCE_MEM;
 327
 328         res[1].start    = pci->irq;
 329         res[1].name     = "dwc_usb3";
 330         res[1].flags    = IORESOURCE_IRQ;
 331
 332         ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
 333         if (ret) {
 334                 dev_err(dev, "couldn't add resources to dwc3 device\n");
 335                 goto err;
 336         }
 337
 338         dwc->pci = pci;
 339         dwc->dwc3->dev.parent = dev;
 340         ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
 341
 342         ret = dwc3_pci_quirks(dwc, (void *)id->driver_data);
 343         if (ret)
 344                 goto err;
 345
 346         ret = platform_device_add(dwc->dwc3);
 347         if (ret) {
 348                 dev_err(dev, "failed to register dwc3 device\n");
 349                 goto err;
 350         }
 351
 352         device_init_wakeup(dev, true);
 353         pci_set_drvdata(pci, dwc);
 354         pm_runtime_put(dev);
 355 #ifdef CONFIG_PM
 356         INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
 357 #endif
 358
 359         return 0;
 360 err:
 361         device_remove_software_node(&dwc->dwc3->dev);
 362         platform_device_put(dwc->dwc3);
 363         return ret;
 364 }
 365
 366 static void dwc3_pci_remove(struct pci_dev *pci)
 367 {
 368         struct dwc3_pci         *dwc = pci_get_drvdata(pci);
 369         struct pci_dev          *pdev = dwc->pci;
 370
 371         if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
 372                 gpiod_remove_lookup_table(&platform_bytcr_gpios);
 373 #ifdef CONFIG_PM
 374         cancel_work_sync(&dwc->wakeup_work);
 375 #endif
 376         device_init_wakeup(&pci->dev, false);
 377         pm_runtime_get(&pci->dev);
 378         device_remove_software_node(&dwc->dwc3->dev);
 379         platform_device_unregister(dwc->dwc3);
 380 }
 381
 382 static const struct pci_device_id dwc3_pci_id_table[] = {
 383         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
 384           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 385
 386         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
 387           (kernel_ulong_t) &dwc3_pci_intel_byt_swnode, },
 388
 389         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
 390           (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
 391
 392         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
 393           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 394
 395         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
 396           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 397
 398         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
 399           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 400
 401         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
 402           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 403
 404         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
 405           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 406
 407         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
 408           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 409
 410         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
 411           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 412
 413         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
 414           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 415
 416         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
 417           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 418
 419         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
 420           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 421
 422         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
 423           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 424
 425         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
 426           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 427
 428         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
 429           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 430
 431         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL),
 432           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 433
 434         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
 435           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 436
 437         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
 438           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 439
 440         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
 441           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 442
 443         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP),
 444           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 445
 446         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM),
 447           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 448
 449         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
 450           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 451
 452         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPLS),
 453           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 454
 455         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
 456           (kernel_ulong_t) &dwc3_pci_intel_swnode, },
 457
 458         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
 459           (kernel_ulong_t) &dwc3_pci_amd_swnode, },
 460
 461         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MR),
 462           (kernel_ulong_t)&dwc3_pci_amd_mr_swnode, },
 463
 464         {  }    /* Terminating Entry */
 465 };
 466 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
 467
 468 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
 469 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
 470 {
 471         union acpi_object *obj;
 472         union acpi_object tmp;
 473         union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
 474
 475         if (!dwc->has_dsm_for_pm)
 476                 return 0;
 477
 478         tmp.type = ACPI_TYPE_INTEGER;
 479         tmp.integer.value = param;
 480
 481         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
 482                         1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
 483         if (!obj) {
 484                 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
 485                 return -EIO;
 486         }
 487
 488         ACPI_FREE(obj);
 489
 490         return 0;
 491 }
 492 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
 493
 494 #ifdef CONFIG_PM
 495 static int dwc3_pci_runtime_suspend(struct device *dev)
 496 {
 497         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 498
 499         if (device_can_wakeup(dev))
 500                 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 501
 502         return -EBUSY;
 503 }
 504
 505 static int dwc3_pci_runtime_resume(struct device *dev)
 506 {
 507         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 508         int                     ret;
 509
 510         ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 511         if (ret)
 512                 return ret;
 513
 514         queue_work(pm_wq, &dwc->wakeup_work);
 515
 516         return 0;
 517 }
 518 #endif /* CONFIG_PM */
 519
 520 #ifdef CONFIG_PM_SLEEP
 521 static int dwc3_pci_suspend(struct device *dev)
 522 {
 523         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 524
 525         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 526 }
 527
 528 static int dwc3_pci_resume(struct device *dev)
 529 {
 530         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 531
 532         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 533 }
 534 #endif /* CONFIG_PM_SLEEP */
 535
 536 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
 537         SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
 538         SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
 539                 NULL)
 540 };
 541
 542 static struct pci_driver dwc3_pci_driver = {
 543         .name           = "dwc3-pci",
 544         .id_table       = dwc3_pci_id_table,
 545         .probe          = dwc3_pci_probe,
 546         .remove         = dwc3_pci_remove,
 547         .driver         = {
 548                 .pm     = &dwc3_pci_dev_pm_ops,
 549         }
 550 };
 551
 552 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 553 MODULE_LICENSE("GPL v2");
 554 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
 555
 556 module_pci_driver(dwc3_pci_driver);