drivers/usb/dwc3/dwc3-meson-gxl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Amlogic GXL DWC3 Glue layer
   4  *
   5  * Copyright (C) 2019 BayLibre, SAS
   6  * Author: Neil Armstrong <narmstrong@baylibre.com>
   7  */
   8
   9 #define DEBUG
  10 #include <common.h>
  11 #include <asm-generic/io.h>
  12 #include <dm.h>
  13 #include <dm/device-internal.h>
  14 #include <dm/lists.h>
  15 #include <dwc3-uboot.h>
  16 #include <generic-phy.h>
  17 #include <linux/usb/ch9.h>
  18 #include <linux/usb/gadget.h>
  19 #include <malloc.h>
  20 #include <regmap.h>
  21 #include <usb.h>
  22 #include "core.h"
  23 #include "gadget.h"
  24 #include <reset.h>
  25 #include <clk.h>
  26 #include <power/regulator.h>
  27 #include <linux/bitfield.h>
  28 #include <linux/bitops.h>
  29 #include <linux/compat.h>
  30 #include <asm/arch/usb-gx.h>
  31
  32 /* USB Glue Control Registers */
  33
  34 #define USB_R0                                                  0x00
  35         #define USB_R0_P30_FSEL_MASK                            GENMASK(5, 0)
  36         #define USB_R0_P30_PHY_RESET                            BIT(6)
  37         #define USB_R0_P30_TEST_POWERDOWN_HSP                   BIT(7)
  38         #define USB_R0_P30_TEST_POWERDOWN_SSP                   BIT(8)
  39         #define USB_R0_P30_ACJT_LEVEL_MASK                      GENMASK(13, 9)
  40         #define USB_R0_P30_TX_BOOST_LEVEL_MASK                  GENMASK(16, 14)
  41         #define USB_R0_P30_LANE0_TX2RX_LOOPBACK                 BIT(17)
  42         #define USB_R0_P30_LANE0_EXT_PCLK_REQ                   BIT(18)
  43         #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK             GENMASK(28, 19)
  44         #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK               GENMASK(30, 29)
  45         #define USB_R0_U2D_ACT                                  BIT(31)
  46
  47 #define USB_R1                                                  0x04
  48         #define USB_R1_U3H_BIGENDIAN_GS                         BIT(0)
  49         #define USB_R1_U3H_PME_ENABLE                           BIT(1)
  50         #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK            GENMASK(6, 2)
  51         #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK            GENMASK(11, 7)
  52         #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK            GENMASK(15, 12)
  53         #define USB_R1_U3H_HOST_U3_PORT_DISABLE                 BIT(16)
  54         #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT      BIT(17)
  55         #define USB_R1_U3H_HOST_MSI_ENABLE                      BIT(18)
  56         #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK                 GENMASK(24, 19)
  57         #define USB_R1_P30_PCS_TX_SWING_FULL_MASK               GENMASK(31, 25)
  58
  59 #define USB_R2                                                  0x08
  60         #define USB_R2_P30_CR_DATA_IN_MASK                      GENMASK(15, 0)
  61         #define USB_R2_P30_CR_READ                              BIT(16)
  62         #define USB_R2_P30_CR_WRITE                             BIT(17)
  63         #define USB_R2_P30_CR_CAP_ADDR                          BIT(18)
  64         #define USB_R2_P30_CR_CAP_DATA                          BIT(19)
  65         #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK             GENMASK(25, 20)
  66         #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK               GENMASK(31, 26)
  67
  68 #define USB_R3                                                  0x0c
  69         #define USB_R3_P30_SSC_ENABLE                           BIT(0)
  70         #define USB_R3_P30_SSC_RANGE_MASK                       GENMASK(3, 1)
  71         #define USB_R3_P30_SSC_REF_CLK_SEL_MASK                 GENMASK(12, 4)
  72         #define USB_R3_P30_REF_SSP_EN                           BIT(13)
  73         #define USB_R3_P30_LOS_BIAS_MASK                        GENMASK(18, 16)
  74         #define USB_R3_P30_LOS_LEVEL_MASK                       GENMASK(23, 19)
  75         #define USB_R3_P30_MPLL_MULTIPLIER_MASK                 GENMASK(30, 24)
  76
  77 #define USB_R4                                                  0x10
  78         #define USB_R4_P21_PORT_RESET_0                         BIT(0)
  79         #define USB_R4_P21_SLEEP_M0                             BIT(1)
  80         #define USB_R4_MEM_PD_MASK                              GENMASK(3, 2)
  81         #define USB_R4_P21_ONLY                                 BIT(4)
  82
  83 #define USB_R5                                                  0x14
  84         #define USB_R5_ID_DIG_SYNC                              BIT(0)
  85         #define USB_R5_ID_DIG_REG                               BIT(1)
  86         #define USB_R5_ID_DIG_CFG_MASK                          GENMASK(3, 2)
  87         #define USB_R5_ID_DIG_EN_0                              BIT(4)
  88         #define USB_R5_ID_DIG_EN_1                              BIT(5)
  89         #define USB_R5_ID_DIG_CURR                              BIT(6)
  90         #define USB_R5_ID_DIG_IRQ                               BIT(7)
  91         #define USB_R5_ID_DIG_TH_MASK                           GENMASK(15, 8)
  92         #define USB_R5_ID_DIG_CNT_MASK                          GENMASK(23, 16)
  93
  94 /* read-only register */
  95 #define USB_R6                                                  0x18
  96         #define USB_R6_P30_CR_DATA_OUT_MASK                     GENMASK(15, 0)
  97         #define USB_R6_P30_CR_ACK                               BIT(16)
  98
  99 enum {
 100         USB2_HOST_PHY0 = 0,
 101         USB2_OTG_PHY1,
 102         USB2_HOST_PHY2,
 103         PHY_COUNT,
 104 };
 105
 106 static const char *phy_names[PHY_COUNT] = {
 107         "usb2-phy0", "usb2-phy1", "usb2-phy2",
 108 };
 109
 110 struct dwc3_meson_gxl {
 111         struct udevice          *dev;
 112         struct regmap           *regmap;
 113         struct clk              clk;
 114         struct reset_ctl        reset;
 115         struct phy              phys[PHY_COUNT];
 116         enum usb_dr_mode        otg_mode;
 117         enum usb_dr_mode        otg_phy_mode;
 118         unsigned int            usb2_ports;
 119 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 120         struct udevice          *vbus_supply;
 121 #endif
 122 };
 123
 124 #define U2P_REG_SIZE                                            0x20
 125 #define USB_REG_OFFSET                                          0x80
 126
 127 #define USB2_OTG_PHY                                            USB2_OTG_PHY1
 128
 129 static void dwc3_meson_gxl_usb2_set_mode(struct dwc3_meson_gxl *priv, enum usb_dr_mode mode)
 130 {
 131         switch (mode) {
 132         case USB_DR_MODE_HOST:
 133         case USB_DR_MODE_OTG:
 134         case USB_DR_MODE_UNKNOWN:
 135                 regmap_update_bits(priv->regmap, USB_R1,
 136                                    USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK, 0);
 137                 regmap_update_bits(priv->regmap, USB_R0,
 138                                    USB_R0_U2D_ACT, 0);
 139                 regmap_update_bits(priv->regmap, USB_R4,
 140                                    USB_R4_P21_SLEEP_M0, 0);
 141                 break;
 142
 143         case USB_DR_MODE_PERIPHERAL:
 144                 regmap_update_bits(priv->regmap, USB_R0,
 145                                    USB_R0_U2D_ACT, USB_R0_U2D_ACT);
 146                 regmap_update_bits(priv->regmap, USB_R0,
 147                                    USB_R0_U2D_SS_SCALEDOWN_MODE_MASK, 0);
 148                 regmap_update_bits(priv->regmap, USB_R4,
 149                                    USB_R4_P21_SLEEP_M0, USB_R4_P21_SLEEP_M0);
 150                 break;
 151         }
 152 }
 153
 154 static int dwc3_meson_gxl_usb2_init(struct dwc3_meson_gxl *priv)
 155 {
 156         int i;
 157
 158         for (i = 0; i < PHY_COUNT; ++i) {
 159                 if (!priv->phys[i].dev)
 160                         continue;
 161
 162                 phy_meson_gxl_usb2_set_mode(&priv->phys[i],
 163                                 (i == USB2_OTG_PHY) ? USB_DR_MODE_PERIPHERAL
 164                                                     : USB_DR_MODE_HOST);
 165         }
 166
 167         return 0;
 168 }
 169
 170 static int dwc3_meson_gxl_usb_init(struct dwc3_meson_gxl *priv)
 171 {
 172         int ret;
 173
 174         ret = dwc3_meson_gxl_usb2_init(priv);
 175         if (ret)
 176                 return ret;
 177
 178         regmap_update_bits(priv->regmap, USB_R1,
 179                            USB_R1_U3H_FLADJ_30MHZ_REG_MASK,
 180                            FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20));
 181
 182         regmap_update_bits(priv->regmap, USB_R5,
 183                            USB_R5_ID_DIG_EN_0,
 184                            USB_R5_ID_DIG_EN_0);
 185         regmap_update_bits(priv->regmap, USB_R5,
 186                            USB_R5_ID_DIG_EN_1,
 187                            USB_R5_ID_DIG_EN_1);
 188         regmap_update_bits(priv->regmap, USB_R5,
 189                            USB_R5_ID_DIG_TH_MASK,
 190                            FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff));
 191
 192         dwc3_meson_gxl_usb2_set_mode(priv, priv->otg_phy_mode);
 193
 194         return 0;
 195 }
 196
 197 int dwc3_meson_gxl_force_mode(struct udevice *dev, enum usb_dr_mode mode)
 198 {
 199         struct dwc3_meson_gxl *priv = dev_get_plat(dev);
 200
 201         if (!priv)
 202                 return -EINVAL;
 203
 204         if (mode != USB_DR_MODE_HOST && mode != USB_DR_MODE_PERIPHERAL)
 205                 return -EINVAL;
 206
 207         if (!priv->phys[USB2_OTG_PHY].dev)
 208                 return -EINVAL;
 209
 210         if (mode == priv->otg_phy_mode)
 211                 return 0;
 212
 213         if (mode == USB_DR_MODE_HOST)
 214                 debug("%s: switching to Host Mode\n", __func__);
 215         else
 216                 debug("%s: switching to Device Mode\n", __func__);
 217
 218 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 219         if (priv->vbus_supply) {
 220                 int ret = regulator_set_enable(priv->vbus_supply,
 221                                         (mode == USB_DR_MODE_PERIPHERAL));
 222                 if (ret)
 223                         return ret;
 224         }
 225 #endif
 226         priv->otg_phy_mode = mode;
 227
 228         phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY], mode);
 229
 230         dwc3_meson_gxl_usb2_set_mode(priv, mode);
 231
 232         return 0;
 233 }
 234
 235 static int dwc3_meson_gxl_get_phys(struct dwc3_meson_gxl *priv)
 236 {
 237         int i, ret;
 238
 239         for (i = 0 ; i < PHY_COUNT ; ++i) {
 240                 ret = generic_phy_get_by_name(priv->dev, phy_names[i],
 241                                               &priv->phys[i]);
 242                 if (ret == -ENOENT || ret == -ENODATA) {
 243                         priv->phys[i].dev = NULL;
 244                         continue;
 245                 }
 246
 247                 if (ret)
 248                         return ret;
 249
 250                 priv->usb2_ports++;
 251         }
 252
 253         debug("%s: usb2 ports: %d\n", __func__, priv->usb2_ports);
 254
 255         return 0;
 256 }
 257
 258 static int dwc3_meson_gxl_reset_init(struct dwc3_meson_gxl *priv)
 259 {
 260         int ret;
 261
 262         ret = reset_get_by_index(priv->dev, 0, &priv->reset);
 263         if (ret)
 264                 return ret;
 265
 266         ret = reset_assert(&priv->reset);
 267         udelay(1);
 268         ret |= reset_deassert(&priv->reset);
 269         if (ret) {
 270                 reset_free(&priv->reset);
 271                 return ret;
 272         }
 273
 274         return 0;
 275 }
 276
 277 static int dwc3_meson_gxl_clk_init(struct dwc3_meson_gxl *priv)
 278 {
 279         int ret;
 280
 281         ret = clk_get_by_index(priv->dev, 0, &priv->clk);
 282         if (ret)
 283                 return ret;
 284
 285 #if CONFIG_IS_ENABLED(CLK)
 286         ret = clk_enable(&priv->clk);
 287         if (ret) {
 288                 clk_free(&priv->clk);
 289                 return ret;
 290         }
 291 #endif
 292
 293         return 0;
 294 }
 295
 296 static int dwc3_meson_gxl_probe(struct udevice *dev)
 297 {
 298         struct dwc3_meson_gxl *priv = dev_get_plat(dev);
 299         int ret, i;
 300
 301         priv->dev = dev;
 302
 303         ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
 304         if (ret)
 305                 return ret;
 306
 307         ret = dwc3_meson_gxl_clk_init(priv);
 308         if (ret)
 309                 return ret;
 310
 311         ret = dwc3_meson_gxl_reset_init(priv);
 312         if (ret)
 313                 return ret;
 314
 315         ret = dwc3_meson_gxl_get_phys(priv);
 316         if (ret)
 317                 return ret;
 318
 319 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 320         ret = device_get_supply_regulator(dev, "vbus-supply",
 321                                           &priv->vbus_supply);
 322         if (ret && ret != -ENOENT) {
 323                 pr_err("Failed to get PHY regulator\n");
 324                 return ret;
 325         }
 326
 327         if (priv->vbus_supply) {
 328                 ret = regulator_set_enable(priv->vbus_supply, true);
 329                 if (ret)
 330                         return ret;
 331         }
 332 #endif
 333
 334         /* On GXL PHY must be started in device mode for DWC2 init */
 335         priv->otg_mode = USB_DR_MODE_PERIPHERAL;
 336
 337         ret = dwc3_meson_gxl_usb_init(priv);
 338         if (ret)
 339                 return ret;
 340
 341         priv->otg_mode = usb_get_dr_mode(dev->node);
 342
 343         if (priv->otg_mode == USB_DR_MODE_PERIPHERAL)
 344                 priv->otg_phy_mode = USB_DR_MODE_PERIPHERAL;
 345         else
 346                 priv->otg_phy_mode = USB_DR_MODE_HOST;
 347
 348         for (i = 0 ; i < PHY_COUNT ; ++i) {
 349                 if (!priv->phys[i].dev)
 350                         continue;
 351
 352                 ret = generic_phy_init(&priv->phys[i]);
 353                 if (ret)
 354                         goto err_phy_init;
 355         }
 356
 357         for (i = 0; i < PHY_COUNT; ++i) {
 358                 if (!priv->phys[i].dev)
 359                         continue;
 360
 361                 ret = generic_phy_power_on(&priv->phys[i]);
 362                 if (ret)
 363                         goto err_phy_init;
 364         }
 365
 366         if (priv->phys[USB2_OTG_PHY].dev)
 367                 phy_meson_gxl_usb2_set_mode(&priv->phys[USB2_OTG_PHY],
 368                                             priv->otg_phy_mode);
 369
 370         dwc3_meson_gxl_usb2_set_mode(priv, priv->otg_phy_mode);
 371
 372         return 0;
 373
 374 err_phy_init:
 375         for (i = 0 ; i < PHY_COUNT ; ++i) {
 376                 if (!priv->phys[i].dev)
 377                         continue;
 378
 379                  generic_phy_exit(&priv->phys[i]);
 380         }
 381
 382         return ret;
 383 }
 384
 385 static int dwc3_meson_gxl_remove(struct udevice *dev)
 386 {
 387         struct dwc3_meson_gxl *priv = dev_get_plat(dev);
 388         int i;
 389
 390         reset_release_all(&priv->reset, 1);
 391
 392         clk_release_all(&priv->clk, 1);
 393
 394         for (i = 0; i < PHY_COUNT; ++i) {
 395                 if (!priv->phys[i].dev)
 396                         continue;
 397
 398                  generic_phy_power_off(&priv->phys[i]);
 399         }
 400
 401         for (i = 0 ; i < PHY_COUNT ; ++i) {
 402                 if (!priv->phys[i].dev)
 403                         continue;
 404
 405                  generic_phy_exit(&priv->phys[i]);
 406         }
 407
 408         return dm_scan_fdt_dev(dev);
 409 }
 410
 411 static const struct udevice_id dwc3_meson_gxl_ids[] = {
 412         { .compatible = "amlogic,meson-gxl-usb-ctrl" },
 413         { .compatible = "amlogic,meson-gxm-usb-ctrl" },
 414         { }
 415 };
 416
 417 U_BOOT_DRIVER(dwc3_generic_wrapper) = {
 418         .name   = "dwc3-meson-gxl",
 419         .id     = UCLASS_SIMPLE_BUS,
 420         .of_match = dwc3_meson_gxl_ids,
 421         .probe = dwc3_meson_gxl_probe,
 422         .remove = dwc3_meson_gxl_remove,
 423         .plat_auto      = sizeof(struct dwc3_meson_gxl),
 424
 425 };