1 // SPDX-License-Identifier: GPL-2.0
3 * Generic DWC3 Glue layer
5 * Copyright (C) 2016 - 2018 Xilinx, Inc.
7 * Based on dwc3-omap.c.
14 #include <dm/device-internal.h>
16 #include <dwc3-uboot.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19 #include <linux/usb/ch9.h>
20 #include <linux/usb/gadget.h>
29 struct dwc3_glue_data {
31 struct reset_ctl_bulk resets;
35 struct dwc3_generic_plat {
38 enum usb_dr_mode dr_mode;
41 struct dwc3_generic_priv {
47 struct dwc3_generic_host_priv {
48 struct xhci_ctrl xhci_ctrl;
49 struct dwc3_generic_priv gen_priv;
52 static int dwc3_generic_probe(struct udevice *dev,
53 struct dwc3_generic_priv *priv)
56 struct dwc3_generic_plat *plat = dev_get_platdata(dev);
57 struct dwc3 *dwc3 = &priv->dwc3;
58 struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
61 dwc3->maximum_speed = plat->maximum_speed;
62 dwc3->dr_mode = plat->dr_mode;
63 #if CONFIG_IS_ENABLED(OF_CONTROL)
68 * It must hold whole USB3.0 OTG controller in resetting to hold pipe
69 * power state in P2 before initializing TypeC PHY on RK3399 platform.
71 if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
72 reset_assert_bulk(&glue->resets);
76 rc = dwc3_setup_phy(dev, &priv->phys);
80 if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
81 reset_deassert_bulk(&glue->resets);
83 priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
84 dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
89 unmap_physmem(priv->base, MAP_NOCACHE);
96 static int dwc3_generic_remove(struct udevice *dev,
97 struct dwc3_generic_priv *priv)
99 struct dwc3 *dwc3 = &priv->dwc3;
102 dwc3_shutdown_phy(dev, &priv->phys);
103 unmap_physmem(dwc3->regs, MAP_NOCACHE);
108 static int dwc3_generic_ofdata_to_platdata(struct udevice *dev)
110 struct dwc3_generic_plat *plat = dev_get_platdata(dev);
111 ofnode node = dev->node;
113 plat->base = dev_read_addr(dev);
115 plat->maximum_speed = usb_get_maximum_speed(node);
116 if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
117 pr_info("No USB maximum speed specified. Using super speed\n");
118 plat->maximum_speed = USB_SPEED_SUPER;
121 plat->dr_mode = usb_get_dr_mode(node);
122 if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
123 pr_err("Invalid usb mode setup\n");
130 #if CONFIG_IS_ENABLED(DM_USB_GADGET)
131 int dm_usb_gadget_handle_interrupts(struct udevice *dev)
133 struct dwc3_generic_priv *priv = dev_get_priv(dev);
134 struct dwc3 *dwc3 = &priv->dwc3;
136 dwc3_gadget_uboot_handle_interrupt(dwc3);
141 static int dwc3_generic_peripheral_probe(struct udevice *dev)
143 struct dwc3_generic_priv *priv = dev_get_priv(dev);
145 return dwc3_generic_probe(dev, priv);
148 static int dwc3_generic_peripheral_remove(struct udevice *dev)
150 struct dwc3_generic_priv *priv = dev_get_priv(dev);
152 return dwc3_generic_remove(dev, priv);
155 U_BOOT_DRIVER(dwc3_generic_peripheral) = {
156 .name = "dwc3-generic-peripheral",
157 .id = UCLASS_USB_GADGET_GENERIC,
158 .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
159 .probe = dwc3_generic_peripheral_probe,
160 .remove = dwc3_generic_peripheral_remove,
161 .priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
162 .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
166 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
167 static int dwc3_generic_host_probe(struct udevice *dev)
169 struct xhci_hcor *hcor;
170 struct xhci_hccr *hccr;
171 struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
174 rc = dwc3_generic_probe(dev, &priv->gen_priv);
178 hccr = (struct xhci_hccr *)priv->gen_priv.base;
179 hcor = (struct xhci_hcor *)(priv->gen_priv.base +
180 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
182 return xhci_register(dev, hccr, hcor);
185 static int dwc3_generic_host_remove(struct udevice *dev)
187 struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
190 rc = xhci_deregister(dev);
194 return dwc3_generic_remove(dev, &priv->gen_priv);
197 U_BOOT_DRIVER(dwc3_generic_host) = {
198 .name = "dwc3-generic-host",
200 .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
201 .probe = dwc3_generic_host_probe,
202 .remove = dwc3_generic_host_remove,
203 .priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv),
204 .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
205 .ops = &xhci_usb_ops,
206 .flags = DM_FLAG_ALLOC_PRIV_DMA,
210 struct dwc3_glue_ops {
211 void (*select_dr_mode)(struct udevice *dev, int index,
212 enum usb_dr_mode mode);
215 void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
216 enum usb_dr_mode mode)
218 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
219 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
221 /* UTMI_OTG_STATUS REGISTER */
222 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
223 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
224 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
225 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
226 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
227 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
228 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
229 enum dwc3_omap_utmi_mode {
230 DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
231 DWC3_OMAP_UTMI_MODE_HW,
232 DWC3_OMAP_UTMI_MODE_SW,
239 u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
241 struct dwc3_glue_data *glue = dev_get_platdata(dev);
242 void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
244 if (device_is_compatible(dev, "ti,am437x-dwc3"))
245 utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
247 utmi_mode = dev_read_u32_default(dev, "utmi-mode",
248 DWC3_OMAP_UTMI_MODE_UNKNOWN);
249 if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
250 debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
252 mode = USB_DR_MODE_PERIPHERAL;
256 case USB_DR_MODE_PERIPHERAL:
260 case USB_DR_MODE_HOST:
264 case USB_DR_MODE_OTG:
271 reg = readl(base + utmi_status_offset);
273 reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
275 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
277 writel(reg, base + utmi_status_offset);
279 reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
280 USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
281 USBOTGSS_UTMI_OTG_STATUS_IDDIG);
283 reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
284 USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
287 reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
288 USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
290 writel(reg, base + utmi_status_offset);
292 unmap_physmem(base, MAP_NOCACHE);
295 struct dwc3_glue_ops ti_ops = {
296 .select_dr_mode = dwc3_ti_select_dr_mode,
299 static int dwc3_glue_bind(struct udevice *parent)
304 ofnode_for_each_subnode(node, parent->node) {
305 const char *name = ofnode_get_name(node);
306 enum usb_dr_mode dr_mode;
308 const char *driver = NULL;
310 debug("%s: subnode name: %s\n", __func__, name);
312 dr_mode = usb_get_dr_mode(node);
315 case USB_DR_MODE_PERIPHERAL:
316 case USB_DR_MODE_OTG:
317 #if CONFIG_IS_ENABLED(DM_USB_GADGET)
318 debug("%s: dr_mode: OTG or Peripheral\n", __func__);
319 driver = "dwc3-generic-peripheral";
322 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
323 case USB_DR_MODE_HOST:
324 debug("%s: dr_mode: HOST\n", __func__);
325 driver = "dwc3-generic-host";
329 debug("%s: unsupported dr_mode\n", __func__);
336 ret = device_bind_driver_to_node(parent, driver, name,
339 debug("%s: not able to bind usb device mode\n",
348 static int dwc3_glue_reset_init(struct udevice *dev,
349 struct dwc3_glue_data *glue)
353 ret = reset_get_bulk(dev, &glue->resets);
354 if (ret == -ENOTSUPP || ret == -ENOENT)
359 ret = reset_deassert_bulk(&glue->resets);
361 reset_release_bulk(&glue->resets);
368 static int dwc3_glue_clk_init(struct udevice *dev,
369 struct dwc3_glue_data *glue)
373 ret = clk_get_bulk(dev, &glue->clks);
374 if (ret == -ENOSYS || ret == -ENOENT)
379 #if CONFIG_IS_ENABLED(CLK)
380 ret = clk_enable_bulk(&glue->clks);
382 clk_release_bulk(&glue->clks);
390 static int dwc3_glue_probe(struct udevice *dev)
392 struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
393 struct dwc3_glue_data *glue = dev_get_platdata(dev);
394 struct udevice *child = NULL;
398 glue->regs = dev_read_addr(dev);
400 ret = dwc3_glue_clk_init(dev, glue);
404 ret = dwc3_glue_reset_init(dev, glue);
408 ret = device_find_first_child(dev, &child);
412 if (glue->resets.count == 0) {
413 ret = dwc3_glue_reset_init(child, glue);
419 enum usb_dr_mode dr_mode;
421 dr_mode = usb_get_dr_mode(child->node);
422 device_find_next_child(&child);
423 if (ops && ops->select_dr_mode)
424 ops->select_dr_mode(dev, index, dr_mode);
431 static int dwc3_glue_remove(struct udevice *dev)
433 struct dwc3_glue_data *glue = dev_get_platdata(dev);
435 reset_release_bulk(&glue->resets);
437 clk_release_bulk(&glue->clks);
442 static const struct udevice_id dwc3_glue_ids[] = {
443 { .compatible = "xlnx,zynqmp-dwc3" },
444 { .compatible = "xlnx,versal-dwc3" },
445 { .compatible = "ti,keystone-dwc3"},
446 { .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
447 { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
448 { .compatible = "ti,am654-dwc3" },
449 { .compatible = "rockchip,rk3328-dwc3" },
450 { .compatible = "rockchip,rk3399-dwc3" },
451 { .compatible = "qcom,dwc3" },
455 U_BOOT_DRIVER(dwc3_generic_wrapper) = {
456 .name = "dwc3-generic-wrapper",
458 .of_match = dwc3_glue_ids,
459 .bind = dwc3_glue_bind,
460 .probe = dwc3_glue_probe,
461 .remove = dwc3_glue_remove,
462 .platdata_auto_alloc_size = sizeof(struct dwc3_glue_data),