drivers/usb/dwc3/dwc3-generic.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Generic DWC3 Glue layer
   4  *
   5  * Copyright (C) 2016 - 2018 Xilinx, Inc.
   6  *
   7  * Based on dwc3-omap.c.
   8  */
   9
  10 #include <cpu_func.h>
  11 #include <log.h>
  12 #include <dm.h>
  13 #include <dm/device-internal.h>
  14 #include <dm/lists.h>
  15 #include <dwc3-uboot.h>
  16 #include <generic-phy.h>
  17 #include <linux/bitops.h>
  18 #include <linux/delay.h>
  19 #include <linux/printk.h>
  20 #include <linux/usb/ch9.h>
  21 #include <linux/usb/gadget.h>
  22 #include <malloc.h>
  23 #include <power/regulator.h>
  24 #include <usb.h>
  25 #include "core.h"
  26 #include "gadget.h"
  27 #include <reset.h>
  28 #include <clk.h>
  29 #include <usb/xhci.h>
  30 #include <asm/gpio.h>
  31
  32 #include "dwc3-generic.h"
  33
  34 struct dwc3_generic_plat {
  35         fdt_addr_t base;
  36         u32 maximum_speed;
  37         enum usb_dr_mode dr_mode;
  38 };
  39
  40 struct dwc3_generic_priv {
  41         void *base;
  42         struct dwc3 dwc3;
  43         struct phy_bulk phys;
  44         struct gpio_desc *ulpi_reset;
  45 };
  46
  47 struct dwc3_generic_host_priv {
  48         struct xhci_ctrl xhci_ctrl;
  49         struct dwc3_generic_priv gen_priv;
  50         struct udevice *vbus_supply;
  51 };
  52
  53 static int dwc3_generic_probe(struct udevice *dev,
  54                               struct dwc3_generic_priv *priv)
  55 {
  56         int rc;
  57         struct dwc3_generic_plat *plat = dev_get_plat(dev);
  58         struct dwc3 *dwc3 = &priv->dwc3;
  59         struct dwc3_glue_data *glue = dev_get_plat(dev->parent);
  60         int __maybe_unused index;
  61         ofnode __maybe_unused node;
  62
  63         dwc3->dev = dev;
  64         dwc3->maximum_speed = plat->maximum_speed;
  65         dwc3->dr_mode = plat->dr_mode;
  66 #if CONFIG_IS_ENABLED(OF_CONTROL)
  67         dwc3_of_parse(dwc3);
  68
  69         /*
  70          * There are currently four disparate placement possibilities of DWC3
  71          * reference clock phandle in SoC DTs:
  72          * - in top level glue node, with generic subnode without clock (ZynqMP)
  73          * - in top level generic node, with no subnode (i.MX8MQ)
  74          * - in generic subnode, with other clock in top level node (i.MX8MP)
  75          * - in both top level node and generic subnode (Rockchip)
  76          * Cover all the possibilities here by looking into both nodes, start
  77          * with the top level node as that seems to be used in majority of DTs
  78          * to reference the clock.
  79          */
  80         node = dev_ofnode(dev->parent);
  81         index = ofnode_stringlist_search(node, "clock-names", "ref");
  82         if (index < 0)
  83                 index = ofnode_stringlist_search(node, "clock-names", "ref_clk");
  84         if (index < 0) {
  85                 node = dev_ofnode(dev);
  86                 index = ofnode_stringlist_search(node, "clock-names", "ref");
  87                 if (index < 0)
  88                         index = ofnode_stringlist_search(node, "clock-names", "ref_clk");
  89         }
  90         if (index >= 0)
  91                 dwc3->ref_clk = &glue->clks.clks[index];
  92 #endif
  93
  94         /*
  95          * It must hold whole USB3.0 OTG controller in resetting to hold pipe
  96          * power state in P2 before initializing TypeC PHY on RK3399 platform.
  97          */
  98         if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
  99                 reset_assert_bulk(&glue->resets);
 100                 udelay(1);
 101         }
 102
 103         rc = dwc3_setup_phy(dev, &priv->phys);
 104         if (rc && rc != -ENOTSUPP)
 105                 return rc;
 106
 107         if (CONFIG_IS_ENABLED(DM_GPIO) &&
 108             device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) {
 109                 priv->ulpi_reset = devm_gpiod_get_optional(dev->parent, "reset",
 110                                                            GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
 111                 /* property is optional, don't return error! */
 112                 if (priv->ulpi_reset) {
 113                         /* Toggle ulpi to reset the phy. */
 114                         rc = dm_gpio_set_value(priv->ulpi_reset, 1);
 115                         if (rc)
 116                                 return rc;
 117
 118                         mdelay(5);
 119
 120                         rc = dm_gpio_set_value(priv->ulpi_reset, 0);
 121                         if (rc)
 122                                 return rc;
 123
 124                         mdelay(5);
 125                 }
 126         }
 127
 128         if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
 129                 reset_deassert_bulk(&glue->resets);
 130
 131         priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
 132         dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
 133
 134         rc =  dwc3_init(dwc3);
 135         if (rc) {
 136                 unmap_physmem(priv->base, MAP_NOCACHE);
 137                 return rc;
 138         }
 139
 140         return 0;
 141 }
 142
 143 static int dwc3_generic_remove(struct udevice *dev,
 144                                struct dwc3_generic_priv *priv)
 145 {
 146         struct dwc3 *dwc3 = &priv->dwc3;
 147
 148         if (CONFIG_IS_ENABLED(DM_GPIO) &&
 149             device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3") &&
 150             priv->ulpi_reset) {
 151                 struct gpio_desc *ulpi_reset = priv->ulpi_reset;
 152
 153                 dm_gpio_free(ulpi_reset->dev, ulpi_reset);
 154         }
 155
 156         dwc3_remove(dwc3);
 157         dwc3_shutdown_phy(dev, &priv->phys);
 158         unmap_physmem(dwc3->regs, MAP_NOCACHE);
 159
 160         return 0;
 161 }
 162
 163 static int dwc3_generic_of_to_plat(struct udevice *dev)
 164 {
 165         struct dwc3_generic_plat *plat = dev_get_plat(dev);
 166         ofnode node = dev_ofnode(dev);
 167
 168         if (!strncmp(dev->name, "port", 4) || !strncmp(dev->name, "hub", 3)) {
 169                 /* This is a leaf so check the parent */
 170                 plat->base = dev_read_addr(dev->parent);
 171         } else {
 172                 plat->base = dev_read_addr(dev);
 173         }
 174
 175         plat->maximum_speed = usb_get_maximum_speed(node);
 176         if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
 177                 pr_info("No USB maximum speed specified. Using super speed\n");
 178                 plat->maximum_speed = USB_SPEED_SUPER;
 179         }
 180
 181         plat->dr_mode = usb_get_dr_mode(node);
 182         if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
 183                 /* might be a leaf so check the parent for mode */
 184                 node = dev_ofnode(dev->parent);
 185                 plat->dr_mode = usb_get_dr_mode(node);
 186                 if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
 187                         pr_err("Invalid usb mode setup\n");
 188                         return -ENODEV;
 189                 }
 190         }
 191
 192         return 0;
 193 }
 194
 195 #if CONFIG_IS_ENABLED(DM_USB_GADGET)
 196 static int dwc3_generic_peripheral_probe(struct udevice *dev)
 197 {
 198         struct dwc3_generic_priv *priv = dev_get_priv(dev);
 199
 200         return dwc3_generic_probe(dev, priv);
 201 }
 202
 203 static int dwc3_generic_peripheral_remove(struct udevice *dev)
 204 {
 205         struct dwc3_generic_priv *priv = dev_get_priv(dev);
 206
 207         return dwc3_generic_remove(dev, priv);
 208 }
 209
 210 static int dwc3_gadget_handle_interrupts(struct udevice *dev)
 211 {
 212         struct dwc3_generic_priv *priv = dev_get_priv(dev);
 213         struct dwc3 *dwc3 = &priv->dwc3;
 214
 215         dwc3_gadget_uboot_handle_interrupt(dwc3);
 216
 217         return 0;
 218 }
 219
 220 static const struct usb_gadget_generic_ops dwc3_gadget_ops = {
 221         .handle_interrupts      = dwc3_gadget_handle_interrupts,
 222 };
 223
 224 U_BOOT_DRIVER(dwc3_generic_peripheral) = {
 225         .name   = "dwc3-generic-peripheral",
 226         .id     = UCLASS_USB_GADGET_GENERIC,
 227         .of_to_plat = dwc3_generic_of_to_plat,
 228         .ops    = &dwc3_gadget_ops,
 229         .probe = dwc3_generic_peripheral_probe,
 230         .remove = dwc3_generic_peripheral_remove,
 231         .priv_auto      = sizeof(struct dwc3_generic_priv),
 232         .plat_auto      = sizeof(struct dwc3_generic_plat),
 233 };
 234 #endif
 235
 236 #if CONFIG_IS_ENABLED(USB_HOST)
 237 static int dwc3_generic_host_probe(struct udevice *dev)
 238 {
 239         struct xhci_hcor *hcor;
 240         struct xhci_hccr *hccr;
 241         struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
 242         int rc;
 243
 244         rc = dwc3_generic_probe(dev, &priv->gen_priv);
 245         if (rc)
 246                 return rc;
 247
 248         rc = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_supply);
 249         if (rc)
 250                 debug("%s: No vbus regulator found: %d\n", dev->name, rc);
 251
 252         /* Only returns an error if regulator is valid and failed to enable due to a driver issue */
 253         rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
 254         if (rc)
 255                 return rc;
 256
 257         hccr = (struct xhci_hccr *)priv->gen_priv.base;
 258         hcor = (struct xhci_hcor *)(priv->gen_priv.base +
 259                         HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
 260
 261         rc = xhci_register(dev, hccr, hcor);
 262         if (rc)
 263                 regulator_set_enable_if_allowed(priv->vbus_supply, false);
 264
 265         return rc;
 266 }
 267
 268 static int dwc3_generic_host_remove(struct udevice *dev)
 269 {
 270         struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
 271         int rc;
 272
 273         /* This function always returns 0 */
 274         xhci_deregister(dev);
 275
 276         rc = regulator_set_enable_if_allowed(priv->vbus_supply, false);
 277         if (rc)
 278                 debug("%s: Failed to disable vbus regulator: %d\n", dev->name, rc);
 279
 280         return dwc3_generic_remove(dev, &priv->gen_priv);
 281 }
 282
 283 U_BOOT_DRIVER(dwc3_generic_host) = {
 284         .name   = "dwc3-generic-host",
 285         .id     = UCLASS_USB,
 286         .of_to_plat = dwc3_generic_of_to_plat,
 287         .probe = dwc3_generic_host_probe,
 288         .remove = dwc3_generic_host_remove,
 289         .priv_auto      = sizeof(struct dwc3_generic_host_priv),
 290         .plat_auto      = sizeof(struct dwc3_generic_plat),
 291         .ops = &xhci_usb_ops,
 292         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 293 };
 294 #endif
 295
 296 void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
 297                                 enum usb_dr_mode mode)
 298 {
 299 /* USB glue registers */
 300 #define USB_CTRL0               0x00
 301 #define USB_CTRL1               0x04
 302
 303 #define USB_CTRL0_PORTPWR_EN    BIT(12) /* 1 - PPC enabled (default) */
 304 #define USB_CTRL0_USB3_FIXED    BIT(22) /* 1 - USB3 permanent attached */
 305 #define USB_CTRL0_USB2_FIXED    BIT(23) /* 1 - USB2 permanent attached */
 306
 307 #define USB_CTRL1_OC_POLARITY   BIT(16) /* 0 - HIGH / 1 - LOW */
 308 #define USB_CTRL1_PWR_POLARITY  BIT(17) /* 0 - HIGH / 1 - LOW */
 309         fdt_addr_t regs = dev_read_addr_index(dev, 1);
 310         void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
 311         u32 value;
 312
 313         value = readl(base + USB_CTRL0);
 314
 315         if (dev_read_bool(dev, "fsl,permanently-attached"))
 316                 value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
 317         else
 318                 value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
 319
 320         if (dev_read_bool(dev, "fsl,disable-port-power-control"))
 321                 value &= ~(USB_CTRL0_PORTPWR_EN);
 322         else
 323                 value |= USB_CTRL0_PORTPWR_EN;
 324
 325         writel(value, base + USB_CTRL0);
 326
 327         value = readl(base + USB_CTRL1);
 328         if (dev_read_bool(dev, "fsl,over-current-active-low"))
 329                 value |= USB_CTRL1_OC_POLARITY;
 330         else
 331                 value &= ~USB_CTRL1_OC_POLARITY;
 332
 333         if (dev_read_bool(dev, "fsl,power-active-low"))
 334                 value |= USB_CTRL1_PWR_POLARITY;
 335         else
 336                 value &= ~USB_CTRL1_PWR_POLARITY;
 337
 338         writel(value, base + USB_CTRL1);
 339
 340         unmap_physmem(base, MAP_NOCACHE);
 341 }
 342
 343 struct dwc3_glue_ops imx8mp_ops = {
 344         .glue_configure = dwc3_imx8mp_glue_configure,
 345 };
 346
 347 void dwc3_ti_glue_configure(struct udevice *dev, int index,
 348                             enum usb_dr_mode mode)
 349 {
 350 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
 351 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
 352
 353 /* UTMI_OTG_STATUS REGISTER */
 354 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        BIT(31)
 355 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   BIT(9)
 356 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
 357 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          BIT(4)
 358 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        BIT(3)
 359 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      BIT(2)
 360 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      BIT(1)
 361 enum dwc3_omap_utmi_mode {
 362         DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
 363         DWC3_OMAP_UTMI_MODE_HW,
 364         DWC3_OMAP_UTMI_MODE_SW,
 365 };
 366
 367         u32 use_id_pin;
 368         u32 host_mode;
 369         u32 reg;
 370         u32 utmi_mode;
 371         u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
 372
 373         struct dwc3_glue_data *glue = dev_get_plat(dev);
 374         void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
 375
 376         if (device_is_compatible(dev, "ti,am437x-dwc3"))
 377                 utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
 378
 379         utmi_mode = dev_read_u32_default(dev, "utmi-mode",
 380                                          DWC3_OMAP_UTMI_MODE_UNKNOWN);
 381         if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
 382                 debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
 383                       dev->name);
 384                 mode = USB_DR_MODE_PERIPHERAL;
 385         }
 386
 387         switch (mode)  {
 388         case USB_DR_MODE_PERIPHERAL:
 389                 use_id_pin = 0;
 390                 host_mode = 0;
 391                 break;
 392         case USB_DR_MODE_HOST:
 393                 use_id_pin = 0;
 394                 host_mode = 1;
 395                 break;
 396         case USB_DR_MODE_OTG:
 397         default:
 398                 use_id_pin = 1;
 399                 host_mode = 0;
 400                 break;
 401         }
 402
 403         reg = readl(base + utmi_status_offset);
 404
 405         reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
 406         if (!use_id_pin)
 407                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 408
 409         writel(reg, base + utmi_status_offset);
 410
 411         reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
 412                 USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
 413                 USBOTGSS_UTMI_OTG_STATUS_IDDIG);
 414
 415         reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
 416                 USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 417
 418         if (!host_mode)
 419                 reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
 420                         USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
 421
 422         writel(reg, base + utmi_status_offset);
 423
 424         unmap_physmem(base, MAP_NOCACHE);
 425 }
 426
 427 struct dwc3_glue_ops ti_ops = {
 428         .glue_configure = dwc3_ti_glue_configure,
 429 };
 430
 431 /* USB QSCRATCH Hardware registers */
 432 #define QSCRATCH_GENERAL_CFG 0x08
 433 #define PIPE_UTMI_CLK_SEL BIT(0)
 434 #define PIPE3_PHYSTATUS_SW BIT(3)
 435 #define PIPE_UTMI_CLK_DIS BIT(8)
 436
 437 #define QSCRATCH_HS_PHY_CTRL 0x10
 438 #define UTMI_OTG_VBUS_VALID BIT(20)
 439 #define SW_SESSVLD_SEL BIT(28)
 440
 441 #define QSCRATCH_SS_PHY_CTRL 0x30
 442 #define LANE0_PWR_PRESENT BIT(24)
 443
 444 #define PWR_EVNT_IRQ_STAT_REG 0x58
 445 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
 446 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
 447
 448 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
 449 #define SDM845_QSCRATCH_SIZE 0x400
 450 #define SDM845_DWC3_CORE_SIZE 0xcd00
 451
 452 static void dwc3_qcom_vbus_override_enable(void __iomem *qscratch_base, bool enable)
 453 {
 454         if (enable) {
 455                 setbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
 456                                   LANE0_PWR_PRESENT);
 457                 setbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
 458                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
 459         } else {
 460                 clrbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
 461                                   LANE0_PWR_PRESENT);
 462                 clrbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
 463                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
 464         }
 465 }
 466
 467 /* For controllers running without superspeed PHYs */
 468 static void dwc3_qcom_select_utmi_clk(void __iomem *qscratch_base)
 469 {
 470         /* Configure dwc3 to use UTMI clock as PIPE clock not present */
 471         setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
 472                           PIPE_UTMI_CLK_DIS);
 473
 474         setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
 475                           PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
 476
 477         clrbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
 478                           PIPE_UTMI_CLK_DIS);
 479 }
 480
 481 static void dwc3_qcom_glue_configure(struct udevice *dev, int index,
 482                                      enum usb_dr_mode mode)
 483 {
 484         struct dwc3_glue_data *glue = dev_get_plat(dev);
 485         void __iomem *qscratch_base = map_physmem(glue->regs, 0x400, MAP_NOCACHE);
 486         if (IS_ERR_OR_NULL(qscratch_base)) {
 487                 log_err("%s: Invalid qscratch base address\n", dev->name);
 488                 return;
 489         }
 490
 491         if (dev_read_bool(dev, "qcom,select-utmi-as-pipe-clk"))
 492                 dwc3_qcom_select_utmi_clk(qscratch_base);
 493
 494         if (mode != USB_DR_MODE_HOST)
 495                 dwc3_qcom_vbus_override_enable(qscratch_base, true);
 496 }
 497
 498 struct dwc3_glue_ops qcom_ops = {
 499         .glue_configure = dwc3_qcom_glue_configure,
 500 };
 501
 502 static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node)
 503 {
 504         *node = dev_ofnode(dev);
 505         if (!ofnode_valid(*node))
 506                 return -EINVAL;
 507
 508         return 0;
 509 }
 510
 511 struct dwc3_glue_ops rk_ops = {
 512         .glue_get_ctrl_dev = dwc3_rk_glue_get_ctrl_dev,
 513 };
 514
 515 static int dwc3_glue_bind_common(struct udevice *parent, ofnode node)
 516 {
 517         const char *name = ofnode_get_name(node);
 518         const char *driver;
 519         enum usb_dr_mode dr_mode;
 520         struct udevice *dev;
 521         int ret;
 522
 523         debug("%s: subnode name: %s\n", __func__, name);
 524
 525         /* if the parent node doesn't have a mode check the leaf */
 526         dr_mode = usb_get_dr_mode(dev_ofnode(parent));
 527         if (!dr_mode)
 528                 dr_mode = usb_get_dr_mode(node);
 529
 530         if (CONFIG_IS_ENABLED(DM_USB_GADGET) &&
 531             (dr_mode == USB_DR_MODE_PERIPHERAL || dr_mode == USB_DR_MODE_OTG)) {
 532                 debug("%s: dr_mode: OTG or Peripheral\n", __func__);
 533                 driver = "dwc3-generic-peripheral";
 534         } else if (CONFIG_IS_ENABLED(USB_HOST) && dr_mode == USB_DR_MODE_HOST) {
 535                 debug("%s: dr_mode: HOST\n", __func__);
 536                 driver = "dwc3-generic-host";
 537         } else {
 538                 debug("%s: unsupported dr_mode %d\n", __func__, dr_mode);
 539                 return -ENODEV;
 540         }
 541
 542         ret = device_bind_driver_to_node(parent, driver, name,
 543                                          node, &dev);
 544         if (ret) {
 545                 debug("%s: not able to bind usb device mode\n",
 546                       __func__);
 547                 return ret;
 548         }
 549
 550         return 0;
 551 }
 552
 553 int dwc3_glue_bind(struct udevice *parent)
 554 {
 555         struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(parent);
 556         ofnode node;
 557         int ret;
 558
 559         if (ops && ops->glue_get_ctrl_dev) {
 560                 ret = ops->glue_get_ctrl_dev(parent, &node);
 561                 if (ret)
 562                         return ret;
 563
 564                 return dwc3_glue_bind_common(parent, node);
 565         }
 566
 567         ofnode_for_each_subnode(node, dev_ofnode(parent)) {
 568                 ret = dwc3_glue_bind_common(parent, node);
 569                 if (ret == -ENXIO)
 570                         continue;
 571                 if (ret)
 572                         return ret;
 573         }
 574
 575         return 0;
 576 }
 577
 578 static int dwc3_glue_reset_init(struct udevice *dev,
 579                                 struct dwc3_glue_data *glue)
 580 {
 581         int ret;
 582
 583         ret = reset_get_bulk(dev, &glue->resets);
 584         if (ret == -ENOTSUPP || ret == -ENOENT)
 585                 return 0;
 586         else if (ret)
 587                 return ret;
 588
 589         if (device_is_compatible(dev, "qcom,dwc3")) {
 590                 reset_assert_bulk(&glue->resets);
 591                 /* We should wait at least 6 sleep clock cycles, that's
 592                  * (6 / 32764) * 1000000 ~= 200us. But some platforms
 593                  * have slower sleep clocks so we'll play it safe.
 594                  */
 595                 udelay(500);
 596         }
 597         ret = reset_deassert_bulk(&glue->resets);
 598         if (ret) {
 599                 reset_release_bulk(&glue->resets);
 600                 return ret;
 601         }
 602
 603         return 0;
 604 }
 605
 606 static int dwc3_glue_clk_init(struct udevice *dev,
 607                               struct dwc3_glue_data *glue)
 608 {
 609         int ret;
 610
 611         ret = clk_get_bulk(dev, &glue->clks);
 612         if (ret == -ENOSYS || ret == -ENOENT)
 613                 return 0;
 614         if (ret)
 615                 return ret;
 616
 617 #if CONFIG_IS_ENABLED(CLK)
 618         ret = clk_enable_bulk(&glue->clks);
 619         if (ret) {
 620                 clk_release_bulk(&glue->clks);
 621                 return ret;
 622         }
 623 #endif
 624
 625         return 0;
 626 }
 627
 628 int dwc3_glue_probe(struct udevice *dev)
 629 {
 630         struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
 631         struct dwc3_glue_data *glue = dev_get_plat(dev);
 632         struct udevice *child = NULL;
 633         int index = 0;
 634         int ret;
 635         struct phy phy;
 636
 637         ret = generic_phy_get_by_name(dev, "usb3-phy", &phy);
 638         if (!ret) {
 639                 ret = generic_phy_init(&phy);
 640                 if (ret)
 641                         return ret;
 642         } else if (ret != -ENOENT && ret != -ENODATA) {
 643                 debug("could not get phy (err %d)\n", ret);
 644                 return ret;
 645         }
 646
 647         glue->regs = dev_read_addr_size_index(dev, 0, &glue->size);
 648
 649         ret = dwc3_glue_clk_init(dev, glue);
 650         if (ret)
 651                 return ret;
 652
 653         ret = dwc3_glue_reset_init(dev, glue);
 654         if (ret)
 655                 return ret;
 656
 657         if (generic_phy_valid(&phy)) {
 658                 ret = generic_phy_power_on(&phy);
 659                 if (ret)
 660                         return ret;
 661         }
 662
 663         device_find_first_child(dev, &child);
 664         if (!child)
 665                 return 0;
 666
 667         if (glue->clks.count == 0) {
 668                 ret = dwc3_glue_clk_init(child, glue);
 669                 if (ret)
 670                         return ret;
 671         }
 672
 673         if (glue->resets.count == 0) {
 674                 ret = dwc3_glue_reset_init(child, glue);
 675                 if (ret)
 676                         return ret;
 677         }
 678
 679         while (child) {
 680                 enum usb_dr_mode dr_mode;
 681
 682                 dr_mode = usb_get_dr_mode(dev_ofnode(child));
 683                 device_find_next_child(&child);
 684                 if (ops && ops->glue_configure)
 685                         ops->glue_configure(dev, index, dr_mode);
 686                 index++;
 687         }
 688
 689         return 0;
 690 }
 691
 692 int dwc3_glue_remove(struct udevice *dev)
 693 {
 694         struct dwc3_glue_data *glue = dev_get_plat(dev);
 695
 696         reset_release_bulk(&glue->resets);
 697
 698         clk_release_bulk(&glue->clks);
 699
 700         return 0;
 701 }
 702
 703 static const struct udevice_id dwc3_glue_ids[] = {
 704         { .compatible = "xlnx,zynqmp-dwc3" },
 705         { .compatible = "xlnx,versal-dwc3" },
 706         { .compatible = "ti,keystone-dwc3"},
 707         { .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
 708         { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
 709         { .compatible = "ti,am654-dwc3" },
 710         { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
 711         { .compatible = "rockchip,rk3399-dwc3" },
 712         { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
 713         { .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops },
 714         { .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops },
 715         { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
 716         { .compatible = "fsl,imx8mq-dwc3" },
 717         { .compatible = "intel,tangier-dwc3" },
 718         { }
 719 };
 720
 721 U_BOOT_DRIVER(dwc3_generic_wrapper) = {
 722         .name   = "dwc3-generic-wrapper",
 723         .id     = UCLASS_NOP,
 724         .of_match = dwc3_glue_ids,
 725         .bind = dwc3_glue_bind,
 726         .probe = dwc3_glue_probe,
 727         .remove = dwc3_glue_remove,
 728         .plat_auto      = sizeof(struct dwc3_glue_data),
 729
 730 };