1 // SPDX-License-Identifier: GPL-2.0
3 * Generic DWC3 Glue layer
5 * Copyright (C) 2016 - 2018 Xilinx, Inc.
7 * Based on dwc3-omap.c.
14 #include <dm/device-internal.h>
16 #include <dwc3-uboot.h>
17 #include <generic-phy.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/usb/ch9.h>
21 #include <linux/usb/gadget.h>
31 #include "dwc3-generic.h"
33 struct dwc3_generic_plat {
36 enum usb_dr_mode dr_mode;
39 struct dwc3_generic_priv {
43 struct gpio_desc *ulpi_reset;
46 struct dwc3_generic_host_priv {
47 struct xhci_ctrl xhci_ctrl;
48 struct dwc3_generic_priv gen_priv;
51 static int dwc3_generic_probe(struct udevice *dev,
52 struct dwc3_generic_priv *priv)
55 struct dwc3_generic_plat *plat = dev_get_plat(dev);
56 struct dwc3 *dwc3 = &priv->dwc3;
57 struct dwc3_glue_data *glue = dev_get_plat(dev->parent);
58 int __maybe_unused index;
59 ofnode __maybe_unused node;
62 dwc3->maximum_speed = plat->maximum_speed;
63 dwc3->dr_mode = plat->dr_mode;
64 #if CONFIG_IS_ENABLED(OF_CONTROL)
68 * There are currently four disparate placement possibilities of DWC3
69 * reference clock phandle in SoC DTs:
70 * - in top level glue node, with generic subnode without clock (ZynqMP)
71 * - in top level generic node, with no subnode (i.MX8MQ)
72 * - in generic subnode, with other clock in top level node (i.MX8MP)
73 * - in both top level node and generic subnode (Rockchip)
74 * Cover all the possibilities here by looking into both nodes, start
75 * with the top level node as that seems to be used in majority of DTs
76 * to reference the clock.
78 node = dev_ofnode(dev->parent);
79 index = ofnode_stringlist_search(node, "clock-names", "ref");
81 index = ofnode_stringlist_search(node, "clock-names", "ref_clk");
83 node = dev_ofnode(dev);
84 index = ofnode_stringlist_search(node, "clock-names", "ref");
86 index = ofnode_stringlist_search(node, "clock-names", "ref_clk");
89 dwc3->ref_clk = &glue->clks.clks[index];
93 * It must hold whole USB3.0 OTG controller in resetting to hold pipe
94 * power state in P2 before initializing TypeC PHY on RK3399 platform.
96 if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
97 reset_assert_bulk(&glue->resets);
101 rc = dwc3_setup_phy(dev, &priv->phys);
102 if (rc && rc != -ENOTSUPP)
105 if (CONFIG_IS_ENABLED(DM_GPIO) &&
106 device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) {
107 priv->ulpi_reset = devm_gpiod_get_optional(dev->parent, "reset",
108 GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
109 /* property is optional, don't return error! */
110 if (priv->ulpi_reset) {
111 /* Toggle ulpi to reset the phy. */
112 rc = dm_gpio_set_value(priv->ulpi_reset, 1);
118 rc = dm_gpio_set_value(priv->ulpi_reset, 0);
126 if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
127 reset_deassert_bulk(&glue->resets);
129 priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
130 dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
133 rc = dwc3_init(dwc3);
135 unmap_physmem(priv->base, MAP_NOCACHE);
142 static int dwc3_generic_remove(struct udevice *dev,
143 struct dwc3_generic_priv *priv)
145 struct dwc3 *dwc3 = &priv->dwc3;
147 if (CONFIG_IS_ENABLED(DM_GPIO) &&
148 device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3") &&
150 struct gpio_desc *ulpi_reset = priv->ulpi_reset;
152 dm_gpio_free(ulpi_reset->dev, ulpi_reset);
156 dwc3_shutdown_phy(dev, &priv->phys);
157 unmap_physmem(dwc3->regs, MAP_NOCACHE);
162 static int dwc3_generic_of_to_plat(struct udevice *dev)
164 struct dwc3_generic_plat *plat = dev_get_plat(dev);
165 ofnode node = dev_ofnode(dev);
167 if (!strncmp(dev->name, "port", 4) || !strncmp(dev->name, "hub", 3)) {
168 /* This is a leaf so check the parent */
169 plat->base = dev_read_addr(dev->parent);
171 plat->base = dev_read_addr(dev);
174 plat->maximum_speed = usb_get_maximum_speed(node);
175 if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
176 pr_info("No USB maximum speed specified. Using super speed\n");
177 plat->maximum_speed = USB_SPEED_SUPER;
180 plat->dr_mode = usb_get_dr_mode(node);
181 if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
182 /* might be a leaf so check the parent for mode */
183 node = dev_ofnode(dev->parent);
184 plat->dr_mode = usb_get_dr_mode(node);
185 if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
186 pr_err("Invalid usb mode setup\n");
194 #if CONFIG_IS_ENABLED(DM_USB_GADGET)
195 int dm_usb_gadget_handle_interrupts(struct udevice *dev)
197 struct dwc3_generic_priv *priv = dev_get_priv(dev);
198 struct dwc3 *dwc3 = &priv->dwc3;
200 dwc3_gadget_uboot_handle_interrupt(dwc3);
205 static int dwc3_generic_peripheral_probe(struct udevice *dev)
207 struct dwc3_generic_priv *priv = dev_get_priv(dev);
209 return dwc3_generic_probe(dev, priv);
212 static int dwc3_generic_peripheral_remove(struct udevice *dev)
214 struct dwc3_generic_priv *priv = dev_get_priv(dev);
216 return dwc3_generic_remove(dev, priv);
219 U_BOOT_DRIVER(dwc3_generic_peripheral) = {
220 .name = "dwc3-generic-peripheral",
221 .id = UCLASS_USB_GADGET_GENERIC,
222 .of_to_plat = dwc3_generic_of_to_plat,
223 .probe = dwc3_generic_peripheral_probe,
224 .remove = dwc3_generic_peripheral_remove,
225 .priv_auto = sizeof(struct dwc3_generic_priv),
226 .plat_auto = sizeof(struct dwc3_generic_plat),
230 #if CONFIG_IS_ENABLED(USB_HOST)
231 static int dwc3_generic_host_probe(struct udevice *dev)
233 struct xhci_hcor *hcor;
234 struct xhci_hccr *hccr;
235 struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
238 rc = dwc3_generic_probe(dev, &priv->gen_priv);
242 hccr = (struct xhci_hccr *)priv->gen_priv.base;
243 hcor = (struct xhci_hcor *)(priv->gen_priv.base +
244 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
246 return xhci_register(dev, hccr, hcor);
249 static int dwc3_generic_host_remove(struct udevice *dev)
251 struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
254 rc = xhci_deregister(dev);
258 return dwc3_generic_remove(dev, &priv->gen_priv);
261 U_BOOT_DRIVER(dwc3_generic_host) = {
262 .name = "dwc3-generic-host",
264 .of_to_plat = dwc3_generic_of_to_plat,
265 .probe = dwc3_generic_host_probe,
266 .remove = dwc3_generic_host_remove,
267 .priv_auto = sizeof(struct dwc3_generic_host_priv),
268 .plat_auto = sizeof(struct dwc3_generic_plat),
269 .ops = &xhci_usb_ops,
270 .flags = DM_FLAG_ALLOC_PRIV_DMA,
274 void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
275 enum usb_dr_mode mode)
277 /* USB glue registers */
278 #define USB_CTRL0 0x00
279 #define USB_CTRL1 0x04
281 #define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
282 #define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
283 #define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
285 #define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
286 #define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
287 fdt_addr_t regs = dev_read_addr_index(dev, 1);
288 void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
291 value = readl(base + USB_CTRL0);
293 if (dev_read_bool(dev, "fsl,permanently-attached"))
294 value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
296 value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
298 if (dev_read_bool(dev, "fsl,disable-port-power-control"))
299 value &= ~(USB_CTRL0_PORTPWR_EN);
301 value |= USB_CTRL0_PORTPWR_EN;
303 writel(value, base + USB_CTRL0);
305 value = readl(base + USB_CTRL1);
306 if (dev_read_bool(dev, "fsl,over-current-active-low"))
307 value |= USB_CTRL1_OC_POLARITY;
309 value &= ~USB_CTRL1_OC_POLARITY;
311 if (dev_read_bool(dev, "fsl,power-active-low"))
312 value |= USB_CTRL1_PWR_POLARITY;
314 value &= ~USB_CTRL1_PWR_POLARITY;
316 writel(value, base + USB_CTRL1);
318 unmap_physmem(base, MAP_NOCACHE);
321 struct dwc3_glue_ops imx8mp_ops = {
322 .glue_configure = dwc3_imx8mp_glue_configure,
325 void dwc3_ti_glue_configure(struct udevice *dev, int index,
326 enum usb_dr_mode mode)
328 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
329 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
331 /* UTMI_OTG_STATUS REGISTER */
332 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
333 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
334 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
335 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
336 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
337 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
338 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
339 enum dwc3_omap_utmi_mode {
340 DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
341 DWC3_OMAP_UTMI_MODE_HW,
342 DWC3_OMAP_UTMI_MODE_SW,
349 u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
351 struct dwc3_glue_data *glue = dev_get_plat(dev);
352 void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
354 if (device_is_compatible(dev, "ti,am437x-dwc3"))
355 utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
357 utmi_mode = dev_read_u32_default(dev, "utmi-mode",
358 DWC3_OMAP_UTMI_MODE_UNKNOWN);
359 if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
360 debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
362 mode = USB_DR_MODE_PERIPHERAL;
366 case USB_DR_MODE_PERIPHERAL:
370 case USB_DR_MODE_HOST:
374 case USB_DR_MODE_OTG:
381 reg = readl(base + utmi_status_offset);
383 reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
385 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
387 writel(reg, base + utmi_status_offset);
389 reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
390 USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
391 USBOTGSS_UTMI_OTG_STATUS_IDDIG);
393 reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
394 USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
397 reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
398 USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
400 writel(reg, base + utmi_status_offset);
402 unmap_physmem(base, MAP_NOCACHE);
405 struct dwc3_glue_ops ti_ops = {
406 .glue_configure = dwc3_ti_glue_configure,
409 static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node)
411 *node = dev_ofnode(dev);
412 if (!ofnode_valid(*node))
418 struct dwc3_glue_ops rk_ops = {
419 .glue_get_ctrl_dev = dwc3_rk_glue_get_ctrl_dev,
422 static int dwc3_glue_bind_common(struct udevice *parent, ofnode node)
424 const char *name = ofnode_get_name(node);
426 enum usb_dr_mode dr_mode;
430 debug("%s: subnode name: %s\n", __func__, name);
432 /* if the parent node doesn't have a mode check the leaf */
433 dr_mode = usb_get_dr_mode(dev_ofnode(parent));
435 dr_mode = usb_get_dr_mode(node);
437 if (CONFIG_IS_ENABLED(DM_USB_GADGET) &&
438 (dr_mode == USB_DR_MODE_PERIPHERAL || dr_mode == USB_DR_MODE_OTG)) {
439 debug("%s: dr_mode: OTG or Peripheral\n", __func__);
440 driver = "dwc3-generic-peripheral";
441 } else if (CONFIG_IS_ENABLED(USB_HOST) && dr_mode == USB_DR_MODE_HOST) {
442 debug("%s: dr_mode: HOST\n", __func__);
443 driver = "dwc3-generic-host";
445 debug("%s: unsupported dr_mode %d\n", __func__, dr_mode);
449 ret = device_bind_driver_to_node(parent, driver, name,
452 debug("%s: not able to bind usb device mode\n",
460 int dwc3_glue_bind(struct udevice *parent)
462 struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(parent);
466 if (ops && ops->glue_get_ctrl_dev) {
467 ret = ops->glue_get_ctrl_dev(parent, &node);
471 return dwc3_glue_bind_common(parent, node);
474 ofnode_for_each_subnode(node, dev_ofnode(parent)) {
475 ret = dwc3_glue_bind_common(parent, node);
485 static int dwc3_glue_reset_init(struct udevice *dev,
486 struct dwc3_glue_data *glue)
490 ret = reset_get_bulk(dev, &glue->resets);
491 if (ret == -ENOTSUPP || ret == -ENOENT)
496 ret = reset_deassert_bulk(&glue->resets);
498 reset_release_bulk(&glue->resets);
505 static int dwc3_glue_clk_init(struct udevice *dev,
506 struct dwc3_glue_data *glue)
510 ret = clk_get_bulk(dev, &glue->clks);
511 if (ret == -ENOSYS || ret == -ENOENT)
516 #if CONFIG_IS_ENABLED(CLK)
517 ret = clk_enable_bulk(&glue->clks);
519 clk_release_bulk(&glue->clks);
527 int dwc3_glue_probe(struct udevice *dev)
529 struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
530 struct dwc3_glue_data *glue = dev_get_plat(dev);
531 struct udevice *child = NULL;
536 ret = generic_phy_get_by_name(dev, "usb3-phy", &phy);
538 ret = generic_phy_init(&phy);
541 } else if (ret != -ENOENT && ret != -ENODATA) {
542 debug("could not get phy (err %d)\n", ret);
548 glue->regs = dev_read_addr_size_index(dev, 0, &glue->size);
550 ret = dwc3_glue_clk_init(dev, glue);
554 ret = dwc3_glue_reset_init(dev, glue);
559 ret = generic_phy_power_on(&phy);
564 device_find_first_child(dev, &child);
568 if (glue->clks.count == 0) {
569 ret = dwc3_glue_clk_init(child, glue);
574 if (glue->resets.count == 0) {
575 ret = dwc3_glue_reset_init(child, glue);
581 enum usb_dr_mode dr_mode;
583 dr_mode = usb_get_dr_mode(dev_ofnode(child));
584 device_find_next_child(&child);
585 if (ops && ops->glue_configure)
586 ops->glue_configure(dev, index, dr_mode);
593 int dwc3_glue_remove(struct udevice *dev)
595 struct dwc3_glue_data *glue = dev_get_plat(dev);
597 reset_release_bulk(&glue->resets);
599 clk_release_bulk(&glue->clks);
604 static const struct udevice_id dwc3_glue_ids[] = {
605 { .compatible = "xlnx,zynqmp-dwc3" },
606 { .compatible = "xlnx,versal-dwc3" },
607 { .compatible = "ti,keystone-dwc3"},
608 { .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
609 { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
610 { .compatible = "ti,am654-dwc3" },
611 { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops },
612 { .compatible = "rockchip,rk3399-dwc3" },
613 { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops },
614 { .compatible = "qcom,dwc3" },
615 { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
616 { .compatible = "fsl,imx8mq-dwc3" },
617 { .compatible = "intel,tangier-dwc3" },
621 U_BOOT_DRIVER(dwc3_generic_wrapper) = {
622 .name = "dwc3-generic-wrapper",
624 .of_match = dwc3_glue_ids,
625 .bind = dwc3_glue_bind,
626 .probe = dwc3_glue_probe,
627 .remove = dwc3_glue_remove,
628 .plat_auto = sizeof(struct dwc3_glue_data),