1 // SPDX-License-Identifier: GPL-2.0
3 * Generic DWC3 Glue layer
5 * Copyright (C) 2016 - 2018 Xilinx, Inc.
7 * Based on dwc3-omap.c.
13 #include <asm-generic/io.h>
15 #include <dm/device-internal.h>
17 #include <dwc3-uboot.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/usb/ch9.h>
21 #include <linux/usb/gadget.h>
30 struct dwc3_glue_data {
32 struct reset_ctl_bulk resets;
36 struct dwc3_generic_plat {
39 enum usb_dr_mode dr_mode;
42 struct dwc3_generic_priv {
48 struct dwc3_generic_host_priv {
49 struct xhci_ctrl xhci_ctrl;
50 struct dwc3_generic_priv gen_priv;
53 static int dwc3_generic_probe(struct udevice *dev,
54 struct dwc3_generic_priv *priv)
57 struct dwc3_generic_plat *plat = dev_get_platdata(dev);
58 struct dwc3 *dwc3 = &priv->dwc3;
59 struct dwc3_glue_data *glue = dev_get_platdata(dev->parent);
62 dwc3->maximum_speed = plat->maximum_speed;
63 dwc3->dr_mode = plat->dr_mode;
64 #if CONFIG_IS_ENABLED(OF_CONTROL)
69 * It must hold whole USB3.0 OTG controller in resetting to hold pipe
70 * power state in P2 before initializing TypeC PHY on RK3399 platform.
72 if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3")) {
73 reset_assert_bulk(&glue->resets);
77 rc = dwc3_setup_phy(dev, &priv->phys);
81 if (device_is_compatible(dev->parent, "rockchip,rk3399-dwc3"))
82 reset_deassert_bulk(&glue->resets);
84 priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
85 dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
90 unmap_physmem(priv->base, MAP_NOCACHE);
97 static int dwc3_generic_remove(struct udevice *dev,
98 struct dwc3_generic_priv *priv)
100 struct dwc3 *dwc3 = &priv->dwc3;
103 dwc3_shutdown_phy(dev, &priv->phys);
104 unmap_physmem(dwc3->regs, MAP_NOCACHE);
109 static int dwc3_generic_ofdata_to_platdata(struct udevice *dev)
111 struct dwc3_generic_plat *plat = dev_get_platdata(dev);
112 ofnode node = dev->node;
114 plat->base = dev_read_addr(dev);
116 plat->maximum_speed = usb_get_maximum_speed(node);
117 if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
118 pr_info("No USB maximum speed specified. Using super speed\n");
119 plat->maximum_speed = USB_SPEED_SUPER;
122 plat->dr_mode = usb_get_dr_mode(node);
123 if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
124 pr_err("Invalid usb mode setup\n");
131 #if CONFIG_IS_ENABLED(DM_USB_GADGET)
132 int dm_usb_gadget_handle_interrupts(struct udevice *dev)
134 struct dwc3_generic_priv *priv = dev_get_priv(dev);
135 struct dwc3 *dwc3 = &priv->dwc3;
137 dwc3_gadget_uboot_handle_interrupt(dwc3);
142 static int dwc3_generic_peripheral_probe(struct udevice *dev)
144 struct dwc3_generic_priv *priv = dev_get_priv(dev);
146 return dwc3_generic_probe(dev, priv);
149 static int dwc3_generic_peripheral_remove(struct udevice *dev)
151 struct dwc3_generic_priv *priv = dev_get_priv(dev);
153 return dwc3_generic_remove(dev, priv);
156 U_BOOT_DRIVER(dwc3_generic_peripheral) = {
157 .name = "dwc3-generic-peripheral",
158 .id = UCLASS_USB_GADGET_GENERIC,
159 .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
160 .probe = dwc3_generic_peripheral_probe,
161 .remove = dwc3_generic_peripheral_remove,
162 .priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
163 .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
167 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
168 static int dwc3_generic_host_probe(struct udevice *dev)
170 struct xhci_hcor *hcor;
171 struct xhci_hccr *hccr;
172 struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
175 rc = dwc3_generic_probe(dev, &priv->gen_priv);
179 hccr = (struct xhci_hccr *)priv->gen_priv.base;
180 hcor = (struct xhci_hcor *)(priv->gen_priv.base +
181 HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
183 return xhci_register(dev, hccr, hcor);
186 static int dwc3_generic_host_remove(struct udevice *dev)
188 struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
191 rc = xhci_deregister(dev);
195 return dwc3_generic_remove(dev, &priv->gen_priv);
198 U_BOOT_DRIVER(dwc3_generic_host) = {
199 .name = "dwc3-generic-host",
201 .ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
202 .probe = dwc3_generic_host_probe,
203 .remove = dwc3_generic_host_remove,
204 .priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv),
205 .platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
206 .ops = &xhci_usb_ops,
207 .flags = DM_FLAG_ALLOC_PRIV_DMA,
211 struct dwc3_glue_ops {
212 void (*select_dr_mode)(struct udevice *dev, int index,
213 enum usb_dr_mode mode);
216 void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
217 enum usb_dr_mode mode)
219 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
220 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
222 /* UTMI_OTG_STATUS REGISTER */
223 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
224 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
225 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
226 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
227 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
228 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
229 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
230 enum dwc3_omap_utmi_mode {
231 DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
232 DWC3_OMAP_UTMI_MODE_HW,
233 DWC3_OMAP_UTMI_MODE_SW,
240 u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
242 struct dwc3_glue_data *glue = dev_get_platdata(dev);
243 void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
245 if (device_is_compatible(dev, "ti,am437x-dwc3"))
246 utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
248 utmi_mode = dev_read_u32_default(dev, "utmi-mode",
249 DWC3_OMAP_UTMI_MODE_UNKNOWN);
250 if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
251 debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
253 mode = USB_DR_MODE_PERIPHERAL;
257 case USB_DR_MODE_PERIPHERAL:
261 case USB_DR_MODE_HOST:
265 case USB_DR_MODE_OTG:
272 reg = readl(base + utmi_status_offset);
274 reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
276 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
278 writel(reg, base + utmi_status_offset);
280 reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
281 USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
282 USBOTGSS_UTMI_OTG_STATUS_IDDIG);
284 reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
285 USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
288 reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
289 USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
291 writel(reg, base + utmi_status_offset);
293 unmap_physmem(base, MAP_NOCACHE);
296 struct dwc3_glue_ops ti_ops = {
297 .select_dr_mode = dwc3_ti_select_dr_mode,
300 static int dwc3_glue_bind(struct udevice *parent)
305 ofnode_for_each_subnode(node, parent->node) {
306 const char *name = ofnode_get_name(node);
307 enum usb_dr_mode dr_mode;
309 const char *driver = NULL;
311 debug("%s: subnode name: %s\n", __func__, name);
313 dr_mode = usb_get_dr_mode(node);
316 case USB_DR_MODE_PERIPHERAL:
317 case USB_DR_MODE_OTG:
318 #if CONFIG_IS_ENABLED(DM_USB_GADGET)
319 debug("%s: dr_mode: OTG or Peripheral\n", __func__);
320 driver = "dwc3-generic-peripheral";
323 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
324 case USB_DR_MODE_HOST:
325 debug("%s: dr_mode: HOST\n", __func__);
326 driver = "dwc3-generic-host";
330 debug("%s: unsupported dr_mode\n", __func__);
337 ret = device_bind_driver_to_node(parent, driver, name,
340 debug("%s: not able to bind usb device mode\n",
349 static int dwc3_glue_reset_init(struct udevice *dev,
350 struct dwc3_glue_data *glue)
354 ret = reset_get_bulk(dev, &glue->resets);
355 if (ret == -ENOTSUPP || ret == -ENOENT)
360 ret = reset_deassert_bulk(&glue->resets);
362 reset_release_bulk(&glue->resets);
369 static int dwc3_glue_clk_init(struct udevice *dev,
370 struct dwc3_glue_data *glue)
374 ret = clk_get_bulk(dev, &glue->clks);
375 if (ret == -ENOSYS || ret == -ENOENT)
380 #if CONFIG_IS_ENABLED(CLK)
381 ret = clk_enable_bulk(&glue->clks);
383 clk_release_bulk(&glue->clks);
391 static int dwc3_glue_probe(struct udevice *dev)
393 struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
394 struct dwc3_glue_data *glue = dev_get_platdata(dev);
395 struct udevice *child = NULL;
399 glue->regs = dev_read_addr(dev);
401 ret = dwc3_glue_clk_init(dev, glue);
405 ret = dwc3_glue_reset_init(dev, glue);
409 ret = device_find_first_child(dev, &child);
413 if (glue->resets.count == 0) {
414 ret = dwc3_glue_reset_init(child, glue);
420 enum usb_dr_mode dr_mode;
422 dr_mode = usb_get_dr_mode(child->node);
423 device_find_next_child(&child);
424 if (ops && ops->select_dr_mode)
425 ops->select_dr_mode(dev, index, dr_mode);
432 static int dwc3_glue_remove(struct udevice *dev)
434 struct dwc3_glue_data *glue = dev_get_platdata(dev);
436 reset_release_bulk(&glue->resets);
438 clk_release_bulk(&glue->clks);
443 static const struct udevice_id dwc3_glue_ids[] = {
444 { .compatible = "xlnx,zynqmp-dwc3" },
445 { .compatible = "xlnx,versal-dwc3" },
446 { .compatible = "ti,keystone-dwc3"},
447 { .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
448 { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
449 { .compatible = "ti,am654-dwc3" },
450 { .compatible = "rockchip,rk3328-dwc3" },
451 { .compatible = "rockchip,rk3399-dwc3" },
452 { .compatible = "qcom,dwc3" },
456 U_BOOT_DRIVER(dwc3_generic_wrapper) = {
457 .name = "dwc3-generic-wrapper",
459 .of_match = dwc3_glue_ids,
460 .bind = dwc3_glue_bind,
461 .probe = dwc3_glue_probe,
462 .remove = dwc3_glue_remove,
463 .platdata_auto_alloc_size = sizeof(struct dwc3_glue_data),