1 /* SPDX-License-Identifier: GPL-2.0 */
3 * core.h - DesignWare USB3 DRD Core Header
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.h) and ported
13 * commit 460d098cb6 : usb: dwc3: make HIRD threshold configurable
17 #ifndef __DRIVERS_USB_DWC3_CORE_H
18 #define __DRIVERS_USB_DWC3_CORE_H
20 #include <linux/ioport.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/otg.h>
25 #define DWC3_MSG_MAX 500
27 /* Global constants */
28 #define DWC3_EP0_BOUNCE_SIZE 512
29 #define DWC3_ENDPOINTS_NUM 32
30 #define DWC3_XHCI_RESOURCES_NUM 2
32 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
33 #define DWC3_EVENT_SIZE 4 /* bytes */
34 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
35 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
36 #define DWC3_EVENT_TYPE_MASK 0xfe
38 #define DWC3_EVENT_TYPE_DEV 0
39 #define DWC3_EVENT_TYPE_CARKIT 3
40 #define DWC3_EVENT_TYPE_I2C 4
42 #define DWC3_DEVICE_EVENT_DISCONNECT 0
43 #define DWC3_DEVICE_EVENT_RESET 1
44 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
45 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
46 #define DWC3_DEVICE_EVENT_WAKEUP 4
47 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
48 #define DWC3_DEVICE_EVENT_EOPF 6
49 #define DWC3_DEVICE_EVENT_SOF 7
50 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
51 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
52 #define DWC3_DEVICE_EVENT_OVERFLOW 11
54 #define DWC3_GEVNTCOUNT_MASK 0xfffc
55 #define DWC3_GSNPSID_MASK 0xffff0000
56 #define DWC3_GSNPSREV_MASK 0xffff
58 /* DWC3 registers memory space boundries */
59 #define DWC3_XHCI_REGS_START 0x0
60 #define DWC3_XHCI_REGS_END 0x7fff
61 #define DWC3_GLOBALS_REGS_START 0xc100
62 #define DWC3_GLOBALS_REGS_END 0xc6ff
63 #define DWC3_DEVICE_REGS_START 0xc700
64 #define DWC3_DEVICE_REGS_END 0xcbff
65 #define DWC3_OTG_REGS_START 0xcc00
66 #define DWC3_OTG_REGS_END 0xccff
68 /* Global Registers */
69 #define DWC3_GSBUSCFG0 0xc100
70 #define DWC3_GSBUSCFG1 0xc104
71 #define DWC3_GTXTHRCFG 0xc108
72 #define DWC3_GRXTHRCFG 0xc10c
73 #define DWC3_GCTL 0xc110
74 #define DWC3_GEVTEN 0xc114
75 #define DWC3_GSTS 0xc118
76 #define DWC3_GSNPSID 0xc120
77 #define DWC3_GGPIO 0xc124
78 #define DWC3_GUID 0xc128
79 #define DWC3_GUCTL 0xc12c
80 #define DWC3_GBUSERRADDR0 0xc130
81 #define DWC3_GBUSERRADDR1 0xc134
82 #define DWC3_GPRTBIMAP0 0xc138
83 #define DWC3_GPRTBIMAP1 0xc13c
84 #define DWC3_GHWPARAMS0 0xc140
85 #define DWC3_GHWPARAMS1 0xc144
86 #define DWC3_GHWPARAMS2 0xc148
87 #define DWC3_GHWPARAMS3 0xc14c
88 #define DWC3_GHWPARAMS4 0xc150
89 #define DWC3_GHWPARAMS5 0xc154
90 #define DWC3_GHWPARAMS6 0xc158
91 #define DWC3_GHWPARAMS7 0xc15c
92 #define DWC3_GDBGFIFOSPACE 0xc160
93 #define DWC3_GDBGLTSSM 0xc164
94 #define DWC3_GPRTBIMAP_HS0 0xc180
95 #define DWC3_GPRTBIMAP_HS1 0xc184
96 #define DWC3_GPRTBIMAP_FS0 0xc188
97 #define DWC3_GPRTBIMAP_FS1 0xc18c
99 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
100 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
102 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
104 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
106 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
107 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
109 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
110 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
111 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
112 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
114 #define DWC3_GHWPARAMS8 0xc600
116 /* Device Registers */
117 #define DWC3_DCFG 0xc700
118 #define DWC3_DCTL 0xc704
119 #define DWC3_DEVTEN 0xc708
120 #define DWC3_DSTS 0xc70c
121 #define DWC3_DGCMDPAR 0xc710
122 #define DWC3_DGCMD 0xc714
123 #define DWC3_DALEPENA 0xc720
124 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
125 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
126 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
127 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
130 #define DWC3_OCFG 0xcc00
131 #define DWC3_OCTL 0xcc04
132 #define DWC3_OEVT 0xcc08
133 #define DWC3_OEVTEN 0xcc0C
134 #define DWC3_OSTS 0xcc10
138 /* Global Configuration Register */
139 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
140 #define DWC3_GCTL_U2RSTECN (1 << 16)
141 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
142 #define DWC3_GCTL_CLK_BUS (0)
143 #define DWC3_GCTL_CLK_PIPE (1)
144 #define DWC3_GCTL_CLK_PIPEHALF (2)
145 #define DWC3_GCTL_CLK_MASK (3)
147 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
148 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
149 #define DWC3_GCTL_PRTCAP_HOST 1
150 #define DWC3_GCTL_PRTCAP_DEVICE 2
151 #define DWC3_GCTL_PRTCAP_OTG 3
153 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
154 #define DWC3_GCTL_SOFITPSYNC (1 << 10)
155 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
156 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
157 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
158 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
159 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
160 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
162 /* Global USB2 PHY Configuration Register */
163 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
164 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
165 #define DWC3_GUSB2PHYCFG_PHYIF BIT(3)
167 /* Global USB2 PHY Configuration Mask */
168 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
170 /* Global USB2 PHY Configuration Offset */
171 #define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
173 #define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
174 DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
175 #define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
176 DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
178 /* Global USB3 PIPE Control Register */
179 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
180 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
181 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
182 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
183 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
184 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
185 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
186 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
187 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
188 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
189 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
190 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
192 /* Global TX Fifo Size Register */
193 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
194 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
196 /* Global Event Size Registers */
197 #define DWC3_GEVNTSIZ_INTMASK (1 << 31)
198 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
200 /* Global HWPARAMS1 Register */
201 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
202 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
203 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
204 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
205 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
206 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
208 /* Global HWPARAMS3 Register */
209 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
210 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
211 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
212 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
213 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
214 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
215 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
216 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
217 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
218 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
219 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
221 /* Global HWPARAMS4 Register */
222 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
223 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
225 /* Global HWPARAMS6 Register */
226 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
228 /* Device Configuration Register */
229 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
230 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
232 #define DWC3_DCFG_SPEED_MASK (7 << 0)
233 #define DWC3_DCFG_SUPERSPEED (4 << 0)
234 #define DWC3_DCFG_HIGHSPEED (0 << 0)
235 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
236 #define DWC3_DCFG_LOWSPEED (2 << 0)
237 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
239 #define DWC3_DCFG_LPM_CAP (1 << 22)
241 /* Device Control Register */
242 #define DWC3_DCTL_RUN_STOP (1 << 31)
243 #define DWC3_DCTL_CSFTRST (1 << 30)
244 #define DWC3_DCTL_LSFTRST (1 << 29)
246 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
247 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
249 #define DWC3_DCTL_APPL1RES (1 << 23)
251 /* These apply for core versions 1.87a and earlier */
252 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
253 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
254 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
255 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
256 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
257 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
258 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
260 /* These apply for core versions 1.94a and later */
261 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
262 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
264 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
265 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
266 #define DWC3_DCTL_CRS (1 << 17)
267 #define DWC3_DCTL_CSS (1 << 16)
269 #define DWC3_DCTL_INITU2ENA (1 << 12)
270 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
271 #define DWC3_DCTL_INITU1ENA (1 << 10)
272 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
273 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
275 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
276 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
278 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
279 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
280 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
281 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
282 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
283 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
284 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
286 /* Device Event Enable Register */
287 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
288 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
289 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
290 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
291 #define DWC3_DEVTEN_SOFEN (1 << 7)
292 #define DWC3_DEVTEN_EOPFEN (1 << 6)
293 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
294 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
295 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
296 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
297 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
298 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
300 /* Device Status Register */
301 #define DWC3_DSTS_DCNRD (1 << 29)
303 /* This applies for core versions 1.87a and earlier */
304 #define DWC3_DSTS_PWRUPREQ (1 << 24)
306 /* These apply for core versions 1.94a and later */
307 #define DWC3_DSTS_RSS (1 << 25)
308 #define DWC3_DSTS_SSS (1 << 24)
310 #define DWC3_DSTS_COREIDLE (1 << 23)
311 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
313 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
314 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
316 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
318 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
319 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
321 #define DWC3_DSTS_CONNECTSPD (7 << 0)
323 #define DWC3_DSTS_SUPERSPEED (4 << 0)
324 #define DWC3_DSTS_HIGHSPEED (0 << 0)
325 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
326 #define DWC3_DSTS_LOWSPEED (2 << 0)
327 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
329 /* Device Generic Command Register */
330 #define DWC3_DGCMD_SET_LMP 0x01
331 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
332 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
334 /* These apply for core versions 1.94a and later */
335 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
336 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
338 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
339 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
340 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
341 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
343 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
344 #define DWC3_DGCMD_CMDACT (1 << 10)
345 #define DWC3_DGCMD_CMDIOC (1 << 8)
347 /* Device Generic Command Parameter Register */
348 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
349 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
350 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
351 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
352 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
353 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
355 /* Device Endpoint Command Register */
356 #define DWC3_DEPCMD_PARAM_SHIFT 16
357 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
358 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
359 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
360 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
361 #define DWC3_DEPCMD_CMDACT (1 << 10)
362 #define DWC3_DEPCMD_CMDIOC (1 << 8)
364 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
365 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
366 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
367 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
368 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
369 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
370 /* This applies for core versions 1.90a and earlier */
371 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
372 /* This applies for core versions 1.94a and later */
373 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
374 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
375 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
377 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
378 #define DWC3_DALEPENA_EP(n) (1 << n)
380 #define DWC3_DEPCMD_TYPE_CONTROL 0
381 #define DWC3_DEPCMD_TYPE_ISOC 1
382 #define DWC3_DEPCMD_TYPE_BULK 2
383 #define DWC3_DEPCMD_TYPE_INTR 3
390 * struct dwc3_event_buffer - Software event buffer representation
392 * @length: size of this buffer
393 * @lpos: event offset
394 * @count: cache of last read event count register
395 * @flags: flags related to this event buffer
397 * @dwc: pointer to DWC controller
399 struct dwc3_event_buffer {
406 #define DWC3_EVENT_PENDING (1UL << 0)
413 #define DWC3_EP_FLAG_STALLED (1 << 0)
414 #define DWC3_EP_FLAG_WEDGED (1 << 1)
416 #define DWC3_EP_DIRECTION_TX true
417 #define DWC3_EP_DIRECTION_RX false
419 #define DWC3_TRB_NUM 32
420 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
423 * struct dwc3_ep - device side endpoint representation
424 * @endpoint: usb endpoint
425 * @request_list: list of requests for this endpoint
426 * @req_queued: list of requests on this ep which have TRBs setup
427 * @trb_pool: array of transaction buffers
428 * @trb_pool_dma: dma address of @trb_pool
429 * @free_slot: next slot which is going to be used
430 * @busy_slot: first slot which is owned by HW
431 * @desc: usb_endpoint_descriptor pointer
432 * @dwc: pointer to DWC controller
433 * @saved_state: ep state saved during hibernation
434 * @flags: endpoint flags (wedged, stalled, ...)
435 * @current_trb: index of current used trb
436 * @number: endpoint number (1 - 15)
437 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
438 * @resource_index: Resource transfer index
439 * @interval: the interval on which the ISOC transfer is started
440 * @name: a human readable name e.g. ep1out-bulk
441 * @direction: true for TX, false for RX
442 * @stream_capable: true when streams are enabled
445 struct usb_ep endpoint;
446 struct list_head request_list;
447 struct list_head req_queued;
449 struct dwc3_trb *trb_pool;
450 dma_addr_t trb_pool_dma;
453 const struct usb_ss_ep_comp_descriptor *comp_desc;
458 #define DWC3_EP_ENABLED (1 << 0)
459 #define DWC3_EP_STALL (1 << 1)
460 #define DWC3_EP_WEDGE (1 << 2)
461 #define DWC3_EP_BUSY (1 << 4)
462 #define DWC3_EP_PENDING_REQUEST (1 << 5)
463 #define DWC3_EP_MISSED_ISOC (1 << 6)
465 /* This last one is specific to EP0 */
466 #define DWC3_EP0_DIR_IN (1 << 31)
468 unsigned current_trb;
477 unsigned direction:1;
478 unsigned stream_capable:1;
482 DWC3_PHY_UNKNOWN = 0,
488 DWC3_EP0_UNKNOWN = 0,
491 DWC3_EP0_NRDY_STATUS,
494 enum dwc3_ep0_state {
501 enum dwc3_link_state {
503 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
504 DWC3_LINK_STATE_U1 = 0x01,
505 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
506 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
507 DWC3_LINK_STATE_SS_DIS = 0x04,
508 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
509 DWC3_LINK_STATE_SS_INACT = 0x06,
510 DWC3_LINK_STATE_POLL = 0x07,
511 DWC3_LINK_STATE_RECOV = 0x08,
512 DWC3_LINK_STATE_HRESET = 0x09,
513 DWC3_LINK_STATE_CMPLY = 0x0a,
514 DWC3_LINK_STATE_LPBK = 0x0b,
515 DWC3_LINK_STATE_RESET = 0x0e,
516 DWC3_LINK_STATE_RESUME = 0x0f,
517 DWC3_LINK_STATE_MASK = 0x0f,
520 /* TRB Length, PCM and Status */
521 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
522 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
523 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
524 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
526 #define DWC3_TRBSTS_OK 0
527 #define DWC3_TRBSTS_MISSED_ISOC 1
528 #define DWC3_TRBSTS_SETUP_PENDING 2
529 #define DWC3_TRB_STS_XFER_IN_PROG 4
532 #define DWC3_TRB_CTRL_HWO (1 << 0)
533 #define DWC3_TRB_CTRL_LST (1 << 1)
534 #define DWC3_TRB_CTRL_CHN (1 << 2)
535 #define DWC3_TRB_CTRL_CSP (1 << 3)
536 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
537 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
538 #define DWC3_TRB_CTRL_IOC (1 << 11)
539 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
541 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
542 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
543 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
544 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
545 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
546 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
547 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
548 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
551 * struct dwc3_trb - transfer request block (hw format)
565 * dwc3_hwparams - copy of HWPARAMS registers
566 * @hwparams0 - GHWPARAMS0
567 * @hwparams1 - GHWPARAMS1
568 * @hwparams2 - GHWPARAMS2
569 * @hwparams3 - GHWPARAMS3
570 * @hwparams4 - GHWPARAMS4
571 * @hwparams5 - GHWPARAMS5
572 * @hwparams6 - GHWPARAMS6
573 * @hwparams7 - GHWPARAMS7
574 * @hwparams8 - GHWPARAMS8
576 struct dwc3_hwparams {
589 #define DWC3_MODE(n) ((n) & 0x7)
591 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
594 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
597 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
598 #define DWC3_NUM_EPS_MASK (0x3f << 12)
599 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
600 (DWC3_NUM_EPS_MASK)) >> 12)
601 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
602 (DWC3_NUM_IN_EPS_MASK)) >> 18)
605 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
607 struct dwc3_request {
608 struct usb_request request;
609 struct list_head list;
614 struct dwc3_trb *trb;
617 unsigned direction:1;
623 * struct dwc3_scratchpad_array - hibernation scratchpad array
624 * (format defined by hw)
626 struct dwc3_scratchpad_array {
627 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
631 * struct dwc3 - representation of our controller
632 * @ctrl_req: usb control request which is used for ep0
633 * @ep0_trb: trb which is used for the ctrl_req
634 * @ep0_bounce: bounce buffer for ep0
635 * @setup_buf: used while precessing STD USB requests
636 * @ctrl_req_addr: dma address of ctrl_req
637 * @ep0_trb: dma address of ep0_trb
638 * @ep0_usb_req: dummy req used while handling STD USB requests
639 * @ep0_bounce_addr: dma address of ep0_bounce
640 * @scratch_addr: dma address of scratchbuf
641 * @lock: for synchronizing
642 * @dev: pointer to our struct device
643 * @xhci: pointer to our xHCI child
644 * @event_buffer_list: a list of event buffers
645 * @gadget: device side representation of the peripheral controller
646 * @gadget_driver: pointer to the gadget driver
647 * @regs: base address for our registers
648 * @regs_size: address space size
649 * @nr_scratch: number of scratch buffers
650 * @num_event_buffers: calculated number of event buffers
651 * @u1u2: only used on revisions <1.83a for workaround
652 * @maximum_speed: maximum speed requested (mainly for testing purposes)
653 * @revision: revision register contents
654 * @dr_mode: requested mode of operation
655 * @dcfg: saved contents of DCFG register
656 * @gctl: saved contents of GCTL register
657 * @isoch_delay: wValue from Set Isochronous Delay request;
658 * @u2sel: parameter from Set SEL request.
659 * @u2pel: parameter from Set SEL request.
660 * @u1sel: parameter from Set SEL request.
661 * @u1pel: parameter from Set SEL request.
662 * @num_out_eps: number of out endpoints
663 * @num_in_eps: number of in endpoints
664 * @ep0_next_event: hold the next expected event
665 * @ep0state: state of endpoint zero
666 * @link_state: link state
667 * @speed: device speed (super, high, full, low)
668 * @mem: points to start of memory which is used for this struct.
669 * @hwparams: copy of hwparams registers
670 * @root: debugfs root folder pointer
671 * @regset: debugfs pointer to regdump file
672 * @test_mode: true when we're entering a USB test mode
673 * @test_mode_nr: test feature selector
674 * @lpm_nyet_threshold: LPM NYET response threshold
675 * @hird_threshold: HIRD threshold
676 * @delayed_status: true when gadget driver asks for delayed status
677 * @ep0_bounced: true when we used bounce buffer
678 * @ep0_expect_in: true when we expect a DATA IN transfer
679 * @has_hibernation: true when dwc3 was configured with Hibernation
680 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
681 * there's now way for software to detect this in runtime.
682 * @is_utmi_l1_suspend: the core asserts output signal
684 * 1 - utmi_l1_suspend_n
685 * @is_selfpowered: true when we are selfpowered
686 * @is_fpga: true when we are using the FPGA board
687 * @needs_fifo_resize: not all users might want fifo resizing, flag it
688 * @pullups_connected: true when Run/Stop bit is set
689 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
690 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
691 * @start_config_issued: true when StartConfig command has been issued
692 * @three_stage_setup: set if we perform a three phase setup
693 * @disable_scramble_quirk: set if we enable the disable scramble quirk
694 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
695 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
696 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
697 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
698 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
699 * @lfps_filter_quirk: set if we enable LFPS filter quirk
700 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
701 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
702 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
703 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
704 * @tx_de_emphasis: Tx de-emphasis value
705 * 0 - -6dB de-emphasis
706 * 1 - -3.5dB de-emphasis
709 * @index: index of _this_ controller
710 * @list: to maintain the list of dwc3 controllers
713 struct usb_ctrlrequest *ctrl_req;
714 struct dwc3_trb *ep0_trb;
718 dma_addr_t ctrl_req_addr;
719 dma_addr_t ep0_trb_addr;
720 dma_addr_t ep0_bounce_addr;
721 dma_addr_t scratch_addr;
722 struct dwc3_request ep0_usb_req;
727 #if defined(__UBOOT__) && CONFIG_IS_ENABLED(DM_USB)
733 struct platform_device *xhci;
734 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
736 struct dwc3_event_buffer **ev_buffs;
737 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
739 struct usb_gadget gadget;
740 struct usb_gadget_driver *gadget_driver;
745 enum usb_dr_mode dr_mode;
747 /* used for suspend/resume */
752 u32 num_event_buffers;
757 #define DWC3_REVISION_173A 0x5533173a
758 #define DWC3_REVISION_175A 0x5533175a
759 #define DWC3_REVISION_180A 0x5533180a
760 #define DWC3_REVISION_183A 0x5533183a
761 #define DWC3_REVISION_185A 0x5533185a
762 #define DWC3_REVISION_187A 0x5533187a
763 #define DWC3_REVISION_188A 0x5533188a
764 #define DWC3_REVISION_190A 0x5533190a
765 #define DWC3_REVISION_194A 0x5533194a
766 #define DWC3_REVISION_200A 0x5533200a
767 #define DWC3_REVISION_202A 0x5533202a
768 #define DWC3_REVISION_210A 0x5533210a
769 #define DWC3_REVISION_220A 0x5533220a
770 #define DWC3_REVISION_230A 0x5533230a
771 #define DWC3_REVISION_240A 0x5533240a
772 #define DWC3_REVISION_250A 0x5533250a
773 #define DWC3_REVISION_260A 0x5533260a
774 #define DWC3_REVISION_270A 0x5533270a
775 #define DWC3_REVISION_280A 0x5533280a
777 enum dwc3_ep0_next ep0_next_event;
778 enum dwc3_ep0_state ep0state;
779 enum dwc3_link_state link_state;
794 struct dwc3_hwparams hwparams;
796 struct debugfs_regset32 *regset;
800 u8 lpm_nyet_threshold;
803 unsigned delayed_status:1;
804 unsigned ep0_bounced:1;
805 unsigned ep0_expect_in:1;
806 unsigned has_hibernation:1;
807 unsigned has_lpm_erratum:1;
808 unsigned is_utmi_l1_suspend:1;
809 unsigned is_selfpowered:1;
811 unsigned needs_fifo_resize:1;
812 unsigned pullups_connected:1;
813 unsigned resize_fifos:1;
814 unsigned setup_packet_pending:1;
815 unsigned start_config_issued:1;
816 unsigned three_stage_setup:1;
818 unsigned disable_scramble_quirk:1;
819 unsigned u2exit_lfps_quirk:1;
820 unsigned u2ss_inp3_quirk:1;
821 unsigned req_p1p2p3_quirk:1;
822 unsigned del_p1p2p3_quirk:1;
823 unsigned del_phy_power_chg_quirk:1;
824 unsigned lfps_filter_quirk:1;
825 unsigned rx_detect_poll_quirk:1;
826 unsigned dis_u3_susphy_quirk:1;
827 unsigned dis_u2_susphy_quirk:1;
829 unsigned tx_de_emphasis_quirk:1;
830 unsigned tx_de_emphasis:2;
832 struct list_head list;
835 /* -------------------------------------------------------------------------- */
837 /* -------------------------------------------------------------------------- */
839 struct dwc3_event_type {
845 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
846 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
847 #define DWC3_DEPEVT_XFERNOTREADY 0x03
848 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
849 #define DWC3_DEPEVT_STREAMEVT 0x06
850 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
853 * dwc3_ep_event_string - returns event name
854 * @event: then event code
856 static inline const char *dwc3_ep_event_string(u8 event)
859 case DWC3_DEPEVT_XFERCOMPLETE:
860 return "Transfer Complete";
861 case DWC3_DEPEVT_XFERINPROGRESS:
862 return "Transfer In-Progress";
863 case DWC3_DEPEVT_XFERNOTREADY:
864 return "Transfer Not Ready";
865 case DWC3_DEPEVT_RXTXFIFOEVT:
867 case DWC3_DEPEVT_STREAMEVT:
869 case DWC3_DEPEVT_EPCMDCMPLT:
870 return "Endpoint Command Complete";
877 * struct dwc3_event_depvt - Device Endpoint Events
878 * @one_bit: indicates this is an endpoint event (not used)
879 * @endpoint_number: number of the endpoint
880 * @endpoint_event: The event we have:
882 * 0x01 - XferComplete
883 * 0x02 - XferInProgress
884 * 0x03 - XferNotReady
885 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
889 * @reserved11_10: Reserved, don't use.
890 * @status: Indicates the status of the event. Refer to databook for
892 * @parameters: Parameters of the current event. Refer to databook for
895 struct dwc3_event_depevt {
897 u32 endpoint_number:5;
898 u32 endpoint_event:4;
902 /* Within XferNotReady */
903 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
905 /* Within XferComplete */
906 #define DEPEVT_STATUS_BUSERR (1 << 0)
907 #define DEPEVT_STATUS_SHORT (1 << 1)
908 #define DEPEVT_STATUS_IOC (1 << 2)
909 #define DEPEVT_STATUS_LST (1 << 3)
911 /* Stream event only */
912 #define DEPEVT_STREAMEVT_FOUND 1
913 #define DEPEVT_STREAMEVT_NOTFOUND 2
915 /* Control-only Status */
916 #define DEPEVT_STATUS_CONTROL_DATA 1
917 #define DEPEVT_STATUS_CONTROL_STATUS 2
923 * struct dwc3_event_devt - Device Events
924 * @one_bit: indicates this is a non-endpoint event (not used)
925 * @device_event: indicates it's a device event. Should read as 0x00
926 * @type: indicates the type of device event.
939 * 12 - VndrDevTstRcved
940 * @reserved15_12: Reserved, not used
941 * @event_info: Information about this event
942 * @reserved31_25: Reserved, not used
944 struct dwc3_event_devt {
954 * struct dwc3_event_gevt - Other Core Events
955 * @one_bit: indicates this is a non-endpoint event (not used)
956 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
957 * @phy_port_number: self-explanatory
958 * @reserved31_12: Reserved, not used.
960 struct dwc3_event_gevt {
963 u32 phy_port_number:4;
964 u32 reserved31_12:20;
968 * union dwc3_event - representation of Event Buffer contents
969 * @raw: raw 32-bit event
970 * @type: the type of the event
971 * @depevt: Device Endpoint Event
972 * @devt: Device Event
973 * @gevt: Global Event
977 struct dwc3_event_type type;
978 struct dwc3_event_depevt depevt;
979 struct dwc3_event_devt devt;
980 struct dwc3_event_gevt gevt;
984 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
986 * @param2: third parameter
987 * @param1: second parameter
988 * @param0: first parameter
990 struct dwc3_gadget_ep_cmd_params {
997 * DWC3 Features to be used as Driver Data
1000 #define DWC3_HAS_PERIPHERAL BIT(0)
1001 #define DWC3_HAS_XHCI BIT(1)
1002 #define DWC3_HAS_OTG BIT(3)
1005 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
1006 void dwc3_of_parse(struct dwc3 *dwc);
1007 int dwc3_init(struct dwc3 *dwc);
1008 void dwc3_remove(struct dwc3 *dwc);
1010 static inline int dwc3_host_init(struct dwc3 *dwc)
1012 static inline void dwc3_host_exit(struct dwc3 *dwc)
1015 #ifdef CONFIG_USB_DWC3_GADGET
1016 int dwc3_gadget_init(struct dwc3 *dwc);
1017 void dwc3_gadget_exit(struct dwc3 *dwc);
1018 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1019 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1020 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1021 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1022 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1023 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1025 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1027 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1029 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1031 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1033 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1034 enum dwc3_link_state state)
1037 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1038 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1040 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1045 #endif /* __DRIVERS_USB_DWC3_CORE_H */