1 /* SPDX-License-Identifier: GPL-2.0 */
3 * core.h - DesignWare USB3 DRD Core Header
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #ifndef __DRIVERS_USB_DWC3_CORE_H
12 #define __DRIVERS_USB_DWC3_CORE_H
14 #include <linux/device.h>
15 #include <linux/spinlock.h>
16 #include <linux/mutex.h>
17 #include <linux/ioport.h>
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/debugfs.h>
23 #include <linux/wait.h>
24 #include <linux/workqueue.h>
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
28 #include <linux/usb/otg.h>
29 #include <linux/usb/role.h>
30 #include <linux/ulpi/interface.h>
32 #include <linux/phy/phy.h>
34 #include <linux/power_supply.h>
36 #define DWC3_MSG_MAX 500
38 /* Global constants */
39 #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
40 #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
41 #define DWC3_EP0_SETUP_SIZE 512
42 #define DWC3_ENDPOINTS_NUM 32
43 #define DWC3_XHCI_RESOURCES_NUM 2
44 #define DWC3_ISOC_MAX_RETRIES 5
46 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
47 #define DWC3_EVENT_BUFFERS_SIZE 4096
48 #define DWC3_EVENT_TYPE_MASK 0xfe
50 #define DWC3_EVENT_TYPE_DEV 0
51 #define DWC3_EVENT_TYPE_CARKIT 3
52 #define DWC3_EVENT_TYPE_I2C 4
54 #define DWC3_DEVICE_EVENT_DISCONNECT 0
55 #define DWC3_DEVICE_EVENT_RESET 1
56 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
57 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
58 #define DWC3_DEVICE_EVENT_WAKEUP 4
59 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
60 #define DWC3_DEVICE_EVENT_SUSPEND 6
61 #define DWC3_DEVICE_EVENT_SOF 7
62 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
63 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
64 #define DWC3_DEVICE_EVENT_OVERFLOW 11
66 /* Controller's role while using the OTG block */
67 #define DWC3_OTG_ROLE_IDLE 0
68 #define DWC3_OTG_ROLE_HOST 1
69 #define DWC3_OTG_ROLE_DEVICE 2
71 #define DWC3_GEVNTCOUNT_MASK 0xfffc
72 #define DWC3_GEVNTCOUNT_EHB BIT(31)
73 #define DWC3_GSNPSID_MASK 0xffff0000
74 #define DWC3_GSNPSREV_MASK 0xffff
75 #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16)
77 /* DWC3 registers memory space boundries */
78 #define DWC3_XHCI_REGS_START 0x0
79 #define DWC3_XHCI_REGS_END 0x7fff
80 #define DWC3_GLOBALS_REGS_START 0xc100
81 #define DWC3_GLOBALS_REGS_END 0xc6ff
82 #define DWC3_DEVICE_REGS_START 0xc700
83 #define DWC3_DEVICE_REGS_END 0xcbff
84 #define DWC3_OTG_REGS_START 0xcc00
85 #define DWC3_OTG_REGS_END 0xccff
87 #define DWC3_RTK_RTD_GLOBALS_REGS_START 0x8100
89 /* Global Registers */
90 #define DWC3_GSBUSCFG0 0xc100
91 #define DWC3_GSBUSCFG1 0xc104
92 #define DWC3_GTXTHRCFG 0xc108
93 #define DWC3_GRXTHRCFG 0xc10c
94 #define DWC3_GCTL 0xc110
95 #define DWC3_GEVTEN 0xc114
96 #define DWC3_GSTS 0xc118
97 #define DWC3_GUCTL1 0xc11c
98 #define DWC3_GSNPSID 0xc120
99 #define DWC3_GGPIO 0xc124
100 #define DWC3_GUID 0xc128
101 #define DWC3_GUCTL 0xc12c
102 #define DWC3_GBUSERRADDR0 0xc130
103 #define DWC3_GBUSERRADDR1 0xc134
104 #define DWC3_GPRTBIMAP0 0xc138
105 #define DWC3_GPRTBIMAP1 0xc13c
106 #define DWC3_GHWPARAMS0 0xc140
107 #define DWC3_GHWPARAMS1 0xc144
108 #define DWC3_GHWPARAMS2 0xc148
109 #define DWC3_GHWPARAMS3 0xc14c
110 #define DWC3_GHWPARAMS4 0xc150
111 #define DWC3_GHWPARAMS5 0xc154
112 #define DWC3_GHWPARAMS6 0xc158
113 #define DWC3_GHWPARAMS7 0xc15c
114 #define DWC3_GDBGFIFOSPACE 0xc160
115 #define DWC3_GDBGLTSSM 0xc164
116 #define DWC3_GDBGBMU 0xc16c
117 #define DWC3_GDBGLSPMUX 0xc170
118 #define DWC3_GDBGLSP 0xc174
119 #define DWC3_GDBGEPINFO0 0xc178
120 #define DWC3_GDBGEPINFO1 0xc17c
121 #define DWC3_GPRTBIMAP_HS0 0xc180
122 #define DWC3_GPRTBIMAP_HS1 0xc184
123 #define DWC3_GPRTBIMAP_FS0 0xc188
124 #define DWC3_GPRTBIMAP_FS1 0xc18c
125 #define DWC3_GUCTL2 0xc19c
127 #define DWC3_VER_NUMBER 0xc1a0
128 #define DWC3_VER_TYPE 0xc1a4
130 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
131 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
133 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
135 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
137 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
138 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
140 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
141 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
142 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
143 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
145 #define DWC3_GHWPARAMS8 0xc600
146 #define DWC3_GUCTL3 0xc60c
147 #define DWC3_GFLADJ 0xc630
148 #define DWC3_GHWPARAMS9 0xc6e0
150 /* Device Registers */
151 #define DWC3_DCFG 0xc700
152 #define DWC3_DCTL 0xc704
153 #define DWC3_DEVTEN 0xc708
154 #define DWC3_DSTS 0xc70c
155 #define DWC3_DGCMDPAR 0xc710
156 #define DWC3_DGCMD 0xc714
157 #define DWC3_DALEPENA 0xc720
158 #define DWC3_DCFG1 0xc740 /* DWC_usb32 only */
160 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
161 #define DWC3_DEPCMDPAR2 0x00
162 #define DWC3_DEPCMDPAR1 0x04
163 #define DWC3_DEPCMDPAR0 0x08
164 #define DWC3_DEPCMD 0x0c
166 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
169 #define DWC3_OCFG 0xcc00
170 #define DWC3_OCTL 0xcc04
171 #define DWC3_OEVT 0xcc08
172 #define DWC3_OEVTEN 0xcc0C
173 #define DWC3_OSTS 0xcc10
177 /* Global SoC Bus Configuration INCRx Register 0 */
178 #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
179 #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
180 #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
181 #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
182 #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
183 #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
184 #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
185 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
186 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
188 /* Global Debug LSP MUX Select */
189 #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
190 #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
191 #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
192 #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
194 /* Global Debug Queue/FIFO Space Available Register */
195 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
196 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
197 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
199 #define DWC3_TXFIFO 0
200 #define DWC3_RXFIFO 1
201 #define DWC3_TXREQQ 2
202 #define DWC3_RXREQQ 3
203 #define DWC3_RXINFOQ 4
204 #define DWC3_PSTATQ 5
205 #define DWC3_DESCFETCHQ 6
206 #define DWC3_EVENTQ 7
207 #define DWC3_AUXEVENTQ 8
209 /* Global RX Threshold Configuration Register */
210 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
211 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
212 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
214 /* Global RX Threshold Configuration Register for DWC_usb31 only */
215 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
216 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
217 #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
218 #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
219 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
220 #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
221 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
222 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
224 /* Global TX Threshold Configuration Register for DWC_usb31 only */
225 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
226 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
227 #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
228 #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
229 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
230 #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
231 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
232 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
234 /* Global Configuration Register */
235 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
236 #define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19)
237 #define DWC3_GCTL_U2RSTECN BIT(16)
238 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
239 #define DWC3_GCTL_CLK_BUS (0)
240 #define DWC3_GCTL_CLK_PIPE (1)
241 #define DWC3_GCTL_CLK_PIPEHALF (2)
242 #define DWC3_GCTL_CLK_MASK (3)
244 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
245 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
246 #define DWC3_GCTL_PRTCAP_HOST 1
247 #define DWC3_GCTL_PRTCAP_DEVICE 2
248 #define DWC3_GCTL_PRTCAP_OTG 3
250 #define DWC3_GCTL_CORESOFTRESET BIT(11)
251 #define DWC3_GCTL_SOFITPSYNC BIT(10)
252 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
253 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
254 #define DWC3_GCTL_DISSCRAMBLE BIT(3)
255 #define DWC3_GCTL_U2EXIT_LFPS BIT(2)
256 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
257 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
259 /* Global User Control Register */
260 #define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
262 /* Global User Control 1 Register */
263 #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
264 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
265 #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
266 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
267 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
268 #define DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT(16)
269 #define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
271 /* Global Status Register */
272 #define DWC3_GSTS_OTG_IP BIT(10)
273 #define DWC3_GSTS_BC_IP BIT(9)
274 #define DWC3_GSTS_ADP_IP BIT(8)
275 #define DWC3_GSTS_HOST_IP BIT(7)
276 #define DWC3_GSTS_DEVICE_IP BIT(6)
277 #define DWC3_GSTS_CSR_TIMEOUT BIT(5)
278 #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
279 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
280 #define DWC3_GSTS_CURMOD_DEVICE 0
281 #define DWC3_GSTS_CURMOD_HOST 1
283 /* Global USB2 PHY Configuration Register */
284 #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
285 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
286 #define DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV BIT(17)
287 #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
288 #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
289 #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
290 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
291 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
292 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
293 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
294 #define USBTRDTIM_UTMI_8_BIT 9
295 #define USBTRDTIM_UTMI_16_BIT 5
296 #define UTMI_PHYIF_16_BIT 1
297 #define UTMI_PHYIF_8_BIT 0
299 /* Global USB2 PHY Vendor Control Register */
300 #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
301 #define DWC3_GUSB2PHYACC_DONE BIT(24)
302 #define DWC3_GUSB2PHYACC_BUSY BIT(23)
303 #define DWC3_GUSB2PHYACC_WRITE BIT(22)
304 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
305 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
306 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
308 /* Global USB3 PIPE Control Register */
309 #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
310 #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
311 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
312 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
313 #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
314 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
315 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
316 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
317 #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
318 #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
319 #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
320 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
321 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
322 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
324 /* Global TX Fifo Size Register */
325 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
326 #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
327 #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
328 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
330 /* Global RX Fifo Size Register */
331 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
332 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
334 /* Global Event Size Registers */
335 #define DWC3_GEVNTSIZ_INTMASK BIT(31)
336 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
338 /* Global HWPARAMS0 Register */
339 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
340 #define DWC3_GHWPARAMS0_MODE_GADGET 0
341 #define DWC3_GHWPARAMS0_MODE_HOST 1
342 #define DWC3_GHWPARAMS0_MODE_DRD 2
343 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
344 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
345 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
346 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
347 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
349 /* Global HWPARAMS1 Register */
350 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
351 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
352 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
353 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
354 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
355 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
356 #define DWC3_GHWPARAMS1_ENDBC BIT(31)
358 /* Global HWPARAMS3 Register */
359 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
360 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
361 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
362 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
363 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
364 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
365 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
366 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
367 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
368 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
369 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
370 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
372 /* Global HWPARAMS4 Register */
373 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
374 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
376 /* Global HWPARAMS6 Register */
377 #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
378 #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
379 #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
380 #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
381 #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
382 #define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
385 #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
387 /* Global HWPARAMS7 Register */
388 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
389 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
391 /* Global HWPARAMS9 Register */
392 #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0)
393 #define DWC3_GHWPARAMS9_DEV_MST BIT(1)
395 /* Global Frame Length Adjustment Register */
396 #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
397 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
398 #define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8)
399 #define DWC3_GFLADJ_REFCLK_LPM_SEL BIT(23)
400 #define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24)
401 #define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31)
403 /* Global User Control Register*/
404 #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000
405 #define DWC3_GUCTL_REFCLKPER_SEL 22
407 /* Global User Control Register 2 */
408 #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
410 /* Global User Control Register 3 */
411 #define DWC3_GUCTL3_SPLITDISABLE BIT(14)
413 /* Device Configuration Register */
414 #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */
416 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
417 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
419 #define DWC3_DCFG_SPEED_MASK (7 << 0)
420 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
421 #define DWC3_DCFG_SUPERSPEED (4 << 0)
422 #define DWC3_DCFG_HIGHSPEED (0 << 0)
423 #define DWC3_DCFG_FULLSPEED BIT(0)
425 #define DWC3_DCFG_NUMP_SHIFT 17
426 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
427 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
428 #define DWC3_DCFG_LPM_CAP BIT(22)
429 #define DWC3_DCFG_IGNSTRMPP BIT(23)
431 /* Device Control Register */
432 #define DWC3_DCTL_RUN_STOP BIT(31)
433 #define DWC3_DCTL_CSFTRST BIT(30)
434 #define DWC3_DCTL_LSFTRST BIT(29)
436 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
437 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
439 #define DWC3_DCTL_APPL1RES BIT(23)
441 /* These apply for core versions 1.87a and earlier */
442 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
443 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
444 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
445 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
446 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
447 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
448 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
450 /* These apply for core versions 1.94a and later */
451 #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
453 #define DWC3_DCTL_KEEP_CONNECT BIT(19)
454 #define DWC3_DCTL_L1_HIBER_EN BIT(18)
455 #define DWC3_DCTL_CRS BIT(17)
456 #define DWC3_DCTL_CSS BIT(16)
458 #define DWC3_DCTL_INITU2ENA BIT(12)
459 #define DWC3_DCTL_ACCEPTU2ENA BIT(11)
460 #define DWC3_DCTL_INITU1ENA BIT(10)
461 #define DWC3_DCTL_ACCEPTU1ENA BIT(9)
462 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
464 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
465 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
467 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
468 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
469 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
470 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
471 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
472 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
473 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
475 /* Device Event Enable Register */
476 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
477 #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
478 #define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
479 #define DWC3_DEVTEN_ERRTICERREN BIT(9)
480 #define DWC3_DEVTEN_SOFEN BIT(7)
481 #define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6)
482 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
483 #define DWC3_DEVTEN_WKUPEVTEN BIT(4)
484 #define DWC3_DEVTEN_ULSTCNGEN BIT(3)
485 #define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
486 #define DWC3_DEVTEN_USBRSTEN BIT(1)
487 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
489 #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */
491 /* Device Status Register */
492 #define DWC3_DSTS_DCNRD BIT(29)
494 /* This applies for core versions 1.87a and earlier */
495 #define DWC3_DSTS_PWRUPREQ BIT(24)
497 /* These apply for core versions 1.94a and later */
498 #define DWC3_DSTS_RSS BIT(25)
499 #define DWC3_DSTS_SSS BIT(24)
501 #define DWC3_DSTS_COREIDLE BIT(23)
502 #define DWC3_DSTS_DEVCTRLHLT BIT(22)
504 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
505 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
507 #define DWC3_DSTS_RXFIFOEMPTY BIT(17)
509 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
510 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
512 #define DWC3_DSTS_CONNECTSPD (7 << 0)
514 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
515 #define DWC3_DSTS_SUPERSPEED (4 << 0)
516 #define DWC3_DSTS_HIGHSPEED (0 << 0)
517 #define DWC3_DSTS_FULLSPEED BIT(0)
519 /* Device Generic Command Register */
520 #define DWC3_DGCMD_SET_LMP 0x01
521 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
522 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
524 /* These apply for core versions 1.94a and later */
525 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
526 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
528 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
529 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
530 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
531 #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
532 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
533 #define DWC3_DGCMD_DEV_NOTIFICATION 0x07
535 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
536 #define DWC3_DGCMD_CMDACT BIT(10)
537 #define DWC3_DGCMD_CMDIOC BIT(8)
539 /* Device Generic Command Parameter Register */
540 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
541 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
542 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
543 #define DWC3_DGCMDPAR_TX_FIFO BIT(5)
544 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
545 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
546 #define DWC3_DGCMDPAR_DN_FUNC_WAKE BIT(0)
547 #define DWC3_DGCMDPAR_INTF_SEL(n) ((n) << 4)
549 /* Device Endpoint Command Register */
550 #define DWC3_DEPCMD_PARAM_SHIFT 16
551 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
552 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
553 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
554 #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
555 #define DWC3_DEPCMD_CLEARPENDIN BIT(11)
556 #define DWC3_DEPCMD_CMDACT BIT(10)
557 #define DWC3_DEPCMD_CMDIOC BIT(8)
559 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
560 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
561 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
562 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
563 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
564 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
565 /* This applies for core versions 1.90a and earlier */
566 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
567 /* This applies for core versions 1.94a and later */
568 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
569 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
570 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
572 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
574 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
575 #define DWC3_DALEPENA_EP(n) BIT(n)
577 /* DWC_usb32 DCFG1 config */
578 #define DWC3_DCFG1_DIS_MST_ENH BIT(1)
580 #define DWC3_DEPCMD_TYPE_CONTROL 0
581 #define DWC3_DEPCMD_TYPE_ISOC 1
582 #define DWC3_DEPCMD_TYPE_BULK 2
583 #define DWC3_DEPCMD_TYPE_INTR 3
585 #define DWC3_DEV_IMOD_COUNT_SHIFT 16
586 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
587 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
588 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
590 /* OTG Configuration Register */
591 #define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
592 #define DWC3_OCFG_HIBDISMASK BIT(4)
593 #define DWC3_OCFG_SFTRSTMASK BIT(3)
594 #define DWC3_OCFG_OTGVERSION BIT(2)
595 #define DWC3_OCFG_HNPCAP BIT(1)
596 #define DWC3_OCFG_SRPCAP BIT(0)
598 /* OTG CTL Register */
599 #define DWC3_OCTL_OTG3GOERR BIT(7)
600 #define DWC3_OCTL_PERIMODE BIT(6)
601 #define DWC3_OCTL_PRTPWRCTL BIT(5)
602 #define DWC3_OCTL_HNPREQ BIT(4)
603 #define DWC3_OCTL_SESREQ BIT(3)
604 #define DWC3_OCTL_TERMSELIDPULSE BIT(2)
605 #define DWC3_OCTL_DEVSETHNPEN BIT(1)
606 #define DWC3_OCTL_HSTSETHNPEN BIT(0)
608 /* OTG Event Register */
609 #define DWC3_OEVT_DEVICEMODE BIT(31)
610 #define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
611 #define DWC3_OEVT_DEVRUNSTPSET BIT(26)
612 #define DWC3_OEVT_HIBENTRY BIT(25)
613 #define DWC3_OEVT_CONIDSTSCHNG BIT(24)
614 #define DWC3_OEVT_HRRCONFNOTIF BIT(23)
615 #define DWC3_OEVT_HRRINITNOTIF BIT(22)
616 #define DWC3_OEVT_ADEVIDLE BIT(21)
617 #define DWC3_OEVT_ADEVBHOSTEND BIT(20)
618 #define DWC3_OEVT_ADEVHOST BIT(19)
619 #define DWC3_OEVT_ADEVHNPCHNG BIT(18)
620 #define DWC3_OEVT_ADEVSRPDET BIT(17)
621 #define DWC3_OEVT_ADEVSESSENDDET BIT(16)
622 #define DWC3_OEVT_BDEVBHOSTEND BIT(11)
623 #define DWC3_OEVT_BDEVHNPCHNG BIT(10)
624 #define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
625 #define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
626 #define DWC3_OEVT_BSESSVLD BIT(3)
627 #define DWC3_OEVT_HSTNEGSTS BIT(2)
628 #define DWC3_OEVT_SESREQSTS BIT(1)
629 #define DWC3_OEVT_ERROR BIT(0)
631 /* OTG Event Enable Register */
632 #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
633 #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
634 #define DWC3_OEVTEN_HIBENTRYEN BIT(25)
635 #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
636 #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
637 #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
638 #define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
639 #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
640 #define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
641 #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
642 #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
643 #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
644 #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
645 #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
646 #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
647 #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
649 /* OTG Status Register */
650 #define DWC3_OSTS_DEVRUNSTP BIT(13)
651 #define DWC3_OSTS_XHCIRUNSTP BIT(12)
652 #define DWC3_OSTS_PERIPHERALSTATE BIT(4)
653 #define DWC3_OSTS_XHCIPRTPOWER BIT(3)
654 #define DWC3_OSTS_BSESVLD BIT(2)
655 #define DWC3_OSTS_VBUSVLD BIT(1)
656 #define DWC3_OSTS_CONIDSTS BIT(0)
663 * struct dwc3_event_buffer - Software event buffer representation
665 * @cache: The buffer cache used in the threaded interrupt
666 * @length: size of this buffer
667 * @lpos: event offset
668 * @count: cache of last read event count register
669 * @flags: flags related to this event buffer
671 * @dwc: pointer to DWC controller
673 struct dwc3_event_buffer {
681 #define DWC3_EVENT_PENDING BIT(0)
688 #define DWC3_EP_FLAG_STALLED BIT(0)
689 #define DWC3_EP_FLAG_WEDGED BIT(1)
691 #define DWC3_EP_DIRECTION_TX true
692 #define DWC3_EP_DIRECTION_RX false
694 #define DWC3_TRB_NUM 256
697 * struct dwc3_ep - device side endpoint representation
698 * @endpoint: usb endpoint
699 * @cancelled_list: list of cancelled requests for this endpoint
700 * @pending_list: list of pending requests for this endpoint
701 * @started_list: list of started requests on this endpoint
702 * @regs: pointer to first endpoint register
703 * @trb_pool: array of transaction buffers
704 * @trb_pool_dma: dma address of @trb_pool
705 * @trb_enqueue: enqueue 'pointer' into TRB array
706 * @trb_dequeue: dequeue 'pointer' into TRB array
707 * @dwc: pointer to DWC controller
708 * @saved_state: ep state saved during hibernation
709 * @flags: endpoint flags (wedged, stalled, ...)
710 * @number: endpoint number (1 - 15)
711 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
712 * @resource_index: Resource transfer index
713 * @frame_number: set to the frame number we want this transfer to start (ISOC)
714 * @interval: the interval on which the ISOC transfer is started
715 * @name: a human readable name e.g. ep1out-bulk
716 * @direction: true for TX, false for RX
717 * @stream_capable: true when streams are enabled
718 * @combo_num: the test combination BIT[15:14] of the frame number to test
719 * isochronous START TRANSFER command failure workaround
720 * @start_cmd_status: the status of testing START TRANSFER command with
724 struct usb_ep endpoint;
725 struct list_head cancelled_list;
726 struct list_head pending_list;
727 struct list_head started_list;
731 struct dwc3_trb *trb_pool;
732 dma_addr_t trb_pool_dma;
737 #define DWC3_EP_ENABLED BIT(0)
738 #define DWC3_EP_STALL BIT(1)
739 #define DWC3_EP_WEDGE BIT(2)
740 #define DWC3_EP_TRANSFER_STARTED BIT(3)
741 #define DWC3_EP_END_TRANSFER_PENDING BIT(4)
742 #define DWC3_EP_PENDING_REQUEST BIT(5)
743 #define DWC3_EP_DELAY_START BIT(6)
744 #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7)
745 #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8)
746 #define DWC3_EP_FORCE_RESTART_STREAM BIT(9)
747 #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10)
748 #define DWC3_EP_PENDING_CLEAR_STALL BIT(11)
749 #define DWC3_EP_TXFIFO_RESIZED BIT(12)
750 #define DWC3_EP_DELAY_STOP BIT(13)
752 /* This last one is specific to EP0 */
753 #define DWC3_EP0_DIR_IN BIT(31)
756 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
757 * use a u8 type here. If anybody decides to increase number of TRBs to
758 * anything larger than 256 - I can't see why people would want to do
759 * this though - then this type needs to be changed.
761 * By using u8 types we ensure that our % operator when incrementing
762 * enqueue and dequeue get optimized away by the compiler.
775 unsigned direction:1;
776 unsigned stream_capable:1;
778 /* For isochronous START TRANSFER workaround only */
780 int start_cmd_status;
784 DWC3_PHY_UNKNOWN = 0,
790 DWC3_EP0_UNKNOWN = 0,
793 DWC3_EP0_NRDY_STATUS,
796 enum dwc3_ep0_state {
803 enum dwc3_link_state {
805 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
806 DWC3_LINK_STATE_U1 = 0x01,
807 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
808 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
809 DWC3_LINK_STATE_SS_DIS = 0x04,
810 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
811 DWC3_LINK_STATE_SS_INACT = 0x06,
812 DWC3_LINK_STATE_POLL = 0x07,
813 DWC3_LINK_STATE_RECOV = 0x08,
814 DWC3_LINK_STATE_HRESET = 0x09,
815 DWC3_LINK_STATE_CMPLY = 0x0a,
816 DWC3_LINK_STATE_LPBK = 0x0b,
817 DWC3_LINK_STATE_RESET = 0x0e,
818 DWC3_LINK_STATE_RESUME = 0x0f,
819 DWC3_LINK_STATE_MASK = 0x0f,
822 /* TRB Length, PCM and Status */
823 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
824 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
825 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
826 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
828 #define DWC3_TRBSTS_OK 0
829 #define DWC3_TRBSTS_MISSED_ISOC 1
830 #define DWC3_TRBSTS_SETUP_PENDING 2
831 #define DWC3_TRB_STS_XFER_IN_PROG 4
834 #define DWC3_TRB_CTRL_HWO BIT(0)
835 #define DWC3_TRB_CTRL_LST BIT(1)
836 #define DWC3_TRB_CTRL_CHN BIT(2)
837 #define DWC3_TRB_CTRL_CSP BIT(3)
838 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
839 #define DWC3_TRB_CTRL_ISP_IMI BIT(10)
840 #define DWC3_TRB_CTRL_IOC BIT(11)
841 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
842 #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
844 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
845 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
846 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
847 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
848 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
849 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
850 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
851 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
852 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
855 * struct dwc3_trb - transfer request block (hw format)
869 * struct dwc3_hwparams - copy of HWPARAMS registers
870 * @hwparams0: GHWPARAMS0
871 * @hwparams1: GHWPARAMS1
872 * @hwparams2: GHWPARAMS2
873 * @hwparams3: GHWPARAMS3
874 * @hwparams4: GHWPARAMS4
875 * @hwparams5: GHWPARAMS5
876 * @hwparams6: GHWPARAMS6
877 * @hwparams7: GHWPARAMS7
878 * @hwparams8: GHWPARAMS8
879 * @hwparams9: GHWPARAMS9
881 struct dwc3_hwparams {
895 #define DWC3_MODE(n) ((n) & 0x7)
898 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
901 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
902 #define DWC3_NUM_EPS_MASK (0x3f << 12)
903 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
904 (DWC3_NUM_EPS_MASK)) >> 12)
905 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
906 (DWC3_NUM_IN_EPS_MASK)) >> 18)
909 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
912 #define DWC3_MST_CAPABLE(p) (!!((p)->hwparams9 & \
913 DWC3_GHWPARAMS9_DEV_MST))
916 * struct dwc3_request - representation of a transfer request
917 * @request: struct usb_request to be transferred
918 * @list: a list_head used for request queueing
919 * @dep: struct dwc3_ep owning this request
920 * @sg: pointer to first incomplete sg
921 * @start_sg: pointer to the sg which should be queued next
922 * @num_pending_sgs: counter to pending sgs
923 * @num_queued_sgs: counter to the number of sgs which already got queued
924 * @remaining: amount of data remaining
925 * @status: internal dwc3 request status tracking
926 * @epnum: endpoint number to which this request refers
927 * @trb: pointer to struct dwc3_trb
928 * @trb_dma: DMA address of @trb
929 * @num_trbs: number of TRBs used by this request
930 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP
932 * @direction: IN or OUT direction flag
933 * @mapped: true when request has been dma-mapped
935 struct dwc3_request {
936 struct usb_request request;
937 struct list_head list;
939 struct scatterlist *sg;
940 struct scatterlist *start_sg;
942 unsigned int num_pending_sgs;
943 unsigned int num_queued_sgs;
944 unsigned int remaining;
947 #define DWC3_REQUEST_STATUS_QUEUED 0
948 #define DWC3_REQUEST_STATUS_STARTED 1
949 #define DWC3_REQUEST_STATUS_DISCONNECTED 2
950 #define DWC3_REQUEST_STATUS_DEQUEUED 3
951 #define DWC3_REQUEST_STATUS_STALLED 4
952 #define DWC3_REQUEST_STATUS_COMPLETED 5
953 #define DWC3_REQUEST_STATUS_UNKNOWN -1
956 struct dwc3_trb *trb;
959 unsigned int num_trbs;
961 unsigned int needs_extra_trb:1;
962 unsigned int direction:1;
963 unsigned int mapped:1;
967 * struct dwc3_scratchpad_array - hibernation scratchpad array
968 * (format defined by hw)
970 struct dwc3_scratchpad_array {
971 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
975 * struct dwc3 - representation of our controller
976 * @drd_work: workqueue used for role swapping
977 * @ep0_trb: trb which is used for the ctrl_req
978 * @bounce: address of bounce buffer
979 * @setup_buf: used while precessing STD USB requests
980 * @ep0_trb_addr: dma address of @ep0_trb
981 * @bounce_addr: dma address of @bounce
982 * @ep0_usb_req: dummy req used while handling STD USB requests
983 * @ep0_in_setup: one control transfer is completed and enter setup phase
984 * @lock: for synchronizing
985 * @mutex: for mode switching
986 * @dev: pointer to our struct device
987 * @sysdev: pointer to the DMA-capable device
988 * @xhci: pointer to our xHCI child
989 * @xhci_resources: struct resources for our @xhci child
990 * @ev_buf: struct dwc3_event_buffer pointer
991 * @eps: endpoint array
992 * @gadget: device side representation of the peripheral controller
993 * @gadget_driver: pointer to the gadget driver
994 * @bus_clk: clock for accessing the registers
995 * @ref_clk: reference clock
996 * @susp_clk: clock used when the SS phy is in low power (S3) state
997 * @reset: reset control
998 * @regs: base address for our registers
999 * @regs_size: address space size
1000 * @fladj: frame length adjustment
1001 * @ref_clk_per: reference clock period configuration
1002 * @irq_gadget: peripheral controller's IRQ number
1003 * @otg_irq: IRQ number for OTG IRQs
1004 * @current_otg_role: current role of operation while using the OTG block
1005 * @desired_otg_role: desired role of operation while using the OTG block
1006 * @otg_restart_host: flag that OTG controller needs to restart host
1007 * @u1u2: only used on revisions <1.83a for workaround
1008 * @maximum_speed: maximum speed requested (mainly for testing purposes)
1009 * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count
1010 * @gadget_max_speed: maximum gadget speed requested
1011 * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling
1012 * rate and lane count.
1013 * @ip: controller's ID
1014 * @revision: controller's version of an IP
1015 * @version_type: VERSIONTYPE register contents, a sub release of a revision
1016 * @dr_mode: requested mode of operation
1017 * @current_dr_role: current role of operation when in dual-role mode
1018 * @desired_dr_role: desired role of operation when in dual-role mode
1019 * @edev: extcon handle
1020 * @edev_nb: extcon notifier
1021 * @hsphy_mode: UTMI phy mode, one of following:
1022 * - USBPHY_INTERFACE_MODE_UTMI
1023 * - USBPHY_INTERFACE_MODE_UTMIW
1024 * @role_sw: usb_role_switch handle
1025 * @role_switch_default_mode: default operation mode of controller while
1026 * usb role is USB_ROLE_NONE.
1027 * @usb_psy: pointer to power supply interface.
1028 * @usb2_phy: pointer to USB2 PHY
1029 * @usb3_phy: pointer to USB3 PHY
1030 * @usb2_generic_phy: pointer to USB2 PHY
1031 * @usb3_generic_phy: pointer to USB3 PHY
1032 * @phys_ready: flag to indicate that PHYs are ready
1033 * @ulpi: pointer to ulpi interface
1034 * @ulpi_ready: flag to indicate that ULPI is initialized
1035 * @u2sel: parameter from Set SEL request.
1036 * @u2pel: parameter from Set SEL request.
1037 * @u1sel: parameter from Set SEL request.
1038 * @u1pel: parameter from Set SEL request.
1039 * @num_eps: number of endpoints
1040 * @ep0_next_event: hold the next expected event
1041 * @ep0state: state of endpoint zero
1042 * @link_state: link state
1043 * @speed: device speed (super, high, full, low)
1044 * @hwparams: copy of hwparams registers
1045 * @regset: debugfs pointer to regdump file
1046 * @dbg_lsp_select: current debug lsp mux register selection
1047 * @test_mode: true when we're entering a USB test mode
1048 * @test_mode_nr: test feature selector
1049 * @lpm_nyet_threshold: LPM NYET response threshold
1050 * @hird_threshold: HIRD threshold
1051 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
1052 * @rx_max_burst_prd: max periodic ESS receive burst size
1053 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
1054 * @tx_max_burst_prd: max periodic ESS transmit burst size
1055 * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
1056 * @clear_stall_protocol: endpoint number that requires a delayed status phase
1057 * @hsphy_interface: "utmi" or "ulpi"
1058 * @connected: true when we're connected to a host, false otherwise
1059 * @softconnect: true when gadget connect is called, false when disconnect runs
1060 * @delayed_status: true when gadget driver asks for delayed status
1061 * @ep0_bounced: true when we used bounce buffer
1062 * @ep0_expect_in: true when we expect a DATA IN transfer
1063 * @sysdev_is_parent: true when dwc3 device has a parent driver
1064 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
1065 * there's now way for software to detect this in runtime.
1066 * @is_utmi_l1_suspend: the core asserts output signal
1068 * 1 - utmi_l1_suspend_n
1069 * @is_fpga: true when we are using the FPGA board
1070 * @pending_events: true when we have pending IRQs to be handled
1071 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
1072 * @pullups_connected: true when Run/Stop bit is set
1073 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
1074 * @three_stage_setup: set if we perform a three phase setup
1075 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
1076 * not needed for DWC_usb31 version 1.70a-ea06 and below
1077 * @usb3_lpm_capable: set if hadrware supports Link Power Management
1078 * @usb2_lpm_disable: set to disable usb2 lpm for host
1079 * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget
1080 * @disable_scramble_quirk: set if we enable the disable scramble quirk
1081 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1082 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
1083 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
1084 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
1085 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
1086 * @lfps_filter_quirk: set if we enable LFPS filter quirk
1087 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
1088 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
1089 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1090 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
1091 * disabling the suspend signal to the PHY.
1092 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1093 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
1094 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
1095 * @async_callbacks: if set, indicate that async callbacks will be used.
1097 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
1098 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
1099 * provide a free-running PHY clock.
1100 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
1102 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1103 * check during HS transmit.
1104 * @resume_hs_terminations: Set if we enable quirk for fixing improper crc
1105 * generation after resume from suspend.
1106 * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
1107 * VBUS with an external supply.
1108 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1109 * instances in park mode.
1110 * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed
1111 * instances in park mode.
1112 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1113 * @tx_de_emphasis: Tx de-emphasis value
1114 * 0 - -6dB de-emphasis
1115 * 1 - -3.5dB de-emphasis
1116 * 2 - No de-emphasis
1118 * @dis_metastability_quirk: set to disable metastability quirk.
1119 * @dis_split_quirk: set to disable split boundary.
1120 * @wakeup_configured: set if the device is configured for remote wakeup.
1121 * @suspended: set to track suspend event due to U3/L2.
1122 * @imod_interval: set the interrupt moderation interval in 250ns
1123 * increments or 0 to disable.
1124 * @max_cfg_eps: current max number of IN eps used across all USB configs.
1125 * @last_fifo_depth: last fifo depth used to determine next fifo ram start
1127 * @num_ep_resized: carries the current number endpoints which have had its tx
1129 * @debug_root: root debugfs directory for this device to put its files in.
1132 struct work_struct drd_work;
1133 struct dwc3_trb *ep0_trb;
1136 dma_addr_t ep0_trb_addr;
1137 dma_addr_t bounce_addr;
1138 struct dwc3_request ep0_usb_req;
1139 struct completion ep0_in_setup;
1144 /* mode switching lock */
1148 struct device *sysdev;
1150 struct platform_device *xhci;
1151 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1153 struct dwc3_event_buffer *ev_buf;
1154 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1156 struct usb_gadget *gadget;
1157 struct usb_gadget_driver *gadget_driver;
1159 struct clk *bus_clk;
1160 struct clk *ref_clk;
1161 struct clk *susp_clk;
1163 struct reset_control *reset;
1165 struct usb_phy *usb2_phy;
1166 struct usb_phy *usb3_phy;
1168 struct phy *usb2_generic_phy;
1169 struct phy *usb3_generic_phy;
1179 enum usb_dr_mode dr_mode;
1180 u32 current_dr_role;
1181 u32 desired_dr_role;
1182 struct extcon_dev *edev;
1183 struct notifier_block edev_nb;
1184 enum usb_phy_interface hsphy_mode;
1185 struct usb_role_switch *role_sw;
1186 enum usb_dr_mode role_switch_default_mode;
1188 struct power_supply *usb_psy;
1194 u32 current_otg_role;
1195 u32 desired_otg_role;
1196 bool otg_restart_host;
1199 u32 gadget_max_speed;
1200 enum usb_ssp_rate max_ssp_rate;
1201 enum usb_ssp_rate gadget_ssp_rate;
1205 #define DWC3_IP 0x5533
1206 #define DWC31_IP 0x3331
1207 #define DWC32_IP 0x3332
1211 #define DWC3_REVISION_ANY 0x0
1212 #define DWC3_REVISION_173A 0x5533173a
1213 #define DWC3_REVISION_175A 0x5533175a
1214 #define DWC3_REVISION_180A 0x5533180a
1215 #define DWC3_REVISION_183A 0x5533183a
1216 #define DWC3_REVISION_185A 0x5533185a
1217 #define DWC3_REVISION_187A 0x5533187a
1218 #define DWC3_REVISION_188A 0x5533188a
1219 #define DWC3_REVISION_190A 0x5533190a
1220 #define DWC3_REVISION_194A 0x5533194a
1221 #define DWC3_REVISION_200A 0x5533200a
1222 #define DWC3_REVISION_202A 0x5533202a
1223 #define DWC3_REVISION_210A 0x5533210a
1224 #define DWC3_REVISION_220A 0x5533220a
1225 #define DWC3_REVISION_230A 0x5533230a
1226 #define DWC3_REVISION_240A 0x5533240a
1227 #define DWC3_REVISION_250A 0x5533250a
1228 #define DWC3_REVISION_260A 0x5533260a
1229 #define DWC3_REVISION_270A 0x5533270a
1230 #define DWC3_REVISION_280A 0x5533280a
1231 #define DWC3_REVISION_290A 0x5533290a
1232 #define DWC3_REVISION_300A 0x5533300a
1233 #define DWC3_REVISION_310A 0x5533310a
1234 #define DWC3_REVISION_330A 0x5533330a
1236 #define DWC31_REVISION_ANY 0x0
1237 #define DWC31_REVISION_110A 0x3131302a
1238 #define DWC31_REVISION_120A 0x3132302a
1239 #define DWC31_REVISION_160A 0x3136302a
1240 #define DWC31_REVISION_170A 0x3137302a
1241 #define DWC31_REVISION_180A 0x3138302a
1242 #define DWC31_REVISION_190A 0x3139302a
1244 #define DWC32_REVISION_ANY 0x0
1245 #define DWC32_REVISION_100A 0x3130302a
1249 #define DWC31_VERSIONTYPE_ANY 0x0
1250 #define DWC31_VERSIONTYPE_EA01 0x65613031
1251 #define DWC31_VERSIONTYPE_EA02 0x65613032
1252 #define DWC31_VERSIONTYPE_EA03 0x65613033
1253 #define DWC31_VERSIONTYPE_EA04 0x65613034
1254 #define DWC31_VERSIONTYPE_EA05 0x65613035
1255 #define DWC31_VERSIONTYPE_EA06 0x65613036
1257 enum dwc3_ep0_next ep0_next_event;
1258 enum dwc3_ep0_state ep0state;
1259 enum dwc3_link_state link_state;
1270 struct dwc3_hwparams hwparams;
1271 struct debugfs_regset32 *regset;
1277 u8 lpm_nyet_threshold;
1279 u8 rx_thr_num_pkt_prd;
1280 u8 rx_max_burst_prd;
1281 u8 tx_thr_num_pkt_prd;
1282 u8 tx_max_burst_prd;
1283 u8 tx_fifo_resize_max_num;
1284 u8 clear_stall_protocol;
1286 const char *hsphy_interface;
1288 unsigned connected:1;
1289 unsigned softconnect:1;
1290 unsigned delayed_status:1;
1291 unsigned ep0_bounced:1;
1292 unsigned ep0_expect_in:1;
1293 unsigned sysdev_is_parent:1;
1294 unsigned has_lpm_erratum:1;
1295 unsigned is_utmi_l1_suspend:1;
1297 unsigned pending_events:1;
1298 unsigned do_fifo_resize:1;
1299 unsigned pullups_connected:1;
1300 unsigned setup_packet_pending:1;
1301 unsigned three_stage_setup:1;
1302 unsigned dis_start_transfer_quirk:1;
1303 unsigned usb3_lpm_capable:1;
1304 unsigned usb2_lpm_disable:1;
1305 unsigned usb2_gadget_lpm_disable:1;
1307 unsigned disable_scramble_quirk:1;
1308 unsigned u2exit_lfps_quirk:1;
1309 unsigned u2ss_inp3_quirk:1;
1310 unsigned req_p1p2p3_quirk:1;
1311 unsigned del_p1p2p3_quirk:1;
1312 unsigned del_phy_power_chg_quirk:1;
1313 unsigned lfps_filter_quirk:1;
1314 unsigned rx_detect_poll_quirk:1;
1315 unsigned dis_u3_susphy_quirk:1;
1316 unsigned dis_u2_susphy_quirk:1;
1317 unsigned dis_enblslpm_quirk:1;
1318 unsigned dis_u1_entry_quirk:1;
1319 unsigned dis_u2_entry_quirk:1;
1320 unsigned dis_rxdet_inp3_quirk:1;
1321 unsigned dis_u2_freeclk_exists_quirk:1;
1322 unsigned dis_del_phy_power_chg_quirk:1;
1323 unsigned dis_tx_ipgap_linecheck_quirk:1;
1324 unsigned resume_hs_terminations:1;
1325 unsigned ulpi_ext_vbus_drv:1;
1326 unsigned parkmode_disable_ss_quirk:1;
1327 unsigned parkmode_disable_hs_quirk:1;
1328 unsigned gfladj_refclk_lpm_sel:1;
1330 unsigned tx_de_emphasis_quirk:1;
1331 unsigned tx_de_emphasis:2;
1333 unsigned dis_metastability_quirk:1;
1335 unsigned dis_split_quirk:1;
1336 unsigned async_callbacks:1;
1337 unsigned wakeup_configured:1;
1338 unsigned suspended:1;
1343 int last_fifo_depth;
1345 struct dentry *debug_root;
1348 #define INCRX_BURST_MODE 0
1349 #define INCRX_UNDEF_LENGTH_BURST_MODE 1
1351 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1353 /* -------------------------------------------------------------------------- */
1355 struct dwc3_event_type {
1358 u32 reserved8_31:24;
1361 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1362 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1363 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1364 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1365 #define DWC3_DEPEVT_STREAMEVT 0x06
1366 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1369 * struct dwc3_event_depevt - Device Endpoint Events
1370 * @one_bit: indicates this is an endpoint event (not used)
1371 * @endpoint_number: number of the endpoint
1372 * @endpoint_event: The event we have:
1374 * 0x01 - XferComplete
1375 * 0x02 - XferInProgress
1376 * 0x03 - XferNotReady
1377 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1381 * @reserved11_10: Reserved, don't use.
1382 * @status: Indicates the status of the event. Refer to databook for
1384 * @parameters: Parameters of the current event. Refer to databook for
1387 struct dwc3_event_depevt {
1389 u32 endpoint_number:5;
1390 u32 endpoint_event:4;
1391 u32 reserved11_10:2;
1394 /* Within XferNotReady */
1395 #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1397 /* Within XferComplete or XferInProgress */
1398 #define DEPEVT_STATUS_BUSERR BIT(0)
1399 #define DEPEVT_STATUS_SHORT BIT(1)
1400 #define DEPEVT_STATUS_IOC BIT(2)
1401 #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */
1402 #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1404 /* Stream event only */
1405 #define DEPEVT_STREAMEVT_FOUND 1
1406 #define DEPEVT_STREAMEVT_NOTFOUND 2
1408 /* Stream event parameter */
1409 #define DEPEVT_STREAM_PRIME 0xfffe
1410 #define DEPEVT_STREAM_NOSTREAM 0x0
1412 /* Control-only Status */
1413 #define DEPEVT_STATUS_CONTROL_DATA 1
1414 #define DEPEVT_STATUS_CONTROL_STATUS 2
1415 #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1417 /* In response to Start Transfer */
1418 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1419 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1423 /* For Command Complete Events */
1424 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1428 * struct dwc3_event_devt - Device Events
1429 * @one_bit: indicates this is a non-endpoint event (not used)
1430 * @device_event: indicates it's a device event. Should read as 0x00
1431 * @type: indicates the type of device event.
1438 * 6 - Suspend (EOPF on revisions 2.10a and prior)
1444 * 12 - VndrDevTstRcved
1445 * @reserved15_12: Reserved, not used
1446 * @event_info: Information about this event
1447 * @reserved31_25: Reserved, not used
1449 struct dwc3_event_devt {
1453 u32 reserved15_12:4;
1455 u32 reserved31_25:7;
1459 * struct dwc3_event_gevt - Other Core Events
1460 * @one_bit: indicates this is a non-endpoint event (not used)
1461 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1462 * @phy_port_number: self-explanatory
1463 * @reserved31_12: Reserved, not used.
1465 struct dwc3_event_gevt {
1468 u32 phy_port_number:4;
1469 u32 reserved31_12:20;
1473 * union dwc3_event - representation of Event Buffer contents
1474 * @raw: raw 32-bit event
1475 * @type: the type of the event
1476 * @depevt: Device Endpoint Event
1477 * @devt: Device Event
1478 * @gevt: Global Event
1482 struct dwc3_event_type type;
1483 struct dwc3_event_depevt depevt;
1484 struct dwc3_event_devt devt;
1485 struct dwc3_event_gevt gevt;
1489 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1491 * @param2: third parameter
1492 * @param1: second parameter
1493 * @param0: first parameter
1495 struct dwc3_gadget_ep_cmd_params {
1502 * DWC3 Features to be used as Driver Data
1505 #define DWC3_HAS_PERIPHERAL BIT(0)
1506 #define DWC3_HAS_XHCI BIT(1)
1507 #define DWC3_HAS_OTG BIT(3)
1510 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1511 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1512 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1514 #define DWC3_IP_IS(_ip) \
1515 (dwc->ip == _ip##_IP)
1517 #define DWC3_VER_IS(_ip, _ver) \
1518 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1520 #define DWC3_VER_IS_PRIOR(_ip, _ver) \
1521 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1523 #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \
1524 (DWC3_IP_IS(_ip) && \
1525 dwc->revision >= _ip##_REVISION_##_from && \
1526 (!(_ip##_REVISION_##_to) || \
1527 dwc->revision <= _ip##_REVISION_##_to))
1529 #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \
1530 (DWC3_VER_IS(_ip, _ver) && \
1531 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \
1532 (!(_ip##_VERSIONTYPE_##_to) || \
1533 dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1536 * dwc3_mdwidth - get MDWIDTH value in bits
1537 * @dwc: pointer to our context structure
1539 * Return MDWIDTH configuration value in bits.
1541 static inline u32 dwc3_mdwidth(struct dwc3 *dwc)
1545 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1546 if (DWC3_IP_IS(DWC32))
1547 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
1552 bool dwc3_has_imod(struct dwc3 *dwc);
1554 int dwc3_event_buffers_setup(struct dwc3 *dwc);
1555 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1557 int dwc3_core_soft_reset(struct dwc3 *dwc);
1559 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1560 int dwc3_host_init(struct dwc3 *dwc);
1561 void dwc3_host_exit(struct dwc3 *dwc);
1563 static inline int dwc3_host_init(struct dwc3 *dwc)
1565 static inline void dwc3_host_exit(struct dwc3 *dwc)
1569 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1570 int dwc3_gadget_init(struct dwc3 *dwc);
1571 void dwc3_gadget_exit(struct dwc3 *dwc);
1572 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1573 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1574 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1575 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1576 struct dwc3_gadget_ep_cmd_params *params);
1577 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
1579 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
1580 void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status);
1582 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1584 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1586 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1588 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1590 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1591 enum dwc3_link_state state)
1594 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1595 struct dwc3_gadget_ep_cmd_params *params)
1597 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1600 static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
1604 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1605 int dwc3_drd_init(struct dwc3 *dwc);
1606 void dwc3_drd_exit(struct dwc3 *dwc);
1607 void dwc3_otg_init(struct dwc3 *dwc);
1608 void dwc3_otg_exit(struct dwc3 *dwc);
1609 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1610 void dwc3_otg_host_init(struct dwc3 *dwc);
1612 static inline int dwc3_drd_init(struct dwc3 *dwc)
1614 static inline void dwc3_drd_exit(struct dwc3 *dwc)
1616 static inline void dwc3_otg_init(struct dwc3 *dwc)
1618 static inline void dwc3_otg_exit(struct dwc3 *dwc)
1620 static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1622 static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1626 /* power management interface */
1627 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1628 int dwc3_gadget_suspend(struct dwc3 *dwc);
1629 int dwc3_gadget_resume(struct dwc3 *dwc);
1630 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1632 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1637 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1642 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1645 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1647 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1648 int dwc3_ulpi_init(struct dwc3 *dwc);
1649 void dwc3_ulpi_exit(struct dwc3 *dwc);
1651 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1653 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1657 #endif /* __DRIVERS_USB_DWC3_CORE_H */