1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
13 * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
19 #include <dwc3-uboot.h>
20 #include <asm/dma-mapping.h>
21 #include <dm/device_compat.h>
22 #include <dm/devres.h>
23 #include <linux/err.h>
24 #include <linux/ioport.h>
26 #include <generic-phy.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
34 #include "linux-compat.h"
36 static LIST_HEAD(dwc3_list);
37 /* -------------------------------------------------------------------------- */
39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
43 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
44 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
45 reg |= DWC3_GCTL_PRTCAPDIR(mode);
46 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
50 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
51 * @dwc: pointer to our context structure
53 static int dwc3_core_soft_reset(struct dwc3 *dwc)
57 /* Before Resetting PHY, put Core in Reset */
58 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
59 reg |= DWC3_GCTL_CORESOFTRESET;
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
62 /* Assert USB3 PHY reset */
63 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
64 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
65 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
67 /* Assert USB2 PHY reset */
68 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
69 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
70 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
74 /* Clear USB3 PHY reset */
75 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
76 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
77 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
79 /* Clear USB2 PHY reset */
80 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
81 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
82 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
86 /* After PHYs are stable we can take Core out of reset state */
87 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
88 reg &= ~DWC3_GCTL_CORESOFTRESET;
89 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
95 * dwc3_free_one_event_buffer - Frees one event buffer
96 * @dwc: Pointer to our controller context structure
97 * @evt: Pointer to event buffer to be freed
99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
100 struct dwc3_event_buffer *evt)
102 dma_free_coherent(evt->buf);
106 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
107 * @dwc: Pointer to our controller context structure
108 * @length: size of the event buffer
110 * Returns a pointer to the allocated event buffer structure on success
111 * otherwise ERR_PTR(errno).
113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
116 struct dwc3_event_buffer *evt;
118 evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
121 return ERR_PTR(-ENOMEM);
124 evt->length = length;
125 evt->buf = dma_alloc_coherent(length,
126 (unsigned long *)&evt->dma);
128 return ERR_PTR(-ENOMEM);
130 dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
136 * dwc3_free_event_buffers - frees all allocated event buffers
137 * @dwc: Pointer to our controller context structure
139 static void dwc3_free_event_buffers(struct dwc3 *dwc)
141 struct dwc3_event_buffer *evt;
144 for (i = 0; i < dwc->num_event_buffers; i++) {
145 evt = dwc->ev_buffs[i];
147 dwc3_free_one_event_buffer(dwc, evt);
152 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
153 * @dwc: pointer to our controller context structure
154 * @length: size of event buffer
156 * Returns 0 on success otherwise negative errno. In the error case, dwc
157 * may contain some buffers allocated but not all which were requested.
159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
164 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
165 dwc->num_event_buffers = num;
167 dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
168 sizeof(*dwc->ev_buffs) * num);
172 for (i = 0; i < num; i++) {
173 struct dwc3_event_buffer *evt;
175 evt = dwc3_alloc_one_event_buffer(dwc, length);
177 dev_err(dwc->dev, "can't allocate event buffer\n");
180 dwc->ev_buffs[i] = evt;
187 * dwc3_event_buffers_setup - setup our allocated event buffers
188 * @dwc: pointer to our controller context structure
190 * Returns 0 on success otherwise negative errno.
192 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
194 struct dwc3_event_buffer *evt;
197 for (n = 0; n < dwc->num_event_buffers; n++) {
198 evt = dwc->ev_buffs[n];
199 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
200 evt->buf, (unsigned long long) evt->dma,
205 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
206 lower_32_bits(evt->dma));
207 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
208 upper_32_bits(evt->dma));
209 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
210 DWC3_GEVNTSIZ_SIZE(evt->length));
211 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
217 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
219 struct dwc3_event_buffer *evt;
222 for (n = 0; n < dwc->num_event_buffers; n++) {
223 evt = dwc->ev_buffs[n];
227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
228 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
229 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
230 | DWC3_GEVNTSIZ_SIZE(0));
231 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
235 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
237 if (!dwc->has_hibernation)
240 if (!dwc->nr_scratch)
243 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
244 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
245 if (!dwc->scratchbuf)
251 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
253 dma_addr_t scratch_addr;
257 if (!dwc->has_hibernation)
260 if (!dwc->nr_scratch)
263 scratch_addr = dma_map_single(dwc->scratchbuf,
264 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
266 if (dma_mapping_error(dwc->dev, scratch_addr)) {
267 dev_err(dwc->dev, "failed to map scratch buffer\n");
272 dwc->scratch_addr = scratch_addr;
274 param = lower_32_bits(scratch_addr);
276 ret = dwc3_send_gadget_generic_command(dwc,
277 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
281 param = upper_32_bits(scratch_addr);
283 ret = dwc3_send_gadget_generic_command(dwc,
284 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
291 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
292 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
298 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
300 if (!dwc->has_hibernation)
303 if (!dwc->nr_scratch)
306 dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
307 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
308 kfree(dwc->scratchbuf);
311 static void dwc3_core_num_eps(struct dwc3 *dwc)
313 struct dwc3_hwparams *parms = &dwc->hwparams;
315 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
316 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
318 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
319 dwc->num_in_eps, dwc->num_out_eps);
322 static void dwc3_cache_hwparams(struct dwc3 *dwc)
324 struct dwc3_hwparams *parms = &dwc->hwparams;
326 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
327 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
328 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
329 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
330 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
331 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
332 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
333 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
334 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
338 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
339 * @dwc: Pointer to our controller context structure
341 static void dwc3_phy_setup(struct dwc3 *dwc)
345 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
348 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
349 * to '0' during coreConsultant configuration. So default value
350 * will be '0' when the core is reset. Application needs to set it
351 * to '1' after the core initialization is completed.
353 if (dwc->revision > DWC3_REVISION_194A)
354 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
356 if (dwc->u2ss_inp3_quirk)
357 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
359 if (dwc->req_p1p2p3_quirk)
360 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
362 if (dwc->del_p1p2p3_quirk)
363 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
365 if (dwc->del_phy_power_chg_quirk)
366 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
368 if (dwc->lfps_filter_quirk)
369 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
371 if (dwc->rx_detect_poll_quirk)
372 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
374 if (dwc->tx_de_emphasis_quirk)
375 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
377 if (dwc->dis_u3_susphy_quirk)
378 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
380 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
384 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
387 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
388 * '0' during coreConsultant configuration. So default value will
389 * be '0' when the core is reset. Application needs to set it to
390 * '1' after the core initialization is completed.
392 if (dwc->revision > DWC3_REVISION_194A)
393 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
395 if (dwc->dis_u2_susphy_quirk)
396 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
398 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
404 * dwc3_core_init - Low-level initialization of DWC3 Core
405 * @dwc: Pointer to our controller context structure
407 * Returns 0 on success otherwise negative errno.
409 static int dwc3_core_init(struct dwc3 *dwc)
411 unsigned long timeout;
412 u32 hwparams4 = dwc->hwparams.hwparams4;
416 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
417 /* This should read as U3 followed by revision number */
418 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
419 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
425 /* Handle USB2.0-only core configuration */
426 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
427 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
428 if (dwc->maximum_speed == USB_SPEED_SUPER)
429 dwc->maximum_speed = USB_SPEED_HIGH;
432 /* issue device SoftReset too */
434 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
436 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
437 if (!(reg & DWC3_DCTL_CSFTRST))
442 dev_err(dwc->dev, "Reset Timed Out\n");
449 ret = dwc3_core_soft_reset(dwc);
453 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
454 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
456 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
457 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
459 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
460 * issue which would cause xHCI compliance tests to fail.
462 * Because of that we cannot enable clock gating on such
467 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
470 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
471 dwc->dr_mode == USB_DR_MODE_OTG) &&
472 (dwc->revision >= DWC3_REVISION_210A &&
473 dwc->revision <= DWC3_REVISION_250A))
474 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
476 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
478 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
479 /* enable hibernation here */
480 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
483 * REVISIT Enabling this bit so that host-mode hibernation
484 * will work. Device-mode hibernation is not yet implemented.
486 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
489 dev_dbg(dwc->dev, "No power optimization available\n");
492 /* check if current dwc3 is on simulation board */
493 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
494 dev_dbg(dwc->dev, "it is on FPGA board\n");
498 if(dwc->disable_scramble_quirk && !dwc->is_fpga)
500 "disable_scramble cannot be used on non-FPGA builds\n");
502 if (dwc->disable_scramble_quirk && dwc->is_fpga)
503 reg |= DWC3_GCTL_DISSCRAMBLE;
505 reg &= ~DWC3_GCTL_DISSCRAMBLE;
507 if (dwc->u2exit_lfps_quirk)
508 reg |= DWC3_GCTL_U2EXIT_LFPS;
511 * WORKAROUND: DWC3 revisions <1.90a have a bug
512 * where the device can fail to connect at SuperSpeed
513 * and falls back to high-speed mode which causes
514 * the device to enter a Connect/Disconnect loop
516 if (dwc->revision < DWC3_REVISION_190A)
517 reg |= DWC3_GCTL_U2RSTECN;
519 dwc3_core_num_eps(dwc);
521 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
523 ret = dwc3_alloc_scratch_buffers(dwc);
527 ret = dwc3_setup_scratch_buffers(dwc);
534 dwc3_free_scratch_buffers(dwc);
540 static void dwc3_core_exit(struct dwc3 *dwc)
542 dwc3_free_scratch_buffers(dwc);
545 static int dwc3_core_init_mode(struct dwc3 *dwc)
549 switch (dwc->dr_mode) {
550 case USB_DR_MODE_PERIPHERAL:
551 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
552 ret = dwc3_gadget_init(dwc);
554 dev_err(dev, "failed to initialize gadget\n");
558 case USB_DR_MODE_HOST:
559 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
560 ret = dwc3_host_init(dwc);
562 dev_err(dev, "failed to initialize host\n");
566 case USB_DR_MODE_OTG:
567 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
568 ret = dwc3_host_init(dwc);
570 dev_err(dev, "failed to initialize host\n");
574 ret = dwc3_gadget_init(dwc);
576 dev_err(dev, "failed to initialize gadget\n");
581 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
588 static void dwc3_gadget_run(struct dwc3 *dwc)
590 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
594 static void dwc3_core_exit_mode(struct dwc3 *dwc)
596 switch (dwc->dr_mode) {
597 case USB_DR_MODE_PERIPHERAL:
598 dwc3_gadget_exit(dwc);
600 case USB_DR_MODE_HOST:
603 case USB_DR_MODE_OTG:
605 dwc3_gadget_exit(dwc);
613 * switch back to peripheral mode
614 * This enables the phy to enter idle and then, if enabled, suspend.
616 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
617 dwc3_gadget_run(dwc);
620 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
623 enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
626 /* Set dwc3 usb2 phy config */
627 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
629 switch (hsphy_mode) {
630 case USBPHY_INTERFACE_MODE_UTMI:
631 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
632 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
633 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
634 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
636 case USBPHY_INTERFACE_MODE_UTMIW:
637 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
638 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
639 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
640 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
646 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
649 #define DWC3_ALIGN_MASK (16 - 1)
652 * dwc3_uboot_init - dwc3 core uboot initialization code
653 * @dwc3_dev: struct dwc3_device containing initialization data
655 * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
656 * kernel driver). Pointer to dwc3_device should be passed containing
657 * base address and other initialization data. Returns '0' on success and
658 * a negative value on failure.
660 * Generally called from board_usb_init() implemented in board file.
662 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
665 struct device *dev = NULL;
666 u8 lpm_nyet_threshold;
674 mem = devm_kzalloc((struct udevice *)dev,
675 sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
679 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
682 dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
683 DWC3_GLOBALS_REGS_START);
685 /* default to highest possible threshold */
686 lpm_nyet_threshold = 0xff;
688 /* default to -3.5dB de-emphasis */
692 * default to assert utmi_sleep_n and use maximum allowed HIRD
693 * threshold value of 0b1100
697 dwc->maximum_speed = dwc3_dev->maximum_speed;
698 dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
699 if (dwc3_dev->lpm_nyet_threshold)
700 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
701 dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
702 if (dwc3_dev->hird_threshold)
703 hird_threshold = dwc3_dev->hird_threshold;
705 dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
706 dwc->dr_mode = dwc3_dev->dr_mode;
708 dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
709 dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
710 dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
711 dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
712 dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
713 dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
714 dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
715 dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
716 dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
717 dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
719 dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
720 if (dwc3_dev->tx_de_emphasis)
721 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
723 /* default to superspeed if no maximum_speed passed */
724 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
725 dwc->maximum_speed = USB_SPEED_SUPER;
727 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
728 dwc->tx_de_emphasis = tx_de_emphasis;
730 dwc->hird_threshold = hird_threshold
731 | (dwc->is_utmi_l1_suspend << 4);
733 dwc->index = dwc3_dev->index;
735 dwc3_cache_hwparams(dwc);
737 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
739 dev_err(dwc->dev, "failed to allocate event buffers\n");
743 if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
744 dwc->dr_mode = USB_DR_MODE_HOST;
745 else if (!IS_ENABLED(CONFIG_USB_HOST))
746 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
748 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
749 dwc->dr_mode = USB_DR_MODE_OTG;
751 ret = dwc3_core_init(dwc);
753 dev_err(dev, "failed to initialize core\n");
757 dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
759 ret = dwc3_event_buffers_setup(dwc);
761 dev_err(dwc->dev, "failed to setup event buffers\n");
765 ret = dwc3_core_init_mode(dwc);
769 list_add_tail(&dwc->list, &dwc3_list);
774 dwc3_event_buffers_cleanup(dwc);
780 dwc3_free_event_buffers(dwc);
786 * dwc3_uboot_exit - dwc3 core uboot cleanup code
787 * @index: index of this controller
789 * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
790 * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
791 * should be passed and should match with the index passed in
792 * dwc3_device during init.
794 * Generally called from board file.
796 void dwc3_uboot_exit(int index)
800 list_for_each_entry(dwc, &dwc3_list, list) {
801 if (dwc->index != index)
804 dwc3_core_exit_mode(dwc);
805 dwc3_event_buffers_cleanup(dwc);
806 dwc3_free_event_buffers(dwc);
808 list_del(&dwc->list);
815 * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
816 * @index: index of this controller
818 * Invokes dwc3 gadget interrupts.
820 * Generally called from board file.
822 void dwc3_uboot_handle_interrupt(int index)
824 struct dwc3 *dwc = NULL;
826 list_for_each_entry(dwc, &dwc3_list, list) {
827 if (dwc->index != index)
830 dwc3_gadget_uboot_handle_interrupt(dwc);
835 MODULE_ALIAS("platform:dwc3");
836 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
837 MODULE_LICENSE("GPL v2");
838 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
840 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
841 int dwc3_setup_phy(struct udevice *dev, struct phy **array, int *num_phys)
844 struct phy *usb_phys;
846 /* Return if no phy declared */
847 if (!dev_read_prop(dev, "phys", NULL))
849 count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
853 usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
858 for (i = 0; i < count; i++) {
859 ret = generic_phy_get_by_index(dev, i, &usb_phys[i]);
860 if (ret && ret != -ENOENT) {
861 pr_err("Failed to get USB PHY%d for %s\n",
867 for (i = 0; i < count; i++) {
868 ret = generic_phy_init(&usb_phys[i]);
870 pr_err("Can't init USB PHY%d for %s\n",
876 for (i = 0; i < count; i++) {
877 ret = generic_phy_power_on(&usb_phys[i]);
879 pr_err("Can't power USB PHY%d for %s\n",
881 goto phys_poweron_err;
890 for (i = count - 1; i >= 0; i--)
891 generic_phy_power_off(&usb_phys[i]);
893 for (i = 0; i < count; i++)
894 generic_phy_exit(&usb_phys[i]);
900 generic_phy_exit(&usb_phys[i]);
905 int dwc3_shutdown_phy(struct udevice *dev, struct phy *usb_phys, int num_phys)
909 for (i = 0; i < num_phys; i++) {
910 if (!generic_phy_valid(&usb_phys[i]))
913 ret = generic_phy_power_off(&usb_phys[i]);
914 ret |= generic_phy_exit(&usb_phys[i]);
916 pr_err("Can't shutdown USB PHY%d for %s\n",
925 #if CONFIG_IS_ENABLED(DM_USB)
926 void dwc3_of_parse(struct dwc3 *dwc)
929 struct udevice *dev = dwc->dev;
930 u8 lpm_nyet_threshold;
934 /* default to highest possible threshold */
935 lpm_nyet_threshold = 0xff;
937 /* default to -3.5dB de-emphasis */
941 * default to assert utmi_sleep_n and use maximum allowed HIRD
942 * threshold value of 0b1100
946 dwc->has_lpm_erratum = dev_read_bool(dev,
947 "snps,has-lpm-erratum");
948 tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
950 lpm_nyet_threshold = *tmp;
952 dwc->is_utmi_l1_suspend = dev_read_bool(dev,
953 "snps,is-utmi-l1-suspend");
954 tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
956 hird_threshold = *tmp;
958 dwc->disable_scramble_quirk = dev_read_bool(dev,
959 "snps,disable_scramble_quirk");
960 dwc->u2exit_lfps_quirk = dev_read_bool(dev,
961 "snps,u2exit_lfps_quirk");
962 dwc->u2ss_inp3_quirk = dev_read_bool(dev,
963 "snps,u2ss_inp3_quirk");
964 dwc->req_p1p2p3_quirk = dev_read_bool(dev,
965 "snps,req_p1p2p3_quirk");
966 dwc->del_p1p2p3_quirk = dev_read_bool(dev,
967 "snps,del_p1p2p3_quirk");
968 dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
969 "snps,del_phy_power_chg_quirk");
970 dwc->lfps_filter_quirk = dev_read_bool(dev,
971 "snps,lfps_filter_quirk");
972 dwc->rx_detect_poll_quirk = dev_read_bool(dev,
973 "snps,rx_detect_poll_quirk");
974 dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
975 "snps,dis_u3_susphy_quirk");
976 dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
977 "snps,dis_u2_susphy_quirk");
978 dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
979 "snps,tx_de_emphasis_quirk");
980 tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
982 tx_de_emphasis = *tmp;
984 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
985 dwc->tx_de_emphasis = tx_de_emphasis;
987 dwc->hird_threshold = hird_threshold
988 | (dwc->is_utmi_l1_suspend << 4);
991 int dwc3_init(struct dwc3 *dwc)
995 dwc3_cache_hwparams(dwc);
997 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
999 dev_err(dwc->dev, "failed to allocate event buffers\n");
1003 ret = dwc3_core_init(dwc);
1005 dev_err(dev, "failed to initialize core\n");
1009 ret = dwc3_event_buffers_setup(dwc);
1011 dev_err(dwc->dev, "failed to setup event buffers\n");
1015 ret = dwc3_core_init_mode(dwc);
1022 dwc3_event_buffers_cleanup(dwc);
1025 dwc3_core_exit(dwc);
1028 dwc3_free_event_buffers(dwc);
1033 void dwc3_remove(struct dwc3 *dwc)
1035 dwc3_core_exit_mode(dwc);
1036 dwc3_event_buffers_cleanup(dwc);
1037 dwc3_free_event_buffers(dwc);
1038 dwc3_core_exit(dwc);