1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
26 #include <linux/of_graph.h>
27 #include <linux/acpi.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/bitfield.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/of.h>
35 #include <linux/usb/otg.h>
43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
65 "Controller does not support host mode.\n");
68 mode = USB_DR_MODE_PERIPHERAL;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
73 "Controller does not support device mode.\n");
76 mode = USB_DR_MODE_HOST;
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
93 mode = USB_DR_MODE_PERIPHERAL;
96 if (mode != dwc->dr_mode) {
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
111 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
113 reg |= DWC3_GCTL_PRTCAPDIR(mode);
114 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
116 dwc->current_dr_role = mode;
119 static void __dwc3_set_mode(struct work_struct *work)
121 struct dwc3 *dwc = work_to_dwc(work);
126 mutex_lock(&dwc->mutex);
128 pm_runtime_get_sync(dwc->dev);
130 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
131 dwc3_otg_update(dwc, 0);
133 if (!dwc->desired_dr_role)
136 if (dwc->desired_dr_role == dwc->current_dr_role)
139 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
142 switch (dwc->current_dr_role) {
143 case DWC3_GCTL_PRTCAP_HOST:
146 case DWC3_GCTL_PRTCAP_DEVICE:
147 dwc3_gadget_exit(dwc);
148 dwc3_event_buffers_cleanup(dwc);
150 case DWC3_GCTL_PRTCAP_OTG:
152 spin_lock_irqsave(&dwc->lock, flags);
153 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
154 spin_unlock_irqrestore(&dwc->lock, flags);
155 dwc3_otg_update(dwc, 1);
161 /* For DRD host or device mode only */
162 if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
163 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
164 reg |= DWC3_GCTL_CORESOFTRESET;
165 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
168 * Wait for internal clocks to synchronized. DWC_usb31 and
169 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
170 * keep it consistent across different IPs, let's wait up to
171 * 100ms before clearing GCTL.CORESOFTRESET.
175 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
176 reg &= ~DWC3_GCTL_CORESOFTRESET;
177 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
180 spin_lock_irqsave(&dwc->lock, flags);
182 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
184 spin_unlock_irqrestore(&dwc->lock, flags);
186 switch (dwc->desired_dr_role) {
187 case DWC3_GCTL_PRTCAP_HOST:
188 ret = dwc3_host_init(dwc);
190 dev_err(dwc->dev, "failed to initialize host\n");
193 otg_set_vbus(dwc->usb2_phy->otg, true);
194 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
195 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
196 if (dwc->dis_split_quirk) {
197 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
198 reg |= DWC3_GUCTL3_SPLITDISABLE;
199 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
203 case DWC3_GCTL_PRTCAP_DEVICE:
204 dwc3_core_soft_reset(dwc);
206 dwc3_event_buffers_setup(dwc);
209 otg_set_vbus(dwc->usb2_phy->otg, false);
210 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
211 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
213 ret = dwc3_gadget_init(dwc);
215 dev_err(dwc->dev, "failed to initialize peripheral\n");
217 case DWC3_GCTL_PRTCAP_OTG:
219 dwc3_otg_update(dwc, 0);
226 pm_runtime_mark_last_busy(dwc->dev);
227 pm_runtime_put_autosuspend(dwc->dev);
228 mutex_unlock(&dwc->mutex);
231 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
235 if (dwc->dr_mode != USB_DR_MODE_OTG)
238 spin_lock_irqsave(&dwc->lock, flags);
239 dwc->desired_dr_role = mode;
240 spin_unlock_irqrestore(&dwc->lock, flags);
242 queue_work(system_freezable_wq, &dwc->drd_work);
245 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
247 struct dwc3 *dwc = dep->dwc;
250 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
251 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
252 DWC3_GDBGFIFOSPACE_TYPE(type));
254 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
256 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
260 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
261 * @dwc: pointer to our context structure
263 int dwc3_core_soft_reset(struct dwc3 *dwc)
269 * We're resetting only the device side because, if we're in host mode,
270 * XHCI driver will reset the host block. If dwc3 was configured for
271 * host-only mode, then we can return early.
273 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
276 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
277 reg |= DWC3_DCTL_CSFTRST;
278 reg &= ~DWC3_DCTL_RUN_STOP;
279 dwc3_gadget_dctl_write_safe(dwc, reg);
282 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
283 * is cleared only after all the clocks are synchronized. This can
284 * take a little more than 50ms. Set the polling rate at 20ms
285 * for 10 times instead.
287 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
291 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
292 if (!(reg & DWC3_DCTL_CSFTRST))
295 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
301 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
306 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
307 * is cleared, we must wait at least 50ms before accessing the PHY
308 * domain (synchronization delay).
310 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
317 * dwc3_frame_length_adjustment - Adjusts frame length if required
318 * @dwc3: Pointer to our controller context structure
320 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
325 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
331 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
332 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
333 if (dft != dwc->fladj) {
334 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
335 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
336 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
341 * dwc3_ref_clk_period - Reference clock period configuration
342 * Default reference clock period depends on hardware
343 * configuration. For systems with reference clock that differs
344 * from the default, this will set clock period in DWC3_GUCTL
346 * @dwc: Pointer to our controller context structure
348 static void dwc3_ref_clk_period(struct dwc3 *dwc)
350 unsigned long period;
357 rate = clk_get_rate(dwc->ref_clk);
360 period = NSEC_PER_SEC / rate;
361 } else if (dwc->ref_clk_per) {
362 period = dwc->ref_clk_per;
363 rate = NSEC_PER_SEC / period;
368 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
369 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
370 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
371 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
373 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
377 * The calculation below is
379 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
381 * but rearranged for fixed-point arithmetic. The division must be
382 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
383 * neither does rate * period).
385 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
386 * nanoseconds of error caused by the truncation which happened during
387 * the division when calculating rate or period (whichever one was
388 * derived from the other). We first calculate the relative error, then
389 * scale it to units of 8 ppm.
391 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
395 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
397 decr = 480000000 / rate;
399 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
400 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
401 & ~DWC3_GFLADJ_240MHZDECR
402 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
403 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
404 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
405 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
406 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
410 * dwc3_free_one_event_buffer - Frees one event buffer
411 * @dwc: Pointer to our controller context structure
412 * @evt: Pointer to event buffer to be freed
414 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
415 struct dwc3_event_buffer *evt)
417 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
421 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
422 * @dwc: Pointer to our controller context structure
423 * @length: size of the event buffer
425 * Returns a pointer to the allocated event buffer structure on success
426 * otherwise ERR_PTR(errno).
428 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
431 struct dwc3_event_buffer *evt;
433 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
435 return ERR_PTR(-ENOMEM);
438 evt->length = length;
439 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
441 return ERR_PTR(-ENOMEM);
443 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
444 &evt->dma, GFP_KERNEL);
446 return ERR_PTR(-ENOMEM);
452 * dwc3_free_event_buffers - frees all allocated event buffers
453 * @dwc: Pointer to our controller context structure
455 static void dwc3_free_event_buffers(struct dwc3 *dwc)
457 struct dwc3_event_buffer *evt;
461 dwc3_free_one_event_buffer(dwc, evt);
465 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
466 * @dwc: pointer to our controller context structure
467 * @length: size of event buffer
469 * Returns 0 on success otherwise negative errno. In the error case, dwc
470 * may contain some buffers allocated but not all which were requested.
472 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
474 struct dwc3_event_buffer *evt;
476 evt = dwc3_alloc_one_event_buffer(dwc, length);
478 dev_err(dwc->dev, "can't allocate event buffer\n");
487 * dwc3_event_buffers_setup - setup our allocated event buffers
488 * @dwc: pointer to our controller context structure
490 * Returns 0 on success otherwise negative errno.
492 int dwc3_event_buffers_setup(struct dwc3 *dwc)
494 struct dwc3_event_buffer *evt;
498 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
499 lower_32_bits(evt->dma));
500 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
501 upper_32_bits(evt->dma));
502 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
503 DWC3_GEVNTSIZ_SIZE(evt->length));
504 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
509 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
511 struct dwc3_event_buffer *evt;
517 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
518 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
519 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
520 | DWC3_GEVNTSIZ_SIZE(0));
521 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
524 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
526 if (!dwc->has_hibernation)
529 if (!dwc->nr_scratch)
532 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
533 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
534 if (!dwc->scratchbuf)
540 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
542 dma_addr_t scratch_addr;
546 if (!dwc->has_hibernation)
549 if (!dwc->nr_scratch)
552 /* should never fall here */
553 if (!WARN_ON(dwc->scratchbuf))
556 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
557 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
559 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
560 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
565 dwc->scratch_addr = scratch_addr;
567 param = lower_32_bits(scratch_addr);
569 ret = dwc3_send_gadget_generic_command(dwc,
570 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
574 param = upper_32_bits(scratch_addr);
576 ret = dwc3_send_gadget_generic_command(dwc,
577 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
584 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
585 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
591 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
593 if (!dwc->has_hibernation)
596 if (!dwc->nr_scratch)
599 /* should never fall here */
600 if (!WARN_ON(dwc->scratchbuf))
603 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
604 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
605 kfree(dwc->scratchbuf);
608 static void dwc3_core_num_eps(struct dwc3 *dwc)
610 struct dwc3_hwparams *parms = &dwc->hwparams;
612 dwc->num_eps = DWC3_NUM_EPS(parms);
615 static void dwc3_cache_hwparams(struct dwc3 *dwc)
617 struct dwc3_hwparams *parms = &dwc->hwparams;
619 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
620 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
621 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
622 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
623 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
624 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
625 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
626 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
627 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
629 if (DWC3_IP_IS(DWC32))
630 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
633 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
638 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
640 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
641 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
642 dwc->hsphy_interface &&
643 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
644 ret = dwc3_ulpi_init(dwc);
650 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
651 * @dwc: Pointer to our controller context structure
653 * Returns 0 on success. The USB PHY interfaces are configured but not
654 * initialized. The PHY interfaces and the PHYs get initialized together with
655 * the core in dwc3_core_init.
657 static int dwc3_phy_setup(struct dwc3 *dwc)
659 unsigned int hw_mode;
662 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
664 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
667 * Make sure UX_EXIT_PX is cleared as that causes issues with some
668 * PHYs. Also, this bit is not supposed to be used in normal operation.
670 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
673 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
674 * to '0' during coreConsultant configuration. So default value
675 * will be '0' when the core is reset. Application needs to set it
676 * to '1' after the core initialization is completed.
678 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
679 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
682 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
683 * power-on reset, and it can be set after core initialization, which is
684 * after device soft-reset during initialization.
686 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
687 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
689 if (dwc->u2ss_inp3_quirk)
690 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
692 if (dwc->dis_rxdet_inp3_quirk)
693 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
695 if (dwc->req_p1p2p3_quirk)
696 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
698 if (dwc->del_p1p2p3_quirk)
699 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
701 if (dwc->del_phy_power_chg_quirk)
702 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
704 if (dwc->lfps_filter_quirk)
705 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
707 if (dwc->rx_detect_poll_quirk)
708 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
710 if (dwc->tx_de_emphasis_quirk)
711 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
713 if (dwc->dis_u3_susphy_quirk)
714 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
716 if (dwc->dis_del_phy_power_chg_quirk)
717 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
719 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
721 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
723 /* Select the HS PHY interface */
724 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
725 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
726 if (dwc->hsphy_interface &&
727 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
728 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
730 } else if (dwc->hsphy_interface &&
731 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
732 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
733 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
735 /* Relying on default value. */
736 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
740 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
745 switch (dwc->hsphy_mode) {
746 case USBPHY_INTERFACE_MODE_UTMI:
747 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
748 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
749 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
750 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
752 case USBPHY_INTERFACE_MODE_UTMIW:
753 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
754 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
755 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
756 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
763 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
764 * '0' during coreConsultant configuration. So default value will
765 * be '0' when the core is reset. Application needs to set it to
766 * '1' after the core initialization is completed.
768 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
769 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
772 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
773 * power-on reset, and it can be set after core initialization, which is
774 * after device soft-reset during initialization.
776 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
777 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
779 if (dwc->dis_u2_susphy_quirk)
780 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
782 if (dwc->dis_enblslpm_quirk)
783 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
785 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
787 if (dwc->dis_u2_freeclk_exists_quirk)
788 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
790 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
795 static int dwc3_clk_enable(struct dwc3 *dwc)
799 ret = clk_prepare_enable(dwc->bus_clk);
803 ret = clk_prepare_enable(dwc->ref_clk);
805 goto disable_bus_clk;
807 ret = clk_prepare_enable(dwc->susp_clk);
809 goto disable_ref_clk;
814 clk_disable_unprepare(dwc->ref_clk);
816 clk_disable_unprepare(dwc->bus_clk);
820 static void dwc3_clk_disable(struct dwc3 *dwc)
822 clk_disable_unprepare(dwc->susp_clk);
823 clk_disable_unprepare(dwc->ref_clk);
824 clk_disable_unprepare(dwc->bus_clk);
827 static void dwc3_core_exit(struct dwc3 *dwc)
829 dwc3_event_buffers_cleanup(dwc);
831 usb_phy_shutdown(dwc->usb2_phy);
832 usb_phy_shutdown(dwc->usb3_phy);
833 phy_exit(dwc->usb2_generic_phy);
834 phy_exit(dwc->usb3_generic_phy);
836 usb_phy_set_suspend(dwc->usb2_phy, 1);
837 usb_phy_set_suspend(dwc->usb3_phy, 1);
838 phy_power_off(dwc->usb2_generic_phy);
839 phy_power_off(dwc->usb3_generic_phy);
840 dwc3_clk_disable(dwc);
841 reset_control_assert(dwc->reset);
844 static bool dwc3_core_is_valid(struct dwc3 *dwc)
848 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
849 dwc->ip = DWC3_GSNPS_ID(reg);
851 /* This should read as U3 followed by revision number */
852 if (DWC3_IP_IS(DWC3)) {
854 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
855 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
856 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
864 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
866 u32 hwparams4 = dwc->hwparams.hwparams4;
869 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
870 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
872 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
873 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
875 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
876 * issue which would cause xHCI compliance tests to fail.
878 * Because of that we cannot enable clock gating on such
883 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
886 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
887 dwc->dr_mode == USB_DR_MODE_OTG) &&
888 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
889 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
891 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
893 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
894 /* enable hibernation here */
895 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
898 * REVISIT Enabling this bit so that host-mode hibernation
899 * will work. Device-mode hibernation is not yet implemented.
901 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
908 /* check if current dwc3 is on simulation board */
909 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
910 dev_info(dwc->dev, "Running with FPGA optimizations\n");
914 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
915 "disable_scramble cannot be used on non-FPGA builds\n");
917 if (dwc->disable_scramble_quirk && dwc->is_fpga)
918 reg |= DWC3_GCTL_DISSCRAMBLE;
920 reg &= ~DWC3_GCTL_DISSCRAMBLE;
922 if (dwc->u2exit_lfps_quirk)
923 reg |= DWC3_GCTL_U2EXIT_LFPS;
926 * WORKAROUND: DWC3 revisions <1.90a have a bug
927 * where the device can fail to connect at SuperSpeed
928 * and falls back to high-speed mode which causes
929 * the device to enter a Connect/Disconnect loop
931 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
932 reg |= DWC3_GCTL_U2RSTECN;
934 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
937 static int dwc3_core_get_phy(struct dwc3 *dwc);
938 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
940 /* set global incr burst type configuration registers */
941 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
943 struct device *dev = dwc->dev;
944 /* incrx_mode : for INCR burst type. */
946 /* incrx_size : for size of INCRX burst. */
954 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
957 * Handle property "snps,incr-burst-type-adjustment".
958 * Get the number of value from this property:
959 * result <= 0, means this property is not supported.
960 * result = 1, means INCRx burst mode supported.
961 * result > 1, means undefined length burst mode supported.
963 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
967 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
971 /* Get INCR burst type, and parse it */
972 ret = device_property_read_u32_array(dev,
973 "snps,incr-burst-type-adjustment", vals, ntype);
976 dev_err(dev, "Error to get property\n");
983 /* INCRX (undefined length) burst mode */
984 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
985 for (i = 1; i < ntype; i++) {
986 if (vals[i] > incrx_size)
987 incrx_size = vals[i];
990 /* INCRX burst mode */
991 incrx_mode = INCRX_BURST_MODE;
996 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
997 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
999 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1000 switch (incrx_size) {
1002 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1005 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1008 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1011 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1014 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1017 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1020 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1025 dev_err(dev, "Invalid property\n");
1029 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1033 * dwc3_core_init - Low-level initialization of DWC3 Core
1034 * @dwc: Pointer to our controller context structure
1036 * Returns 0 on success otherwise negative errno.
1038 static int dwc3_core_init(struct dwc3 *dwc)
1040 unsigned int hw_mode;
1044 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1047 * Write Linux Version Code to our GUID register so it's easy to figure
1048 * out which kernel version a bug was found.
1050 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1052 ret = dwc3_phy_setup(dwc);
1056 if (!dwc->ulpi_ready) {
1057 ret = dwc3_core_ulpi_init(dwc);
1060 dwc->ulpi_ready = true;
1063 if (!dwc->phys_ready) {
1064 ret = dwc3_core_get_phy(dwc);
1067 dwc->phys_ready = true;
1070 usb_phy_init(dwc->usb2_phy);
1071 usb_phy_init(dwc->usb3_phy);
1072 ret = phy_init(dwc->usb2_generic_phy);
1076 ret = phy_init(dwc->usb3_generic_phy);
1078 phy_exit(dwc->usb2_generic_phy);
1082 ret = dwc3_core_soft_reset(dwc);
1086 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1087 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1088 if (!dwc->dis_u3_susphy_quirk) {
1089 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1090 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1091 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1094 if (!dwc->dis_u2_susphy_quirk) {
1095 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1096 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1097 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1101 dwc3_core_setup_global_control(dwc);
1102 dwc3_core_num_eps(dwc);
1104 ret = dwc3_setup_scratch_buffers(dwc);
1108 /* Adjust Frame Length */
1109 dwc3_frame_length_adjustment(dwc);
1111 /* Adjust Reference Clock Period */
1112 dwc3_ref_clk_period(dwc);
1114 dwc3_set_incr_burst_type(dwc);
1116 usb_phy_set_suspend(dwc->usb2_phy, 0);
1117 usb_phy_set_suspend(dwc->usb3_phy, 0);
1118 ret = phy_power_on(dwc->usb2_generic_phy);
1122 ret = phy_power_on(dwc->usb3_generic_phy);
1126 ret = dwc3_event_buffers_setup(dwc);
1128 dev_err(dwc->dev, "failed to setup event buffers\n");
1133 * ENDXFER polling is available on version 3.10a and later of
1134 * the DWC_usb3 controller. It is NOT available in the
1135 * DWC_usb31 controller.
1137 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1138 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1139 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1140 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1143 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1144 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1147 * Enable hardware control of sending remote wakeup
1148 * in HS when the device is in the L1 state.
1150 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1151 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1154 * Decouple USB 2.0 L1 & L2 events which will allow for
1155 * gadget driver to only receive U3/L2 suspend & wakeup
1156 * events and prevent the more frequent L1 LPM transitions
1157 * from interrupting the driver.
1159 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1160 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1162 if (dwc->dis_tx_ipgap_linecheck_quirk)
1163 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1165 if (dwc->parkmode_disable_ss_quirk)
1166 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1168 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1169 (dwc->maximum_speed == USB_SPEED_HIGH ||
1170 dwc->maximum_speed == USB_SPEED_FULL))
1171 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1173 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1176 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1177 dwc->dr_mode == USB_DR_MODE_OTG) {
1178 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1181 * Enable Auto retry Feature to make the controller operating in
1182 * Host mode on seeing transaction errors(CRC errors or internal
1183 * overrun scenerios) on IN transfers to reply to the device
1184 * with a non-terminating retry ACK (i.e, an ACK transcation
1185 * packet with Retry=1 & Nump != 0)
1187 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1189 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1193 * Must config both number of packets and max burst settings to enable
1194 * RX and/or TX threshold.
1196 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1197 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1198 u8 rx_maxburst = dwc->rx_max_burst_prd;
1199 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1200 u8 tx_maxburst = dwc->tx_max_burst_prd;
1202 if (rx_thr_num && rx_maxburst) {
1203 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1204 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1206 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1207 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1209 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1210 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1212 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1215 if (tx_thr_num && tx_maxburst) {
1216 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1217 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1219 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1220 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1222 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1223 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1225 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1232 phy_power_off(dwc->usb3_generic_phy);
1235 phy_power_off(dwc->usb2_generic_phy);
1238 usb_phy_set_suspend(dwc->usb2_phy, 1);
1239 usb_phy_set_suspend(dwc->usb3_phy, 1);
1242 usb_phy_shutdown(dwc->usb2_phy);
1243 usb_phy_shutdown(dwc->usb3_phy);
1244 phy_exit(dwc->usb2_generic_phy);
1245 phy_exit(dwc->usb3_generic_phy);
1248 dwc3_ulpi_exit(dwc);
1254 static int dwc3_core_get_phy(struct dwc3 *dwc)
1256 struct device *dev = dwc->dev;
1257 struct device_node *node = dev->of_node;
1261 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1262 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1264 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1265 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1268 if (IS_ERR(dwc->usb2_phy)) {
1269 ret = PTR_ERR(dwc->usb2_phy);
1270 if (ret == -ENXIO || ret == -ENODEV)
1271 dwc->usb2_phy = NULL;
1273 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1276 if (IS_ERR(dwc->usb3_phy)) {
1277 ret = PTR_ERR(dwc->usb3_phy);
1278 if (ret == -ENXIO || ret == -ENODEV)
1279 dwc->usb3_phy = NULL;
1281 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1284 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1285 if (IS_ERR(dwc->usb2_generic_phy)) {
1286 ret = PTR_ERR(dwc->usb2_generic_phy);
1287 if (ret == -ENOSYS || ret == -ENODEV)
1288 dwc->usb2_generic_phy = NULL;
1290 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1293 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1294 if (IS_ERR(dwc->usb3_generic_phy)) {
1295 ret = PTR_ERR(dwc->usb3_generic_phy);
1296 if (ret == -ENOSYS || ret == -ENODEV)
1297 dwc->usb3_generic_phy = NULL;
1299 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1305 static int dwc3_core_init_mode(struct dwc3 *dwc)
1307 struct device *dev = dwc->dev;
1310 switch (dwc->dr_mode) {
1311 case USB_DR_MODE_PERIPHERAL:
1312 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1315 otg_set_vbus(dwc->usb2_phy->otg, false);
1316 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1317 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1319 ret = dwc3_gadget_init(dwc);
1321 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1323 case USB_DR_MODE_HOST:
1324 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1327 otg_set_vbus(dwc->usb2_phy->otg, true);
1328 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1329 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1331 ret = dwc3_host_init(dwc);
1333 return dev_err_probe(dev, ret, "failed to initialize host\n");
1335 case USB_DR_MODE_OTG:
1336 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1337 ret = dwc3_drd_init(dwc);
1339 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1342 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1349 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1351 switch (dwc->dr_mode) {
1352 case USB_DR_MODE_PERIPHERAL:
1353 dwc3_gadget_exit(dwc);
1355 case USB_DR_MODE_HOST:
1356 dwc3_host_exit(dwc);
1358 case USB_DR_MODE_OTG:
1366 /* de-assert DRVVBUS for HOST and OTG mode */
1367 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1370 static void dwc3_get_properties(struct dwc3 *dwc)
1372 struct device *dev = dwc->dev;
1373 u8 lpm_nyet_threshold;
1376 u8 rx_thr_num_pkt_prd = 0;
1377 u8 rx_max_burst_prd = 0;
1378 u8 tx_thr_num_pkt_prd = 0;
1379 u8 tx_max_burst_prd = 0;
1380 u8 tx_fifo_resize_max_num;
1381 const char *usb_psy_name;
1384 /* default to highest possible threshold */
1385 lpm_nyet_threshold = 0xf;
1387 /* default to -3.5dB de-emphasis */
1391 * default to assert utmi_sleep_n and use maximum allowed HIRD
1392 * threshold value of 0b1100
1394 hird_threshold = 12;
1397 * default to a TXFIFO size large enough to fit 6 max packets. This
1398 * allows for systems with larger bus latencies to have some headroom
1399 * for endpoints that have a large bMaxBurst value.
1401 tx_fifo_resize_max_num = 6;
1403 dwc->maximum_speed = usb_get_maximum_speed(dev);
1404 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1405 dwc->dr_mode = usb_get_dr_mode(dev);
1406 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1408 dwc->sysdev_is_parent = device_property_read_bool(dev,
1409 "linux,sysdev_is_parent");
1410 if (dwc->sysdev_is_parent)
1411 dwc->sysdev = dwc->dev->parent;
1413 dwc->sysdev = dwc->dev;
1415 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1417 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1419 dev_err(dev, "couldn't get usb power supply\n");
1422 dwc->has_lpm_erratum = device_property_read_bool(dev,
1423 "snps,has-lpm-erratum");
1424 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1425 &lpm_nyet_threshold);
1426 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1427 "snps,is-utmi-l1-suspend");
1428 device_property_read_u8(dev, "snps,hird-threshold",
1430 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1431 "snps,dis-start-transfer-quirk");
1432 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1433 "snps,usb3_lpm_capable");
1434 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1435 "snps,usb2-lpm-disable");
1436 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1437 "snps,usb2-gadget-lpm-disable");
1438 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1439 &rx_thr_num_pkt_prd);
1440 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1442 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1443 &tx_thr_num_pkt_prd);
1444 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1446 dwc->do_fifo_resize = device_property_read_bool(dev,
1448 if (dwc->do_fifo_resize)
1449 device_property_read_u8(dev, "tx-fifo-max-num",
1450 &tx_fifo_resize_max_num);
1452 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1453 "snps,disable_scramble_quirk");
1454 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1455 "snps,u2exit_lfps_quirk");
1456 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1457 "snps,u2ss_inp3_quirk");
1458 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1459 "snps,req_p1p2p3_quirk");
1460 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1461 "snps,del_p1p2p3_quirk");
1462 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1463 "snps,del_phy_power_chg_quirk");
1464 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1465 "snps,lfps_filter_quirk");
1466 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1467 "snps,rx_detect_poll_quirk");
1468 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1469 "snps,dis_u3_susphy_quirk");
1470 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1471 "snps,dis_u2_susphy_quirk");
1472 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1473 "snps,dis_enblslpm_quirk");
1474 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1475 "snps,dis-u1-entry-quirk");
1476 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1477 "snps,dis-u2-entry-quirk");
1478 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1479 "snps,dis_rxdet_inp3_quirk");
1480 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1481 "snps,dis-u2-freeclk-exists-quirk");
1482 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1483 "snps,dis-del-phy-power-chg-quirk");
1484 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1485 "snps,dis-tx-ipgap-linecheck-quirk");
1486 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1487 "snps,parkmode-disable-ss-quirk");
1489 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1490 "snps,tx_de_emphasis_quirk");
1491 device_property_read_u8(dev, "snps,tx_de_emphasis",
1493 device_property_read_string(dev, "snps,hsphy_interface",
1494 &dwc->hsphy_interface);
1495 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1497 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1500 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1501 "snps,dis_metastability_quirk");
1503 dwc->dis_split_quirk = device_property_read_bool(dev,
1504 "snps,dis-split-quirk");
1506 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1507 dwc->tx_de_emphasis = tx_de_emphasis;
1509 dwc->hird_threshold = hird_threshold;
1511 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1512 dwc->rx_max_burst_prd = rx_max_burst_prd;
1514 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1515 dwc->tx_max_burst_prd = tx_max_burst_prd;
1517 dwc->imod_interval = 0;
1519 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1522 /* check whether the core supports IMOD */
1523 bool dwc3_has_imod(struct dwc3 *dwc)
1525 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1526 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1530 static void dwc3_check_params(struct dwc3 *dwc)
1532 struct device *dev = dwc->dev;
1533 unsigned int hwparam_gen =
1534 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1536 /* Check for proper value of imod_interval */
1537 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1538 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1539 dwc->imod_interval = 0;
1543 * Workaround for STAR 9000961433 which affects only version
1544 * 3.00a of the DWC_usb3 core. This prevents the controller
1545 * interrupt from being masked while handling events. IMOD
1546 * allows us to work around this issue. Enable it for the
1549 if (!dwc->imod_interval &&
1550 DWC3_VER_IS(DWC3, 300A))
1551 dwc->imod_interval = 1;
1553 /* Check the maximum_speed parameter */
1554 switch (dwc->maximum_speed) {
1555 case USB_SPEED_FULL:
1556 case USB_SPEED_HIGH:
1558 case USB_SPEED_SUPER:
1559 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1560 dev_warn(dev, "UDC doesn't support Gen 1\n");
1562 case USB_SPEED_SUPER_PLUS:
1563 if ((DWC3_IP_IS(DWC32) &&
1564 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1565 (!DWC3_IP_IS(DWC32) &&
1566 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1567 dev_warn(dev, "UDC doesn't support SSP\n");
1570 dev_err(dev, "invalid maximum_speed parameter %d\n",
1571 dwc->maximum_speed);
1573 case USB_SPEED_UNKNOWN:
1574 switch (hwparam_gen) {
1575 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1576 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1578 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1579 if (DWC3_IP_IS(DWC32))
1580 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1582 dwc->maximum_speed = USB_SPEED_SUPER;
1584 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1585 dwc->maximum_speed = USB_SPEED_HIGH;
1588 dwc->maximum_speed = USB_SPEED_SUPER;
1595 * Currently the controller does not have visibility into the HW
1596 * parameter to determine the maximum number of lanes the HW supports.
1597 * If the number of lanes is not specified in the device property, then
1598 * set the default to support dual-lane for DWC_usb32 and single-lane
1599 * for DWC_usb31 for super-speed-plus.
1601 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1602 switch (dwc->max_ssp_rate) {
1603 case USB_SSP_GEN_2x1:
1604 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1605 dev_warn(dev, "UDC only supports Gen 1\n");
1607 case USB_SSP_GEN_1x2:
1608 case USB_SSP_GEN_2x2:
1609 if (DWC3_IP_IS(DWC31))
1610 dev_warn(dev, "UDC only supports single lane\n");
1612 case USB_SSP_GEN_UNKNOWN:
1614 switch (hwparam_gen) {
1615 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1616 if (DWC3_IP_IS(DWC32))
1617 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1619 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1621 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1622 if (DWC3_IP_IS(DWC32))
1623 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1631 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1633 struct device *dev = dwc->dev;
1634 struct device_node *np_phy;
1635 struct extcon_dev *edev = NULL;
1638 if (device_property_read_bool(dev, "extcon"))
1639 return extcon_get_edev_by_phandle(dev, 0);
1642 * Device tree platforms should get extcon via phandle.
1643 * On ACPI platforms, we get the name from a device property.
1644 * This device property is for kernel internal use only and
1645 * is expected to be set by the glue code.
1647 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) {
1648 edev = extcon_get_extcon_dev(name);
1650 return ERR_PTR(-EPROBE_DEFER);
1656 * Try to get an extcon device from the USB PHY controller's "port"
1657 * node. Check if it has the "port" node first, to avoid printing the
1658 * error message from underlying code, as it's a valid case: extcon
1659 * device (and "port" node) may be missing in case of "usb-role-switch"
1662 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1663 if (of_graph_is_present(np_phy)) {
1664 struct device_node *np_conn;
1666 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1668 edev = extcon_find_edev_by_node(np_conn);
1669 of_node_put(np_conn);
1671 of_node_put(np_phy);
1676 static int dwc3_probe(struct platform_device *pdev)
1678 struct device *dev = &pdev->dev;
1679 struct resource *res, dwc_res;
1686 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1694 dev_err(dev, "missing memory resource\n");
1698 dwc->xhci_resources[0].start = res->start;
1699 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1701 dwc->xhci_resources[0].flags = res->flags;
1702 dwc->xhci_resources[0].name = res->name;
1705 * Request memory region but exclude xHCI regs,
1706 * since it will be requested by the xhci-plat driver.
1709 dwc_res.start += DWC3_GLOBALS_REGS_START;
1711 regs = devm_ioremap_resource(dev, &dwc_res);
1713 return PTR_ERR(regs);
1716 dwc->regs_size = resource_size(&dwc_res);
1718 dwc3_get_properties(dwc);
1720 if (!dwc->sysdev_is_parent) {
1721 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1726 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1727 if (IS_ERR(dwc->reset))
1728 return PTR_ERR(dwc->reset);
1732 * Clocks are optional, but new DT platforms should support all
1733 * clocks as required by the DT-binding.
1734 * Some devices have different clock names in legacy device trees,
1735 * check for them to retain backwards compatibility.
1737 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1738 if (IS_ERR(dwc->bus_clk))
1739 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1740 "could not get bus clock\n");
1742 if (dwc->bus_clk == NULL) {
1743 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1744 if (IS_ERR(dwc->bus_clk))
1745 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1746 "could not get bus clock\n");
1749 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1750 if (IS_ERR(dwc->ref_clk))
1751 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1752 "could not get ref clock\n");
1754 if (dwc->ref_clk == NULL) {
1755 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1756 if (IS_ERR(dwc->ref_clk))
1757 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1758 "could not get ref clock\n");
1761 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1762 if (IS_ERR(dwc->susp_clk))
1763 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1764 "could not get suspend clock\n");
1766 if (dwc->susp_clk == NULL) {
1767 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1768 if (IS_ERR(dwc->susp_clk))
1769 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1770 "could not get suspend clock\n");
1774 ret = reset_control_deassert(dwc->reset);
1778 ret = dwc3_clk_enable(dwc);
1782 if (!dwc3_core_is_valid(dwc)) {
1783 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1788 platform_set_drvdata(pdev, dwc);
1789 dwc3_cache_hwparams(dwc);
1791 spin_lock_init(&dwc->lock);
1792 mutex_init(&dwc->mutex);
1794 pm_runtime_set_active(dev);
1795 pm_runtime_use_autosuspend(dev);
1796 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1797 pm_runtime_enable(dev);
1798 ret = pm_runtime_get_sync(dev);
1802 pm_runtime_forbid(dev);
1804 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1806 dev_err(dwc->dev, "failed to allocate event buffers\n");
1811 dwc->edev = dwc3_get_extcon(dwc);
1812 if (IS_ERR(dwc->edev)) {
1813 ret = PTR_ERR(dwc->edev);
1814 dev_err_probe(dwc->dev, ret, "failed to get extcon\n");
1818 ret = dwc3_get_dr_mode(dwc);
1822 ret = dwc3_alloc_scratch_buffers(dwc);
1826 ret = dwc3_core_init(dwc);
1828 dev_err_probe(dev, ret, "failed to initialize core\n");
1832 dwc3_check_params(dwc);
1833 dwc3_debugfs_init(dwc);
1835 ret = dwc3_core_init_mode(dwc);
1839 pm_runtime_put(dev);
1844 dwc3_debugfs_exit(dwc);
1845 dwc3_event_buffers_cleanup(dwc);
1847 usb_phy_shutdown(dwc->usb2_phy);
1848 usb_phy_shutdown(dwc->usb3_phy);
1849 phy_exit(dwc->usb2_generic_phy);
1850 phy_exit(dwc->usb3_generic_phy);
1852 usb_phy_set_suspend(dwc->usb2_phy, 1);
1853 usb_phy_set_suspend(dwc->usb3_phy, 1);
1854 phy_power_off(dwc->usb2_generic_phy);
1855 phy_power_off(dwc->usb3_generic_phy);
1857 dwc3_ulpi_exit(dwc);
1860 dwc3_free_scratch_buffers(dwc);
1863 dwc3_free_event_buffers(dwc);
1866 pm_runtime_allow(&pdev->dev);
1869 pm_runtime_put_sync(&pdev->dev);
1870 pm_runtime_disable(&pdev->dev);
1873 dwc3_clk_disable(dwc);
1875 reset_control_assert(dwc->reset);
1878 power_supply_put(dwc->usb_psy);
1883 static int dwc3_remove(struct platform_device *pdev)
1885 struct dwc3 *dwc = platform_get_drvdata(pdev);
1887 pm_runtime_get_sync(&pdev->dev);
1889 dwc3_core_exit_mode(dwc);
1890 dwc3_debugfs_exit(dwc);
1892 dwc3_core_exit(dwc);
1893 dwc3_ulpi_exit(dwc);
1895 pm_runtime_disable(&pdev->dev);
1896 pm_runtime_put_noidle(&pdev->dev);
1897 pm_runtime_set_suspended(&pdev->dev);
1899 dwc3_free_event_buffers(dwc);
1900 dwc3_free_scratch_buffers(dwc);
1903 power_supply_put(dwc->usb_psy);
1909 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1913 ret = reset_control_deassert(dwc->reset);
1917 ret = dwc3_clk_enable(dwc);
1921 ret = dwc3_core_init(dwc);
1928 dwc3_clk_disable(dwc);
1930 reset_control_assert(dwc->reset);
1935 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1937 unsigned long flags;
1940 switch (dwc->current_dr_role) {
1941 case DWC3_GCTL_PRTCAP_DEVICE:
1942 if (pm_runtime_suspended(dwc->dev))
1944 spin_lock_irqsave(&dwc->lock, flags);
1945 dwc3_gadget_suspend(dwc);
1946 spin_unlock_irqrestore(&dwc->lock, flags);
1947 synchronize_irq(dwc->irq_gadget);
1948 dwc3_core_exit(dwc);
1950 case DWC3_GCTL_PRTCAP_HOST:
1951 if (!PMSG_IS_AUTO(msg)) {
1952 dwc3_core_exit(dwc);
1956 /* Let controller to suspend HSPHY before PHY driver suspends */
1957 if (dwc->dis_u2_susphy_quirk ||
1958 dwc->dis_enblslpm_quirk) {
1959 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1960 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1961 DWC3_GUSB2PHYCFG_SUSPHY;
1962 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1964 /* Give some time for USB2 PHY to suspend */
1965 usleep_range(5000, 6000);
1968 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1969 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1971 case DWC3_GCTL_PRTCAP_OTG:
1972 /* do nothing during runtime_suspend */
1973 if (PMSG_IS_AUTO(msg))
1976 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1977 spin_lock_irqsave(&dwc->lock, flags);
1978 dwc3_gadget_suspend(dwc);
1979 spin_unlock_irqrestore(&dwc->lock, flags);
1980 synchronize_irq(dwc->irq_gadget);
1984 dwc3_core_exit(dwc);
1994 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1996 unsigned long flags;
2000 switch (dwc->current_dr_role) {
2001 case DWC3_GCTL_PRTCAP_DEVICE:
2002 ret = dwc3_core_init_for_resume(dwc);
2006 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2007 spin_lock_irqsave(&dwc->lock, flags);
2008 dwc3_gadget_resume(dwc);
2009 spin_unlock_irqrestore(&dwc->lock, flags);
2011 case DWC3_GCTL_PRTCAP_HOST:
2012 if (!PMSG_IS_AUTO(msg)) {
2013 ret = dwc3_core_init_for_resume(dwc);
2016 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2019 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2020 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2021 if (dwc->dis_u2_susphy_quirk)
2022 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2024 if (dwc->dis_enblslpm_quirk)
2025 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2027 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2029 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2030 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2032 case DWC3_GCTL_PRTCAP_OTG:
2033 /* nothing to do on runtime_resume */
2034 if (PMSG_IS_AUTO(msg))
2037 ret = dwc3_core_init_for_resume(dwc);
2041 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2044 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2045 dwc3_otg_host_init(dwc);
2046 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2047 spin_lock_irqsave(&dwc->lock, flags);
2048 dwc3_gadget_resume(dwc);
2049 spin_unlock_irqrestore(&dwc->lock, flags);
2061 static int dwc3_runtime_checks(struct dwc3 *dwc)
2063 switch (dwc->current_dr_role) {
2064 case DWC3_GCTL_PRTCAP_DEVICE:
2068 case DWC3_GCTL_PRTCAP_HOST:
2077 static int dwc3_runtime_suspend(struct device *dev)
2079 struct dwc3 *dwc = dev_get_drvdata(dev);
2082 if (dwc3_runtime_checks(dwc))
2085 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2089 device_init_wakeup(dev, true);
2094 static int dwc3_runtime_resume(struct device *dev)
2096 struct dwc3 *dwc = dev_get_drvdata(dev);
2099 device_init_wakeup(dev, false);
2101 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2105 switch (dwc->current_dr_role) {
2106 case DWC3_GCTL_PRTCAP_DEVICE:
2107 dwc3_gadget_process_pending_events(dwc);
2109 case DWC3_GCTL_PRTCAP_HOST:
2115 pm_runtime_mark_last_busy(dev);
2120 static int dwc3_runtime_idle(struct device *dev)
2122 struct dwc3 *dwc = dev_get_drvdata(dev);
2124 switch (dwc->current_dr_role) {
2125 case DWC3_GCTL_PRTCAP_DEVICE:
2126 if (dwc3_runtime_checks(dwc))
2129 case DWC3_GCTL_PRTCAP_HOST:
2135 pm_runtime_mark_last_busy(dev);
2136 pm_runtime_autosuspend(dev);
2140 #endif /* CONFIG_PM */
2142 #ifdef CONFIG_PM_SLEEP
2143 static int dwc3_suspend(struct device *dev)
2145 struct dwc3 *dwc = dev_get_drvdata(dev);
2148 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2152 pinctrl_pm_select_sleep_state(dev);
2157 static int dwc3_resume(struct device *dev)
2159 struct dwc3 *dwc = dev_get_drvdata(dev);
2162 pinctrl_pm_select_default_state(dev);
2164 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2168 pm_runtime_disable(dev);
2169 pm_runtime_set_active(dev);
2170 pm_runtime_enable(dev);
2175 static void dwc3_complete(struct device *dev)
2177 struct dwc3 *dwc = dev_get_drvdata(dev);
2180 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2181 dwc->dis_split_quirk) {
2182 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2183 reg |= DWC3_GUCTL3_SPLITDISABLE;
2184 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2188 #define dwc3_complete NULL
2189 #endif /* CONFIG_PM_SLEEP */
2191 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2192 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2193 .complete = dwc3_complete,
2194 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2199 static const struct of_device_id of_dwc3_match[] = {
2201 .compatible = "snps,dwc3"
2204 .compatible = "synopsys,dwc3"
2208 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2213 #define ACPI_ID_INTEL_BSW "808622B7"
2215 static const struct acpi_device_id dwc3_acpi_match[] = {
2216 { ACPI_ID_INTEL_BSW, 0 },
2219 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2222 static struct platform_driver dwc3_driver = {
2223 .probe = dwc3_probe,
2224 .remove = dwc3_remove,
2227 .of_match_table = of_match_ptr(of_dwc3_match),
2228 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2229 .pm = &dwc3_dev_pm_ops,
2233 module_platform_driver(dwc3_driver);
2235 MODULE_ALIAS("platform:dwc3");
2236 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2237 MODULE_LICENSE("GPL v2");
2238 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");