drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/of_graph.h>
  27 #include <linux/acpi.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/reset.h>
  30 #include <linux/bitfield.h>
  31
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/of.h>
  35 #include <linux/usb/otg.h>
  36
  37 #include "core.h"
  38 #include "gadget.h"
  39 #include "io.h"
  40
  41 #include "debug.h"
  42
  43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  44
  45 /**
  46  * dwc3_get_dr_mode - Validates and sets dr_mode
  47  * @dwc: pointer to our context structure
  48  */
  49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  50 {
  51         enum usb_dr_mode mode;
  52         struct device *dev = dwc->dev;
  53         unsigned int hw_mode;
  54
  55         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  56                 dwc->dr_mode = USB_DR_MODE_OTG;
  57
  58         mode = dwc->dr_mode;
  59         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  60
  61         switch (hw_mode) {
  62         case DWC3_GHWPARAMS0_MODE_GADGET:
  63                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  64                         dev_err(dev,
  65                                 "Controller does not support host mode.\n");
  66                         return -EINVAL;
  67                 }
  68                 mode = USB_DR_MODE_PERIPHERAL;
  69                 break;
  70         case DWC3_GHWPARAMS0_MODE_HOST:
  71                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  72                         dev_err(dev,
  73                                 "Controller does not support device mode.\n");
  74                         return -EINVAL;
  75                 }
  76                 mode = USB_DR_MODE_HOST;
  77                 break;
  78         default:
  79                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  80                         mode = USB_DR_MODE_HOST;
  81                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  82                         mode = USB_DR_MODE_PERIPHERAL;
  83
  84                 /*
  85                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  86                  * mode. If the controller supports DRD but the dr_mode is not
  87                  * specified or set to OTG, then set the mode to peripheral.
  88                  */
  89                 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
  90                     (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
  91                      !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
  92                     !DWC3_VER_IS_PRIOR(DWC3, 330A))
  93                         mode = USB_DR_MODE_PERIPHERAL;
  94         }
  95
  96         if (mode != dwc->dr_mode) {
  97                 dev_warn(dev,
  98                          "Configuration mismatch. dr_mode forced to %s\n",
  99                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
 100
 101                 dwc->dr_mode = mode;
 102         }
 103
 104         return 0;
 105 }
 106
 107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 108 {
 109         u32 reg;
 110
 111         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 112         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 113         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 114         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 115
 116         dwc->current_dr_role = mode;
 117 }
 118
 119 static void __dwc3_set_mode(struct work_struct *work)
 120 {
 121         struct dwc3 *dwc = work_to_dwc(work);
 122         unsigned long flags;
 123         int ret;
 124         u32 reg;
 125
 126         mutex_lock(&dwc->mutex);
 127
 128         pm_runtime_get_sync(dwc->dev);
 129
 130         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 131                 dwc3_otg_update(dwc, 0);
 132
 133         if (!dwc->desired_dr_role)
 134                 goto out;
 135
 136         if (dwc->desired_dr_role == dwc->current_dr_role)
 137                 goto out;
 138
 139         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 140                 goto out;
 141
 142         switch (dwc->current_dr_role) {
 143         case DWC3_GCTL_PRTCAP_HOST:
 144                 dwc3_host_exit(dwc);
 145                 break;
 146         case DWC3_GCTL_PRTCAP_DEVICE:
 147                 dwc3_gadget_exit(dwc);
 148                 dwc3_event_buffers_cleanup(dwc);
 149                 break;
 150         case DWC3_GCTL_PRTCAP_OTG:
 151                 dwc3_otg_exit(dwc);
 152                 spin_lock_irqsave(&dwc->lock, flags);
 153                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 154                 spin_unlock_irqrestore(&dwc->lock, flags);
 155                 dwc3_otg_update(dwc, 1);
 156                 break;
 157         default:
 158                 break;
 159         }
 160
 161         /* For DRD host or device mode only */
 162         if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
 163                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 164                 reg |= DWC3_GCTL_CORESOFTRESET;
 165                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 166
 167                 /*
 168                  * Wait for internal clocks to synchronized. DWC_usb31 and
 169                  * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
 170                  * keep it consistent across different IPs, let's wait up to
 171                  * 100ms before clearing GCTL.CORESOFTRESET.
 172                  */
 173                 msleep(100);
 174
 175                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 176                 reg &= ~DWC3_GCTL_CORESOFTRESET;
 177                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 178         }
 179
 180         spin_lock_irqsave(&dwc->lock, flags);
 181
 182         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 183
 184         spin_unlock_irqrestore(&dwc->lock, flags);
 185
 186         switch (dwc->desired_dr_role) {
 187         case DWC3_GCTL_PRTCAP_HOST:
 188                 ret = dwc3_host_init(dwc);
 189                 if (ret) {
 190                         dev_err(dwc->dev, "failed to initialize host\n");
 191                 } else {
 192                         if (dwc->usb2_phy)
 193                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 194                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 195                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 196                         if (dwc->dis_split_quirk) {
 197                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 198                                 reg |= DWC3_GUCTL3_SPLITDISABLE;
 199                                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
 200                         }
 201                 }
 202                 break;
 203         case DWC3_GCTL_PRTCAP_DEVICE:
 204                 dwc3_core_soft_reset(dwc);
 205
 206                 dwc3_event_buffers_setup(dwc);
 207
 208                 if (dwc->usb2_phy)
 209                         otg_set_vbus(dwc->usb2_phy->otg, false);
 210                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 211                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 212
 213                 ret = dwc3_gadget_init(dwc);
 214                 if (ret)
 215                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 216                 break;
 217         case DWC3_GCTL_PRTCAP_OTG:
 218                 dwc3_otg_init(dwc);
 219                 dwc3_otg_update(dwc, 0);
 220                 break;
 221         default:
 222                 break;
 223         }
 224
 225 out:
 226         pm_runtime_mark_last_busy(dwc->dev);
 227         pm_runtime_put_autosuspend(dwc->dev);
 228         mutex_unlock(&dwc->mutex);
 229 }
 230
 231 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 232 {
 233         unsigned long flags;
 234
 235         if (dwc->dr_mode != USB_DR_MODE_OTG)
 236                 return;
 237
 238         spin_lock_irqsave(&dwc->lock, flags);
 239         dwc->desired_dr_role = mode;
 240         spin_unlock_irqrestore(&dwc->lock, flags);
 241
 242         queue_work(system_freezable_wq, &dwc->drd_work);
 243 }
 244
 245 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 246 {
 247         struct dwc3             *dwc = dep->dwc;
 248         u32                     reg;
 249
 250         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 251                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 252                         DWC3_GDBGFIFOSPACE_TYPE(type));
 253
 254         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 255
 256         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 257 }
 258
 259 /**
 260  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 261  * @dwc: pointer to our context structure
 262  */
 263 int dwc3_core_soft_reset(struct dwc3 *dwc)
 264 {
 265         u32             reg;
 266         int             retries = 1000;
 267
 268         /*
 269          * We're resetting only the device side because, if we're in host mode,
 270          * XHCI driver will reset the host block. If dwc3 was configured for
 271          * host-only mode, then we can return early.
 272          */
 273         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 274                 return 0;
 275
 276         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 277         reg |= DWC3_DCTL_CSFTRST;
 278         reg &= ~DWC3_DCTL_RUN_STOP;
 279         dwc3_gadget_dctl_write_safe(dwc, reg);
 280
 281         /*
 282          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 283          * is cleared only after all the clocks are synchronized. This can
 284          * take a little more than 50ms. Set the polling rate at 20ms
 285          * for 10 times instead.
 286          */
 287         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 288                 retries = 10;
 289
 290         do {
 291                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 292                 if (!(reg & DWC3_DCTL_CSFTRST))
 293                         goto done;
 294
 295                 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 296                         msleep(20);
 297                 else
 298                         udelay(1);
 299         } while (--retries);
 300
 301         return -ETIMEDOUT;
 302
 303 done:
 304         /*
 305          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 306          * is cleared, we must wait at least 50ms before accessing the PHY
 307          * domain (synchronization delay).
 308          */
 309         if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
 310                 msleep(50);
 311
 312         return 0;
 313 }
 314
 315 /*
 316  * dwc3_frame_length_adjustment - Adjusts frame length if required
 317  * @dwc3: Pointer to our controller context structure
 318  */
 319 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 320 {
 321         u32 reg;
 322         u32 dft;
 323
 324         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 325                 return;
 326
 327         if (dwc->fladj == 0)
 328                 return;
 329
 330         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 331         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 332         if (dft != dwc->fladj) {
 333                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 334                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 335                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 336         }
 337 }
 338
 339 /**
 340  * dwc3_ref_clk_period - Reference clock period configuration
 341  *              Default reference clock period depends on hardware
 342  *              configuration. For systems with reference clock that differs
 343  *              from the default, this will set clock period in DWC3_GUCTL
 344  *              register.
 345  * @dwc: Pointer to our controller context structure
 346  */
 347 static void dwc3_ref_clk_period(struct dwc3 *dwc)
 348 {
 349         unsigned long period;
 350         unsigned long fladj;
 351         unsigned long decr;
 352         unsigned long rate;
 353         u32 reg;
 354
 355         if (dwc->ref_clk) {
 356                 rate = clk_get_rate(dwc->ref_clk);
 357                 if (!rate)
 358                         return;
 359                 period = NSEC_PER_SEC / rate;
 360         } else if (dwc->ref_clk_per) {
 361                 period = dwc->ref_clk_per;
 362                 rate = NSEC_PER_SEC / period;
 363         } else {
 364                 return;
 365         }
 366
 367         reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 368         reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
 369         reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
 370         dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
 371
 372         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 373                 return;
 374
 375         /*
 376          * The calculation below is
 377          *
 378          * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
 379          *
 380          * but rearranged for fixed-point arithmetic. The division must be
 381          * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
 382          * neither does rate * period).
 383          *
 384          * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
 385          * nanoseconds of error caused by the truncation which happened during
 386          * the division when calculating rate or period (whichever one was
 387          * derived from the other). We first calculate the relative error, then
 388          * scale it to units of 8 ppm.
 389          */
 390         fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
 391         fladj -= 125000;
 392
 393         /*
 394          * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
 395          */
 396         decr = 480000000 / rate;
 397
 398         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 399         reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
 400             &  ~DWC3_GFLADJ_240MHZDECR
 401             &  ~DWC3_GFLADJ_240MHZDECR_PLS1;
 402         reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
 403             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
 404             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
 405         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 406 }
 407
 408 /**
 409  * dwc3_free_one_event_buffer - Frees one event buffer
 410  * @dwc: Pointer to our controller context structure
 411  * @evt: Pointer to event buffer to be freed
 412  */
 413 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 414                 struct dwc3_event_buffer *evt)
 415 {
 416         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 417 }
 418
 419 /**
 420  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 421  * @dwc: Pointer to our controller context structure
 422  * @length: size of the event buffer
 423  *
 424  * Returns a pointer to the allocated event buffer structure on success
 425  * otherwise ERR_PTR(errno).
 426  */
 427 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 428                 unsigned length)
 429 {
 430         struct dwc3_event_buffer        *evt;
 431
 432         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 433         if (!evt)
 434                 return ERR_PTR(-ENOMEM);
 435
 436         evt->dwc        = dwc;
 437         evt->length     = length;
 438         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 439         if (!evt->cache)
 440                 return ERR_PTR(-ENOMEM);
 441
 442         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 443                         &evt->dma, GFP_KERNEL);
 444         if (!evt->buf)
 445                 return ERR_PTR(-ENOMEM);
 446
 447         return evt;
 448 }
 449
 450 /**
 451  * dwc3_free_event_buffers - frees all allocated event buffers
 452  * @dwc: Pointer to our controller context structure
 453  */
 454 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 455 {
 456         struct dwc3_event_buffer        *evt;
 457
 458         evt = dwc->ev_buf;
 459         if (evt)
 460                 dwc3_free_one_event_buffer(dwc, evt);
 461 }
 462
 463 /**
 464  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 465  * @dwc: pointer to our controller context structure
 466  * @length: size of event buffer
 467  *
 468  * Returns 0 on success otherwise negative errno. In the error case, dwc
 469  * may contain some buffers allocated but not all which were requested.
 470  */
 471 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 472 {
 473         struct dwc3_event_buffer *evt;
 474
 475         evt = dwc3_alloc_one_event_buffer(dwc, length);
 476         if (IS_ERR(evt)) {
 477                 dev_err(dwc->dev, "can't allocate event buffer\n");
 478                 return PTR_ERR(evt);
 479         }
 480         dwc->ev_buf = evt;
 481
 482         return 0;
 483 }
 484
 485 /**
 486  * dwc3_event_buffers_setup - setup our allocated event buffers
 487  * @dwc: pointer to our controller context structure
 488  *
 489  * Returns 0 on success otherwise negative errno.
 490  */
 491 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 492 {
 493         struct dwc3_event_buffer        *evt;
 494
 495         evt = dwc->ev_buf;
 496         evt->lpos = 0;
 497         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 498                         lower_32_bits(evt->dma));
 499         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 500                         upper_32_bits(evt->dma));
 501         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 502                         DWC3_GEVNTSIZ_SIZE(evt->length));
 503         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 504
 505         return 0;
 506 }
 507
 508 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 509 {
 510         struct dwc3_event_buffer        *evt;
 511
 512         evt = dwc->ev_buf;
 513
 514         evt->lpos = 0;
 515
 516         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 517         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 518         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 519                         | DWC3_GEVNTSIZ_SIZE(0));
 520         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 521 }
 522
 523 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 524 {
 525         if (!dwc->has_hibernation)
 526                 return 0;
 527
 528         if (!dwc->nr_scratch)
 529                 return 0;
 530
 531         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 532                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 533         if (!dwc->scratchbuf)
 534                 return -ENOMEM;
 535
 536         return 0;
 537 }
 538
 539 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 540 {
 541         dma_addr_t scratch_addr;
 542         u32 param;
 543         int ret;
 544
 545         if (!dwc->has_hibernation)
 546                 return 0;
 547
 548         if (!dwc->nr_scratch)
 549                 return 0;
 550
 551          /* should never fall here */
 552         if (!WARN_ON(dwc->scratchbuf))
 553                 return 0;
 554
 555         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 556                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 557                         DMA_BIDIRECTIONAL);
 558         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 559                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 560                 ret = -EFAULT;
 561                 goto err0;
 562         }
 563
 564         dwc->scratch_addr = scratch_addr;
 565
 566         param = lower_32_bits(scratch_addr);
 567
 568         ret = dwc3_send_gadget_generic_command(dwc,
 569                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 570         if (ret < 0)
 571                 goto err1;
 572
 573         param = upper_32_bits(scratch_addr);
 574
 575         ret = dwc3_send_gadget_generic_command(dwc,
 576                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 577         if (ret < 0)
 578                 goto err1;
 579
 580         return 0;
 581
 582 err1:
 583         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 584                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 585
 586 err0:
 587         return ret;
 588 }
 589
 590 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 591 {
 592         if (!dwc->has_hibernation)
 593                 return;
 594
 595         if (!dwc->nr_scratch)
 596                 return;
 597
 598          /* should never fall here */
 599         if (!WARN_ON(dwc->scratchbuf))
 600                 return;
 601
 602         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 603                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 604         kfree(dwc->scratchbuf);
 605 }
 606
 607 static void dwc3_core_num_eps(struct dwc3 *dwc)
 608 {
 609         struct dwc3_hwparams    *parms = &dwc->hwparams;
 610
 611         dwc->num_eps = DWC3_NUM_EPS(parms);
 612 }
 613
 614 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 615 {
 616         struct dwc3_hwparams    *parms = &dwc->hwparams;
 617
 618         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 619         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 620         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 621         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 622         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 623         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 624         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 625         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 626         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 627
 628         if (DWC3_IP_IS(DWC32))
 629                 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
 630 }
 631
 632 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 633 {
 634         int intf;
 635         int ret = 0;
 636
 637         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 638
 639         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 640             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 641              dwc->hsphy_interface &&
 642              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 643                 ret = dwc3_ulpi_init(dwc);
 644
 645         return ret;
 646 }
 647
 648 /**
 649  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 650  * @dwc: Pointer to our controller context structure
 651  *
 652  * Returns 0 on success. The USB PHY interfaces are configured but not
 653  * initialized. The PHY interfaces and the PHYs get initialized together with
 654  * the core in dwc3_core_init.
 655  */
 656 static int dwc3_phy_setup(struct dwc3 *dwc)
 657 {
 658         unsigned int hw_mode;
 659         u32 reg;
 660
 661         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 662
 663         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 664
 665         /*
 666          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 667          * PHYs. Also, this bit is not supposed to be used in normal operation.
 668          */
 669         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 670
 671         /*
 672          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 673          * to '0' during coreConsultant configuration. So default value
 674          * will be '0' when the core is reset. Application needs to set it
 675          * to '1' after the core initialization is completed.
 676          */
 677         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 678                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 679
 680         /*
 681          * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
 682          * power-on reset, and it can be set after core initialization, which is
 683          * after device soft-reset during initialization.
 684          */
 685         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 686                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 687
 688         if (dwc->u2ss_inp3_quirk)
 689                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 690
 691         if (dwc->dis_rxdet_inp3_quirk)
 692                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 693
 694         if (dwc->req_p1p2p3_quirk)
 695                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 696
 697         if (dwc->del_p1p2p3_quirk)
 698                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 699
 700         if (dwc->del_phy_power_chg_quirk)
 701                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 702
 703         if (dwc->lfps_filter_quirk)
 704                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 705
 706         if (dwc->rx_detect_poll_quirk)
 707                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 708
 709         if (dwc->tx_de_emphasis_quirk)
 710                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 711
 712         if (dwc->dis_u3_susphy_quirk)
 713                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 714
 715         if (dwc->dis_del_phy_power_chg_quirk)
 716                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 717
 718         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 719
 720         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 721
 722         /* Select the HS PHY interface */
 723         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 724         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 725                 if (dwc->hsphy_interface &&
 726                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 727                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 728                         break;
 729                 } else if (dwc->hsphy_interface &&
 730                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 731                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 732                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 733                 } else {
 734                         /* Relying on default value. */
 735                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 736                                 break;
 737                 }
 738                 fallthrough;
 739         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 740         default:
 741                 break;
 742         }
 743
 744         switch (dwc->hsphy_mode) {
 745         case USBPHY_INTERFACE_MODE_UTMI:
 746                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 747                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 748                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 749                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 750                 break;
 751         case USBPHY_INTERFACE_MODE_UTMIW:
 752                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 753                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 754                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 755                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 756                 break;
 757         default:
 758                 break;
 759         }
 760
 761         /*
 762          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 763          * '0' during coreConsultant configuration. So default value will
 764          * be '0' when the core is reset. Application needs to set it to
 765          * '1' after the core initialization is completed.
 766          */
 767         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 768                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 769
 770         /*
 771          * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
 772          * power-on reset, and it can be set after core initialization, which is
 773          * after device soft-reset during initialization.
 774          */
 775         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 776                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 777
 778         if (dwc->dis_u2_susphy_quirk)
 779                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 780
 781         if (dwc->dis_enblslpm_quirk)
 782                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 783         else
 784                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 785
 786         if (dwc->dis_u2_freeclk_exists_quirk)
 787                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 788
 789         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 790
 791         return 0;
 792 }
 793
 794 static int dwc3_clk_enable(struct dwc3 *dwc)
 795 {
 796         int ret;
 797
 798         ret = clk_prepare_enable(dwc->bus_clk);
 799         if (ret)
 800                 return ret;
 801
 802         ret = clk_prepare_enable(dwc->ref_clk);
 803         if (ret)
 804                 goto disable_bus_clk;
 805
 806         ret = clk_prepare_enable(dwc->susp_clk);
 807         if (ret)
 808                 goto disable_ref_clk;
 809
 810         return 0;
 811
 812 disable_ref_clk:
 813         clk_disable_unprepare(dwc->ref_clk);
 814 disable_bus_clk:
 815         clk_disable_unprepare(dwc->bus_clk);
 816         return ret;
 817 }
 818
 819 static void dwc3_clk_disable(struct dwc3 *dwc)
 820 {
 821         clk_disable_unprepare(dwc->susp_clk);
 822         clk_disable_unprepare(dwc->ref_clk);
 823         clk_disable_unprepare(dwc->bus_clk);
 824 }
 825
 826 static void dwc3_core_exit(struct dwc3 *dwc)
 827 {
 828         dwc3_event_buffers_cleanup(dwc);
 829
 830         usb_phy_shutdown(dwc->usb2_phy);
 831         usb_phy_shutdown(dwc->usb3_phy);
 832         phy_exit(dwc->usb2_generic_phy);
 833         phy_exit(dwc->usb3_generic_phy);
 834
 835         usb_phy_set_suspend(dwc->usb2_phy, 1);
 836         usb_phy_set_suspend(dwc->usb3_phy, 1);
 837         phy_power_off(dwc->usb2_generic_phy);
 838         phy_power_off(dwc->usb3_generic_phy);
 839         dwc3_clk_disable(dwc);
 840         reset_control_assert(dwc->reset);
 841 }
 842
 843 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 844 {
 845         u32 reg;
 846
 847         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 848         dwc->ip = DWC3_GSNPS_ID(reg);
 849
 850         /* This should read as U3 followed by revision number */
 851         if (DWC3_IP_IS(DWC3)) {
 852                 dwc->revision = reg;
 853         } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
 854                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 855                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 856         } else {
 857                 return false;
 858         }
 859
 860         return true;
 861 }
 862
 863 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 864 {
 865         u32 hwparams4 = dwc->hwparams.hwparams4;
 866         u32 reg;
 867
 868         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 869         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 870
 871         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 872         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 873                 /**
 874                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 875                  * issue which would cause xHCI compliance tests to fail.
 876                  *
 877                  * Because of that we cannot enable clock gating on such
 878                  * configurations.
 879                  *
 880                  * Refers to:
 881                  *
 882                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 883                  * SOF/ITP Mode Used
 884                  */
 885                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 886                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 887                                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
 888                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 889                 else
 890                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 891                 break;
 892         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 893                 /* enable hibernation here */
 894                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 895
 896                 /*
 897                  * REVISIT Enabling this bit so that host-mode hibernation
 898                  * will work. Device-mode hibernation is not yet implemented.
 899                  */
 900                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 901                 break;
 902         default:
 903                 /* nothing */
 904                 break;
 905         }
 906
 907         /* check if current dwc3 is on simulation board */
 908         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 909                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 910                 dwc->is_fpga = true;
 911         }
 912
 913         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 914                         "disable_scramble cannot be used on non-FPGA builds\n");
 915
 916         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 917                 reg |= DWC3_GCTL_DISSCRAMBLE;
 918         else
 919                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 920
 921         if (dwc->u2exit_lfps_quirk)
 922                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 923
 924         /*
 925          * WORKAROUND: DWC3 revisions <1.90a have a bug
 926          * where the device can fail to connect at SuperSpeed
 927          * and falls back to high-speed mode which causes
 928          * the device to enter a Connect/Disconnect loop
 929          */
 930         if (DWC3_VER_IS_PRIOR(DWC3, 190A))
 931                 reg |= DWC3_GCTL_U2RSTECN;
 932
 933         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 934 }
 935
 936 static int dwc3_core_get_phy(struct dwc3 *dwc);
 937 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 938
 939 /* set global incr burst type configuration registers */
 940 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 941 {
 942         struct device *dev = dwc->dev;
 943         /* incrx_mode : for INCR burst type. */
 944         bool incrx_mode;
 945         /* incrx_size : for size of INCRX burst. */
 946         u32 incrx_size;
 947         u32 *vals;
 948         u32 cfg;
 949         int ntype;
 950         int ret;
 951         int i;
 952
 953         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 954
 955         /*
 956          * Handle property "snps,incr-burst-type-adjustment".
 957          * Get the number of value from this property:
 958          * result <= 0, means this property is not supported.
 959          * result = 1, means INCRx burst mode supported.
 960          * result > 1, means undefined length burst mode supported.
 961          */
 962         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 963         if (ntype <= 0)
 964                 return;
 965
 966         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 967         if (!vals)
 968                 return;
 969
 970         /* Get INCR burst type, and parse it */
 971         ret = device_property_read_u32_array(dev,
 972                         "snps,incr-burst-type-adjustment", vals, ntype);
 973         if (ret) {
 974                 kfree(vals);
 975                 dev_err(dev, "Error to get property\n");
 976                 return;
 977         }
 978
 979         incrx_size = *vals;
 980
 981         if (ntype > 1) {
 982                 /* INCRX (undefined length) burst mode */
 983                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 984                 for (i = 1; i < ntype; i++) {
 985                         if (vals[i] > incrx_size)
 986                                 incrx_size = vals[i];
 987                 }
 988         } else {
 989                 /* INCRX burst mode */
 990                 incrx_mode = INCRX_BURST_MODE;
 991         }
 992
 993         kfree(vals);
 994
 995         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 996         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 997         if (incrx_mode)
 998                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 999         switch (incrx_size) {
1000         case 256:
1001                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1002                 break;
1003         case 128:
1004                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1005                 break;
1006         case 64:
1007                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1008                 break;
1009         case 32:
1010                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1011                 break;
1012         case 16:
1013                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1014                 break;
1015         case 8:
1016                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1017                 break;
1018         case 4:
1019                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1020                 break;
1021         case 1:
1022                 break;
1023         default:
1024                 dev_err(dev, "Invalid property\n");
1025                 break;
1026         }
1027
1028         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1029 }
1030
1031 /**
1032  * dwc3_core_init - Low-level initialization of DWC3 Core
1033  * @dwc: Pointer to our controller context structure
1034  *
1035  * Returns 0 on success otherwise negative errno.
1036  */
1037 static int dwc3_core_init(struct dwc3 *dwc)
1038 {
1039         unsigned int            hw_mode;
1040         u32                     reg;
1041         int                     ret;
1042
1043         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1044
1045         /*
1046          * Write Linux Version Code to our GUID register so it's easy to figure
1047          * out which kernel version a bug was found.
1048          */
1049         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1050
1051         ret = dwc3_phy_setup(dwc);
1052         if (ret)
1053                 goto err0;
1054
1055         if (!dwc->ulpi_ready) {
1056                 ret = dwc3_core_ulpi_init(dwc);
1057                 if (ret)
1058                         goto err0;
1059                 dwc->ulpi_ready = true;
1060         }
1061
1062         if (!dwc->phys_ready) {
1063                 ret = dwc3_core_get_phy(dwc);
1064                 if (ret)
1065                         goto err0a;
1066                 dwc->phys_ready = true;
1067         }
1068
1069         usb_phy_init(dwc->usb2_phy);
1070         usb_phy_init(dwc->usb3_phy);
1071         ret = phy_init(dwc->usb2_generic_phy);
1072         if (ret < 0)
1073                 goto err0a;
1074
1075         ret = phy_init(dwc->usb3_generic_phy);
1076         if (ret < 0) {
1077                 phy_exit(dwc->usb2_generic_phy);
1078                 goto err0a;
1079         }
1080
1081         ret = dwc3_core_soft_reset(dwc);
1082         if (ret)
1083                 goto err1;
1084
1085         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1086             !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1087                 if (!dwc->dis_u3_susphy_quirk) {
1088                         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1089                         reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1090                         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1091                 }
1092
1093                 if (!dwc->dis_u2_susphy_quirk) {
1094                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1095                         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1096                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1097                 }
1098         }
1099
1100         dwc3_core_setup_global_control(dwc);
1101         dwc3_core_num_eps(dwc);
1102
1103         ret = dwc3_setup_scratch_buffers(dwc);
1104         if (ret)
1105                 goto err1;
1106
1107         /* Adjust Frame Length */
1108         dwc3_frame_length_adjustment(dwc);
1109
1110         /* Adjust Reference Clock Period */
1111         dwc3_ref_clk_period(dwc);
1112
1113         dwc3_set_incr_burst_type(dwc);
1114
1115         usb_phy_set_suspend(dwc->usb2_phy, 0);
1116         usb_phy_set_suspend(dwc->usb3_phy, 0);
1117         ret = phy_power_on(dwc->usb2_generic_phy);
1118         if (ret < 0)
1119                 goto err2;
1120
1121         ret = phy_power_on(dwc->usb3_generic_phy);
1122         if (ret < 0)
1123                 goto err3;
1124
1125         ret = dwc3_event_buffers_setup(dwc);
1126         if (ret) {
1127                 dev_err(dwc->dev, "failed to setup event buffers\n");
1128                 goto err4;
1129         }
1130
1131         /*
1132          * ENDXFER polling is available on version 3.10a and later of
1133          * the DWC_usb3 controller. It is NOT available in the
1134          * DWC_usb31 controller.
1135          */
1136         if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1137                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1138                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1139                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1140         }
1141
1142         if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1143                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1144
1145                 /*
1146                  * Enable hardware control of sending remote wakeup
1147                  * in HS when the device is in the L1 state.
1148                  */
1149                 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1150                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1151
1152                 /*
1153                  * Decouple USB 2.0 L1 & L2 events which will allow for
1154                  * gadget driver to only receive U3/L2 suspend & wakeup
1155                  * events and prevent the more frequent L1 LPM transitions
1156                  * from interrupting the driver.
1157                  */
1158                 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1159                         reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1160
1161                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1162                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1163
1164                 if (dwc->parkmode_disable_ss_quirk)
1165                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1166
1167                 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1168                     (dwc->maximum_speed == USB_SPEED_HIGH ||
1169                      dwc->maximum_speed == USB_SPEED_FULL))
1170                         reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1171
1172                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1173         }
1174
1175         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1176             dwc->dr_mode == USB_DR_MODE_OTG) {
1177                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1178
1179                 /*
1180                  * Enable Auto retry Feature to make the controller operating in
1181                  * Host mode on seeing transaction errors(CRC errors or internal
1182                  * overrun scenerios) on IN transfers to reply to the device
1183                  * with a non-terminating retry ACK (i.e, an ACK transcation
1184                  * packet with Retry=1 & Nump != 0)
1185                  */
1186                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1187
1188                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1189         }
1190
1191         /*
1192          * Must config both number of packets and max burst settings to enable
1193          * RX and/or TX threshold.
1194          */
1195         if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1196                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1197                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1198                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1199                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1200
1201                 if (rx_thr_num && rx_maxburst) {
1202                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1203                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1204
1205                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1206                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1207
1208                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1209                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1210
1211                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1212                 }
1213
1214                 if (tx_thr_num && tx_maxburst) {
1215                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1216                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1217
1218                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1219                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1220
1221                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1222                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1223
1224                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1225                 }
1226         }
1227
1228         return 0;
1229
1230 err4:
1231         phy_power_off(dwc->usb3_generic_phy);
1232
1233 err3:
1234         phy_power_off(dwc->usb2_generic_phy);
1235
1236 err2:
1237         usb_phy_set_suspend(dwc->usb2_phy, 1);
1238         usb_phy_set_suspend(dwc->usb3_phy, 1);
1239
1240 err1:
1241         usb_phy_shutdown(dwc->usb2_phy);
1242         usb_phy_shutdown(dwc->usb3_phy);
1243         phy_exit(dwc->usb2_generic_phy);
1244         phy_exit(dwc->usb3_generic_phy);
1245
1246 err0a:
1247         dwc3_ulpi_exit(dwc);
1248
1249 err0:
1250         return ret;
1251 }
1252
1253 static int dwc3_core_get_phy(struct dwc3 *dwc)
1254 {
1255         struct device           *dev = dwc->dev;
1256         struct device_node      *node = dev->of_node;
1257         int ret;
1258
1259         if (node) {
1260                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1261                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1262         } else {
1263                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1264                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1265         }
1266
1267         if (IS_ERR(dwc->usb2_phy)) {
1268                 ret = PTR_ERR(dwc->usb2_phy);
1269                 if (ret == -ENXIO || ret == -ENODEV)
1270                         dwc->usb2_phy = NULL;
1271                 else
1272                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1273         }
1274
1275         if (IS_ERR(dwc->usb3_phy)) {
1276                 ret = PTR_ERR(dwc->usb3_phy);
1277                 if (ret == -ENXIO || ret == -ENODEV)
1278                         dwc->usb3_phy = NULL;
1279                 else
1280                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1281         }
1282
1283         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1284         if (IS_ERR(dwc->usb2_generic_phy)) {
1285                 ret = PTR_ERR(dwc->usb2_generic_phy);
1286                 if (ret == -ENOSYS || ret == -ENODEV)
1287                         dwc->usb2_generic_phy = NULL;
1288                 else
1289                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1290         }
1291
1292         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1293         if (IS_ERR(dwc->usb3_generic_phy)) {
1294                 ret = PTR_ERR(dwc->usb3_generic_phy);
1295                 if (ret == -ENOSYS || ret == -ENODEV)
1296                         dwc->usb3_generic_phy = NULL;
1297                 else
1298                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1299         }
1300
1301         return 0;
1302 }
1303
1304 static int dwc3_core_init_mode(struct dwc3 *dwc)
1305 {
1306         struct device *dev = dwc->dev;
1307         int ret;
1308
1309         switch (dwc->dr_mode) {
1310         case USB_DR_MODE_PERIPHERAL:
1311                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1312
1313                 if (dwc->usb2_phy)
1314                         otg_set_vbus(dwc->usb2_phy->otg, false);
1315                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1316                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1317
1318                 ret = dwc3_gadget_init(dwc);
1319                 if (ret)
1320                         return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1321                 break;
1322         case USB_DR_MODE_HOST:
1323                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1324
1325                 if (dwc->usb2_phy)
1326                         otg_set_vbus(dwc->usb2_phy->otg, true);
1327                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1328                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1329
1330                 ret = dwc3_host_init(dwc);
1331                 if (ret)
1332                         return dev_err_probe(dev, ret, "failed to initialize host\n");
1333                 break;
1334         case USB_DR_MODE_OTG:
1335                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1336                 ret = dwc3_drd_init(dwc);
1337                 if (ret)
1338                         return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1339                 break;
1340         default:
1341                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1342                 return -EINVAL;
1343         }
1344
1345         return 0;
1346 }
1347
1348 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1349 {
1350         switch (dwc->dr_mode) {
1351         case USB_DR_MODE_PERIPHERAL:
1352                 dwc3_gadget_exit(dwc);
1353                 break;
1354         case USB_DR_MODE_HOST:
1355                 dwc3_host_exit(dwc);
1356                 break;
1357         case USB_DR_MODE_OTG:
1358                 dwc3_drd_exit(dwc);
1359                 break;
1360         default:
1361                 /* do nothing */
1362                 break;
1363         }
1364
1365         /* de-assert DRVVBUS for HOST and OTG mode */
1366         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1367 }
1368
1369 static void dwc3_get_properties(struct dwc3 *dwc)
1370 {
1371         struct device           *dev = dwc->dev;
1372         u8                      lpm_nyet_threshold;
1373         u8                      tx_de_emphasis;
1374         u8                      hird_threshold;
1375         u8                      rx_thr_num_pkt_prd = 0;
1376         u8                      rx_max_burst_prd = 0;
1377         u8                      tx_thr_num_pkt_prd = 0;
1378         u8                      tx_max_burst_prd = 0;
1379         u8                      tx_fifo_resize_max_num;
1380         const char              *usb_psy_name;
1381         int                     ret;
1382
1383         /* default to highest possible threshold */
1384         lpm_nyet_threshold = 0xf;
1385
1386         /* default to -3.5dB de-emphasis */
1387         tx_de_emphasis = 1;
1388
1389         /*
1390          * default to assert utmi_sleep_n and use maximum allowed HIRD
1391          * threshold value of 0b1100
1392          */
1393         hird_threshold = 12;
1394
1395         /*
1396          * default to a TXFIFO size large enough to fit 6 max packets.  This
1397          * allows for systems with larger bus latencies to have some headroom
1398          * for endpoints that have a large bMaxBurst value.
1399          */
1400         tx_fifo_resize_max_num = 6;
1401
1402         dwc->maximum_speed = usb_get_maximum_speed(dev);
1403         dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1404         dwc->dr_mode = usb_get_dr_mode(dev);
1405         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1406
1407         dwc->sysdev_is_parent = device_property_read_bool(dev,
1408                                 "linux,sysdev_is_parent");
1409         if (dwc->sysdev_is_parent)
1410                 dwc->sysdev = dwc->dev->parent;
1411         else
1412                 dwc->sysdev = dwc->dev;
1413
1414         ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1415         if (ret >= 0) {
1416                 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1417                 if (!dwc->usb_psy)
1418                         dev_err(dev, "couldn't get usb power supply\n");
1419         }
1420
1421         dwc->has_lpm_erratum = device_property_read_bool(dev,
1422                                 "snps,has-lpm-erratum");
1423         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1424                                 &lpm_nyet_threshold);
1425         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1426                                 "snps,is-utmi-l1-suspend");
1427         device_property_read_u8(dev, "snps,hird-threshold",
1428                                 &hird_threshold);
1429         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1430                                 "snps,dis-start-transfer-quirk");
1431         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1432                                 "snps,usb3_lpm_capable");
1433         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1434                                 "snps,usb2-lpm-disable");
1435         dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1436                                 "snps,usb2-gadget-lpm-disable");
1437         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1438                                 &rx_thr_num_pkt_prd);
1439         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1440                                 &rx_max_burst_prd);
1441         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1442                                 &tx_thr_num_pkt_prd);
1443         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1444                                 &tx_max_burst_prd);
1445         dwc->do_fifo_resize = device_property_read_bool(dev,
1446                                                         "tx-fifo-resize");
1447         if (dwc->do_fifo_resize)
1448                 device_property_read_u8(dev, "tx-fifo-max-num",
1449                                         &tx_fifo_resize_max_num);
1450
1451         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1452                                 "snps,disable_scramble_quirk");
1453         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1454                                 "snps,u2exit_lfps_quirk");
1455         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1456                                 "snps,u2ss_inp3_quirk");
1457         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1458                                 "snps,req_p1p2p3_quirk");
1459         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1460                                 "snps,del_p1p2p3_quirk");
1461         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1462                                 "snps,del_phy_power_chg_quirk");
1463         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1464                                 "snps,lfps_filter_quirk");
1465         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1466                                 "snps,rx_detect_poll_quirk");
1467         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1468                                 "snps,dis_u3_susphy_quirk");
1469         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1470                                 "snps,dis_u2_susphy_quirk");
1471         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1472                                 "snps,dis_enblslpm_quirk");
1473         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1474                                 "snps,dis-u1-entry-quirk");
1475         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1476                                 "snps,dis-u2-entry-quirk");
1477         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1478                                 "snps,dis_rxdet_inp3_quirk");
1479         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1480                                 "snps,dis-u2-freeclk-exists-quirk");
1481         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1482                                 "snps,dis-del-phy-power-chg-quirk");
1483         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1484                                 "snps,dis-tx-ipgap-linecheck-quirk");
1485         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1486                                 "snps,parkmode-disable-ss-quirk");
1487
1488         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1489                                 "snps,tx_de_emphasis_quirk");
1490         device_property_read_u8(dev, "snps,tx_de_emphasis",
1491                                 &tx_de_emphasis);
1492         device_property_read_string(dev, "snps,hsphy_interface",
1493                                     &dwc->hsphy_interface);
1494         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1495                                  &dwc->fladj);
1496         device_property_read_u32(dev, "snps,ref-clock-period-ns",
1497                                  &dwc->ref_clk_per);
1498
1499         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1500                                 "snps,dis_metastability_quirk");
1501
1502         dwc->dis_split_quirk = device_property_read_bool(dev,
1503                                 "snps,dis-split-quirk");
1504
1505         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1506         dwc->tx_de_emphasis = tx_de_emphasis;
1507
1508         dwc->hird_threshold = hird_threshold;
1509
1510         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1511         dwc->rx_max_burst_prd = rx_max_burst_prd;
1512
1513         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1514         dwc->tx_max_burst_prd = tx_max_burst_prd;
1515
1516         dwc->imod_interval = 0;
1517
1518         dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1519 }
1520
1521 /* check whether the core supports IMOD */
1522 bool dwc3_has_imod(struct dwc3 *dwc)
1523 {
1524         return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1525                 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1526                 DWC3_IP_IS(DWC32);
1527 }
1528
1529 static void dwc3_check_params(struct dwc3 *dwc)
1530 {
1531         struct device *dev = dwc->dev;
1532         unsigned int hwparam_gen =
1533                 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1534
1535         /* Check for proper value of imod_interval */
1536         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1537                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1538                 dwc->imod_interval = 0;
1539         }
1540
1541         /*
1542          * Workaround for STAR 9000961433 which affects only version
1543          * 3.00a of the DWC_usb3 core. This prevents the controller
1544          * interrupt from being masked while handling events. IMOD
1545          * allows us to work around this issue. Enable it for the
1546          * affected version.
1547          */
1548         if (!dwc->imod_interval &&
1549             DWC3_VER_IS(DWC3, 300A))
1550                 dwc->imod_interval = 1;
1551
1552         /* Check the maximum_speed parameter */
1553         switch (dwc->maximum_speed) {
1554         case USB_SPEED_FULL:
1555         case USB_SPEED_HIGH:
1556                 break;
1557         case USB_SPEED_SUPER:
1558                 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1559                         dev_warn(dev, "UDC doesn't support Gen 1\n");
1560                 break;
1561         case USB_SPEED_SUPER_PLUS:
1562                 if ((DWC3_IP_IS(DWC32) &&
1563                      hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1564                     (!DWC3_IP_IS(DWC32) &&
1565                      hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1566                         dev_warn(dev, "UDC doesn't support SSP\n");
1567                 break;
1568         default:
1569                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1570                         dwc->maximum_speed);
1571                 fallthrough;
1572         case USB_SPEED_UNKNOWN:
1573                 switch (hwparam_gen) {
1574                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1575                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1576                         break;
1577                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1578                         if (DWC3_IP_IS(DWC32))
1579                                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1580                         else
1581                                 dwc->maximum_speed = USB_SPEED_SUPER;
1582                         break;
1583                 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1584                         dwc->maximum_speed = USB_SPEED_HIGH;
1585                         break;
1586                 default:
1587                         dwc->maximum_speed = USB_SPEED_SUPER;
1588                         break;
1589                 }
1590                 break;
1591         }
1592
1593         /*
1594          * Currently the controller does not have visibility into the HW
1595          * parameter to determine the maximum number of lanes the HW supports.
1596          * If the number of lanes is not specified in the device property, then
1597          * set the default to support dual-lane for DWC_usb32 and single-lane
1598          * for DWC_usb31 for super-speed-plus.
1599          */
1600         if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1601                 switch (dwc->max_ssp_rate) {
1602                 case USB_SSP_GEN_2x1:
1603                         if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1604                                 dev_warn(dev, "UDC only supports Gen 1\n");
1605                         break;
1606                 case USB_SSP_GEN_1x2:
1607                 case USB_SSP_GEN_2x2:
1608                         if (DWC3_IP_IS(DWC31))
1609                                 dev_warn(dev, "UDC only supports single lane\n");
1610                         break;
1611                 case USB_SSP_GEN_UNKNOWN:
1612                 default:
1613                         switch (hwparam_gen) {
1614                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1615                                 if (DWC3_IP_IS(DWC32))
1616                                         dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1617                                 else
1618                                         dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1619                                 break;
1620                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1621                                 if (DWC3_IP_IS(DWC32))
1622                                         dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1623                                 break;
1624                         }
1625                         break;
1626                 }
1627         }
1628 }
1629
1630 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1631 {
1632         struct device *dev = dwc->dev;
1633         struct device_node *np_phy;
1634         struct extcon_dev *edev = NULL;
1635         const char *name;
1636
1637         if (device_property_read_bool(dev, "extcon"))
1638                 return extcon_get_edev_by_phandle(dev, 0);
1639
1640         /*
1641          * Device tree platforms should get extcon via phandle.
1642          * On ACPI platforms, we get the name from a device property.
1643          * This device property is for kernel internal use only and
1644          * is expected to be set by the glue code.
1645          */
1646         if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) {
1647                 edev = extcon_get_extcon_dev(name);
1648                 if (!edev)
1649                         return ERR_PTR(-EPROBE_DEFER);
1650
1651                 return edev;
1652         }
1653
1654         /*
1655          * Try to get an extcon device from the USB PHY controller's "port"
1656          * node. Check if it has the "port" node first, to avoid printing the
1657          * error message from underlying code, as it's a valid case: extcon
1658          * device (and "port" node) may be missing in case of "usb-role-switch"
1659          * or OTG mode.
1660          */
1661         np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1662         if (of_graph_is_present(np_phy)) {
1663                 struct device_node *np_conn;
1664
1665                 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1666                 if (np_conn)
1667                         edev = extcon_find_edev_by_node(np_conn);
1668                 of_node_put(np_conn);
1669         }
1670         of_node_put(np_phy);
1671
1672         return edev;
1673 }
1674
1675 static int dwc3_probe(struct platform_device *pdev)
1676 {
1677         struct device           *dev = &pdev->dev;
1678         struct resource         *res, dwc_res;
1679         struct dwc3             *dwc;
1680
1681         int                     ret;
1682
1683         void __iomem            *regs;
1684
1685         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1686         if (!dwc)
1687                 return -ENOMEM;
1688
1689         dwc->dev = dev;
1690
1691         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1692         if (!res) {
1693                 dev_err(dev, "missing memory resource\n");
1694                 return -ENODEV;
1695         }
1696
1697         dwc->xhci_resources[0].start = res->start;
1698         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1699                                         DWC3_XHCI_REGS_END;
1700         dwc->xhci_resources[0].flags = res->flags;
1701         dwc->xhci_resources[0].name = res->name;
1702
1703         /*
1704          * Request memory region but exclude xHCI regs,
1705          * since it will be requested by the xhci-plat driver.
1706          */
1707         dwc_res = *res;
1708         dwc_res.start += DWC3_GLOBALS_REGS_START;
1709
1710         regs = devm_ioremap_resource(dev, &dwc_res);
1711         if (IS_ERR(regs))
1712                 return PTR_ERR(regs);
1713
1714         dwc->regs       = regs;
1715         dwc->regs_size  = resource_size(&dwc_res);
1716
1717         dwc3_get_properties(dwc);
1718
1719         if (!dwc->sysdev_is_parent) {
1720                 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1721                 if (ret)
1722                         return ret;
1723         }
1724
1725         dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1726         if (IS_ERR(dwc->reset))
1727                 return PTR_ERR(dwc->reset);
1728
1729         if (dev->of_node) {
1730                 /*
1731                  * Clocks are optional, but new DT platforms should support all
1732                  * clocks as required by the DT-binding.
1733                  * Some devices have different clock names in legacy device trees,
1734                  * check for them to retain backwards compatibility.
1735                  */
1736                 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1737                 if (IS_ERR(dwc->bus_clk))
1738                         return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1739                                              "could not get bus clock\n");
1740
1741                 if (dwc->bus_clk == NULL) {
1742                         dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1743                         if (IS_ERR(dwc->bus_clk))
1744                                 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1745                                                      "could not get bus clock\n");
1746                 }
1747
1748                 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1749                 if (IS_ERR(dwc->ref_clk))
1750                         return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1751                                              "could not get ref clock\n");
1752
1753                 if (dwc->ref_clk == NULL) {
1754                         dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1755                         if (IS_ERR(dwc->ref_clk))
1756                                 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1757                                                      "could not get ref clock\n");
1758                 }
1759
1760                 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1761                 if (IS_ERR(dwc->susp_clk))
1762                         return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1763                                              "could not get suspend clock\n");
1764
1765                 if (dwc->susp_clk == NULL) {
1766                         dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1767                         if (IS_ERR(dwc->susp_clk))
1768                                 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1769                                                      "could not get suspend clock\n");
1770                 }
1771         }
1772
1773         ret = reset_control_deassert(dwc->reset);
1774         if (ret)
1775                 return ret;
1776
1777         ret = dwc3_clk_enable(dwc);
1778         if (ret)
1779                 goto assert_reset;
1780
1781         if (!dwc3_core_is_valid(dwc)) {
1782                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1783                 ret = -ENODEV;
1784                 goto disable_clks;
1785         }
1786
1787         platform_set_drvdata(pdev, dwc);
1788         dwc3_cache_hwparams(dwc);
1789
1790         spin_lock_init(&dwc->lock);
1791         mutex_init(&dwc->mutex);
1792
1793         pm_runtime_set_active(dev);
1794         pm_runtime_use_autosuspend(dev);
1795         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1796         pm_runtime_enable(dev);
1797         ret = pm_runtime_get_sync(dev);
1798         if (ret < 0)
1799                 goto err1;
1800
1801         pm_runtime_forbid(dev);
1802
1803         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1804         if (ret) {
1805                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1806                 ret = -ENOMEM;
1807                 goto err2;
1808         }
1809
1810         dwc->edev = dwc3_get_extcon(dwc);
1811         if (IS_ERR(dwc->edev)) {
1812                 ret = PTR_ERR(dwc->edev);
1813                 dev_err_probe(dwc->dev, ret, "failed to get extcon\n");
1814                 goto err3;
1815         }
1816
1817         ret = dwc3_get_dr_mode(dwc);
1818         if (ret)
1819                 goto err3;
1820
1821         ret = dwc3_alloc_scratch_buffers(dwc);
1822         if (ret)
1823                 goto err3;
1824
1825         ret = dwc3_core_init(dwc);
1826         if (ret) {
1827                 dev_err_probe(dev, ret, "failed to initialize core\n");
1828                 goto err4;
1829         }
1830
1831         dwc3_check_params(dwc);
1832         dwc3_debugfs_init(dwc);
1833
1834         ret = dwc3_core_init_mode(dwc);
1835         if (ret)
1836                 goto err5;
1837
1838         pm_runtime_put(dev);
1839
1840         return 0;
1841
1842 err5:
1843         dwc3_debugfs_exit(dwc);
1844         dwc3_event_buffers_cleanup(dwc);
1845
1846         usb_phy_shutdown(dwc->usb2_phy);
1847         usb_phy_shutdown(dwc->usb3_phy);
1848         phy_exit(dwc->usb2_generic_phy);
1849         phy_exit(dwc->usb3_generic_phy);
1850
1851         usb_phy_set_suspend(dwc->usb2_phy, 1);
1852         usb_phy_set_suspend(dwc->usb3_phy, 1);
1853         phy_power_off(dwc->usb2_generic_phy);
1854         phy_power_off(dwc->usb3_generic_phy);
1855
1856         dwc3_ulpi_exit(dwc);
1857
1858 err4:
1859         dwc3_free_scratch_buffers(dwc);
1860
1861 err3:
1862         dwc3_free_event_buffers(dwc);
1863
1864 err2:
1865         pm_runtime_allow(&pdev->dev);
1866
1867 err1:
1868         pm_runtime_put_sync(&pdev->dev);
1869         pm_runtime_disable(&pdev->dev);
1870
1871 disable_clks:
1872         dwc3_clk_disable(dwc);
1873 assert_reset:
1874         reset_control_assert(dwc->reset);
1875
1876         if (dwc->usb_psy)
1877                 power_supply_put(dwc->usb_psy);
1878
1879         return ret;
1880 }
1881
1882 static int dwc3_remove(struct platform_device *pdev)
1883 {
1884         struct dwc3     *dwc = platform_get_drvdata(pdev);
1885
1886         pm_runtime_get_sync(&pdev->dev);
1887
1888         dwc3_core_exit_mode(dwc);
1889         dwc3_debugfs_exit(dwc);
1890
1891         dwc3_core_exit(dwc);
1892         dwc3_ulpi_exit(dwc);
1893
1894         pm_runtime_disable(&pdev->dev);
1895         pm_runtime_put_noidle(&pdev->dev);
1896         pm_runtime_set_suspended(&pdev->dev);
1897
1898         dwc3_free_event_buffers(dwc);
1899         dwc3_free_scratch_buffers(dwc);
1900
1901         if (dwc->usb_psy)
1902                 power_supply_put(dwc->usb_psy);
1903
1904         return 0;
1905 }
1906
1907 #ifdef CONFIG_PM
1908 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1909 {
1910         int ret;
1911
1912         ret = reset_control_deassert(dwc->reset);
1913         if (ret)
1914                 return ret;
1915
1916         ret = dwc3_clk_enable(dwc);
1917         if (ret)
1918                 goto assert_reset;
1919
1920         ret = dwc3_core_init(dwc);
1921         if (ret)
1922                 goto disable_clks;
1923
1924         return 0;
1925
1926 disable_clks:
1927         dwc3_clk_disable(dwc);
1928 assert_reset:
1929         reset_control_assert(dwc->reset);
1930
1931         return ret;
1932 }
1933
1934 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1935 {
1936         unsigned long   flags;
1937         u32 reg;
1938
1939         switch (dwc->current_dr_role) {
1940         case DWC3_GCTL_PRTCAP_DEVICE:
1941                 if (pm_runtime_suspended(dwc->dev))
1942                         break;
1943                 spin_lock_irqsave(&dwc->lock, flags);
1944                 dwc3_gadget_suspend(dwc);
1945                 spin_unlock_irqrestore(&dwc->lock, flags);
1946                 synchronize_irq(dwc->irq_gadget);
1947                 dwc3_core_exit(dwc);
1948                 break;
1949         case DWC3_GCTL_PRTCAP_HOST:
1950                 if (!PMSG_IS_AUTO(msg)) {
1951                         dwc3_core_exit(dwc);
1952                         break;
1953                 }
1954
1955                 /* Let controller to suspend HSPHY before PHY driver suspends */
1956                 if (dwc->dis_u2_susphy_quirk ||
1957                     dwc->dis_enblslpm_quirk) {
1958                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1959                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1960                                 DWC3_GUSB2PHYCFG_SUSPHY;
1961                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1962
1963                         /* Give some time for USB2 PHY to suspend */
1964                         usleep_range(5000, 6000);
1965                 }
1966
1967                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1968                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1969                 break;
1970         case DWC3_GCTL_PRTCAP_OTG:
1971                 /* do nothing during runtime_suspend */
1972                 if (PMSG_IS_AUTO(msg))
1973                         break;
1974
1975                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1976                         spin_lock_irqsave(&dwc->lock, flags);
1977                         dwc3_gadget_suspend(dwc);
1978                         spin_unlock_irqrestore(&dwc->lock, flags);
1979                         synchronize_irq(dwc->irq_gadget);
1980                 }
1981
1982                 dwc3_otg_exit(dwc);
1983                 dwc3_core_exit(dwc);
1984                 break;
1985         default:
1986                 /* do nothing */
1987                 break;
1988         }
1989
1990         return 0;
1991 }
1992
1993 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1994 {
1995         unsigned long   flags;
1996         int             ret;
1997         u32             reg;
1998
1999         switch (dwc->current_dr_role) {
2000         case DWC3_GCTL_PRTCAP_DEVICE:
2001                 ret = dwc3_core_init_for_resume(dwc);
2002                 if (ret)
2003                         return ret;
2004
2005                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2006                 spin_lock_irqsave(&dwc->lock, flags);
2007                 dwc3_gadget_resume(dwc);
2008                 spin_unlock_irqrestore(&dwc->lock, flags);
2009                 break;
2010         case DWC3_GCTL_PRTCAP_HOST:
2011                 if (!PMSG_IS_AUTO(msg)) {
2012                         ret = dwc3_core_init_for_resume(dwc);
2013                         if (ret)
2014                                 return ret;
2015                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2016                         break;
2017                 }
2018                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2019                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2020                 if (dwc->dis_u2_susphy_quirk)
2021                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2022
2023                 if (dwc->dis_enblslpm_quirk)
2024                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2025
2026                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2027
2028                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2029                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2030                 break;
2031         case DWC3_GCTL_PRTCAP_OTG:
2032                 /* nothing to do on runtime_resume */
2033                 if (PMSG_IS_AUTO(msg))
2034                         break;
2035
2036                 ret = dwc3_core_init_for_resume(dwc);
2037                 if (ret)
2038                         return ret;
2039
2040                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2041
2042                 dwc3_otg_init(dwc);
2043                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2044                         dwc3_otg_host_init(dwc);
2045                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2046                         spin_lock_irqsave(&dwc->lock, flags);
2047                         dwc3_gadget_resume(dwc);
2048                         spin_unlock_irqrestore(&dwc->lock, flags);
2049                 }
2050
2051                 break;
2052         default:
2053                 /* do nothing */
2054                 break;
2055         }
2056
2057         return 0;
2058 }
2059
2060 static int dwc3_runtime_checks(struct dwc3 *dwc)
2061 {
2062         switch (dwc->current_dr_role) {
2063         case DWC3_GCTL_PRTCAP_DEVICE:
2064                 if (dwc->connected)
2065                         return -EBUSY;
2066                 break;
2067         case DWC3_GCTL_PRTCAP_HOST:
2068         default:
2069                 /* do nothing */
2070                 break;
2071         }
2072
2073         return 0;
2074 }
2075
2076 static int dwc3_runtime_suspend(struct device *dev)
2077 {
2078         struct dwc3     *dwc = dev_get_drvdata(dev);
2079         int             ret;
2080
2081         if (dwc3_runtime_checks(dwc))
2082                 return -EBUSY;
2083
2084         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2085         if (ret)
2086                 return ret;
2087
2088         device_init_wakeup(dev, true);
2089
2090         return 0;
2091 }
2092
2093 static int dwc3_runtime_resume(struct device *dev)
2094 {
2095         struct dwc3     *dwc = dev_get_drvdata(dev);
2096         int             ret;
2097
2098         device_init_wakeup(dev, false);
2099
2100         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2101         if (ret)
2102                 return ret;
2103
2104         switch (dwc->current_dr_role) {
2105         case DWC3_GCTL_PRTCAP_DEVICE:
2106                 dwc3_gadget_process_pending_events(dwc);
2107                 break;
2108         case DWC3_GCTL_PRTCAP_HOST:
2109         default:
2110                 /* do nothing */
2111                 break;
2112         }
2113
2114         pm_runtime_mark_last_busy(dev);
2115
2116         return 0;
2117 }
2118
2119 static int dwc3_runtime_idle(struct device *dev)
2120 {
2121         struct dwc3     *dwc = dev_get_drvdata(dev);
2122
2123         switch (dwc->current_dr_role) {
2124         case DWC3_GCTL_PRTCAP_DEVICE:
2125                 if (dwc3_runtime_checks(dwc))
2126                         return -EBUSY;
2127                 break;
2128         case DWC3_GCTL_PRTCAP_HOST:
2129         default:
2130                 /* do nothing */
2131                 break;
2132         }
2133
2134         pm_runtime_mark_last_busy(dev);
2135         pm_runtime_autosuspend(dev);
2136
2137         return 0;
2138 }
2139 #endif /* CONFIG_PM */
2140
2141 #ifdef CONFIG_PM_SLEEP
2142 static int dwc3_suspend(struct device *dev)
2143 {
2144         struct dwc3     *dwc = dev_get_drvdata(dev);
2145         int             ret;
2146
2147         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2148         if (ret)
2149                 return ret;
2150
2151         pinctrl_pm_select_sleep_state(dev);
2152
2153         return 0;
2154 }
2155
2156 static int dwc3_resume(struct device *dev)
2157 {
2158         struct dwc3     *dwc = dev_get_drvdata(dev);
2159         int             ret;
2160
2161         pinctrl_pm_select_default_state(dev);
2162
2163         ret = dwc3_resume_common(dwc, PMSG_RESUME);
2164         if (ret)
2165                 return ret;
2166
2167         pm_runtime_disable(dev);
2168         pm_runtime_set_active(dev);
2169         pm_runtime_enable(dev);
2170
2171         return 0;
2172 }
2173
2174 static void dwc3_complete(struct device *dev)
2175 {
2176         struct dwc3     *dwc = dev_get_drvdata(dev);
2177         u32             reg;
2178
2179         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2180                         dwc->dis_split_quirk) {
2181                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2182                 reg |= DWC3_GUCTL3_SPLITDISABLE;
2183                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2184         }
2185 }
2186 #else
2187 #define dwc3_complete NULL
2188 #endif /* CONFIG_PM_SLEEP */
2189
2190 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2191         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2192         .complete = dwc3_complete,
2193         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2194                         dwc3_runtime_idle)
2195 };
2196
2197 #ifdef CONFIG_OF
2198 static const struct of_device_id of_dwc3_match[] = {
2199         {
2200                 .compatible = "snps,dwc3"
2201         },
2202         {
2203                 .compatible = "synopsys,dwc3"
2204         },
2205         { },
2206 };
2207 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2208 #endif
2209
2210 #ifdef CONFIG_ACPI
2211
2212 #define ACPI_ID_INTEL_BSW       "808622B7"
2213
2214 static const struct acpi_device_id dwc3_acpi_match[] = {
2215         { ACPI_ID_INTEL_BSW, 0 },
2216         { },
2217 };
2218 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2219 #endif
2220
2221 static struct platform_driver dwc3_driver = {
2222         .probe          = dwc3_probe,
2223         .remove         = dwc3_remove,
2224         .driver         = {
2225                 .name   = "dwc3",
2226                 .of_match_table = of_match_ptr(of_dwc3_match),
2227                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2228                 .pm     = &dwc3_dev_pm_ops,
2229         },
2230 };
2231
2232 module_platform_driver(dwc3_driver);
2233
2234 MODULE_ALIAS("platform:dwc3");
2235 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2236 MODULE_LICENSE("GPL v2");
2237 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");