drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11  * to uboot.
  12  *
  13  * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14  */
  15
  16 #include <common.h>
  17 #include <cpu_func.h>
  18 #include <malloc.h>
  19 #include <dwc3-uboot.h>
  20 #include <dm/device_compat.h>
  21 #include <dm/devres.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/err.h>
  24 #include <linux/ioport.h>
  25 #include <dm.h>
  26 #include <generic-phy.h>
  27 #include <linux/usb/ch9.h>
  28 #include <linux/usb/gadget.h>
  29
  30 #include "core.h"
  31 #include "gadget.h"
  32 #include "io.h"
  33
  34 #include "linux-compat.h"
  35
  36 static LIST_HEAD(dwc3_list);
  37 /* -------------------------------------------------------------------------- */
  38
  39 static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  40 {
  41         u32 reg;
  42
  43         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  44         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  45         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  46         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  47 }
  48
  49 /**
  50  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  51  * @dwc: pointer to our context structure
  52  */
  53 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  54 {
  55         u32             reg;
  56
  57         /* Before Resetting PHY, put Core in Reset */
  58         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  59         reg |= DWC3_GCTL_CORESOFTRESET;
  60         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  61
  62         /* Assert USB3 PHY reset */
  63         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  64         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  65         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  66
  67         /* Assert USB2 PHY reset */
  68         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  69         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  70         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  71
  72         mdelay(100);
  73
  74         /* Clear USB3 PHY reset */
  75         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  76         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  77         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  78
  79         /* Clear USB2 PHY reset */
  80         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  81         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  82         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  83
  84         mdelay(100);
  85
  86         /* After PHYs are stable we can take Core out of reset state */
  87         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  88         reg &= ~DWC3_GCTL_CORESOFTRESET;
  89         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  90
  91         return 0;
  92 }
  93
  94 /**
  95  * dwc3_free_one_event_buffer - Frees one event buffer
  96  * @dwc: Pointer to our controller context structure
  97  * @evt: Pointer to event buffer to be freed
  98  */
  99 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 100                 struct dwc3_event_buffer *evt)
 101 {
 102         dma_free_coherent(evt->buf);
 103 }
 104
 105 /**
 106  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 107  * @dwc: Pointer to our controller context structure
 108  * @length: size of the event buffer
 109  *
 110  * Returns a pointer to the allocated event buffer structure on success
 111  * otherwise ERR_PTR(errno).
 112  */
 113 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 114                 unsigned length)
 115 {
 116         struct dwc3_event_buffer        *evt;
 117
 118         evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
 119                            GFP_KERNEL);
 120         if (!evt)
 121                 return ERR_PTR(-ENOMEM);
 122
 123         evt->dwc        = dwc;
 124         evt->length     = length;
 125         evt->buf        = dma_alloc_coherent(length,
 126                                              (unsigned long *)&evt->dma);
 127         if (!evt->buf)
 128                 return ERR_PTR(-ENOMEM);
 129
 130         dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
 131
 132         return evt;
 133 }
 134
 135 /**
 136  * dwc3_free_event_buffers - frees all allocated event buffers
 137  * @dwc: Pointer to our controller context structure
 138  */
 139 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 140 {
 141         struct dwc3_event_buffer        *evt;
 142         int i;
 143
 144         for (i = 0; i < dwc->num_event_buffers; i++) {
 145                 evt = dwc->ev_buffs[i];
 146                 if (evt)
 147                         dwc3_free_one_event_buffer(dwc, evt);
 148         }
 149 }
 150
 151 /**
 152  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 153  * @dwc: pointer to our controller context structure
 154  * @length: size of event buffer
 155  *
 156  * Returns 0 on success otherwise negative errno. In the error case, dwc
 157  * may contain some buffers allocated but not all which were requested.
 158  */
 159 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 160 {
 161         int                     num;
 162         int                     i;
 163
 164         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 165         dwc->num_event_buffers = num;
 166
 167         dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
 168                                  sizeof(*dwc->ev_buffs) * num);
 169         if (!dwc->ev_buffs)
 170                 return -ENOMEM;
 171
 172         for (i = 0; i < num; i++) {
 173                 struct dwc3_event_buffer        *evt;
 174
 175                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 176                 if (IS_ERR(evt)) {
 177                         dev_err(dwc->dev, "can't allocate event buffer\n");
 178                         return PTR_ERR(evt);
 179                 }
 180                 dwc->ev_buffs[i] = evt;
 181         }
 182
 183         return 0;
 184 }
 185
 186 /**
 187  * dwc3_event_buffers_setup - setup our allocated event buffers
 188  * @dwc: pointer to our controller context structure
 189  *
 190  * Returns 0 on success otherwise negative errno.
 191  */
 192 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 193 {
 194         struct dwc3_event_buffer        *evt;
 195         int                             n;
 196
 197         for (n = 0; n < dwc->num_event_buffers; n++) {
 198                 evt = dwc->ev_buffs[n];
 199                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 200                                 evt->buf, (unsigned long long) evt->dma,
 201                                 evt->length);
 202
 203                 evt->lpos = 0;
 204
 205                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 206                                 lower_32_bits(evt->dma));
 207                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 208                                 upper_32_bits(evt->dma));
 209                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 210                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 211                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 212         }
 213
 214         return 0;
 215 }
 216
 217 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 218 {
 219         struct dwc3_event_buffer        *evt;
 220         int                             n;
 221
 222         for (n = 0; n < dwc->num_event_buffers; n++) {
 223                 evt = dwc->ev_buffs[n];
 224
 225                 evt->lpos = 0;
 226
 227                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 228                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 229                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 230                                 | DWC3_GEVNTSIZ_SIZE(0));
 231                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 232         }
 233 }
 234
 235 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 236 {
 237         if (!dwc->has_hibernation)
 238                 return 0;
 239
 240         if (!dwc->nr_scratch)
 241                 return 0;
 242
 243         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 244                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 245         if (!dwc->scratchbuf)
 246                 return -ENOMEM;
 247
 248         return 0;
 249 }
 250
 251 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 252 {
 253         dma_addr_t scratch_addr;
 254         u32 param;
 255         int ret;
 256
 257         if (!dwc->has_hibernation)
 258                 return 0;
 259
 260         if (!dwc->nr_scratch)
 261                 return 0;
 262
 263         scratch_addr = dma_map_single(dwc->scratchbuf,
 264                                       dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 265                                       DMA_BIDIRECTIONAL);
 266         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 267                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 268                 ret = -EFAULT;
 269                 goto err0;
 270         }
 271
 272         dwc->scratch_addr = scratch_addr;
 273
 274         param = lower_32_bits(scratch_addr);
 275
 276         ret = dwc3_send_gadget_generic_command(dwc,
 277                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 278         if (ret < 0)
 279                 goto err1;
 280
 281         param = upper_32_bits(scratch_addr);
 282
 283         ret = dwc3_send_gadget_generic_command(dwc,
 284                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 285         if (ret < 0)
 286                 goto err1;
 287
 288         return 0;
 289
 290 err1:
 291         dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 292                          DMA_BIDIRECTIONAL);
 293
 294 err0:
 295         return ret;
 296 }
 297
 298 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 299 {
 300         if (!dwc->has_hibernation)
 301                 return;
 302
 303         if (!dwc->nr_scratch)
 304                 return;
 305
 306         dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
 307                          DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 308         kfree(dwc->scratchbuf);
 309 }
 310
 311 static void dwc3_core_num_eps(struct dwc3 *dwc)
 312 {
 313         struct dwc3_hwparams    *parms = &dwc->hwparams;
 314
 315         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 316         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 317
 318         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 319                         dwc->num_in_eps, dwc->num_out_eps);
 320 }
 321
 322 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 323 {
 324         struct dwc3_hwparams    *parms = &dwc->hwparams;
 325
 326         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 327         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 328         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 329         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 330         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 331         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 332         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 333         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 334         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 335 }
 336
 337 /**
 338  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 339  * @dwc: Pointer to our controller context structure
 340  */
 341 static void dwc3_phy_setup(struct dwc3 *dwc)
 342 {
 343         u32 reg;
 344
 345         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 346
 347         /*
 348          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 349          * to '0' during coreConsultant configuration. So default value
 350          * will be '0' when the core is reset. Application needs to set it
 351          * to '1' after the core initialization is completed.
 352          */
 353         if (dwc->revision > DWC3_REVISION_194A)
 354                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 355
 356         if (dwc->u2ss_inp3_quirk)
 357                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 358
 359         if (dwc->req_p1p2p3_quirk)
 360                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 361
 362         if (dwc->del_p1p2p3_quirk)
 363                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 364
 365         if (dwc->del_phy_power_chg_quirk)
 366                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 367
 368         if (dwc->lfps_filter_quirk)
 369                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 370
 371         if (dwc->rx_detect_poll_quirk)
 372                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 373
 374         if (dwc->tx_de_emphasis_quirk)
 375                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 376
 377         if (dwc->dis_u3_susphy_quirk)
 378                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 379
 380         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 381
 382         mdelay(100);
 383
 384         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 385
 386         /*
 387          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 388          * '0' during coreConsultant configuration. So default value will
 389          * be '0' when the core is reset. Application needs to set it to
 390          * '1' after the core initialization is completed.
 391          */
 392         if (dwc->revision > DWC3_REVISION_194A)
 393                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 394
 395         if (dwc->dis_u2_susphy_quirk)
 396                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 397
 398         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 399
 400         mdelay(100);
 401 }
 402
 403 /**
 404  * dwc3_core_init - Low-level initialization of DWC3 Core
 405  * @dwc: Pointer to our controller context structure
 406  *
 407  * Returns 0 on success otherwise negative errno.
 408  */
 409 static int dwc3_core_init(struct dwc3 *dwc)
 410 {
 411         unsigned long           timeout;
 412         u32                     hwparams4 = dwc->hwparams.hwparams4;
 413         u32                     reg;
 414         int                     ret;
 415
 416         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 417         /* This should read as U3 followed by revision number */
 418         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 419                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 420                 ret = -ENODEV;
 421                 goto err0;
 422         }
 423         dwc->revision = reg;
 424
 425         /* Handle USB2.0-only core configuration */
 426         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 427                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 428                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 429                         dwc->maximum_speed = USB_SPEED_HIGH;
 430         }
 431
 432         /* issue device SoftReset too */
 433         timeout = 5000;
 434         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 435         while (timeout--) {
 436                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 437                 if (!(reg & DWC3_DCTL_CSFTRST))
 438                         break;
 439         };
 440
 441         if (!timeout) {
 442                 dev_err(dwc->dev, "Reset Timed Out\n");
 443                 ret = -ETIMEDOUT;
 444                 goto err0;
 445         }
 446
 447         dwc3_phy_setup(dwc);
 448
 449         ret = dwc3_core_soft_reset(dwc);
 450         if (ret)
 451                 goto err0;
 452
 453         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 454         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 455
 456         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 457         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 458                 /**
 459                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 460                  * issue which would cause xHCI compliance tests to fail.
 461                  *
 462                  * Because of that we cannot enable clock gating on such
 463                  * configurations.
 464                  *
 465                  * Refers to:
 466                  *
 467                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 468                  * SOF/ITP Mode Used
 469                  */
 470                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 471                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 472                                 (dwc->revision >= DWC3_REVISION_210A &&
 473                                 dwc->revision <= DWC3_REVISION_250A))
 474                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 475                 else
 476                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 477                 break;
 478         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 479                 /* enable hibernation here */
 480                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 481
 482                 /*
 483                  * REVISIT Enabling this bit so that host-mode hibernation
 484                  * will work. Device-mode hibernation is not yet implemented.
 485                  */
 486                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 487                 break;
 488         default:
 489                 dev_dbg(dwc->dev, "No power optimization available\n");
 490         }
 491
 492         /* check if current dwc3 is on simulation board */
 493         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 494                 dev_dbg(dwc->dev, "it is on FPGA board\n");
 495                 dwc->is_fpga = true;
 496         }
 497
 498         if(dwc->disable_scramble_quirk && !dwc->is_fpga)
 499                 WARN(true,
 500                      "disable_scramble cannot be used on non-FPGA builds\n");
 501
 502         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 503                 reg |= DWC3_GCTL_DISSCRAMBLE;
 504         else
 505                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 506
 507         if (dwc->u2exit_lfps_quirk)
 508                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 509
 510         /*
 511          * WORKAROUND: DWC3 revisions <1.90a have a bug
 512          * where the device can fail to connect at SuperSpeed
 513          * and falls back to high-speed mode which causes
 514          * the device to enter a Connect/Disconnect loop
 515          */
 516         if (dwc->revision < DWC3_REVISION_190A)
 517                 reg |= DWC3_GCTL_U2RSTECN;
 518
 519         dwc3_core_num_eps(dwc);
 520
 521         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 522
 523         ret = dwc3_alloc_scratch_buffers(dwc);
 524         if (ret)
 525                 goto err0;
 526
 527         ret = dwc3_setup_scratch_buffers(dwc);
 528         if (ret)
 529                 goto err1;
 530
 531         return 0;
 532
 533 err1:
 534         dwc3_free_scratch_buffers(dwc);
 535
 536 err0:
 537         return ret;
 538 }
 539
 540 static void dwc3_core_exit(struct dwc3 *dwc)
 541 {
 542         dwc3_free_scratch_buffers(dwc);
 543 }
 544
 545 static int dwc3_core_init_mode(struct dwc3 *dwc)
 546 {
 547         int ret;
 548
 549         switch (dwc->dr_mode) {
 550         case USB_DR_MODE_PERIPHERAL:
 551                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 552                 ret = dwc3_gadget_init(dwc);
 553                 if (ret) {
 554                         dev_err(dev, "failed to initialize gadget\n");
 555                         return ret;
 556                 }
 557                 break;
 558         case USB_DR_MODE_HOST:
 559                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 560                 ret = dwc3_host_init(dwc);
 561                 if (ret) {
 562                         dev_err(dev, "failed to initialize host\n");
 563                         return ret;
 564                 }
 565                 break;
 566         case USB_DR_MODE_OTG:
 567                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 568                 ret = dwc3_host_init(dwc);
 569                 if (ret) {
 570                         dev_err(dev, "failed to initialize host\n");
 571                         return ret;
 572                 }
 573
 574                 ret = dwc3_gadget_init(dwc);
 575                 if (ret) {
 576                         dev_err(dev, "failed to initialize gadget\n");
 577                         return ret;
 578                 }
 579                 break;
 580         default:
 581                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 582                 return -EINVAL;
 583         }
 584
 585         return 0;
 586 }
 587
 588 static void dwc3_gadget_run(struct dwc3 *dwc)
 589 {
 590         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
 591         mdelay(100);
 592 }
 593
 594 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 595 {
 596         switch (dwc->dr_mode) {
 597         case USB_DR_MODE_PERIPHERAL:
 598                 dwc3_gadget_exit(dwc);
 599                 break;
 600         case USB_DR_MODE_HOST:
 601                 dwc3_host_exit(dwc);
 602                 break;
 603         case USB_DR_MODE_OTG:
 604                 dwc3_host_exit(dwc);
 605                 dwc3_gadget_exit(dwc);
 606                 break;
 607         default:
 608                 /* do nothing */
 609                 break;
 610         }
 611
 612         /*
 613          * switch back to peripheral mode
 614          * This enables the phy to enter idle and then, if enabled, suspend.
 615          */
 616         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 617         dwc3_gadget_run(dwc);
 618 }
 619
 620 static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
 621                                   struct dwc3 *dwc)
 622 {
 623         enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
 624         u32 reg;
 625
 626         /* Set dwc3 usb2 phy config */
 627         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 628
 629         switch (hsphy_mode) {
 630         case USBPHY_INTERFACE_MODE_UTMI:
 631                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 632                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 633                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 634                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 635                 break;
 636         case USBPHY_INTERFACE_MODE_UTMIW:
 637                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 638                         DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 639                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 640                         DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 641                 break;
 642         default:
 643                 break;
 644         }
 645
 646         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 647 }
 648
 649 #define DWC3_ALIGN_MASK         (16 - 1)
 650
 651 /**
 652  * dwc3_uboot_init - dwc3 core uboot initialization code
 653  * @dwc3_dev: struct dwc3_device containing initialization data
 654  *
 655  * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
 656  * kernel driver). Pointer to dwc3_device should be passed containing
 657  * base address and other initialization data. Returns '0' on success and
 658  * a negative value on failure.
 659  *
 660  * Generally called from board_usb_init() implemented in board file.
 661  */
 662 int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 663 {
 664         struct dwc3             *dwc;
 665         struct device           *dev = NULL;
 666         u8                      lpm_nyet_threshold;
 667         u8                      tx_de_emphasis;
 668         u8                      hird_threshold;
 669
 670         int                     ret;
 671
 672         void                    *mem;
 673
 674         mem = devm_kzalloc((struct udevice *)dev,
 675                            sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 676         if (!mem)
 677                 return -ENOMEM;
 678
 679         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 680         dwc->mem = mem;
 681
 682         dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
 683                                         DWC3_GLOBALS_REGS_START);
 684
 685         /* default to highest possible threshold */
 686         lpm_nyet_threshold = 0xff;
 687
 688         /* default to -3.5dB de-emphasis */
 689         tx_de_emphasis = 1;
 690
 691         /*
 692          * default to assert utmi_sleep_n and use maximum allowed HIRD
 693          * threshold value of 0b1100
 694          */
 695         hird_threshold = 12;
 696
 697         dwc->maximum_speed = dwc3_dev->maximum_speed;
 698         dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
 699         if (dwc3_dev->lpm_nyet_threshold)
 700                 lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
 701         dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
 702         if (dwc3_dev->hird_threshold)
 703                 hird_threshold = dwc3_dev->hird_threshold;
 704
 705         dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
 706         dwc->dr_mode = dwc3_dev->dr_mode;
 707
 708         dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
 709         dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
 710         dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
 711         dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
 712         dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
 713         dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
 714         dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
 715         dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
 716         dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
 717         dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
 718
 719         dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
 720         if (dwc3_dev->tx_de_emphasis)
 721                 tx_de_emphasis = dwc3_dev->tx_de_emphasis;
 722
 723         /* default to superspeed if no maximum_speed passed */
 724         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 725                 dwc->maximum_speed = USB_SPEED_SUPER;
 726
 727         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 728         dwc->tx_de_emphasis = tx_de_emphasis;
 729
 730         dwc->hird_threshold = hird_threshold
 731                 | (dwc->is_utmi_l1_suspend << 4);
 732
 733         dwc->index = dwc3_dev->index;
 734
 735         dwc3_cache_hwparams(dwc);
 736
 737         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 738         if (ret) {
 739                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 740                 return -ENOMEM;
 741         }
 742
 743         if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 744                 dwc->dr_mode = USB_DR_MODE_HOST;
 745         else if (!IS_ENABLED(CONFIG_USB_HOST))
 746                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 747
 748         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 749                 dwc->dr_mode = USB_DR_MODE_OTG;
 750
 751         ret = dwc3_core_init(dwc);
 752         if (ret) {
 753                 dev_err(dev, "failed to initialize core\n");
 754                 goto err0;
 755         }
 756
 757         dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
 758
 759         ret = dwc3_event_buffers_setup(dwc);
 760         if (ret) {
 761                 dev_err(dwc->dev, "failed to setup event buffers\n");
 762                 goto err1;
 763         }
 764
 765         ret = dwc3_core_init_mode(dwc);
 766         if (ret)
 767                 goto err2;
 768
 769         list_add_tail(&dwc->list, &dwc3_list);
 770
 771         return 0;
 772
 773 err2:
 774         dwc3_event_buffers_cleanup(dwc);
 775
 776 err1:
 777         dwc3_core_exit(dwc);
 778
 779 err0:
 780         dwc3_free_event_buffers(dwc);
 781
 782         return ret;
 783 }
 784
 785 /**
 786  * dwc3_uboot_exit - dwc3 core uboot cleanup code
 787  * @index: index of this controller
 788  *
 789  * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
 790  * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
 791  * should be passed and should match with the index passed in
 792  * dwc3_device during init.
 793  *
 794  * Generally called from board file.
 795  */
 796 void dwc3_uboot_exit(int index)
 797 {
 798         struct dwc3 *dwc;
 799
 800         list_for_each_entry(dwc, &dwc3_list, list) {
 801                 if (dwc->index != index)
 802                         continue;
 803
 804                 dwc3_core_exit_mode(dwc);
 805                 dwc3_event_buffers_cleanup(dwc);
 806                 dwc3_free_event_buffers(dwc);
 807                 dwc3_core_exit(dwc);
 808                 list_del(&dwc->list);
 809                 kfree(dwc->mem);
 810                 break;
 811         }
 812 }
 813
 814 /**
 815  * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
 816  * @index: index of this controller
 817  *
 818  * Invokes dwc3 gadget interrupts.
 819  *
 820  * Generally called from board file.
 821  */
 822 void dwc3_uboot_handle_interrupt(int index)
 823 {
 824         struct dwc3 *dwc = NULL;
 825
 826         list_for_each_entry(dwc, &dwc3_list, list) {
 827                 if (dwc->index != index)
 828                         continue;
 829
 830                 dwc3_gadget_uboot_handle_interrupt(dwc);
 831                 break;
 832         }
 833 }
 834
 835 MODULE_ALIAS("platform:dwc3");
 836 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 837 MODULE_LICENSE("GPL v2");
 838 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
 839
 840 #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
 841 int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
 842 {
 843         int ret;
 844
 845         ret = generic_phy_get_bulk(dev, phys);
 846         if (ret)
 847                 return ret;
 848
 849         ret = generic_phy_init_bulk(phys);
 850         if (ret)
 851                 return ret;
 852
 853         ret = generic_phy_power_on_bulk(phys);
 854         if (ret)
 855                 generic_phy_exit_bulk(phys);
 856
 857         return ret;
 858 }
 859
 860 int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
 861 {
 862         int ret;
 863
 864         ret = generic_phy_power_off_bulk(phys);
 865         ret |= generic_phy_exit_bulk(phys);
 866         return ret;
 867 }
 868 #endif
 869
 870 #if CONFIG_IS_ENABLED(DM_USB)
 871 void dwc3_of_parse(struct dwc3 *dwc)
 872 {
 873         const u8 *tmp;
 874         struct udevice *dev = dwc->dev;
 875         u8 lpm_nyet_threshold;
 876         u8 tx_de_emphasis;
 877         u8 hird_threshold;
 878
 879         /* default to highest possible threshold */
 880         lpm_nyet_threshold = 0xff;
 881
 882         /* default to -3.5dB de-emphasis */
 883         tx_de_emphasis = 1;
 884
 885         /*
 886          * default to assert utmi_sleep_n and use maximum allowed HIRD
 887          * threshold value of 0b1100
 888          */
 889         hird_threshold = 12;
 890
 891         dwc->has_lpm_erratum = dev_read_bool(dev,
 892                                 "snps,has-lpm-erratum");
 893         tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
 894         if (tmp)
 895                 lpm_nyet_threshold = *tmp;
 896
 897         dwc->is_utmi_l1_suspend = dev_read_bool(dev,
 898                                 "snps,is-utmi-l1-suspend");
 899         tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
 900         if (tmp)
 901                 hird_threshold = *tmp;
 902
 903         dwc->disable_scramble_quirk = dev_read_bool(dev,
 904                                 "snps,disable_scramble_quirk");
 905         dwc->u2exit_lfps_quirk = dev_read_bool(dev,
 906                                 "snps,u2exit_lfps_quirk");
 907         dwc->u2ss_inp3_quirk = dev_read_bool(dev,
 908                                 "snps,u2ss_inp3_quirk");
 909         dwc->req_p1p2p3_quirk = dev_read_bool(dev,
 910                                 "snps,req_p1p2p3_quirk");
 911         dwc->del_p1p2p3_quirk = dev_read_bool(dev,
 912                                 "snps,del_p1p2p3_quirk");
 913         dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
 914                                 "snps,del_phy_power_chg_quirk");
 915         dwc->lfps_filter_quirk = dev_read_bool(dev,
 916                                 "snps,lfps_filter_quirk");
 917         dwc->rx_detect_poll_quirk = dev_read_bool(dev,
 918                                 "snps,rx_detect_poll_quirk");
 919         dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
 920                                 "snps,dis_u3_susphy_quirk");
 921         dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
 922                                 "snps,dis_u2_susphy_quirk");
 923         dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
 924                                 "snps,tx_de_emphasis_quirk");
 925         tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
 926         if (tmp)
 927                 tx_de_emphasis = *tmp;
 928
 929         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 930         dwc->tx_de_emphasis = tx_de_emphasis;
 931
 932         dwc->hird_threshold = hird_threshold
 933                 | (dwc->is_utmi_l1_suspend << 4);
 934 }
 935
 936 int dwc3_init(struct dwc3 *dwc)
 937 {
 938         int ret;
 939
 940         dwc3_cache_hwparams(dwc);
 941
 942         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 943         if (ret) {
 944                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 945                 return -ENOMEM;
 946         }
 947
 948         ret = dwc3_core_init(dwc);
 949         if (ret) {
 950                 dev_err(dev, "failed to initialize core\n");
 951                 goto core_fail;
 952         }
 953
 954         ret = dwc3_event_buffers_setup(dwc);
 955         if (ret) {
 956                 dev_err(dwc->dev, "failed to setup event buffers\n");
 957                 goto event_fail;
 958         }
 959
 960         ret = dwc3_core_init_mode(dwc);
 961         if (ret)
 962                 goto mode_fail;
 963
 964         return 0;
 965
 966 mode_fail:
 967         dwc3_event_buffers_cleanup(dwc);
 968
 969 event_fail:
 970         dwc3_core_exit(dwc);
 971
 972 core_fail:
 973         dwc3_free_event_buffers(dwc);
 974
 975         return ret;
 976 }
 977
 978 void dwc3_remove(struct dwc3 *dwc)
 979 {
 980         dwc3_core_exit_mode(dwc);
 981         dwc3_event_buffers_cleanup(dwc);
 982         dwc3_free_event_buffers(dwc);
 983         dwc3_core_exit(dwc);
 984         kfree(dwc->mem);
 985 }
 986 #endif