drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/ioport.h>
  30 #include <linux/io.h>
  31 #include <linux/list.h>
  32 #include <linux/delay.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/of.h>
  35
  36 #include <linux/usb/otg.h>
  37 #include <linux/usb/ch9.h>
  38 #include <linux/usb/gadget.h>
  39 #include <linux/usb/of.h>
  40 #include <linux/usb/otg.h>
  41
  42 #include "platform_data.h"
  43 #include "core.h"
  44 #include "gadget.h"
  45 #include "io.h"
  46
  47 #include "debug.h"
  48
  49 /* -------------------------------------------------------------------------- */
  50
  51 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  52 {
  53         u32 reg;
  54
  55         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  56         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  57         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  58         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  59 }
  60
  61 /**
  62  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  63  * @dwc: pointer to our context structure
  64  */
  65 static void dwc3_core_soft_reset(struct dwc3 *dwc)
  66 {
  67         u32             reg;
  68
  69         /* Before Resetting PHY, put Core in Reset */
  70         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  71         reg |= DWC3_GCTL_CORESOFTRESET;
  72         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  73
  74         /* Assert USB3 PHY reset */
  75         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  76         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  77         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  78
  79         /* Assert USB2 PHY reset */
  80         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  81         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  82         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  83
  84         usb_phy_init(dwc->usb2_phy);
  85         usb_phy_init(dwc->usb3_phy);
  86         mdelay(100);
  87
  88         /* Clear USB3 PHY reset */
  89         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  90         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  91         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  92
  93         /* Clear USB2 PHY reset */
  94         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  95         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  96         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  97
  98         mdelay(100);
  99
 100         /* After PHYs are stable we can take Core out of reset state */
 101         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 102         reg &= ~DWC3_GCTL_CORESOFTRESET;
 103         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 104 }
 105
 106 /**
 107  * dwc3_free_one_event_buffer - Frees one event buffer
 108  * @dwc: Pointer to our controller context structure
 109  * @evt: Pointer to event buffer to be freed
 110  */
 111 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 112                 struct dwc3_event_buffer *evt)
 113 {
 114         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 115 }
 116
 117 /**
 118  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 119  * @dwc: Pointer to our controller context structure
 120  * @length: size of the event buffer
 121  *
 122  * Returns a pointer to the allocated event buffer structure on success
 123  * otherwise ERR_PTR(errno).
 124  */
 125 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 126                 unsigned length)
 127 {
 128         struct dwc3_event_buffer        *evt;
 129
 130         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 131         if (!evt)
 132                 return ERR_PTR(-ENOMEM);
 133
 134         evt->dwc        = dwc;
 135         evt->length     = length;
 136         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 137                         &evt->dma, GFP_KERNEL);
 138         if (!evt->buf)
 139                 return ERR_PTR(-ENOMEM);
 140
 141         return evt;
 142 }
 143
 144 /**
 145  * dwc3_free_event_buffers - frees all allocated event buffers
 146  * @dwc: Pointer to our controller context structure
 147  */
 148 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 149 {
 150         struct dwc3_event_buffer        *evt;
 151         int i;
 152
 153         for (i = 0; i < dwc->num_event_buffers; i++) {
 154                 evt = dwc->ev_buffs[i];
 155                 if (evt)
 156                         dwc3_free_one_event_buffer(dwc, evt);
 157         }
 158 }
 159
 160 /**
 161  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 162  * @dwc: pointer to our controller context structure
 163  * @length: size of event buffer
 164  *
 165  * Returns 0 on success otherwise negative errno. In the error case, dwc
 166  * may contain some buffers allocated but not all which were requested.
 167  */
 168 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 169 {
 170         int                     num;
 171         int                     i;
 172
 173         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 174         dwc->num_event_buffers = num;
 175
 176         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 177                         GFP_KERNEL);
 178         if (!dwc->ev_buffs) {
 179                 dev_err(dwc->dev, "can't allocate event buffers array\n");
 180                 return -ENOMEM;
 181         }
 182
 183         for (i = 0; i < num; i++) {
 184                 struct dwc3_event_buffer        *evt;
 185
 186                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 187                 if (IS_ERR(evt)) {
 188                         dev_err(dwc->dev, "can't allocate event buffer\n");
 189                         return PTR_ERR(evt);
 190                 }
 191                 dwc->ev_buffs[i] = evt;
 192         }
 193
 194         return 0;
 195 }
 196
 197 /**
 198  * dwc3_event_buffers_setup - setup our allocated event buffers
 199  * @dwc: pointer to our controller context structure
 200  *
 201  * Returns 0 on success otherwise negative errno.
 202  */
 203 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 204 {
 205         struct dwc3_event_buffer        *evt;
 206         int                             n;
 207
 208         for (n = 0; n < dwc->num_event_buffers; n++) {
 209                 evt = dwc->ev_buffs[n];
 210                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 211                                 evt->buf, (unsigned long long) evt->dma,
 212                                 evt->length);
 213
 214                 evt->lpos = 0;
 215
 216                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 217                                 lower_32_bits(evt->dma));
 218                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 219                                 upper_32_bits(evt->dma));
 220                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 221                                 evt->length & 0xffff);
 222                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 223         }
 224
 225         return 0;
 226 }
 227
 228 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 229 {
 230         struct dwc3_event_buffer        *evt;
 231         int                             n;
 232
 233         for (n = 0; n < dwc->num_event_buffers; n++) {
 234                 evt = dwc->ev_buffs[n];
 235
 236                 evt->lpos = 0;
 237
 238                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 239                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 240                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
 241                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 242         }
 243 }
 244
 245 static void dwc3_core_num_eps(struct dwc3 *dwc)
 246 {
 247         struct dwc3_hwparams    *parms = &dwc->hwparams;
 248
 249         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 250         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 251
 252         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 253                         dwc->num_in_eps, dwc->num_out_eps);
 254 }
 255
 256 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 257 {
 258         struct dwc3_hwparams    *parms = &dwc->hwparams;
 259
 260         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 261         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 262         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 263         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 264         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 265         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 266         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 267         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 268         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 269 }
 270
 271 /**
 272  * dwc3_core_init - Low-level initialization of DWC3 Core
 273  * @dwc: Pointer to our controller context structure
 274  *
 275  * Returns 0 on success otherwise negative errno.
 276  */
 277 static int dwc3_core_init(struct dwc3 *dwc)
 278 {
 279         unsigned long           timeout;
 280         u32                     reg;
 281         int                     ret;
 282
 283         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 284         /* This should read as U3 followed by revision number */
 285         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 286                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 287                 ret = -ENODEV;
 288                 goto err0;
 289         }
 290         dwc->revision = reg;
 291
 292         /* issue device SoftReset too */
 293         timeout = jiffies + msecs_to_jiffies(500);
 294         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 295         do {
 296                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 297                 if (!(reg & DWC3_DCTL_CSFTRST))
 298                         break;
 299
 300                 if (time_after(jiffies, timeout)) {
 301                         dev_err(dwc->dev, "Reset Timed Out\n");
 302                         ret = -ETIMEDOUT;
 303                         goto err0;
 304                 }
 305
 306                 cpu_relax();
 307         } while (true);
 308
 309         dwc3_core_soft_reset(dwc);
 310
 311         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 312         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 313         reg &= ~DWC3_GCTL_DISSCRAMBLE;
 314
 315         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 316         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 317                 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 318                 break;
 319         default:
 320                 dev_dbg(dwc->dev, "No power optimization available\n");
 321         }
 322
 323         /*
 324          * WORKAROUND: DWC3 revisions <1.90a have a bug
 325          * where the device can fail to connect at SuperSpeed
 326          * and falls back to high-speed mode which causes
 327          * the device to enter a Connect/Disconnect loop
 328          */
 329         if (dwc->revision < DWC3_REVISION_190A)
 330                 reg |= DWC3_GCTL_U2RSTECN;
 331
 332         dwc3_core_num_eps(dwc);
 333
 334         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 335
 336         return 0;
 337
 338 err0:
 339         return ret;
 340 }
 341
 342 static void dwc3_core_exit(struct dwc3 *dwc)
 343 {
 344         usb_phy_shutdown(dwc->usb2_phy);
 345         usb_phy_shutdown(dwc->usb3_phy);
 346 }
 347
 348 #define DWC3_ALIGN_MASK         (16 - 1)
 349
 350 static int dwc3_probe(struct platform_device *pdev)
 351 {
 352         struct dwc3_platform_data *pdata = pdev->dev.platform_data;
 353         struct device_node      *node = pdev->dev.of_node;
 354         struct resource         *res;
 355         struct dwc3             *dwc;
 356         struct device           *dev = &pdev->dev;
 357
 358         int                     ret = -ENOMEM;
 359
 360         void __iomem            *regs;
 361         void                    *mem;
 362
 363         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 364         if (!mem) {
 365                 dev_err(dev, "not enough memory\n");
 366                 return -ENOMEM;
 367         }
 368         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 369         dwc->mem = mem;
 370
 371         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 372         if (!res) {
 373                 dev_err(dev, "missing IRQ\n");
 374                 return -ENODEV;
 375         }
 376         dwc->xhci_resources[1].start = res->start;
 377         dwc->xhci_resources[1].end = res->end;
 378         dwc->xhci_resources[1].flags = res->flags;
 379         dwc->xhci_resources[1].name = res->name;
 380
 381         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 382         if (!res) {
 383                 dev_err(dev, "missing memory resource\n");
 384                 return -ENODEV;
 385         }
 386         dwc->xhci_resources[0].start = res->start;
 387         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 388                                         DWC3_XHCI_REGS_END;
 389         dwc->xhci_resources[0].flags = res->flags;
 390         dwc->xhci_resources[0].name = res->name;
 391
 392         res->start += DWC3_GLOBALS_REGS_START;
 393
 394          /*
 395           * Request memory region but exclude xHCI regs,
 396           * since it will be requested by the xhci-plat driver.
 397           */
 398         regs = devm_ioremap_resource(dev, res);
 399         if (IS_ERR(regs))
 400                 return PTR_ERR(regs);
 401
 402         if (node) {
 403                 dwc->maximum_speed = of_usb_get_maximum_speed(node);
 404
 405                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 406                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 407
 408                 dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
 409                 dwc->dr_mode = of_usb_get_dr_mode(node);
 410         } else {
 411                 dwc->maximum_speed = pdata->maximum_speed;
 412
 413                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 414                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 415
 416                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 417                 dwc->dr_mode = pdata->dr_mode;
 418         }
 419
 420         /* default to superspeed if no maximum_speed passed */
 421         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 422                 dwc->maximum_speed = USB_SPEED_SUPER;
 423
 424         if (IS_ERR(dwc->usb2_phy)) {
 425                 ret = PTR_ERR(dwc->usb2_phy);
 426
 427                 /*
 428                  * if -ENXIO is returned, it means PHY layer wasn't
 429                  * enabled, so it makes no sense to return -EPROBE_DEFER
 430                  * in that case, since no PHY driver will ever probe.
 431                  */
 432                 if (ret == -ENXIO)
 433                         return ret;
 434
 435                 dev_err(dev, "no usb2 phy configured\n");
 436                 return -EPROBE_DEFER;
 437         }
 438
 439         if (IS_ERR(dwc->usb3_phy)) {
 440                 ret = PTR_ERR(dwc->usb3_phy);
 441
 442                 /*
 443                  * if -ENXIO is returned, it means PHY layer wasn't
 444                  * enabled, so it makes no sense to return -EPROBE_DEFER
 445                  * in that case, since no PHY driver will ever probe.
 446                  */
 447                 if (ret == -ENXIO)
 448                         return ret;
 449
 450                 dev_err(dev, "no usb3 phy configured\n");
 451                 return -EPROBE_DEFER;
 452         }
 453
 454         usb_phy_set_suspend(dwc->usb2_phy, 0);
 455         usb_phy_set_suspend(dwc->usb3_phy, 0);
 456
 457         spin_lock_init(&dwc->lock);
 458         platform_set_drvdata(pdev, dwc);
 459
 460         dwc->regs       = regs;
 461         dwc->regs_size  = resource_size(res);
 462         dwc->dev        = dev;
 463
 464         dev->dma_mask   = dev->parent->dma_mask;
 465         dev->dma_parms  = dev->parent->dma_parms;
 466         dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 467
 468         pm_runtime_enable(dev);
 469         pm_runtime_get_sync(dev);
 470         pm_runtime_forbid(dev);
 471
 472         dwc3_cache_hwparams(dwc);
 473
 474         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 475         if (ret) {
 476                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 477                 ret = -ENOMEM;
 478                 goto err0;
 479         }
 480
 481         ret = dwc3_core_init(dwc);
 482         if (ret) {
 483                 dev_err(dev, "failed to initialize core\n");
 484                 goto err0;
 485         }
 486
 487         ret = dwc3_event_buffers_setup(dwc);
 488         if (ret) {
 489                 dev_err(dwc->dev, "failed to setup event buffers\n");
 490                 goto err1;
 491         }
 492
 493         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
 494                 dwc->dr_mode = USB_DR_MODE_HOST;
 495         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 496                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 497
 498         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 499                 dwc->dr_mode = USB_DR_MODE_OTG;
 500
 501         switch (dwc->dr_mode) {
 502         case USB_DR_MODE_PERIPHERAL:
 503                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 504                 ret = dwc3_gadget_init(dwc);
 505                 if (ret) {
 506                         dev_err(dev, "failed to initialize gadget\n");
 507                         goto err2;
 508                 }
 509                 break;
 510         case USB_DR_MODE_HOST:
 511                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 512                 ret = dwc3_host_init(dwc);
 513                 if (ret) {
 514                         dev_err(dev, "failed to initialize host\n");
 515                         goto err2;
 516                 }
 517                 break;
 518         case USB_DR_MODE_OTG:
 519                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 520                 ret = dwc3_host_init(dwc);
 521                 if (ret) {
 522                         dev_err(dev, "failed to initialize host\n");
 523                         goto err2;
 524                 }
 525
 526                 ret = dwc3_gadget_init(dwc);
 527                 if (ret) {
 528                         dev_err(dev, "failed to initialize gadget\n");
 529                         goto err2;
 530                 }
 531                 break;
 532         default:
 533                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 534                 goto err2;
 535         }
 536
 537         ret = dwc3_debugfs_init(dwc);
 538         if (ret) {
 539                 dev_err(dev, "failed to initialize debugfs\n");
 540                 goto err3;
 541         }
 542
 543         pm_runtime_allow(dev);
 544
 545         return 0;
 546
 547 err3:
 548         switch (dwc->dr_mode) {
 549         case USB_DR_MODE_PERIPHERAL:
 550                 dwc3_gadget_exit(dwc);
 551                 break;
 552         case USB_DR_MODE_HOST:
 553                 dwc3_host_exit(dwc);
 554                 break;
 555         case USB_DR_MODE_OTG:
 556                 dwc3_host_exit(dwc);
 557                 dwc3_gadget_exit(dwc);
 558                 break;
 559         default:
 560                 /* do nothing */
 561                 break;
 562         }
 563
 564 err2:
 565         dwc3_event_buffers_cleanup(dwc);
 566
 567 err1:
 568         dwc3_core_exit(dwc);
 569
 570 err0:
 571         dwc3_free_event_buffers(dwc);
 572
 573         return ret;
 574 }
 575
 576 static int dwc3_remove(struct platform_device *pdev)
 577 {
 578         struct dwc3     *dwc = platform_get_drvdata(pdev);
 579
 580         usb_phy_set_suspend(dwc->usb2_phy, 1);
 581         usb_phy_set_suspend(dwc->usb3_phy, 1);
 582
 583         pm_runtime_put(&pdev->dev);
 584         pm_runtime_disable(&pdev->dev);
 585
 586         dwc3_debugfs_exit(dwc);
 587
 588         switch (dwc->dr_mode) {
 589         case USB_DR_MODE_PERIPHERAL:
 590                 dwc3_gadget_exit(dwc);
 591                 break;
 592         case USB_DR_MODE_HOST:
 593                 dwc3_host_exit(dwc);
 594                 break;
 595         case USB_DR_MODE_OTG:
 596                 dwc3_host_exit(dwc);
 597                 dwc3_gadget_exit(dwc);
 598                 break;
 599         default:
 600                 /* do nothing */
 601                 break;
 602         }
 603
 604         dwc3_event_buffers_cleanup(dwc);
 605         dwc3_free_event_buffers(dwc);
 606         dwc3_core_exit(dwc);
 607
 608         return 0;
 609 }
 610
 611 #ifdef CONFIG_PM_SLEEP
 612 static int dwc3_prepare(struct device *dev)
 613 {
 614         struct dwc3     *dwc = dev_get_drvdata(dev);
 615         unsigned long   flags;
 616
 617         spin_lock_irqsave(&dwc->lock, flags);
 618
 619         switch (dwc->dr_mode) {
 620         case USB_DR_MODE_PERIPHERAL:
 621         case USB_DR_MODE_OTG:
 622                 dwc3_gadget_prepare(dwc);
 623                 /* FALLTHROUGH */
 624         case USB_DR_MODE_HOST:
 625         default:
 626                 dwc3_event_buffers_cleanup(dwc);
 627                 break;
 628         }
 629
 630         spin_unlock_irqrestore(&dwc->lock, flags);
 631
 632         return 0;
 633 }
 634
 635 static void dwc3_complete(struct device *dev)
 636 {
 637         struct dwc3     *dwc = dev_get_drvdata(dev);
 638         unsigned long   flags;
 639
 640         spin_lock_irqsave(&dwc->lock, flags);
 641
 642         switch (dwc->dr_mode) {
 643         case USB_DR_MODE_PERIPHERAL:
 644         case USB_DR_MODE_OTG:
 645                 dwc3_gadget_complete(dwc);
 646                 /* FALLTHROUGH */
 647         case USB_DR_MODE_HOST:
 648         default:
 649                 dwc3_event_buffers_setup(dwc);
 650                 break;
 651         }
 652
 653         spin_unlock_irqrestore(&dwc->lock, flags);
 654 }
 655
 656 static int dwc3_suspend(struct device *dev)
 657 {
 658         struct dwc3     *dwc = dev_get_drvdata(dev);
 659         unsigned long   flags;
 660
 661         spin_lock_irqsave(&dwc->lock, flags);
 662
 663         switch (dwc->dr_mode) {
 664         case USB_DR_MODE_PERIPHERAL:
 665         case USB_DR_MODE_OTG:
 666                 dwc3_gadget_suspend(dwc);
 667                 /* FALLTHROUGH */
 668         case USB_DR_MODE_HOST:
 669         default:
 670                 /* do nothing */
 671                 break;
 672         }
 673
 674         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
 675         spin_unlock_irqrestore(&dwc->lock, flags);
 676
 677         usb_phy_shutdown(dwc->usb3_phy);
 678         usb_phy_shutdown(dwc->usb2_phy);
 679
 680         return 0;
 681 }
 682
 683 static int dwc3_resume(struct device *dev)
 684 {
 685         struct dwc3     *dwc = dev_get_drvdata(dev);
 686         unsigned long   flags;
 687
 688         usb_phy_init(dwc->usb3_phy);
 689         usb_phy_init(dwc->usb2_phy);
 690         msleep(100);
 691
 692         spin_lock_irqsave(&dwc->lock, flags);
 693
 694         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
 695
 696         switch (dwc->dr_mode) {
 697         case USB_DR_MODE_PERIPHERAL:
 698         case USB_DR_MODE_OTG:
 699                 dwc3_gadget_resume(dwc);
 700                 /* FALLTHROUGH */
 701         case USB_DR_MODE_HOST:
 702         default:
 703                 /* do nothing */
 704                 break;
 705         }
 706
 707         spin_unlock_irqrestore(&dwc->lock, flags);
 708
 709         pm_runtime_disable(dev);
 710         pm_runtime_set_active(dev);
 711         pm_runtime_enable(dev);
 712
 713         return 0;
 714 }
 715
 716 static const struct dev_pm_ops dwc3_dev_pm_ops = {
 717         .prepare        = dwc3_prepare,
 718         .complete       = dwc3_complete,
 719
 720         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
 721 };
 722
 723 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
 724 #else
 725 #define DWC3_PM_OPS     NULL
 726 #endif
 727
 728 #ifdef CONFIG_OF
 729 static const struct of_device_id of_dwc3_match[] = {
 730         {
 731                 .compatible = "snps,dwc3"
 732         },
 733         {
 734                 .compatible = "synopsys,dwc3"
 735         },
 736         { },
 737 };
 738 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 739 #endif
 740
 741 static struct platform_driver dwc3_driver = {
 742         .probe          = dwc3_probe,
 743         .remove         = dwc3_remove,
 744         .driver         = {
 745                 .name   = "dwc3",
 746                 .of_match_table = of_match_ptr(of_dwc3_match),
 747                 .pm     = DWC3_PM_OPS,
 748         },
 749 };
 750
 751 module_platform_driver(dwc3_driver);
 752
 753 MODULE_ALIAS("platform:dwc3");
 754 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 755 MODULE_LICENSE("GPL v2");
 756 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");