drivers/usb/dwc2/hcd.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * hcd.c - DesignWare HS OTG Controller host-mode routines
   4  *
   5  * Copyright (C) 2004-2013 Synopsys, Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The names of the above-listed copyright holders may not be used
  17  *    to endorse or promote products derived from this software without
  18  *    specific prior written permission.
  19  *
  20  * ALTERNATIVELY, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") as published by the Free Software
  22  * Foundation; either version 2 of the License, or (at your option) any
  23  * later version.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * This file contains the core HCD code, and implements the Linux hc_driver
  40  * API
  41  */
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/spinlock.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/delay.h>
  49 #include <linux/io.h>
  50 #include <linux/slab.h>
  51 #include <linux/usb.h>
  52
  53 #include <linux/usb/hcd.h>
  54 #include <linux/usb/ch11.h>
  55
  56 #include "core.h"
  57 #include "hcd.h"
  58
  59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
  60
  61 /*
  62  * =========================================================================
  63  *  Host Core Layer Functions
  64  * =========================================================================
  65  */
  66
  67 /**
  68  * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
  69  * used in both device and host modes
  70  *
  71  * @hsotg: Programming view of the DWC_otg controller
  72  */
  73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
  74 {
  75         u32 intmsk;
  76
  77         /* Clear any pending OTG Interrupts */
  78         dwc2_writel(hsotg, 0xffffffff, GOTGINT);
  79
  80         /* Clear any pending interrupts */
  81         dwc2_writel(hsotg, 0xffffffff, GINTSTS);
  82
  83         /* Enable the interrupts in the GINTMSK */
  84         intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
  85
  86         if (!hsotg->params.host_dma)
  87                 intmsk |= GINTSTS_RXFLVL;
  88         if (!hsotg->params.external_id_pin_ctl)
  89                 intmsk |= GINTSTS_CONIDSTSCHNG;
  90
  91         intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
  92                   GINTSTS_SESSREQINT;
  93
  94         if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
  95                 intmsk |= GINTSTS_LPMTRANRCVD;
  96
  97         dwc2_writel(hsotg, intmsk, GINTMSK);
  98 }
  99
 100 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 101 {
 102         u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
 103
 104         switch (hsotg->hw_params.arch) {
 105         case GHWCFG2_EXT_DMA_ARCH:
 106                 dev_err(hsotg->dev, "External DMA Mode not supported\n");
 107                 return -EINVAL;
 108
 109         case GHWCFG2_INT_DMA_ARCH:
 110                 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
 111                 if (hsotg->params.ahbcfg != -1) {
 112                         ahbcfg &= GAHBCFG_CTRL_MASK;
 113                         ahbcfg |= hsotg->params.ahbcfg &
 114                                   ~GAHBCFG_CTRL_MASK;
 115                 }
 116                 break;
 117
 118         case GHWCFG2_SLAVE_ONLY_ARCH:
 119         default:
 120                 dev_dbg(hsotg->dev, "Slave Only Mode\n");
 121                 break;
 122         }
 123
 124         if (hsotg->params.host_dma)
 125                 ahbcfg |= GAHBCFG_DMA_EN;
 126         else
 127                 hsotg->params.dma_desc_enable = false;
 128
 129         dwc2_writel(hsotg, ahbcfg, GAHBCFG);
 130
 131         return 0;
 132 }
 133
 134 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
 135 {
 136         u32 usbcfg;
 137
 138         usbcfg = dwc2_readl(hsotg, GUSBCFG);
 139         usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
 140
 141         switch (hsotg->hw_params.op_mode) {
 142         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 143                 if (hsotg->params.otg_cap ==
 144                                 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
 145                         usbcfg |= GUSBCFG_HNPCAP;
 146                 if (hsotg->params.otg_cap !=
 147                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 148                         usbcfg |= GUSBCFG_SRPCAP;
 149                 break;
 150
 151         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 152         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 153         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 154                 if (hsotg->params.otg_cap !=
 155                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 156                         usbcfg |= GUSBCFG_SRPCAP;
 157                 break;
 158
 159         case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
 160         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
 161         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
 162         default:
 163                 break;
 164         }
 165
 166         dwc2_writel(hsotg, usbcfg, GUSBCFG);
 167 }
 168
 169 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
 170 {
 171         if (hsotg->vbus_supply)
 172                 return regulator_enable(hsotg->vbus_supply);
 173
 174         return 0;
 175 }
 176
 177 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
 178 {
 179         if (hsotg->vbus_supply)
 180                 return regulator_disable(hsotg->vbus_supply);
 181
 182         return 0;
 183 }
 184
 185 /**
 186  * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
 187  *
 188  * @hsotg: Programming view of DWC_otg controller
 189  */
 190 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
 191 {
 192         u32 intmsk;
 193
 194         dev_dbg(hsotg->dev, "%s()\n", __func__);
 195
 196         /* Disable all interrupts */
 197         dwc2_writel(hsotg, 0, GINTMSK);
 198         dwc2_writel(hsotg, 0, HAINTMSK);
 199
 200         /* Enable the common interrupts */
 201         dwc2_enable_common_interrupts(hsotg);
 202
 203         /* Enable host mode interrupts without disturbing common interrupts */
 204         intmsk = dwc2_readl(hsotg, GINTMSK);
 205         intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
 206         dwc2_writel(hsotg, intmsk, GINTMSK);
 207 }
 208
 209 /**
 210  * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
 211  *
 212  * @hsotg: Programming view of DWC_otg controller
 213  */
 214 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
 215 {
 216         u32 intmsk = dwc2_readl(hsotg, GINTMSK);
 217
 218         /* Disable host mode interrupts without disturbing common interrupts */
 219         intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
 220                     GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
 221         dwc2_writel(hsotg, intmsk, GINTMSK);
 222 }
 223
 224 /*
 225  * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
 226  * For system that have a total fifo depth that is smaller than the default
 227  * RX + TX fifo size.
 228  *
 229  * @hsotg: Programming view of DWC_otg controller
 230  */
 231 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
 232 {
 233         struct dwc2_core_params *params = &hsotg->params;
 234         struct dwc2_hw_params *hw = &hsotg->hw_params;
 235         u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
 236
 237         total_fifo_size = hw->total_fifo_size;
 238         rxfsiz = params->host_rx_fifo_size;
 239         nptxfsiz = params->host_nperio_tx_fifo_size;
 240         ptxfsiz = params->host_perio_tx_fifo_size;
 241
 242         /*
 243          * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
 244          * allocation with support for high bandwidth endpoints. Synopsys
 245          * defines MPS(Max Packet size) for a periodic EP=1024, and for
 246          * non-periodic as 512.
 247          */
 248         if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
 249                 /*
 250                  * For Buffer DMA mode/Scatter Gather DMA mode
 251                  * 2 * ((Largest Packet size / 4) + 1 + 1) + n
 252                  * with n = number of host channel.
 253                  * 2 * ((1024/4) + 2) = 516
 254                  */
 255                 rxfsiz = 516 + hw->host_channels;
 256
 257                 /*
 258                  * min non-periodic tx fifo depth
 259                  * 2 * (largest non-periodic USB packet used / 4)
 260                  * 2 * (512/4) = 256
 261                  */
 262                 nptxfsiz = 256;
 263
 264                 /*
 265                  * min periodic tx fifo depth
 266                  * (largest packet size*MC)/4
 267                  * (1024 * 3)/4 = 768
 268                  */
 269                 ptxfsiz = 768;
 270
 271                 params->host_rx_fifo_size = rxfsiz;
 272                 params->host_nperio_tx_fifo_size = nptxfsiz;
 273                 params->host_perio_tx_fifo_size = ptxfsiz;
 274         }
 275
 276         /*
 277          * If the summation of RX, NPTX and PTX fifo sizes is still
 278          * bigger than the total_fifo_size, then we have a problem.
 279          *
 280          * We won't be able to allocate as many endpoints. Right now,
 281          * we're just printing an error message, but ideally this FIFO
 282          * allocation algorithm would be improved in the future.
 283          *
 284          * FIXME improve this FIFO allocation algorithm.
 285          */
 286         if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
 287                 dev_err(hsotg->dev, "invalid fifo sizes\n");
 288 }
 289
 290 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
 291 {
 292         struct dwc2_core_params *params = &hsotg->params;
 293         u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
 294
 295         if (!params->enable_dynamic_fifo)
 296                 return;
 297
 298         dwc2_calculate_dynamic_fifo(hsotg);
 299
 300         /* Rx FIFO */
 301         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 302         dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
 303         grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
 304         grxfsiz |= params->host_rx_fifo_size <<
 305                    GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
 306         dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
 307         dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
 308                 dwc2_readl(hsotg, GRXFSIZ));
 309
 310         /* Non-periodic Tx FIFO */
 311         dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
 312                 dwc2_readl(hsotg, GNPTXFSIZ));
 313         nptxfsiz = params->host_nperio_tx_fifo_size <<
 314                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 315         nptxfsiz |= params->host_rx_fifo_size <<
 316                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 317         dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
 318         dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
 319                 dwc2_readl(hsotg, GNPTXFSIZ));
 320
 321         /* Periodic Tx FIFO */
 322         dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
 323                 dwc2_readl(hsotg, HPTXFSIZ));
 324         hptxfsiz = params->host_perio_tx_fifo_size <<
 325                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 326         hptxfsiz |= (params->host_rx_fifo_size +
 327                      params->host_nperio_tx_fifo_size) <<
 328                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 329         dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
 330         dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
 331                 dwc2_readl(hsotg, HPTXFSIZ));
 332
 333         if (hsotg->params.en_multiple_tx_fifo &&
 334             hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
 335                 /*
 336                  * This feature was implemented in 2.91a version
 337                  * Global DFIFOCFG calculation for Host mode -
 338                  * include RxFIFO, NPTXFIFO and HPTXFIFO
 339                  */
 340                 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
 341                 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
 342                 dfifocfg |= (params->host_rx_fifo_size +
 343                              params->host_nperio_tx_fifo_size +
 344                              params->host_perio_tx_fifo_size) <<
 345                             GDFIFOCFG_EPINFOBASE_SHIFT &
 346                             GDFIFOCFG_EPINFOBASE_MASK;
 347                 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
 348         }
 349 }
 350
 351 /**
 352  * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
 353  * the HFIR register according to PHY type and speed
 354  *
 355  * @hsotg: Programming view of DWC_otg controller
 356  *
 357  * NOTE: The caller can modify the value of the HFIR register only after the
 358  * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
 359  * has been set
 360  */
 361 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
 362 {
 363         u32 usbcfg;
 364         u32 hprt0;
 365         int clock = 60; /* default value */
 366
 367         usbcfg = dwc2_readl(hsotg, GUSBCFG);
 368         hprt0 = dwc2_readl(hsotg, HPRT0);
 369
 370         if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
 371             !(usbcfg & GUSBCFG_PHYIF16))
 372                 clock = 60;
 373         if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
 374             GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
 375                 clock = 48;
 376         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 377             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
 378                 clock = 30;
 379         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 380             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
 381                 clock = 60;
 382         if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 383             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
 384                 clock = 48;
 385         if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
 386             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
 387                 clock = 48;
 388         if ((usbcfg & GUSBCFG_PHYSEL) &&
 389             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 390                 clock = 48;
 391
 392         if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
 393                 /* High speed case */
 394                 return 125 * clock - 1;
 395
 396         /* FS/LS case */
 397         return 1000 * clock - 1;
 398 }
 399
 400 /**
 401  * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
 402  * buffer
 403  *
 404  * @hsotg: Programming view of DWC_otg controller
 405  * @dest:    Destination buffer for the packet
 406  * @bytes:   Number of bytes to copy to the destination
 407  */
 408 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
 409 {
 410         u32 *data_buf = (u32 *)dest;
 411         int word_count = (bytes + 3) / 4;
 412         int i;
 413
 414         /*
 415          * Todo: Account for the case where dest is not dword aligned. This
 416          * requires reading data from the FIFO into a u32 temp buffer, then
 417          * moving it into the data buffer.
 418          */
 419
 420         dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
 421
 422         for (i = 0; i < word_count; i++, data_buf++)
 423                 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
 424 }
 425
 426 /**
 427  * dwc2_dump_channel_info() - Prints the state of a host channel
 428  *
 429  * @hsotg: Programming view of DWC_otg controller
 430  * @chan:  Pointer to the channel to dump
 431  *
 432  * Must be called with interrupt disabled and spinlock held
 433  *
 434  * NOTE: This function will be removed once the peripheral controller code
 435  * is integrated and the driver is stable
 436  */
 437 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
 438                                    struct dwc2_host_chan *chan)
 439 {
 440 #ifdef VERBOSE_DEBUG
 441         int num_channels = hsotg->params.host_channels;
 442         struct dwc2_qh *qh;
 443         u32 hcchar;
 444         u32 hcsplt;
 445         u32 hctsiz;
 446         u32 hc_dma;
 447         int i;
 448
 449         if (!chan)
 450                 return;
 451
 452         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
 453         hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
 454         hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
 455         hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
 456
 457         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
 458         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
 459                 hcchar, hcsplt);
 460         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
 461                 hctsiz, hc_dma);
 462         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 463                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
 464         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
 465         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
 466         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
 467         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
 468         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 469         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 470         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 471                 (unsigned long)chan->xfer_dma);
 472         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 473         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 474         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 475         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 476                             qh_list_entry)
 477                 dev_dbg(hsotg->dev, "    %p\n", qh);
 478         dev_dbg(hsotg->dev, "  NP waiting sched:\n");
 479         list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
 480                             qh_list_entry)
 481                 dev_dbg(hsotg->dev, "    %p\n", qh);
 482         dev_dbg(hsotg->dev, "  NP active sched:\n");
 483         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 484                             qh_list_entry)
 485                 dev_dbg(hsotg->dev, "    %p\n", qh);
 486         dev_dbg(hsotg->dev, "  Channels:\n");
 487         for (i = 0; i < num_channels; i++) {
 488                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 489
 490                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 491         }
 492 #endif /* VERBOSE_DEBUG */
 493 }
 494
 495 static int _dwc2_hcd_start(struct usb_hcd *hcd);
 496
 497 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
 498 {
 499         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
 500
 501         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
 502         _dwc2_hcd_start(hcd);
 503 }
 504
 505 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
 506 {
 507         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
 508
 509         hcd->self.is_b_host = 0;
 510 }
 511
 512 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
 513                                int *hub_addr, int *hub_port)
 514 {
 515         struct urb *urb = context;
 516
 517         if (urb->dev->tt)
 518                 *hub_addr = urb->dev->tt->hub->devnum;
 519         else
 520                 *hub_addr = 0;
 521         *hub_port = urb->dev->ttport;
 522 }
 523
 524 /*
 525  * =========================================================================
 526  *  Low Level Host Channel Access Functions
 527  * =========================================================================
 528  */
 529
 530 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
 531                                       struct dwc2_host_chan *chan)
 532 {
 533         u32 hcintmsk = HCINTMSK_CHHLTD;
 534
 535         switch (chan->ep_type) {
 536         case USB_ENDPOINT_XFER_CONTROL:
 537         case USB_ENDPOINT_XFER_BULK:
 538                 dev_vdbg(hsotg->dev, "control/bulk\n");
 539                 hcintmsk |= HCINTMSK_XFERCOMPL;
 540                 hcintmsk |= HCINTMSK_STALL;
 541                 hcintmsk |= HCINTMSK_XACTERR;
 542                 hcintmsk |= HCINTMSK_DATATGLERR;
 543                 if (chan->ep_is_in) {
 544                         hcintmsk |= HCINTMSK_BBLERR;
 545                 } else {
 546                         hcintmsk |= HCINTMSK_NAK;
 547                         hcintmsk |= HCINTMSK_NYET;
 548                         if (chan->do_ping)
 549                                 hcintmsk |= HCINTMSK_ACK;
 550                 }
 551
 552                 if (chan->do_split) {
 553                         hcintmsk |= HCINTMSK_NAK;
 554                         if (chan->complete_split)
 555                                 hcintmsk |= HCINTMSK_NYET;
 556                         else
 557                                 hcintmsk |= HCINTMSK_ACK;
 558                 }
 559
 560                 if (chan->error_state)
 561                         hcintmsk |= HCINTMSK_ACK;
 562                 break;
 563
 564         case USB_ENDPOINT_XFER_INT:
 565                 if (dbg_perio())
 566                         dev_vdbg(hsotg->dev, "intr\n");
 567                 hcintmsk |= HCINTMSK_XFERCOMPL;
 568                 hcintmsk |= HCINTMSK_NAK;
 569                 hcintmsk |= HCINTMSK_STALL;
 570                 hcintmsk |= HCINTMSK_XACTERR;
 571                 hcintmsk |= HCINTMSK_DATATGLERR;
 572                 hcintmsk |= HCINTMSK_FRMOVRUN;
 573
 574                 if (chan->ep_is_in)
 575                         hcintmsk |= HCINTMSK_BBLERR;
 576                 if (chan->error_state)
 577                         hcintmsk |= HCINTMSK_ACK;
 578                 if (chan->do_split) {
 579                         if (chan->complete_split)
 580                                 hcintmsk |= HCINTMSK_NYET;
 581                         else
 582                                 hcintmsk |= HCINTMSK_ACK;
 583                 }
 584                 break;
 585
 586         case USB_ENDPOINT_XFER_ISOC:
 587                 if (dbg_perio())
 588                         dev_vdbg(hsotg->dev, "isoc\n");
 589                 hcintmsk |= HCINTMSK_XFERCOMPL;
 590                 hcintmsk |= HCINTMSK_FRMOVRUN;
 591                 hcintmsk |= HCINTMSK_ACK;
 592
 593                 if (chan->ep_is_in) {
 594                         hcintmsk |= HCINTMSK_XACTERR;
 595                         hcintmsk |= HCINTMSK_BBLERR;
 596                 }
 597                 break;
 598         default:
 599                 dev_err(hsotg->dev, "## Unknown EP type ##\n");
 600                 break;
 601         }
 602
 603         dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
 604         if (dbg_hc(chan))
 605                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 606 }
 607
 608 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
 609                                     struct dwc2_host_chan *chan)
 610 {
 611         u32 hcintmsk = HCINTMSK_CHHLTD;
 612
 613         /*
 614          * For Descriptor DMA mode core halts the channel on AHB error.
 615          * Interrupt is not required.
 616          */
 617         if (!hsotg->params.dma_desc_enable) {
 618                 if (dbg_hc(chan))
 619                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
 620                 hcintmsk |= HCINTMSK_AHBERR;
 621         } else {
 622                 if (dbg_hc(chan))
 623                         dev_vdbg(hsotg->dev, "desc DMA enabled\n");
 624                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 625                         hcintmsk |= HCINTMSK_XFERCOMPL;
 626         }
 627
 628         if (chan->error_state && !chan->do_split &&
 629             chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
 630                 if (dbg_hc(chan))
 631                         dev_vdbg(hsotg->dev, "setting ACK\n");
 632                 hcintmsk |= HCINTMSK_ACK;
 633                 if (chan->ep_is_in) {
 634                         hcintmsk |= HCINTMSK_DATATGLERR;
 635                         if (chan->ep_type != USB_ENDPOINT_XFER_INT)
 636                                 hcintmsk |= HCINTMSK_NAK;
 637                 }
 638         }
 639
 640         dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
 641         if (dbg_hc(chan))
 642                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 643 }
 644
 645 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
 646                                 struct dwc2_host_chan *chan)
 647 {
 648         u32 intmsk;
 649
 650         if (hsotg->params.host_dma) {
 651                 if (dbg_hc(chan))
 652                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 653                 dwc2_hc_enable_dma_ints(hsotg, chan);
 654         } else {
 655                 if (dbg_hc(chan))
 656                         dev_vdbg(hsotg->dev, "DMA disabled\n");
 657                 dwc2_hc_enable_slave_ints(hsotg, chan);
 658         }
 659
 660         /* Enable the top level host channel interrupt */
 661         intmsk = dwc2_readl(hsotg, HAINTMSK);
 662         intmsk |= 1 << chan->hc_num;
 663         dwc2_writel(hsotg, intmsk, HAINTMSK);
 664         if (dbg_hc(chan))
 665                 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
 666
 667         /* Make sure host channel interrupts are enabled */
 668         intmsk = dwc2_readl(hsotg, GINTMSK);
 669         intmsk |= GINTSTS_HCHINT;
 670         dwc2_writel(hsotg, intmsk, GINTMSK);
 671         if (dbg_hc(chan))
 672                 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
 673 }
 674
 675 /**
 676  * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
 677  * a specific endpoint
 678  *
 679  * @hsotg: Programming view of DWC_otg controller
 680  * @chan:  Information needed to initialize the host channel
 681  *
 682  * The HCCHARn register is set up with the characteristics specified in chan.
 683  * Host channel interrupts that may need to be serviced while this transfer is
 684  * in progress are enabled.
 685  */
 686 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
 687 {
 688         u8 hc_num = chan->hc_num;
 689         u32 hcintmsk;
 690         u32 hcchar;
 691         u32 hcsplt = 0;
 692
 693         if (dbg_hc(chan))
 694                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 695
 696         /* Clear old interrupt conditions for this host channel */
 697         hcintmsk = 0xffffffff;
 698         hcintmsk &= ~HCINTMSK_RESERVED14_31;
 699         dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
 700
 701         /* Enable channel interrupts required for this transfer */
 702         dwc2_hc_enable_ints(hsotg, chan);
 703
 704         /*
 705          * Program the HCCHARn register with the endpoint characteristics for
 706          * the current transfer
 707          */
 708         hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
 709         hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
 710         if (chan->ep_is_in)
 711                 hcchar |= HCCHAR_EPDIR;
 712         if (chan->speed == USB_SPEED_LOW)
 713                 hcchar |= HCCHAR_LSPDDEV;
 714         hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
 715         hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
 716         dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
 717         if (dbg_hc(chan)) {
 718                 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
 719                          hc_num, hcchar);
 720
 721                 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
 722                          __func__, hc_num);
 723                 dev_vdbg(hsotg->dev, "   Dev Addr: %d\n",
 724                          chan->dev_addr);
 725                 dev_vdbg(hsotg->dev, "   Ep Num: %d\n",
 726                          chan->ep_num);
 727                 dev_vdbg(hsotg->dev, "   Is In: %d\n",
 728                          chan->ep_is_in);
 729                 dev_vdbg(hsotg->dev, "   Is Low Speed: %d\n",
 730                          chan->speed == USB_SPEED_LOW);
 731                 dev_vdbg(hsotg->dev, "   Ep Type: %d\n",
 732                          chan->ep_type);
 733                 dev_vdbg(hsotg->dev, "   Max Pkt: %d\n",
 734                          chan->max_packet);
 735         }
 736
 737         /* Program the HCSPLT register for SPLITs */
 738         if (chan->do_split) {
 739                 if (dbg_hc(chan))
 740                         dev_vdbg(hsotg->dev,
 741                                  "Programming HC %d with split --> %s\n",
 742                                  hc_num,
 743                                  chan->complete_split ? "CSPLIT" : "SSPLIT");
 744                 if (chan->complete_split)
 745                         hcsplt |= HCSPLT_COMPSPLT;
 746                 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
 747                           HCSPLT_XACTPOS_MASK;
 748                 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
 749                           HCSPLT_HUBADDR_MASK;
 750                 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
 751                           HCSPLT_PRTADDR_MASK;
 752                 if (dbg_hc(chan)) {
 753                         dev_vdbg(hsotg->dev, "    comp split %d\n",
 754                                  chan->complete_split);
 755                         dev_vdbg(hsotg->dev, "    xact pos %d\n",
 756                                  chan->xact_pos);
 757                         dev_vdbg(hsotg->dev, "    hub addr %d\n",
 758                                  chan->hub_addr);
 759                         dev_vdbg(hsotg->dev, "    hub port %d\n",
 760                                  chan->hub_port);
 761                         dev_vdbg(hsotg->dev, "    is_in %d\n",
 762                                  chan->ep_is_in);
 763                         dev_vdbg(hsotg->dev, "    Max Pkt %d\n",
 764                                  chan->max_packet);
 765                         dev_vdbg(hsotg->dev, "    xferlen %d\n",
 766                                  chan->xfer_len);
 767                 }
 768         }
 769
 770         dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
 771 }
 772
 773 /**
 774  * dwc2_hc_halt() - Attempts to halt a host channel
 775  *
 776  * @hsotg:       Controller register interface
 777  * @chan:        Host channel to halt
 778  * @halt_status: Reason for halting the channel
 779  *
 780  * This function should only be called in Slave mode or to abort a transfer in
 781  * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
 782  * controller halts the channel when the transfer is complete or a condition
 783  * occurs that requires application intervention.
 784  *
 785  * In slave mode, checks for a free request queue entry, then sets the Channel
 786  * Enable and Channel Disable bits of the Host Channel Characteristics
 787  * register of the specified channel to intiate the halt. If there is no free
 788  * request queue entry, sets only the Channel Disable bit of the HCCHARn
 789  * register to flush requests for this channel. In the latter case, sets a
 790  * flag to indicate that the host channel needs to be halted when a request
 791  * queue slot is open.
 792  *
 793  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
 794  * HCCHARn register. The controller ensures there is space in the request
 795  * queue before submitting the halt request.
 796  *
 797  * Some time may elapse before the core flushes any posted requests for this
 798  * host channel and halts. The Channel Halted interrupt handler completes the
 799  * deactivation of the host channel.
 800  */
 801 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 802                   enum dwc2_halt_status halt_status)
 803 {
 804         u32 nptxsts, hptxsts, hcchar;
 805
 806         if (dbg_hc(chan))
 807                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 808
 809         /*
 810          * In buffer DMA or external DMA mode channel can't be halted
 811          * for non-split periodic channels. At the end of the next
 812          * uframe/frame (in the worst case), the core generates a channel
 813          * halted and disables the channel automatically.
 814          */
 815         if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
 816             hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
 817                 if (!chan->do_split &&
 818                     (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
 819                      chan->ep_type == USB_ENDPOINT_XFER_INT)) {
 820                         dev_err(hsotg->dev, "%s() Channel can't be halted\n",
 821                                 __func__);
 822                         return;
 823                 }
 824         }
 825
 826         if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
 827                 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
 828
 829         if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
 830             halt_status == DWC2_HC_XFER_AHB_ERR) {
 831                 /*
 832                  * Disable all channel interrupts except Ch Halted. The QTD
 833                  * and QH state associated with this transfer has been cleared
 834                  * (in the case of URB_DEQUEUE), so the channel needs to be
 835                  * shut down carefully to prevent crashes.
 836                  */
 837                 u32 hcintmsk = HCINTMSK_CHHLTD;
 838
 839                 dev_vdbg(hsotg->dev, "dequeue/error\n");
 840                 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
 841
 842                 /*
 843                  * Make sure no other interrupts besides halt are currently
 844                  * pending. Handling another interrupt could cause a crash due
 845                  * to the QTD and QH state.
 846                  */
 847                 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
 848
 849                 /*
 850                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
 851                  * even if the channel was already halted for some other
 852                  * reason
 853                  */
 854                 chan->halt_status = halt_status;
 855
 856                 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
 857                 if (!(hcchar & HCCHAR_CHENA)) {
 858                         /*
 859                          * The channel is either already halted or it hasn't
 860                          * started yet. In DMA mode, the transfer may halt if
 861                          * it finishes normally or a condition occurs that
 862                          * requires driver intervention. Don't want to halt
 863                          * the channel again. In either Slave or DMA mode,
 864                          * it's possible that the transfer has been assigned
 865                          * to a channel, but not started yet when an URB is
 866                          * dequeued. Don't want to halt a channel that hasn't
 867                          * started yet.
 868                          */
 869                         return;
 870                 }
 871         }
 872         if (chan->halt_pending) {
 873                 /*
 874                  * A halt has already been issued for this channel. This might
 875                  * happen when a transfer is aborted by a higher level in
 876                  * the stack.
 877                  */
 878                 dev_vdbg(hsotg->dev,
 879                          "*** %s: Channel %d, chan->halt_pending already set ***\n",
 880                          __func__, chan->hc_num);
 881                 return;
 882         }
 883
 884         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
 885
 886         /* No need to set the bit in DDMA for disabling the channel */
 887         /* TODO check it everywhere channel is disabled */
 888         if (!hsotg->params.dma_desc_enable) {
 889                 if (dbg_hc(chan))
 890                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
 891                 hcchar |= HCCHAR_CHENA;
 892         } else {
 893                 if (dbg_hc(chan))
 894                         dev_dbg(hsotg->dev, "desc DMA enabled\n");
 895         }
 896         hcchar |= HCCHAR_CHDIS;
 897
 898         if (!hsotg->params.host_dma) {
 899                 if (dbg_hc(chan))
 900                         dev_vdbg(hsotg->dev, "DMA not enabled\n");
 901                 hcchar |= HCCHAR_CHENA;
 902
 903                 /* Check for space in the request queue to issue the halt */
 904                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 905                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 906                         dev_vdbg(hsotg->dev, "control/bulk\n");
 907                         nptxsts = dwc2_readl(hsotg, GNPTXSTS);
 908                         if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
 909                                 dev_vdbg(hsotg->dev, "Disabling channel\n");
 910                                 hcchar &= ~HCCHAR_CHENA;
 911                         }
 912                 } else {
 913                         if (dbg_perio())
 914                                 dev_vdbg(hsotg->dev, "isoc/intr\n");
 915                         hptxsts = dwc2_readl(hsotg, HPTXSTS);
 916                         if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
 917                             hsotg->queuing_high_bandwidth) {
 918                                 if (dbg_perio())
 919                                         dev_vdbg(hsotg->dev, "Disabling channel\n");
 920                                 hcchar &= ~HCCHAR_CHENA;
 921                         }
 922                 }
 923         } else {
 924                 if (dbg_hc(chan))
 925                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 926         }
 927
 928         dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
 929         chan->halt_status = halt_status;
 930
 931         if (hcchar & HCCHAR_CHENA) {
 932                 if (dbg_hc(chan))
 933                         dev_vdbg(hsotg->dev, "Channel enabled\n");
 934                 chan->halt_pending = 1;
 935                 chan->halt_on_queue = 0;
 936         } else {
 937                 if (dbg_hc(chan))
 938                         dev_vdbg(hsotg->dev, "Channel disabled\n");
 939                 chan->halt_on_queue = 1;
 940         }
 941
 942         if (dbg_hc(chan)) {
 943                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
 944                          chan->hc_num);
 945                 dev_vdbg(hsotg->dev, "   hcchar: 0x%08x\n",
 946                          hcchar);
 947                 dev_vdbg(hsotg->dev, "   halt_pending: %d\n",
 948                          chan->halt_pending);
 949                 dev_vdbg(hsotg->dev, "   halt_on_queue: %d\n",
 950                          chan->halt_on_queue);
 951                 dev_vdbg(hsotg->dev, "   halt_status: %d\n",
 952                          chan->halt_status);
 953         }
 954 }
 955
 956 /**
 957  * dwc2_hc_cleanup() - Clears the transfer state for a host channel
 958  *
 959  * @hsotg: Programming view of DWC_otg controller
 960  * @chan:  Identifies the host channel to clean up
 961  *
 962  * This function is normally called after a transfer is done and the host
 963  * channel is being released
 964  */
 965 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
 966 {
 967         u32 hcintmsk;
 968
 969         chan->xfer_started = 0;
 970
 971         list_del_init(&chan->split_order_list_entry);
 972
 973         /*
 974          * Clear channel interrupt enables and any unhandled channel interrupt
 975          * conditions
 976          */
 977         dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
 978         hcintmsk = 0xffffffff;
 979         hcintmsk &= ~HCINTMSK_RESERVED14_31;
 980         dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
 981 }
 982
 983 /**
 984  * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
 985  * which frame a periodic transfer should occur
 986  *
 987  * @hsotg:  Programming view of DWC_otg controller
 988  * @chan:   Identifies the host channel to set up and its properties
 989  * @hcchar: Current value of the HCCHAR register for the specified host channel
 990  *
 991  * This function has no effect on non-periodic transfers
 992  */
 993 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
 994                                        struct dwc2_host_chan *chan, u32 *hcchar)
 995 {
 996         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
 997             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
 998                 int host_speed;
 999                 int xfer_ns;
1000                 int xfer_us;
1001                 int bytes_in_fifo;
1002                 u16 fifo_space;
1003                 u16 frame_number;
1004                 u16 wire_frame;
1005
1006                 /*
1007                  * Try to figure out if we're an even or odd frame. If we set
1008                  * even and the current frame number is even the the transfer
1009                  * will happen immediately.  Similar if both are odd. If one is
1010                  * even and the other is odd then the transfer will happen when
1011                  * the frame number ticks.
1012                  *
1013                  * There's a bit of a balancing act to get this right.
1014                  * Sometimes we may want to send data in the current frame (AK
1015                  * right away).  We might want to do this if the frame number
1016                  * _just_ ticked, but we might also want to do this in order
1017                  * to continue a split transaction that happened late in a
1018                  * microframe (so we didn't know to queue the next transfer
1019                  * until the frame number had ticked).  The problem is that we
1020                  * need a lot of knowledge to know if there's actually still
1021                  * time to send things or if it would be better to wait until
1022                  * the next frame.
1023                  *
1024                  * We can look at how much time is left in the current frame
1025                  * and make a guess about whether we'll have time to transfer.
1026                  * We'll do that.
1027                  */
1028
1029                 /* Get speed host is running at */
1030                 host_speed = (chan->speed != USB_SPEED_HIGH &&
1031                               !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1032
1033                 /* See how many bytes are in the periodic FIFO right now */
1034                 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1035                               TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1036                 bytes_in_fifo = sizeof(u32) *
1037                                 (hsotg->params.host_perio_tx_fifo_size -
1038                                  fifo_space);
1039
1040                 /*
1041                  * Roughly estimate bus time for everything in the periodic
1042                  * queue + our new transfer.  This is "rough" because we're
1043                  * using a function that makes takes into account IN/OUT
1044                  * and INT/ISO and we're just slamming in one value for all
1045                  * transfers.  This should be an over-estimate and that should
1046                  * be OK, but we can probably tighten it.
1047                  */
1048                 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1049                                             chan->xfer_len + bytes_in_fifo);
1050                 xfer_us = NS_TO_US(xfer_ns);
1051
1052                 /* See what frame number we'll be at by the time we finish */
1053                 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1054
1055                 /* This is when we were scheduled to be on the wire */
1056                 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1057
1058                 /*
1059                  * If we'd finish _after_ the frame we're scheduled in then
1060                  * it's hopeless.  Just schedule right away and hope for the
1061                  * best.  Note that it _might_ be wise to call back into the
1062                  * scheduler to pick a better frame, but this is better than
1063                  * nothing.
1064                  */
1065                 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1066                         dwc2_sch_vdbg(hsotg,
1067                                       "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1068                                       chan->qh, wire_frame, frame_number,
1069                                       dwc2_frame_num_dec(frame_number,
1070                                                          wire_frame));
1071                         wire_frame = frame_number;
1072
1073                         /*
1074                          * We picked a different frame number; communicate this
1075                          * back to the scheduler so it doesn't try to schedule
1076                          * another in the same frame.
1077                          *
1078                          * Remember that next_active_frame is 1 before the wire
1079                          * frame.
1080                          */
1081                         chan->qh->next_active_frame =
1082                                 dwc2_frame_num_dec(frame_number, 1);
1083                 }
1084
1085                 if (wire_frame & 1)
1086                         *hcchar |= HCCHAR_ODDFRM;
1087                 else
1088                         *hcchar &= ~HCCHAR_ODDFRM;
1089         }
1090 }
1091
1092 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1093 {
1094         /* Set up the initial PID for the transfer */
1095         if (chan->speed == USB_SPEED_HIGH) {
1096                 if (chan->ep_is_in) {
1097                         if (chan->multi_count == 1)
1098                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1099                         else if (chan->multi_count == 2)
1100                                 chan->data_pid_start = DWC2_HC_PID_DATA1;
1101                         else
1102                                 chan->data_pid_start = DWC2_HC_PID_DATA2;
1103                 } else {
1104                         if (chan->multi_count == 1)
1105                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1106                         else
1107                                 chan->data_pid_start = DWC2_HC_PID_MDATA;
1108                 }
1109         } else {
1110                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1111         }
1112 }
1113
1114 /**
1115  * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1116  * the Host Channel
1117  *
1118  * @hsotg: Programming view of DWC_otg controller
1119  * @chan:  Information needed to initialize the host channel
1120  *
1121  * This function should only be called in Slave mode. For a channel associated
1122  * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1123  * associated with a periodic EP, the periodic Tx FIFO is written.
1124  *
1125  * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1126  * the number of bytes written to the Tx FIFO.
1127  */
1128 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1129                                  struct dwc2_host_chan *chan)
1130 {
1131         u32 i;
1132         u32 remaining_count;
1133         u32 byte_count;
1134         u32 dword_count;
1135         u32 *data_buf = (u32 *)chan->xfer_buf;
1136
1137         if (dbg_hc(chan))
1138                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1139
1140         remaining_count = chan->xfer_len - chan->xfer_count;
1141         if (remaining_count > chan->max_packet)
1142                 byte_count = chan->max_packet;
1143         else
1144                 byte_count = remaining_count;
1145
1146         dword_count = (byte_count + 3) / 4;
1147
1148         if (((unsigned long)data_buf & 0x3) == 0) {
1149                 /* xfer_buf is DWORD aligned */
1150                 for (i = 0; i < dword_count; i++, data_buf++)
1151                         dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1152         } else {
1153                 /* xfer_buf is not DWORD aligned */
1154                 for (i = 0; i < dword_count; i++, data_buf++) {
1155                         u32 data = data_buf[0] | data_buf[1] << 8 |
1156                                    data_buf[2] << 16 | data_buf[3] << 24;
1157                         dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1158                 }
1159         }
1160
1161         chan->xfer_count += byte_count;
1162         chan->xfer_buf += byte_count;
1163 }
1164
1165 /**
1166  * dwc2_hc_do_ping() - Starts a PING transfer
1167  *
1168  * @hsotg: Programming view of DWC_otg controller
1169  * @chan:  Information needed to initialize the host channel
1170  *
1171  * This function should only be called in Slave mode. The Do Ping bit is set in
1172  * the HCTSIZ register, then the channel is enabled.
1173  */
1174 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1175                             struct dwc2_host_chan *chan)
1176 {
1177         u32 hcchar;
1178         u32 hctsiz;
1179
1180         if (dbg_hc(chan))
1181                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1182                          chan->hc_num);
1183
1184         hctsiz = TSIZ_DOPNG;
1185         hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1186         dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1187
1188         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1189         hcchar |= HCCHAR_CHENA;
1190         hcchar &= ~HCCHAR_CHDIS;
1191         dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1192 }
1193
1194 /**
1195  * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1196  * channel and starts the transfer
1197  *
1198  * @hsotg: Programming view of DWC_otg controller
1199  * @chan:  Information needed to initialize the host channel. The xfer_len value
1200  *         may be reduced to accommodate the max widths of the XferSize and
1201  *         PktCnt fields in the HCTSIZn register. The multi_count value may be
1202  *         changed to reflect the final xfer_len value.
1203  *
1204  * This function may be called in either Slave mode or DMA mode. In Slave mode,
1205  * the caller must ensure that there is sufficient space in the request queue
1206  * and Tx Data FIFO.
1207  *
1208  * For an OUT transfer in Slave mode, it loads a data packet into the
1209  * appropriate FIFO. If necessary, additional data packets are loaded in the
1210  * Host ISR.
1211  *
1212  * For an IN transfer in Slave mode, a data packet is requested. The data
1213  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1214  * additional data packets are requested in the Host ISR.
1215  *
1216  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1217  * register along with a packet count of 1 and the channel is enabled. This
1218  * causes a single PING transaction to occur. Other fields in HCTSIZ are
1219  * simply set to 0 since no data transfer occurs in this case.
1220  *
1221  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1222  * all the information required to perform the subsequent data transfer. In
1223  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1224  * controller performs the entire PING protocol, then starts the data
1225  * transfer.
1226  */
1227 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1228                                    struct dwc2_host_chan *chan)
1229 {
1230         u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1231         u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1232         u32 hcchar;
1233         u32 hctsiz = 0;
1234         u16 num_packets;
1235         u32 ec_mc;
1236
1237         if (dbg_hc(chan))
1238                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1239
1240         if (chan->do_ping) {
1241                 if (!hsotg->params.host_dma) {
1242                         if (dbg_hc(chan))
1243                                 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1244                         dwc2_hc_do_ping(hsotg, chan);
1245                         chan->xfer_started = 1;
1246                         return;
1247                 }
1248
1249                 if (dbg_hc(chan))
1250                         dev_vdbg(hsotg->dev, "ping, DMA\n");
1251
1252                 hctsiz |= TSIZ_DOPNG;
1253         }
1254
1255         if (chan->do_split) {
1256                 if (dbg_hc(chan))
1257                         dev_vdbg(hsotg->dev, "split\n");
1258                 num_packets = 1;
1259
1260                 if (chan->complete_split && !chan->ep_is_in)
1261                         /*
1262                          * For CSPLIT OUT Transfer, set the size to 0 so the
1263                          * core doesn't expect any data written to the FIFO
1264                          */
1265                         chan->xfer_len = 0;
1266                 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1267                         chan->xfer_len = chan->max_packet;
1268                 else if (!chan->ep_is_in && chan->xfer_len > 188)
1269                         chan->xfer_len = 188;
1270
1271                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1272                           TSIZ_XFERSIZE_MASK;
1273
1274                 /* For split set ec_mc for immediate retries */
1275                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1276                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1277                         ec_mc = 3;
1278                 else
1279                         ec_mc = 1;
1280         } else {
1281                 if (dbg_hc(chan))
1282                         dev_vdbg(hsotg->dev, "no split\n");
1283                 /*
1284                  * Ensure that the transfer length and packet count will fit
1285                  * in the widths allocated for them in the HCTSIZn register
1286                  */
1287                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1288                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1289                         /*
1290                          * Make sure the transfer size is no larger than one
1291                          * (micro)frame's worth of data. (A check was done
1292                          * when the periodic transfer was accepted to ensure
1293                          * that a (micro)frame's worth of data can be
1294                          * programmed into a channel.)
1295                          */
1296                         u32 max_periodic_len =
1297                                 chan->multi_count * chan->max_packet;
1298
1299                         if (chan->xfer_len > max_periodic_len)
1300                                 chan->xfer_len = max_periodic_len;
1301                 } else if (chan->xfer_len > max_hc_xfer_size) {
1302                         /*
1303                          * Make sure that xfer_len is a multiple of max packet
1304                          * size
1305                          */
1306                         chan->xfer_len =
1307                                 max_hc_xfer_size - chan->max_packet + 1;
1308                 }
1309
1310                 if (chan->xfer_len > 0) {
1311                         num_packets = (chan->xfer_len + chan->max_packet - 1) /
1312                                         chan->max_packet;
1313                         if (num_packets > max_hc_pkt_count) {
1314                                 num_packets = max_hc_pkt_count;
1315                                 chan->xfer_len = num_packets * chan->max_packet;
1316                         } else if (chan->ep_is_in) {
1317                                 /*
1318                                  * Always program an integral # of max packets
1319                                  * for IN transfers.
1320                                  * Note: This assumes that the input buffer is
1321                                  * aligned and sized accordingly.
1322                                  */
1323                                 chan->xfer_len = num_packets * chan->max_packet;
1324                         }
1325                 } else {
1326                         /* Need 1 packet for transfer length of 0 */
1327                         num_packets = 1;
1328                 }
1329
1330                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1331                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1332                         /*
1333                          * Make sure that the multi_count field matches the
1334                          * actual transfer length
1335                          */
1336                         chan->multi_count = num_packets;
1337
1338                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1339                         dwc2_set_pid_isoc(chan);
1340
1341                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1342                           TSIZ_XFERSIZE_MASK;
1343
1344                 /* The ec_mc gets the multi_count for non-split */
1345                 ec_mc = chan->multi_count;
1346         }
1347
1348         chan->start_pkt_count = num_packets;
1349         hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1350         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1351                   TSIZ_SC_MC_PID_MASK;
1352         dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1353         if (dbg_hc(chan)) {
1354                 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1355                          hctsiz, chan->hc_num);
1356
1357                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1358                          chan->hc_num);
1359                 dev_vdbg(hsotg->dev, "   Xfer Size: %d\n",
1360                          (hctsiz & TSIZ_XFERSIZE_MASK) >>
1361                          TSIZ_XFERSIZE_SHIFT);
1362                 dev_vdbg(hsotg->dev, "   Num Pkts: %d\n",
1363                          (hctsiz & TSIZ_PKTCNT_MASK) >>
1364                          TSIZ_PKTCNT_SHIFT);
1365                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1366                          (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1367                          TSIZ_SC_MC_PID_SHIFT);
1368         }
1369
1370         if (hsotg->params.host_dma) {
1371                 dma_addr_t dma_addr;
1372
1373                 if (chan->align_buf) {
1374                         if (dbg_hc(chan))
1375                                 dev_vdbg(hsotg->dev, "align_buf\n");
1376                         dma_addr = chan->align_buf;
1377                 } else {
1378                         dma_addr = chan->xfer_dma;
1379                 }
1380                 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1381
1382                 if (dbg_hc(chan))
1383                         dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1384                                  (unsigned long)dma_addr, chan->hc_num);
1385         }
1386
1387         /* Start the split */
1388         if (chan->do_split) {
1389                 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1390
1391                 hcsplt |= HCSPLT_SPLTENA;
1392                 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1393         }
1394
1395         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1396         hcchar &= ~HCCHAR_MULTICNT_MASK;
1397         hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1398         dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1399
1400         if (hcchar & HCCHAR_CHDIS)
1401                 dev_warn(hsotg->dev,
1402                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1403                          __func__, chan->hc_num, hcchar);
1404
1405         /* Set host channel enable after all other setup is complete */
1406         hcchar |= HCCHAR_CHENA;
1407         hcchar &= ~HCCHAR_CHDIS;
1408
1409         if (dbg_hc(chan))
1410                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1411                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1412                          HCCHAR_MULTICNT_SHIFT);
1413
1414         dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1415         if (dbg_hc(chan))
1416                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1417                          chan->hc_num);
1418
1419         chan->xfer_started = 1;
1420         chan->requests++;
1421
1422         if (!hsotg->params.host_dma &&
1423             !chan->ep_is_in && chan->xfer_len > 0)
1424                 /* Load OUT packet into the appropriate Tx FIFO */
1425                 dwc2_hc_write_packet(hsotg, chan);
1426 }
1427
1428 /**
1429  * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1430  * host channel and starts the transfer in Descriptor DMA mode
1431  *
1432  * @hsotg: Programming view of DWC_otg controller
1433  * @chan:  Information needed to initialize the host channel
1434  *
1435  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1436  * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1437  * with micro-frame bitmap.
1438  *
1439  * Initializes HCDMA register with descriptor list address and CTD value then
1440  * starts the transfer via enabling the channel.
1441  */
1442 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1443                                  struct dwc2_host_chan *chan)
1444 {
1445         u32 hcchar;
1446         u32 hctsiz = 0;
1447
1448         if (chan->do_ping)
1449                 hctsiz |= TSIZ_DOPNG;
1450
1451         if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1452                 dwc2_set_pid_isoc(chan);
1453
1454         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1455         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1456                   TSIZ_SC_MC_PID_MASK;
1457
1458         /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1459         hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1460
1461         /* Non-zero only for high-speed interrupt endpoints */
1462         hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1463
1464         if (dbg_hc(chan)) {
1465                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1466                          chan->hc_num);
1467                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1468                          chan->data_pid_start);
1469                 dev_vdbg(hsotg->dev, "   NTD: %d\n", chan->ntd - 1);
1470         }
1471
1472         dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1473
1474         dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1475                                    chan->desc_list_sz, DMA_TO_DEVICE);
1476
1477         dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1478
1479         if (dbg_hc(chan))
1480                 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1481                          &chan->desc_list_addr, chan->hc_num);
1482
1483         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1484         hcchar &= ~HCCHAR_MULTICNT_MASK;
1485         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1486                   HCCHAR_MULTICNT_MASK;
1487
1488         if (hcchar & HCCHAR_CHDIS)
1489                 dev_warn(hsotg->dev,
1490                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1491                          __func__, chan->hc_num, hcchar);
1492
1493         /* Set host channel enable after all other setup is complete */
1494         hcchar |= HCCHAR_CHENA;
1495         hcchar &= ~HCCHAR_CHDIS;
1496
1497         if (dbg_hc(chan))
1498                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1499                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1500                          HCCHAR_MULTICNT_SHIFT);
1501
1502         dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1503         if (dbg_hc(chan))
1504                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1505                          chan->hc_num);
1506
1507         chan->xfer_started = 1;
1508         chan->requests++;
1509 }
1510
1511 /**
1512  * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1513  * a previous call to dwc2_hc_start_transfer()
1514  *
1515  * @hsotg: Programming view of DWC_otg controller
1516  * @chan:  Information needed to initialize the host channel
1517  *
1518  * The caller must ensure there is sufficient space in the request queue and Tx
1519  * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1520  * the controller acts autonomously to complete transfers programmed to a host
1521  * channel.
1522  *
1523  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1524  * if there is any data remaining to be queued. For an IN transfer, another
1525  * data packet is always requested. For the SETUP phase of a control transfer,
1526  * this function does nothing.
1527  *
1528  * Return: 1 if a new request is queued, 0 if no more requests are required
1529  * for this transfer
1530  */
1531 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1532                                      struct dwc2_host_chan *chan)
1533 {
1534         if (dbg_hc(chan))
1535                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1536                          chan->hc_num);
1537
1538         if (chan->do_split)
1539                 /* SPLITs always queue just once per channel */
1540                 return 0;
1541
1542         if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1543                 /* SETUPs are queued only once since they can't be NAK'd */
1544                 return 0;
1545
1546         if (chan->ep_is_in) {
1547                 /*
1548                  * Always queue another request for other IN transfers. If
1549                  * back-to-back INs are issued and NAKs are received for both,
1550                  * the driver may still be processing the first NAK when the
1551                  * second NAK is received. When the interrupt handler clears
1552                  * the NAK interrupt for the first NAK, the second NAK will
1553                  * not be seen. So we can't depend on the NAK interrupt
1554                  * handler to requeue a NAK'd request. Instead, IN requests
1555                  * are issued each time this function is called. When the
1556                  * transfer completes, the extra requests for the channel will
1557                  * be flushed.
1558                  */
1559                 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1560
1561                 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1562                 hcchar |= HCCHAR_CHENA;
1563                 hcchar &= ~HCCHAR_CHDIS;
1564                 if (dbg_hc(chan))
1565                         dev_vdbg(hsotg->dev, "   IN xfer: hcchar = 0x%08x\n",
1566                                  hcchar);
1567                 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1568                 chan->requests++;
1569                 return 1;
1570         }
1571
1572         /* OUT transfers */
1573
1574         if (chan->xfer_count < chan->xfer_len) {
1575                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1576                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1577                         u32 hcchar = dwc2_readl(hsotg,
1578                                                 HCCHAR(chan->hc_num));
1579
1580                         dwc2_hc_set_even_odd_frame(hsotg, chan,
1581                                                    &hcchar);
1582                 }
1583
1584                 /* Load OUT packet into the appropriate Tx FIFO */
1585                 dwc2_hc_write_packet(hsotg, chan);
1586                 chan->requests++;
1587                 return 1;
1588         }
1589
1590         return 0;
1591 }
1592
1593 /*
1594  * =========================================================================
1595  *  HCD
1596  * =========================================================================
1597  */
1598
1599 /*
1600  * Processes all the URBs in a single list of QHs. Completes them with
1601  * -ETIMEDOUT and frees the QTD.
1602  *
1603  * Must be called with interrupt disabled and spinlock held
1604  */
1605 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1606                                       struct list_head *qh_list)
1607 {
1608         struct dwc2_qh *qh, *qh_tmp;
1609         struct dwc2_qtd *qtd, *qtd_tmp;
1610
1611         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1612                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1613                                          qtd_list_entry) {
1614                         dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1615                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1616                 }
1617         }
1618 }
1619
1620 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1621                               struct list_head *qh_list)
1622 {
1623         struct dwc2_qtd *qtd, *qtd_tmp;
1624         struct dwc2_qh *qh, *qh_tmp;
1625         unsigned long flags;
1626
1627         if (!qh_list->next)
1628                 /* The list hasn't been initialized yet */
1629                 return;
1630
1631         spin_lock_irqsave(&hsotg->lock, flags);
1632
1633         /* Ensure there are no QTDs or URBs left */
1634         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1635
1636         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1637                 dwc2_hcd_qh_unlink(hsotg, qh);
1638
1639                 /* Free each QTD in the QH's QTD list */
1640                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1641                                          qtd_list_entry)
1642                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1643
1644                 if (qh->channel && qh->channel->qh == qh)
1645                         qh->channel->qh = NULL;
1646
1647                 spin_unlock_irqrestore(&hsotg->lock, flags);
1648                 dwc2_hcd_qh_free(hsotg, qh);
1649                 spin_lock_irqsave(&hsotg->lock, flags);
1650         }
1651
1652         spin_unlock_irqrestore(&hsotg->lock, flags);
1653 }
1654
1655 /*
1656  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1657  * and periodic schedules. The QTD associated with each URB is removed from
1658  * the schedule and freed. This function may be called when a disconnect is
1659  * detected or when the HCD is being stopped.
1660  *
1661  * Must be called with interrupt disabled and spinlock held
1662  */
1663 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1664 {
1665         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1666         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1667         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1668         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1669         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1670         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1671         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1672 }
1673
1674 /**
1675  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1676  *
1677  * @hsotg: Pointer to struct dwc2_hsotg
1678  */
1679 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1680 {
1681         u32 hprt0;
1682
1683         if (hsotg->op_state == OTG_STATE_B_HOST) {
1684                 /*
1685                  * Reset the port. During a HNP mode switch the reset
1686                  * needs to occur within 1ms and have a duration of at
1687                  * least 50ms.
1688                  */
1689                 hprt0 = dwc2_read_hprt0(hsotg);
1690                 hprt0 |= HPRT0_RST;
1691                 dwc2_writel(hsotg, hprt0, HPRT0);
1692         }
1693
1694         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1695                            msecs_to_jiffies(50));
1696 }
1697
1698 /* Must be called with interrupt disabled and spinlock held */
1699 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1700 {
1701         int num_channels = hsotg->params.host_channels;
1702         struct dwc2_host_chan *channel;
1703         u32 hcchar;
1704         int i;
1705
1706         if (!hsotg->params.host_dma) {
1707                 /* Flush out any channel requests in slave mode */
1708                 for (i = 0; i < num_channels; i++) {
1709                         channel = hsotg->hc_ptr_array[i];
1710                         if (!list_empty(&channel->hc_list_entry))
1711                                 continue;
1712                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
1713                         if (hcchar & HCCHAR_CHENA) {
1714                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1715                                 hcchar |= HCCHAR_CHDIS;
1716                                 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1717                         }
1718                 }
1719         }
1720
1721         for (i = 0; i < num_channels; i++) {
1722                 channel = hsotg->hc_ptr_array[i];
1723                 if (!list_empty(&channel->hc_list_entry))
1724                         continue;
1725                 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1726                 if (hcchar & HCCHAR_CHENA) {
1727                         /* Halt the channel */
1728                         hcchar |= HCCHAR_CHDIS;
1729                         dwc2_writel(hsotg, hcchar, HCCHAR(i));
1730                 }
1731
1732                 dwc2_hc_cleanup(hsotg, channel);
1733                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1734                 /*
1735                  * Added for Descriptor DMA to prevent channel double cleanup in
1736                  * release_channel_ddma(), which is called from ep_disable when
1737                  * device disconnects
1738                  */
1739                 channel->qh = NULL;
1740         }
1741         /* All channels have been freed, mark them available */
1742         if (hsotg->params.uframe_sched) {
1743                 hsotg->available_host_channels =
1744                         hsotg->params.host_channels;
1745         } else {
1746                 hsotg->non_periodic_channels = 0;
1747                 hsotg->periodic_channels = 0;
1748         }
1749 }
1750
1751 /**
1752  * dwc2_hcd_connect() - Handles connect of the HCD
1753  *
1754  * @hsotg: Pointer to struct dwc2_hsotg
1755  *
1756  * Must be called with interrupt disabled and spinlock held
1757  */
1758 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1759 {
1760         if (hsotg->lx_state != DWC2_L0)
1761                 usb_hcd_resume_root_hub(hsotg->priv);
1762
1763         hsotg->flags.b.port_connect_status_change = 1;
1764         hsotg->flags.b.port_connect_status = 1;
1765 }
1766
1767 /**
1768  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1769  *
1770  * @hsotg: Pointer to struct dwc2_hsotg
1771  * @force: If true, we won't try to reconnect even if we see device connected.
1772  *
1773  * Must be called with interrupt disabled and spinlock held
1774  */
1775 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1776 {
1777         u32 intr;
1778         u32 hprt0;
1779
1780         /* Set status flags for the hub driver */
1781         hsotg->flags.b.port_connect_status_change = 1;
1782         hsotg->flags.b.port_connect_status = 0;
1783
1784         /*
1785          * Shutdown any transfers in process by clearing the Tx FIFO Empty
1786          * interrupt mask and status bits and disabling subsequent host
1787          * channel interrupts.
1788          */
1789         intr = dwc2_readl(hsotg, GINTMSK);
1790         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1791         dwc2_writel(hsotg, intr, GINTMSK);
1792         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1793         dwc2_writel(hsotg, intr, GINTSTS);
1794
1795         /*
1796          * Turn off the vbus power only if the core has transitioned to device
1797          * mode. If still in host mode, need to keep power on to detect a
1798          * reconnection.
1799          */
1800         if (dwc2_is_device_mode(hsotg)) {
1801                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1802                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1803                         dwc2_writel(hsotg, 0, HPRT0);
1804                 }
1805
1806                 dwc2_disable_host_interrupts(hsotg);
1807         }
1808
1809         /* Respond with an error status to all URBs in the schedule */
1810         dwc2_kill_all_urbs(hsotg);
1811
1812         if (dwc2_is_host_mode(hsotg))
1813                 /* Clean up any host channels that were in use */
1814                 dwc2_hcd_cleanup_channels(hsotg);
1815
1816         dwc2_host_disconnect(hsotg);
1817
1818         /*
1819          * Add an extra check here to see if we're actually connected but
1820          * we don't have a detection interrupt pending.  This can happen if:
1821          *   1. hardware sees connect
1822          *   2. hardware sees disconnect
1823          *   3. hardware sees connect
1824          *   4. dwc2_port_intr() - clears connect interrupt
1825          *   5. dwc2_handle_common_intr() - calls here
1826          *
1827          * Without the extra check here we will end calling disconnect
1828          * and won't get any future interrupts to handle the connect.
1829          */
1830         if (!force) {
1831                 hprt0 = dwc2_readl(hsotg, HPRT0);
1832                 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
1833                         dwc2_hcd_connect(hsotg);
1834         }
1835 }
1836
1837 /**
1838  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1839  *
1840  * @hsotg: Pointer to struct dwc2_hsotg
1841  */
1842 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1843 {
1844         if (hsotg->bus_suspended) {
1845                 hsotg->flags.b.port_suspend_change = 1;
1846                 usb_hcd_resume_root_hub(hsotg->priv);
1847         }
1848
1849         if (hsotg->lx_state == DWC2_L1)
1850                 hsotg->flags.b.port_l1_change = 1;
1851 }
1852
1853 /**
1854  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
1855  *
1856  * @hsotg: Pointer to struct dwc2_hsotg
1857  *
1858  * Must be called with interrupt disabled and spinlock held
1859  */
1860 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1861 {
1862         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1863
1864         /*
1865          * The root hub should be disconnected before this function is called.
1866          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1867          * and the QH lists (via ..._hcd_endpoint_disable).
1868          */
1869
1870         /* Turn off all host-specific interrupts */
1871         dwc2_disable_host_interrupts(hsotg);
1872
1873         /* Turn off the vbus power */
1874         dev_dbg(hsotg->dev, "PortPower off\n");
1875         dwc2_writel(hsotg, 0, HPRT0);
1876 }
1877
1878 /* Caller must hold driver lock */
1879 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
1880                                 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
1881                                 struct dwc2_qtd *qtd)
1882 {
1883         u32 intr_mask;
1884         int retval;
1885         int dev_speed;
1886
1887         if (!hsotg->flags.b.port_connect_status) {
1888                 /* No longer connected */
1889                 dev_err(hsotg->dev, "Not connected\n");
1890                 return -ENODEV;
1891         }
1892
1893         dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1894
1895         /* Some configurations cannot support LS traffic on a FS root port */
1896         if ((dev_speed == USB_SPEED_LOW) &&
1897             (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
1898             (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
1899                 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
1900                 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1901
1902                 if (prtspd == HPRT0_SPD_FULL_SPEED)
1903                         return -ENODEV;
1904         }
1905
1906         if (!qtd)
1907                 return -EINVAL;
1908
1909         dwc2_hcd_qtd_init(qtd, urb);
1910         retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
1911         if (retval) {
1912                 dev_err(hsotg->dev,
1913                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
1914                         retval);
1915                 return retval;
1916         }
1917
1918         intr_mask = dwc2_readl(hsotg, GINTMSK);
1919         if (!(intr_mask & GINTSTS_SOF)) {
1920                 enum dwc2_transaction_type tr_type;
1921
1922                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
1923                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
1924                         /*
1925                          * Do not schedule SG transactions until qtd has
1926                          * URB_GIVEBACK_ASAP set
1927                          */
1928                         return 0;
1929
1930                 tr_type = dwc2_hcd_select_transactions(hsotg);
1931                 if (tr_type != DWC2_TRANSACTION_NONE)
1932                         dwc2_hcd_queue_transactions(hsotg, tr_type);
1933         }
1934
1935         return 0;
1936 }
1937
1938 /* Must be called with interrupt disabled and spinlock held */
1939 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
1940                                 struct dwc2_hcd_urb *urb)
1941 {
1942         struct dwc2_qh *qh;
1943         struct dwc2_qtd *urb_qtd;
1944
1945         urb_qtd = urb->qtd;
1946         if (!urb_qtd) {
1947                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
1948                 return -EINVAL;
1949         }
1950
1951         qh = urb_qtd->qh;
1952         if (!qh) {
1953                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
1954                 return -EINVAL;
1955         }
1956
1957         urb->priv = NULL;
1958
1959         if (urb_qtd->in_process && qh->channel) {
1960                 dwc2_dump_channel_info(hsotg, qh->channel);
1961
1962                 /* The QTD is in process (it has been assigned to a channel) */
1963                 if (hsotg->flags.b.port_connect_status)
1964                         /*
1965                          * If still connected (i.e. in host mode), halt the
1966                          * channel so it can be used for other transfers. If
1967                          * no longer connected, the host registers can't be
1968                          * written to halt the channel since the core is in
1969                          * device mode.
1970                          */
1971                         dwc2_hc_halt(hsotg, qh->channel,
1972                                      DWC2_HC_XFER_URB_DEQUEUE);
1973         }
1974
1975         /*
1976          * Free the QTD and clean up the associated QH. Leave the QH in the
1977          * schedule if it has any remaining QTDs.
1978          */
1979         if (!hsotg->params.dma_desc_enable) {
1980                 u8 in_process = urb_qtd->in_process;
1981
1982                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1983                 if (in_process) {
1984                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
1985                         qh->channel = NULL;
1986                 } else if (list_empty(&qh->qtd_list)) {
1987                         dwc2_hcd_qh_unlink(hsotg, qh);
1988                 }
1989         } else {
1990                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1991         }
1992
1993         return 0;
1994 }
1995
1996 /* Must NOT be called with interrupt disabled or spinlock held */
1997 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
1998                                      struct usb_host_endpoint *ep, int retry)
1999 {
2000         struct dwc2_qtd *qtd, *qtd_tmp;
2001         struct dwc2_qh *qh;
2002         unsigned long flags;
2003         int rc;
2004
2005         spin_lock_irqsave(&hsotg->lock, flags);
2006
2007         qh = ep->hcpriv;
2008         if (!qh) {
2009                 rc = -EINVAL;
2010                 goto err;
2011         }
2012
2013         while (!list_empty(&qh->qtd_list) && retry--) {
2014                 if (retry == 0) {
2015                         dev_err(hsotg->dev,
2016                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2017                         rc = -EBUSY;
2018                         goto err;
2019                 }
2020
2021                 spin_unlock_irqrestore(&hsotg->lock, flags);
2022                 msleep(20);
2023                 spin_lock_irqsave(&hsotg->lock, flags);
2024                 qh = ep->hcpriv;
2025                 if (!qh) {
2026                         rc = -EINVAL;
2027                         goto err;
2028                 }
2029         }
2030
2031         dwc2_hcd_qh_unlink(hsotg, qh);
2032
2033         /* Free each QTD in the QH's QTD list */
2034         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2035                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2036
2037         ep->hcpriv = NULL;
2038
2039         if (qh->channel && qh->channel->qh == qh)
2040                 qh->channel->qh = NULL;
2041
2042         spin_unlock_irqrestore(&hsotg->lock, flags);
2043
2044         dwc2_hcd_qh_free(hsotg, qh);
2045
2046         return 0;
2047
2048 err:
2049         ep->hcpriv = NULL;
2050         spin_unlock_irqrestore(&hsotg->lock, flags);
2051
2052         return rc;
2053 }
2054
2055 /* Must be called with interrupt disabled and spinlock held */
2056 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2057                                    struct usb_host_endpoint *ep)
2058 {
2059         struct dwc2_qh *qh = ep->hcpriv;
2060
2061         if (!qh)
2062                 return -EINVAL;
2063
2064         qh->data_toggle = DWC2_HC_PID_DATA0;
2065
2066         return 0;
2067 }
2068
2069 /**
2070  * dwc2_core_init() - Initializes the DWC_otg controller registers and
2071  * prepares the core for device mode or host mode operation
2072  *
2073  * @hsotg:         Programming view of the DWC_otg controller
2074  * @initial_setup: If true then this is the first init for this instance.
2075  */
2076 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2077 {
2078         u32 usbcfg, otgctl;
2079         int retval;
2080
2081         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2082
2083         usbcfg = dwc2_readl(hsotg, GUSBCFG);
2084
2085         /* Set ULPI External VBUS bit if needed */
2086         usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2087         if (hsotg->params.phy_ulpi_ext_vbus)
2088                 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2089
2090         /* Set external TS Dline pulsing bit if needed */
2091         usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2092         if (hsotg->params.ts_dline)
2093                 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2094
2095         dwc2_writel(hsotg, usbcfg, GUSBCFG);
2096
2097         /*
2098          * Reset the Controller
2099          *
2100          * We only need to reset the controller if this is a re-init.
2101          * For the first init we know for sure that earlier code reset us (it
2102          * needed to in order to properly detect various parameters).
2103          */
2104         if (!initial_setup) {
2105                 retval = dwc2_core_reset(hsotg, false);
2106                 if (retval) {
2107                         dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2108                                 __func__);
2109                         return retval;
2110                 }
2111         }
2112
2113         /*
2114          * This needs to happen in FS mode before any other programming occurs
2115          */
2116         retval = dwc2_phy_init(hsotg, initial_setup);
2117         if (retval)
2118                 return retval;
2119
2120         /* Program the GAHBCFG Register */
2121         retval = dwc2_gahbcfg_init(hsotg);
2122         if (retval)
2123                 return retval;
2124
2125         /* Program the GUSBCFG register */
2126         dwc2_gusbcfg_init(hsotg);
2127
2128         /* Program the GOTGCTL register */
2129         otgctl = dwc2_readl(hsotg, GOTGCTL);
2130         otgctl &= ~GOTGCTL_OTGVER;
2131         dwc2_writel(hsotg, otgctl, GOTGCTL);
2132
2133         /* Clear the SRP success bit for FS-I2c */
2134         hsotg->srp_success = 0;
2135
2136         /* Enable common interrupts */
2137         dwc2_enable_common_interrupts(hsotg);
2138
2139         /*
2140          * Do device or host initialization based on mode during PCD and
2141          * HCD initialization
2142          */
2143         if (dwc2_is_host_mode(hsotg)) {
2144                 dev_dbg(hsotg->dev, "Host Mode\n");
2145                 hsotg->op_state = OTG_STATE_A_HOST;
2146         } else {
2147                 dev_dbg(hsotg->dev, "Device Mode\n");
2148                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2149         }
2150
2151         return 0;
2152 }
2153
2154 /**
2155  * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2156  * Host mode
2157  *
2158  * @hsotg: Programming view of DWC_otg controller
2159  *
2160  * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2161  * request queues. Host channels are reset to ensure that they are ready for
2162  * performing transfers.
2163  */
2164 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2165 {
2166         u32 hcfg, hfir, otgctl, usbcfg;
2167
2168         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2169
2170         /* Set HS/FS Timeout Calibration to 7 (max available value).
2171          * The number of PHY clocks that the application programs in
2172          * this field is added to the high/full speed interpacket timeout
2173          * duration in the core to account for any additional delays
2174          * introduced by the PHY. This can be required, because the delay
2175          * introduced by the PHY in generating the linestate condition
2176          * can vary from one PHY to another.
2177          */
2178         usbcfg = dwc2_readl(hsotg, GUSBCFG);
2179         usbcfg |= GUSBCFG_TOUTCAL(7);
2180         dwc2_writel(hsotg, usbcfg, GUSBCFG);
2181
2182         /* Restart the Phy Clock */
2183         dwc2_writel(hsotg, 0, PCGCTL);
2184
2185         /* Initialize Host Configuration Register */
2186         dwc2_init_fs_ls_pclk_sel(hsotg);
2187         if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2188             hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2189                 hcfg = dwc2_readl(hsotg, HCFG);
2190                 hcfg |= HCFG_FSLSSUPP;
2191                 dwc2_writel(hsotg, hcfg, HCFG);
2192         }
2193
2194         /*
2195          * This bit allows dynamic reloading of the HFIR register during
2196          * runtime. This bit needs to be programmed during initial configuration
2197          * and its value must not be changed during runtime.
2198          */
2199         if (hsotg->params.reload_ctl) {
2200                 hfir = dwc2_readl(hsotg, HFIR);
2201                 hfir |= HFIR_RLDCTRL;
2202                 dwc2_writel(hsotg, hfir, HFIR);
2203         }
2204
2205         if (hsotg->params.dma_desc_enable) {
2206                 u32 op_mode = hsotg->hw_params.op_mode;
2207
2208                 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2209                     !hsotg->hw_params.dma_desc_enable ||
2210                     op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2211                     op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2212                     op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2213                         dev_err(hsotg->dev,
2214                                 "Hardware does not support descriptor DMA mode -\n");
2215                         dev_err(hsotg->dev,
2216                                 "falling back to buffer DMA mode.\n");
2217                         hsotg->params.dma_desc_enable = false;
2218                 } else {
2219                         hcfg = dwc2_readl(hsotg, HCFG);
2220                         hcfg |= HCFG_DESCDMA;
2221                         dwc2_writel(hsotg, hcfg, HCFG);
2222                 }
2223         }
2224
2225         /* Configure data FIFO sizes */
2226         dwc2_config_fifos(hsotg);
2227
2228         /* TODO - check this */
2229         /* Clear Host Set HNP Enable in the OTG Control Register */
2230         otgctl = dwc2_readl(hsotg, GOTGCTL);
2231         otgctl &= ~GOTGCTL_HSTSETHNPEN;
2232         dwc2_writel(hsotg, otgctl, GOTGCTL);
2233
2234         /* Make sure the FIFOs are flushed */
2235         dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2236         dwc2_flush_rx_fifo(hsotg);
2237
2238         /* Clear Host Set HNP Enable in the OTG Control Register */
2239         otgctl = dwc2_readl(hsotg, GOTGCTL);
2240         otgctl &= ~GOTGCTL_HSTSETHNPEN;
2241         dwc2_writel(hsotg, otgctl, GOTGCTL);
2242
2243         if (!hsotg->params.dma_desc_enable) {
2244                 int num_channels, i;
2245                 u32 hcchar;
2246
2247                 /* Flush out any leftover queued requests */
2248                 num_channels = hsotg->params.host_channels;
2249                 for (i = 0; i < num_channels; i++) {
2250                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
2251                         if (hcchar & HCCHAR_CHENA) {
2252                                 hcchar &= ~HCCHAR_CHENA;
2253                                 hcchar |= HCCHAR_CHDIS;
2254                                 hcchar &= ~HCCHAR_EPDIR;
2255                                 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2256                         }
2257                 }
2258
2259                 /* Halt all channels to put them into a known state */
2260                 for (i = 0; i < num_channels; i++) {
2261                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
2262                         if (hcchar & HCCHAR_CHENA) {
2263                                 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2264                                 hcchar &= ~HCCHAR_EPDIR;
2265                                 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2266                                 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2267                                         __func__, i);
2268
2269                                 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2270                                                               HCCHAR_CHENA,
2271                                                               1000)) {
2272                                         dev_warn(hsotg->dev,
2273                                                  "Unable to clear enable on channel %d\n",
2274                                                  i);
2275                                 }
2276                         }
2277                 }
2278         }
2279
2280         /* Enable ACG feature in host mode, if supported */
2281         dwc2_enable_acg(hsotg);
2282
2283         /* Turn on the vbus power */
2284         dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2285         if (hsotg->op_state == OTG_STATE_A_HOST) {
2286                 u32 hprt0 = dwc2_read_hprt0(hsotg);
2287
2288                 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2289                         !!(hprt0 & HPRT0_PWR));
2290                 if (!(hprt0 & HPRT0_PWR)) {
2291                         hprt0 |= HPRT0_PWR;
2292                         dwc2_writel(hsotg, hprt0, HPRT0);
2293                 }
2294         }
2295
2296         dwc2_enable_host_interrupts(hsotg);
2297 }
2298
2299 /*
2300  * Initializes dynamic portions of the DWC_otg HCD state
2301  *
2302  * Must be called with interrupt disabled and spinlock held
2303  */
2304 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2305 {
2306         struct dwc2_host_chan *chan, *chan_tmp;
2307         int num_channels;
2308         int i;
2309
2310         hsotg->flags.d32 = 0;
2311         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2312
2313         if (hsotg->params.uframe_sched) {
2314                 hsotg->available_host_channels =
2315                         hsotg->params.host_channels;
2316         } else {
2317                 hsotg->non_periodic_channels = 0;
2318                 hsotg->periodic_channels = 0;
2319         }
2320
2321         /*
2322          * Put all channels in the free channel list and clean up channel
2323          * states
2324          */
2325         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2326                                  hc_list_entry)
2327                 list_del_init(&chan->hc_list_entry);
2328
2329         num_channels = hsotg->params.host_channels;
2330         for (i = 0; i < num_channels; i++) {
2331                 chan = hsotg->hc_ptr_array[i];
2332                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2333                 dwc2_hc_cleanup(hsotg, chan);
2334         }
2335
2336         /* Initialize the DWC core for host mode operation */
2337         dwc2_core_host_init(hsotg);
2338 }
2339
2340 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2341                                struct dwc2_host_chan *chan,
2342                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2343 {
2344         int hub_addr, hub_port;
2345
2346         chan->do_split = 1;
2347         chan->xact_pos = qtd->isoc_split_pos;
2348         chan->complete_split = qtd->complete_split;
2349         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2350         chan->hub_addr = (u8)hub_addr;
2351         chan->hub_port = (u8)hub_port;
2352 }
2353
2354 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2355                               struct dwc2_host_chan *chan,
2356                               struct dwc2_qtd *qtd)
2357 {
2358         struct dwc2_hcd_urb *urb = qtd->urb;
2359         struct dwc2_hcd_iso_packet_desc *frame_desc;
2360
2361         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2362         case USB_ENDPOINT_XFER_CONTROL:
2363                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2364
2365                 switch (qtd->control_phase) {
2366                 case DWC2_CONTROL_SETUP:
2367                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
2368                         chan->do_ping = 0;
2369                         chan->ep_is_in = 0;
2370                         chan->data_pid_start = DWC2_HC_PID_SETUP;
2371                         if (hsotg->params.host_dma)
2372                                 chan->xfer_dma = urb->setup_dma;
2373                         else
2374                                 chan->xfer_buf = urb->setup_packet;
2375                         chan->xfer_len = 8;
2376                         break;
2377
2378                 case DWC2_CONTROL_DATA:
2379                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
2380                         chan->data_pid_start = qtd->data_toggle;
2381                         break;
2382
2383                 case DWC2_CONTROL_STATUS:
2384                         /*
2385                          * Direction is opposite of data direction or IN if no
2386                          * data
2387                          */
2388                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
2389                         if (urb->length == 0)
2390                                 chan->ep_is_in = 1;
2391                         else
2392                                 chan->ep_is_in =
2393                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
2394                         if (chan->ep_is_in)
2395                                 chan->do_ping = 0;
2396                         chan->data_pid_start = DWC2_HC_PID_DATA1;
2397                         chan->xfer_len = 0;
2398                         if (hsotg->params.host_dma)
2399                                 chan->xfer_dma = hsotg->status_buf_dma;
2400                         else
2401                                 chan->xfer_buf = hsotg->status_buf;
2402                         break;
2403                 }
2404                 break;
2405
2406         case USB_ENDPOINT_XFER_BULK:
2407                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2408                 break;
2409
2410         case USB_ENDPOINT_XFER_INT:
2411                 chan->ep_type = USB_ENDPOINT_XFER_INT;
2412                 break;
2413
2414         case USB_ENDPOINT_XFER_ISOC:
2415                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2416                 if (hsotg->params.dma_desc_enable)
2417                         break;
2418
2419                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2420                 frame_desc->status = 0;
2421
2422                 if (hsotg->params.host_dma) {
2423                         chan->xfer_dma = urb->dma;
2424                         chan->xfer_dma += frame_desc->offset +
2425                                         qtd->isoc_split_offset;
2426                 } else {
2427                         chan->xfer_buf = urb->buf;
2428                         chan->xfer_buf += frame_desc->offset +
2429                                         qtd->isoc_split_offset;
2430                 }
2431
2432                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2433
2434                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2435                         if (chan->xfer_len <= 188)
2436                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2437                         else
2438                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2439                 }
2440                 break;
2441         }
2442 }
2443
2444 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2445                                             struct dwc2_qh *qh,
2446                                             struct dwc2_host_chan *chan)
2447 {
2448         if (!hsotg->unaligned_cache ||
2449             chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2450                 return -ENOMEM;
2451
2452         if (!qh->dw_align_buf) {
2453                 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2454                                                     GFP_ATOMIC | GFP_DMA);
2455                 if (!qh->dw_align_buf)
2456                         return -ENOMEM;
2457         }
2458
2459         qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2460                                               DWC2_KMEM_UNALIGNED_BUF_SIZE,
2461                                               DMA_FROM_DEVICE);
2462
2463         if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2464                 dev_err(hsotg->dev, "can't map align_buf\n");
2465                 chan->align_buf = 0;
2466                 return -EINVAL;
2467         }
2468
2469         chan->align_buf = qh->dw_align_buf_dma;
2470         return 0;
2471 }
2472
2473 #define DWC2_USB_DMA_ALIGN 4
2474
2475 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2476 {
2477         void *stored_xfer_buffer;
2478         size_t length;
2479
2480         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2481                 return;
2482
2483         /* Restore urb->transfer_buffer from the end of the allocated area */
2484         memcpy(&stored_xfer_buffer,
2485                PTR_ALIGN(urb->transfer_buffer + urb->transfer_buffer_length,
2486                          dma_get_cache_alignment()),
2487                sizeof(urb->transfer_buffer));
2488
2489         if (usb_urb_dir_in(urb)) {
2490                 if (usb_pipeisoc(urb->pipe))
2491                         length = urb->transfer_buffer_length;
2492                 else
2493                         length = urb->actual_length;
2494
2495                 memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
2496         }
2497         kfree(urb->transfer_buffer);
2498         urb->transfer_buffer = stored_xfer_buffer;
2499
2500         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2501 }
2502
2503 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2504 {
2505         void *kmalloc_ptr;
2506         size_t kmalloc_size;
2507
2508         if (urb->num_sgs || urb->sg ||
2509             urb->transfer_buffer_length == 0 ||
2510             !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2511                 return 0;
2512
2513         /*
2514          * Allocate a buffer with enough padding for original transfer_buffer
2515          * pointer. This allocation is guaranteed to be aligned properly for
2516          * DMA
2517          */
2518         kmalloc_size = urb->transfer_buffer_length +
2519                 (dma_get_cache_alignment() - 1) +
2520                 sizeof(urb->transfer_buffer);
2521
2522         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2523         if (!kmalloc_ptr)
2524                 return -ENOMEM;
2525
2526         /*
2527          * Position value of original urb->transfer_buffer pointer to the end
2528          * of allocation for later referencing
2529          */
2530         memcpy(PTR_ALIGN(kmalloc_ptr + urb->transfer_buffer_length,
2531                          dma_get_cache_alignment()),
2532                &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2533
2534         if (usb_urb_dir_out(urb))
2535                 memcpy(kmalloc_ptr, urb->transfer_buffer,
2536                        urb->transfer_buffer_length);
2537         urb->transfer_buffer = kmalloc_ptr;
2538
2539         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2540
2541         return 0;
2542 }
2543
2544 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2545                                 gfp_t mem_flags)
2546 {
2547         int ret;
2548
2549         /* We assume setup_dma is always aligned; warn if not */
2550         WARN_ON_ONCE(urb->setup_dma &&
2551                      (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2552
2553         ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2554         if (ret)
2555                 return ret;
2556
2557         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2558         if (ret)
2559                 dwc2_free_dma_aligned_buffer(urb);
2560
2561         return ret;
2562 }
2563
2564 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2565 {
2566         usb_hcd_unmap_urb_for_dma(hcd, urb);
2567         dwc2_free_dma_aligned_buffer(urb);
2568 }
2569
2570 /**
2571  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2572  * channel and initializes the host channel to perform the transactions. The
2573  * host channel is removed from the free list.
2574  *
2575  * @hsotg: The HCD state structure
2576  * @qh:    Transactions from the first QTD for this QH are selected and assigned
2577  *         to a free host channel
2578  */
2579 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2580 {
2581         struct dwc2_host_chan *chan;
2582         struct dwc2_hcd_urb *urb;
2583         struct dwc2_qtd *qtd;
2584
2585         if (dbg_qh(qh))
2586                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2587
2588         if (list_empty(&qh->qtd_list)) {
2589                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2590                 return -ENOMEM;
2591         }
2592
2593         if (list_empty(&hsotg->free_hc_list)) {
2594                 dev_dbg(hsotg->dev, "No free channel to assign\n");
2595                 return -ENOMEM;
2596         }
2597
2598         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2599                                 hc_list_entry);
2600
2601         /* Remove host channel from free list */
2602         list_del_init(&chan->hc_list_entry);
2603
2604         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2605         urb = qtd->urb;
2606         qh->channel = chan;
2607         qtd->in_process = 1;
2608
2609         /*
2610          * Use usb_pipedevice to determine device address. This address is
2611          * 0 before the SET_ADDRESS command and the correct address afterward.
2612          */
2613         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2614         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2615         chan->speed = qh->dev_speed;
2616         chan->max_packet = qh->maxp;
2617
2618         chan->xfer_started = 0;
2619         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2620         chan->error_state = (qtd->error_count > 0);
2621         chan->halt_on_queue = 0;
2622         chan->halt_pending = 0;
2623         chan->requests = 0;
2624
2625         /*
2626          * The following values may be modified in the transfer type section
2627          * below. The xfer_len value may be reduced when the transfer is
2628          * started to accommodate the max widths of the XferSize and PktCnt
2629          * fields in the HCTSIZn register.
2630          */
2631
2632         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2633         if (chan->ep_is_in)
2634                 chan->do_ping = 0;
2635         else
2636                 chan->do_ping = qh->ping_state;
2637
2638         chan->data_pid_start = qh->data_toggle;
2639         chan->multi_count = 1;
2640
2641         if (urb->actual_length > urb->length &&
2642             !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2643                 urb->actual_length = urb->length;
2644
2645         if (hsotg->params.host_dma)
2646                 chan->xfer_dma = urb->dma + urb->actual_length;
2647         else
2648                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2649
2650         chan->xfer_len = urb->length - urb->actual_length;
2651         chan->xfer_count = 0;
2652
2653         /* Set the split attributes if required */
2654         if (qh->do_split)
2655                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2656         else
2657                 chan->do_split = 0;
2658
2659         /* Set the transfer attributes */
2660         dwc2_hc_init_xfer(hsotg, chan, qtd);
2661
2662         /* For non-dword aligned buffers */
2663         if (hsotg->params.host_dma && qh->do_split &&
2664             chan->ep_is_in && (chan->xfer_dma & 0x3)) {
2665                 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2666                 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2667                         dev_err(hsotg->dev,
2668                                 "Failed to allocate memory to handle non-aligned buffer\n");
2669                         /* Add channel back to free list */
2670                         chan->align_buf = 0;
2671                         chan->multi_count = 0;
2672                         list_add_tail(&chan->hc_list_entry,
2673                                       &hsotg->free_hc_list);
2674                         qtd->in_process = 0;
2675                         qh->channel = NULL;
2676                         return -ENOMEM;
2677                 }
2678         } else {
2679                 /*
2680                  * We assume that DMA is always aligned in non-split
2681                  * case or split out case. Warn if not.
2682                  */
2683                 WARN_ON_ONCE(hsotg->params.host_dma &&
2684                              (chan->xfer_dma & 0x3));
2685                 chan->align_buf = 0;
2686         }
2687
2688         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2689             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2690                 /*
2691                  * This value may be modified when the transfer is started
2692                  * to reflect the actual transfer length
2693                  */
2694                 chan->multi_count = qh->maxp_mult;
2695
2696         if (hsotg->params.dma_desc_enable) {
2697                 chan->desc_list_addr = qh->desc_list_dma;
2698                 chan->desc_list_sz = qh->desc_list_sz;
2699         }
2700
2701         dwc2_hc_init(hsotg, chan);
2702         chan->qh = qh;
2703
2704         return 0;
2705 }
2706
2707 /**
2708  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2709  * schedule and assigns them to available host channels. Called from the HCD
2710  * interrupt handler functions.
2711  *
2712  * @hsotg: The HCD state structure
2713  *
2714  * Return: The types of new transactions that were assigned to host channels
2715  */
2716 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2717                 struct dwc2_hsotg *hsotg)
2718 {
2719         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2720         struct list_head *qh_ptr;
2721         struct dwc2_qh *qh;
2722         int num_channels;
2723
2724 #ifdef DWC2_DEBUG_SOF
2725         dev_vdbg(hsotg->dev, "  Select Transactions\n");
2726 #endif
2727
2728         /* Process entries in the periodic ready list */
2729         qh_ptr = hsotg->periodic_sched_ready.next;
2730         while (qh_ptr != &hsotg->periodic_sched_ready) {
2731                 if (list_empty(&hsotg->free_hc_list))
2732                         break;
2733                 if (hsotg->params.uframe_sched) {
2734                         if (hsotg->available_host_channels <= 1)
2735                                 break;
2736                         hsotg->available_host_channels--;
2737                 }
2738                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2739                 if (dwc2_assign_and_init_hc(hsotg, qh))
2740                         break;
2741
2742                 /*
2743                  * Move the QH from the periodic ready schedule to the
2744                  * periodic assigned schedule
2745                  */
2746                 qh_ptr = qh_ptr->next;
2747                 list_move_tail(&qh->qh_list_entry,
2748                                &hsotg->periodic_sched_assigned);
2749                 ret_val = DWC2_TRANSACTION_PERIODIC;
2750         }
2751
2752         /*
2753          * Process entries in the inactive portion of the non-periodic
2754          * schedule. Some free host channels may not be used if they are
2755          * reserved for periodic transfers.
2756          */
2757         num_channels = hsotg->params.host_channels;
2758         qh_ptr = hsotg->non_periodic_sched_inactive.next;
2759         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2760                 if (!hsotg->params.uframe_sched &&
2761                     hsotg->non_periodic_channels >= num_channels -
2762                                                 hsotg->periodic_channels)
2763                         break;
2764                 if (list_empty(&hsotg->free_hc_list))
2765                         break;
2766                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2767                 if (hsotg->params.uframe_sched) {
2768                         if (hsotg->available_host_channels < 1)
2769                                 break;
2770                         hsotg->available_host_channels--;
2771                 }
2772
2773                 if (dwc2_assign_and_init_hc(hsotg, qh))
2774                         break;
2775
2776                 /*
2777                  * Move the QH from the non-periodic inactive schedule to the
2778                  * non-periodic active schedule
2779                  */
2780                 qh_ptr = qh_ptr->next;
2781                 list_move_tail(&qh->qh_list_entry,
2782                                &hsotg->non_periodic_sched_active);
2783
2784                 if (ret_val == DWC2_TRANSACTION_NONE)
2785                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2786                 else
2787                         ret_val = DWC2_TRANSACTION_ALL;
2788
2789                 if (!hsotg->params.uframe_sched)
2790                         hsotg->non_periodic_channels++;
2791         }
2792
2793         return ret_val;
2794 }
2795
2796 /**
2797  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2798  * a host channel associated with either a periodic or non-periodic transfer
2799  *
2800  * @hsotg: The HCD state structure
2801  * @chan:  Host channel descriptor associated with either a periodic or
2802  *         non-periodic transfer
2803  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2804  *                     for periodic transfers or the non-periodic Tx FIFO
2805  *                     for non-periodic transfers
2806  *
2807  * Return: 1 if a request is queued and more requests may be needed to
2808  * complete the transfer, 0 if no more requests are required for this
2809  * transfer, -1 if there is insufficient space in the Tx FIFO
2810  *
2811  * This function assumes that there is space available in the appropriate
2812  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2813  * it checks whether space is available in the appropriate Tx FIFO.
2814  *
2815  * Must be called with interrupt disabled and spinlock held
2816  */
2817 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2818                                   struct dwc2_host_chan *chan,
2819                                   u16 fifo_dwords_avail)
2820 {
2821         int retval = 0;
2822
2823         if (chan->do_split)
2824                 /* Put ourselves on the list to keep order straight */
2825                 list_move_tail(&chan->split_order_list_entry,
2826                                &hsotg->split_order);
2827
2828         if (hsotg->params.host_dma && chan->qh) {
2829                 if (hsotg->params.dma_desc_enable) {
2830                         if (!chan->xfer_started ||
2831                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2832                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2833                                 chan->qh->ping_state = 0;
2834                         }
2835                 } else if (!chan->xfer_started) {
2836                         dwc2_hc_start_transfer(hsotg, chan);
2837                         chan->qh->ping_state = 0;
2838                 }
2839         } else if (chan->halt_pending) {
2840                 /* Don't queue a request if the channel has been halted */
2841         } else if (chan->halt_on_queue) {
2842                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2843         } else if (chan->do_ping) {
2844                 if (!chan->xfer_started)
2845                         dwc2_hc_start_transfer(hsotg, chan);
2846         } else if (!chan->ep_is_in ||
2847                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
2848                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2849                         if (!chan->xfer_started) {
2850                                 dwc2_hc_start_transfer(hsotg, chan);
2851                                 retval = 1;
2852                         } else {
2853                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
2854                         }
2855                 } else {
2856                         retval = -1;
2857                 }
2858         } else {
2859                 if (!chan->xfer_started) {
2860                         dwc2_hc_start_transfer(hsotg, chan);
2861                         retval = 1;
2862                 } else {
2863                         retval = dwc2_hc_continue_transfer(hsotg, chan);
2864                 }
2865         }
2866
2867         return retval;
2868 }
2869
2870 /*
2871  * Processes periodic channels for the next frame and queues transactions for
2872  * these channels to the DWC_otg controller. After queueing transactions, the
2873  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2874  * to queue as Periodic Tx FIFO or request queue space becomes available.
2875  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2876  *
2877  * Must be called with interrupt disabled and spinlock held
2878  */
2879 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2880 {
2881         struct list_head *qh_ptr;
2882         struct dwc2_qh *qh;
2883         u32 tx_status;
2884         u32 fspcavail;
2885         u32 gintmsk;
2886         int status;
2887         bool no_queue_space = false;
2888         bool no_fifo_space = false;
2889         u32 qspcavail;
2890
2891         /* If empty list then just adjust interrupt enables */
2892         if (list_empty(&hsotg->periodic_sched_assigned))
2893                 goto exit;
2894
2895         if (dbg_perio())
2896                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2897
2898         tx_status = dwc2_readl(hsotg, HPTXSTS);
2899         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2900                     TXSTS_QSPCAVAIL_SHIFT;
2901         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2902                     TXSTS_FSPCAVAIL_SHIFT;
2903
2904         if (dbg_perio()) {
2905                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
2906                          qspcavail);
2907                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
2908                          fspcavail);
2909         }
2910
2911         qh_ptr = hsotg->periodic_sched_assigned.next;
2912         while (qh_ptr != &hsotg->periodic_sched_assigned) {
2913                 tx_status = dwc2_readl(hsotg, HPTXSTS);
2914                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2915                             TXSTS_QSPCAVAIL_SHIFT;
2916                 if (qspcavail == 0) {
2917                         no_queue_space = true;
2918                         break;
2919                 }
2920
2921                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2922                 if (!qh->channel) {
2923                         qh_ptr = qh_ptr->next;
2924                         continue;
2925                 }
2926
2927                 /* Make sure EP's TT buffer is clean before queueing qtds */
2928                 if (qh->tt_buffer_dirty) {
2929                         qh_ptr = qh_ptr->next;
2930                         continue;
2931                 }
2932
2933                 /*
2934                  * Set a flag if we're queuing high-bandwidth in slave mode.
2935                  * The flag prevents any halts to get into the request queue in
2936                  * the middle of multiple high-bandwidth packets getting queued.
2937                  */
2938                 if (!hsotg->params.host_dma &&
2939                     qh->channel->multi_count > 1)
2940                         hsotg->queuing_high_bandwidth = 1;
2941
2942                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2943                             TXSTS_FSPCAVAIL_SHIFT;
2944                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2945                 if (status < 0) {
2946                         no_fifo_space = true;
2947                         break;
2948                 }
2949
2950                 /*
2951                  * In Slave mode, stay on the current transfer until there is
2952                  * nothing more to do or the high-bandwidth request count is
2953                  * reached. In DMA mode, only need to queue one request. The
2954                  * controller automatically handles multiple packets for
2955                  * high-bandwidth transfers.
2956                  */
2957                 if (hsotg->params.host_dma || status == 0 ||
2958                     qh->channel->requests == qh->channel->multi_count) {
2959                         qh_ptr = qh_ptr->next;
2960                         /*
2961                          * Move the QH from the periodic assigned schedule to
2962                          * the periodic queued schedule
2963                          */
2964                         list_move_tail(&qh->qh_list_entry,
2965                                        &hsotg->periodic_sched_queued);
2966
2967                         /* done queuing high bandwidth */
2968                         hsotg->queuing_high_bandwidth = 0;
2969                 }
2970         }
2971
2972 exit:
2973         if (no_queue_space || no_fifo_space ||
2974             (!hsotg->params.host_dma &&
2975              !list_empty(&hsotg->periodic_sched_assigned))) {
2976                 /*
2977                  * May need to queue more transactions as the request
2978                  * queue or Tx FIFO empties. Enable the periodic Tx
2979                  * FIFO empty interrupt. (Always use the half-empty
2980                  * level to ensure that new requests are loaded as
2981                  * soon as possible.)
2982                  */
2983                 gintmsk = dwc2_readl(hsotg, GINTMSK);
2984                 if (!(gintmsk & GINTSTS_PTXFEMP)) {
2985                         gintmsk |= GINTSTS_PTXFEMP;
2986                         dwc2_writel(hsotg, gintmsk, GINTMSK);
2987                 }
2988         } else {
2989                 /*
2990                  * Disable the Tx FIFO empty interrupt since there are
2991                  * no more transactions that need to be queued right
2992                  * now. This function is called from interrupt
2993                  * handlers to queue more transactions as transfer
2994                  * states change.
2995                  */
2996                 gintmsk = dwc2_readl(hsotg, GINTMSK);
2997                 if (gintmsk & GINTSTS_PTXFEMP) {
2998                         gintmsk &= ~GINTSTS_PTXFEMP;
2999                         dwc2_writel(hsotg, gintmsk, GINTMSK);
3000                 }
3001         }
3002 }
3003
3004 /*
3005  * Processes active non-periodic channels and queues transactions for these
3006  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3007  * FIFO Empty interrupt is enabled if there are more transactions to queue as
3008  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3009  * FIFO Empty interrupt is disabled.
3010  *
3011  * Must be called with interrupt disabled and spinlock held
3012  */
3013 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3014 {
3015         struct list_head *orig_qh_ptr;
3016         struct dwc2_qh *qh;
3017         u32 tx_status;
3018         u32 qspcavail;
3019         u32 fspcavail;
3020         u32 gintmsk;
3021         int status;
3022         int no_queue_space = 0;
3023         int no_fifo_space = 0;
3024         int more_to_do = 0;
3025
3026         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3027
3028         tx_status = dwc2_readl(hsotg, GNPTXSTS);
3029         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3030                     TXSTS_QSPCAVAIL_SHIFT;
3031         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3032                     TXSTS_FSPCAVAIL_SHIFT;
3033         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
3034                  qspcavail);
3035         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
3036                  fspcavail);
3037
3038         /*
3039          * Keep track of the starting point. Skip over the start-of-list
3040          * entry.
3041          */
3042         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3043                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3044         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3045
3046         /*
3047          * Process once through the active list or until no more space is
3048          * available in the request queue or the Tx FIFO
3049          */
3050         do {
3051                 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3052                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3053                             TXSTS_QSPCAVAIL_SHIFT;
3054                 if (!hsotg->params.host_dma && qspcavail == 0) {
3055                         no_queue_space = 1;
3056                         break;
3057                 }
3058
3059                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3060                                 qh_list_entry);
3061                 if (!qh->channel)
3062                         goto next;
3063
3064                 /* Make sure EP's TT buffer is clean before queueing qtds */
3065                 if (qh->tt_buffer_dirty)
3066                         goto next;
3067
3068                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3069                             TXSTS_FSPCAVAIL_SHIFT;
3070                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3071
3072                 if (status > 0) {
3073                         more_to_do = 1;
3074                 } else if (status < 0) {
3075                         no_fifo_space = 1;
3076                         break;
3077                 }
3078 next:
3079                 /* Advance to next QH, skipping start-of-list entry */
3080                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3081                 if (hsotg->non_periodic_qh_ptr ==
3082                                 &hsotg->non_periodic_sched_active)
3083                         hsotg->non_periodic_qh_ptr =
3084                                         hsotg->non_periodic_qh_ptr->next;
3085         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3086
3087         if (!hsotg->params.host_dma) {
3088                 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3089                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3090                             TXSTS_QSPCAVAIL_SHIFT;
3091                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3092                             TXSTS_FSPCAVAIL_SHIFT;
3093                 dev_vdbg(hsotg->dev,
3094                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
3095                          qspcavail);
3096                 dev_vdbg(hsotg->dev,
3097                          "  NP Tx FIFO Space Avail (after queue): %d\n",
3098                          fspcavail);
3099
3100                 if (more_to_do || no_queue_space || no_fifo_space) {
3101                         /*
3102                          * May need to queue more transactions as the request
3103                          * queue or Tx FIFO empties. Enable the non-periodic
3104                          * Tx FIFO empty interrupt. (Always use the half-empty
3105                          * level to ensure that new requests are loaded as
3106                          * soon as possible.)
3107                          */
3108                         gintmsk = dwc2_readl(hsotg, GINTMSK);
3109                         gintmsk |= GINTSTS_NPTXFEMP;
3110                         dwc2_writel(hsotg, gintmsk, GINTMSK);
3111                 } else {
3112                         /*
3113                          * Disable the Tx FIFO empty interrupt since there are
3114                          * no more transactions that need to be queued right
3115                          * now. This function is called from interrupt
3116                          * handlers to queue more transactions as transfer
3117                          * states change.
3118                          */
3119                         gintmsk = dwc2_readl(hsotg, GINTMSK);
3120                         gintmsk &= ~GINTSTS_NPTXFEMP;
3121                         dwc2_writel(hsotg, gintmsk, GINTMSK);
3122                 }
3123         }
3124 }
3125
3126 /**
3127  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3128  * and queues transactions for these channels to the DWC_otg controller. Called
3129  * from the HCD interrupt handler functions.
3130  *
3131  * @hsotg:   The HCD state structure
3132  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3133  *           or both)
3134  *
3135  * Must be called with interrupt disabled and spinlock held
3136  */
3137 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3138                                  enum dwc2_transaction_type tr_type)
3139 {
3140 #ifdef DWC2_DEBUG_SOF
3141         dev_vdbg(hsotg->dev, "Queue Transactions\n");
3142 #endif
3143         /* Process host channels associated with periodic transfers */
3144         if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3145             tr_type == DWC2_TRANSACTION_ALL)
3146                 dwc2_process_periodic_channels(hsotg);
3147
3148         /* Process host channels associated with non-periodic transfers */
3149         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3150             tr_type == DWC2_TRANSACTION_ALL) {
3151                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3152                         dwc2_process_non_periodic_channels(hsotg);
3153                 } else {
3154                         /*
3155                          * Ensure NP Tx FIFO empty interrupt is disabled when
3156                          * there are no non-periodic transfers to process
3157                          */
3158                         u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3159
3160                         gintmsk &= ~GINTSTS_NPTXFEMP;
3161                         dwc2_writel(hsotg, gintmsk, GINTMSK);
3162                 }
3163         }
3164 }
3165
3166 static void dwc2_conn_id_status_change(struct work_struct *work)
3167 {
3168         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3169                                                 wf_otg);
3170         u32 count = 0;
3171         u32 gotgctl;
3172         unsigned long flags;
3173
3174         dev_dbg(hsotg->dev, "%s()\n", __func__);
3175
3176         gotgctl = dwc2_readl(hsotg, GOTGCTL);
3177         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3178         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3179                 !!(gotgctl & GOTGCTL_CONID_B));
3180
3181         /* B-Device connector (Device Mode) */
3182         if (gotgctl & GOTGCTL_CONID_B) {
3183                 dwc2_vbus_supply_exit(hsotg);
3184                 /* Wait for switch to device mode */
3185                 dev_dbg(hsotg->dev, "connId B\n");
3186                 if (hsotg->bus_suspended) {
3187                         dev_info(hsotg->dev,
3188                                  "Do port resume before switching to device mode\n");
3189                         dwc2_port_resume(hsotg);
3190                 }
3191                 while (!dwc2_is_device_mode(hsotg)) {
3192                         dev_info(hsotg->dev,
3193                                  "Waiting for Peripheral Mode, Mode=%s\n",
3194                                  dwc2_is_host_mode(hsotg) ? "Host" :
3195                                  "Peripheral");
3196                         msleep(20);
3197                         /*
3198                          * Sometimes the initial GOTGCTRL read is wrong, so
3199                          * check it again and jump to host mode if that was
3200                          * the case.
3201                          */
3202                         gotgctl = dwc2_readl(hsotg, GOTGCTL);
3203                         if (!(gotgctl & GOTGCTL_CONID_B))
3204                                 goto host;
3205                         if (++count > 250)
3206                                 break;
3207                 }
3208                 if (count > 250)
3209                         dev_err(hsotg->dev,
3210                                 "Connection id status change timed out\n");
3211                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3212                 dwc2_core_init(hsotg, false);
3213                 dwc2_enable_global_interrupts(hsotg);
3214                 spin_lock_irqsave(&hsotg->lock, flags);
3215                 dwc2_hsotg_core_init_disconnected(hsotg, false);
3216                 spin_unlock_irqrestore(&hsotg->lock, flags);
3217                 /* Enable ACG feature in device mode,if supported */
3218                 dwc2_enable_acg(hsotg);
3219                 dwc2_hsotg_core_connect(hsotg);
3220         } else {
3221 host:
3222                 /* A-Device connector (Host Mode) */
3223                 dev_dbg(hsotg->dev, "connId A\n");
3224                 while (!dwc2_is_host_mode(hsotg)) {
3225                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3226                                  dwc2_is_host_mode(hsotg) ?
3227                                  "Host" : "Peripheral");
3228                         msleep(20);
3229                         if (++count > 250)
3230                                 break;
3231                 }
3232                 if (count > 250)
3233                         dev_err(hsotg->dev,
3234                                 "Connection id status change timed out\n");
3235
3236                 spin_lock_irqsave(&hsotg->lock, flags);
3237                 dwc2_hsotg_disconnect(hsotg);
3238                 spin_unlock_irqrestore(&hsotg->lock, flags);
3239
3240                 hsotg->op_state = OTG_STATE_A_HOST;
3241                 /* Initialize the Core for Host mode */
3242                 dwc2_core_init(hsotg, false);
3243                 dwc2_enable_global_interrupts(hsotg);
3244                 dwc2_hcd_start(hsotg);
3245         }
3246 }
3247
3248 static void dwc2_wakeup_detected(struct timer_list *t)
3249 {
3250         struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3251         u32 hprt0;
3252
3253         dev_dbg(hsotg->dev, "%s()\n", __func__);
3254
3255         /*
3256          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3257          * so that OPT tests pass with all PHYs.)
3258          */
3259         hprt0 = dwc2_read_hprt0(hsotg);
3260         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3261         hprt0 &= ~HPRT0_RES;
3262         dwc2_writel(hsotg, hprt0, HPRT0);
3263         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3264                 dwc2_readl(hsotg, HPRT0));
3265
3266         dwc2_hcd_rem_wakeup(hsotg);
3267         hsotg->bus_suspended = false;
3268
3269         /* Change to L0 state */
3270         hsotg->lx_state = DWC2_L0;
3271 }
3272
3273 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3274 {
3275         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3276
3277         return hcd->self.b_hnp_enable;
3278 }
3279
3280 /* Must NOT be called with interrupt disabled or spinlock held */
3281 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3282 {
3283         unsigned long flags;
3284         u32 hprt0;
3285         u32 pcgctl;
3286         u32 gotgctl;
3287
3288         dev_dbg(hsotg->dev, "%s()\n", __func__);
3289
3290         spin_lock_irqsave(&hsotg->lock, flags);
3291
3292         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3293                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3294                 gotgctl |= GOTGCTL_HSTSETHNPEN;
3295                 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3296                 hsotg->op_state = OTG_STATE_A_SUSPEND;
3297         }
3298
3299         hprt0 = dwc2_read_hprt0(hsotg);
3300         hprt0 |= HPRT0_SUSP;
3301         dwc2_writel(hsotg, hprt0, HPRT0);
3302
3303         hsotg->bus_suspended = true;
3304
3305         /*
3306          * If power_down is supported, Phy clock will be suspended
3307          * after registers are backuped.
3308          */
3309         if (!hsotg->params.power_down) {
3310                 /* Suspend the Phy Clock */
3311                 pcgctl = dwc2_readl(hsotg, PCGCTL);
3312                 pcgctl |= PCGCTL_STOPPCLK;
3313                 dwc2_writel(hsotg, pcgctl, PCGCTL);
3314                 udelay(10);
3315         }
3316
3317         /* For HNP the bus must be suspended for at least 200ms */
3318         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3319                 pcgctl = dwc2_readl(hsotg, PCGCTL);
3320                 pcgctl &= ~PCGCTL_STOPPCLK;
3321                 dwc2_writel(hsotg, pcgctl, PCGCTL);
3322
3323                 spin_unlock_irqrestore(&hsotg->lock, flags);
3324
3325                 msleep(200);
3326         } else {
3327                 spin_unlock_irqrestore(&hsotg->lock, flags);
3328         }
3329 }
3330
3331 /* Must NOT be called with interrupt disabled or spinlock held */
3332 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3333 {
3334         unsigned long flags;
3335         u32 hprt0;
3336         u32 pcgctl;
3337
3338         spin_lock_irqsave(&hsotg->lock, flags);
3339
3340         /*
3341          * If power_down is supported, Phy clock is already resumed
3342          * after registers restore.
3343          */
3344         if (!hsotg->params.power_down) {
3345                 pcgctl = dwc2_readl(hsotg, PCGCTL);
3346                 pcgctl &= ~PCGCTL_STOPPCLK;
3347                 dwc2_writel(hsotg, pcgctl, PCGCTL);
3348                 spin_unlock_irqrestore(&hsotg->lock, flags);
3349                 msleep(20);
3350                 spin_lock_irqsave(&hsotg->lock, flags);
3351         }
3352
3353         hprt0 = dwc2_read_hprt0(hsotg);
3354         hprt0 |= HPRT0_RES;
3355         hprt0 &= ~HPRT0_SUSP;
3356         dwc2_writel(hsotg, hprt0, HPRT0);
3357         spin_unlock_irqrestore(&hsotg->lock, flags);
3358
3359         msleep(USB_RESUME_TIMEOUT);
3360
3361         spin_lock_irqsave(&hsotg->lock, flags);
3362         hprt0 = dwc2_read_hprt0(hsotg);
3363         hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3364         dwc2_writel(hsotg, hprt0, HPRT0);
3365         hsotg->bus_suspended = false;
3366         spin_unlock_irqrestore(&hsotg->lock, flags);
3367 }
3368
3369 /* Handles hub class-specific requests */
3370 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3371                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
3372 {
3373         struct usb_hub_descriptor *hub_desc;
3374         int retval = 0;
3375         u32 hprt0;
3376         u32 port_status;
3377         u32 speed;
3378         u32 pcgctl;
3379         u32 pwr;
3380
3381         switch (typereq) {
3382         case ClearHubFeature:
3383                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3384
3385                 switch (wvalue) {
3386                 case C_HUB_LOCAL_POWER:
3387                 case C_HUB_OVER_CURRENT:
3388                         /* Nothing required here */
3389                         break;
3390
3391                 default:
3392                         retval = -EINVAL;
3393                         dev_err(hsotg->dev,
3394                                 "ClearHubFeature request %1xh unknown\n",
3395                                 wvalue);
3396                 }
3397                 break;
3398
3399         case ClearPortFeature:
3400                 if (wvalue != USB_PORT_FEAT_L1)
3401                         if (!windex || windex > 1)
3402                                 goto error;
3403                 switch (wvalue) {
3404                 case USB_PORT_FEAT_ENABLE:
3405                         dev_dbg(hsotg->dev,
3406                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3407                         hprt0 = dwc2_read_hprt0(hsotg);
3408                         hprt0 |= HPRT0_ENA;
3409                         dwc2_writel(hsotg, hprt0, HPRT0);
3410                         break;
3411
3412                 case USB_PORT_FEAT_SUSPEND:
3413                         dev_dbg(hsotg->dev,
3414                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3415
3416                         if (hsotg->bus_suspended) {
3417                                 if (hsotg->hibernated)
3418                                         dwc2_exit_hibernation(hsotg, 0, 0, 1);
3419                                 else
3420                                         dwc2_port_resume(hsotg);
3421                         }
3422                         break;
3423
3424                 case USB_PORT_FEAT_POWER:
3425                         dev_dbg(hsotg->dev,
3426                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3427                         hprt0 = dwc2_read_hprt0(hsotg);
3428                         pwr = hprt0 & HPRT0_PWR;
3429                         hprt0 &= ~HPRT0_PWR;
3430                         dwc2_writel(hsotg, hprt0, HPRT0);
3431                         if (pwr)
3432                                 dwc2_vbus_supply_exit(hsotg);
3433                         break;
3434
3435                 case USB_PORT_FEAT_INDICATOR:
3436                         dev_dbg(hsotg->dev,
3437                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3438                         /* Port indicator not supported */
3439                         break;
3440
3441                 case USB_PORT_FEAT_C_CONNECTION:
3442                         /*
3443                          * Clears driver's internal Connect Status Change flag
3444                          */
3445                         dev_dbg(hsotg->dev,
3446                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3447                         hsotg->flags.b.port_connect_status_change = 0;
3448                         break;
3449
3450                 case USB_PORT_FEAT_C_RESET:
3451                         /* Clears driver's internal Port Reset Change flag */
3452                         dev_dbg(hsotg->dev,
3453                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3454                         hsotg->flags.b.port_reset_change = 0;
3455                         break;
3456
3457                 case USB_PORT_FEAT_C_ENABLE:
3458                         /*
3459                          * Clears the driver's internal Port Enable/Disable
3460                          * Change flag
3461                          */
3462                         dev_dbg(hsotg->dev,
3463                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3464                         hsotg->flags.b.port_enable_change = 0;
3465                         break;
3466
3467                 case USB_PORT_FEAT_C_SUSPEND:
3468                         /*
3469                          * Clears the driver's internal Port Suspend Change
3470                          * flag, which is set when resume signaling on the host
3471                          * port is complete
3472                          */
3473                         dev_dbg(hsotg->dev,
3474                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3475                         hsotg->flags.b.port_suspend_change = 0;
3476                         break;
3477
3478                 case USB_PORT_FEAT_C_PORT_L1:
3479                         dev_dbg(hsotg->dev,
3480                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3481                         hsotg->flags.b.port_l1_change = 0;
3482                         break;
3483
3484                 case USB_PORT_FEAT_C_OVER_CURRENT:
3485                         dev_dbg(hsotg->dev,
3486                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3487                         hsotg->flags.b.port_over_current_change = 0;
3488                         break;
3489
3490                 default:
3491                         retval = -EINVAL;
3492                         dev_err(hsotg->dev,
3493                                 "ClearPortFeature request %1xh unknown or unsupported\n",
3494                                 wvalue);
3495                 }
3496                 break;
3497
3498         case GetHubDescriptor:
3499                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3500                 hub_desc = (struct usb_hub_descriptor *)buf;
3501                 hub_desc->bDescLength = 9;
3502                 hub_desc->bDescriptorType = USB_DT_HUB;
3503                 hub_desc->bNbrPorts = 1;
3504                 hub_desc->wHubCharacteristics =
3505                         cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3506                                     HUB_CHAR_INDV_PORT_OCPM);
3507                 hub_desc->bPwrOn2PwrGood = 1;
3508                 hub_desc->bHubContrCurrent = 0;
3509                 hub_desc->u.hs.DeviceRemovable[0] = 0;
3510                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3511                 break;
3512
3513         case GetHubStatus:
3514                 dev_dbg(hsotg->dev, "GetHubStatus\n");
3515                 memset(buf, 0, 4);
3516                 break;
3517
3518         case GetPortStatus:
3519                 dev_vdbg(hsotg->dev,
3520                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3521                          hsotg->flags.d32);
3522                 if (!windex || windex > 1)
3523                         goto error;
3524
3525                 port_status = 0;
3526                 if (hsotg->flags.b.port_connect_status_change)
3527                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3528                 if (hsotg->flags.b.port_enable_change)
3529                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
3530                 if (hsotg->flags.b.port_suspend_change)
3531                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3532                 if (hsotg->flags.b.port_l1_change)
3533                         port_status |= USB_PORT_STAT_C_L1 << 16;
3534                 if (hsotg->flags.b.port_reset_change)
3535                         port_status |= USB_PORT_STAT_C_RESET << 16;
3536                 if (hsotg->flags.b.port_over_current_change) {
3537                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
3538                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3539                 }
3540
3541                 if (!hsotg->flags.b.port_connect_status) {
3542                         /*
3543                          * The port is disconnected, which means the core is
3544                          * either in device mode or it soon will be. Just
3545                          * return 0's for the remainder of the port status
3546                          * since the port register can't be read if the core
3547                          * is in device mode.
3548                          */
3549                         *(__le32 *)buf = cpu_to_le32(port_status);
3550                         break;
3551                 }
3552
3553                 hprt0 = dwc2_readl(hsotg, HPRT0);
3554                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
3555
3556                 if (hprt0 & HPRT0_CONNSTS)
3557                         port_status |= USB_PORT_STAT_CONNECTION;
3558                 if (hprt0 & HPRT0_ENA)
3559                         port_status |= USB_PORT_STAT_ENABLE;
3560                 if (hprt0 & HPRT0_SUSP)
3561                         port_status |= USB_PORT_STAT_SUSPEND;
3562                 if (hprt0 & HPRT0_OVRCURRACT)
3563                         port_status |= USB_PORT_STAT_OVERCURRENT;
3564                 if (hprt0 & HPRT0_RST)
3565                         port_status |= USB_PORT_STAT_RESET;
3566                 if (hprt0 & HPRT0_PWR)
3567                         port_status |= USB_PORT_STAT_POWER;
3568
3569                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3570                 if (speed == HPRT0_SPD_HIGH_SPEED)
3571                         port_status |= USB_PORT_STAT_HIGH_SPEED;
3572                 else if (speed == HPRT0_SPD_LOW_SPEED)
3573                         port_status |= USB_PORT_STAT_LOW_SPEED;
3574
3575                 if (hprt0 & HPRT0_TSTCTL_MASK)
3576                         port_status |= USB_PORT_STAT_TEST;
3577                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3578
3579                 if (hsotg->params.dma_desc_fs_enable) {
3580                         /*
3581                          * Enable descriptor DMA only if a full speed
3582                          * device is connected.
3583                          */
3584                         if (hsotg->new_connection &&
3585                             ((port_status &
3586                               (USB_PORT_STAT_CONNECTION |
3587                                USB_PORT_STAT_HIGH_SPEED |
3588                                USB_PORT_STAT_LOW_SPEED)) ==
3589                                USB_PORT_STAT_CONNECTION)) {
3590                                 u32 hcfg;
3591
3592                                 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3593                                 hsotg->params.dma_desc_enable = true;
3594                                 hcfg = dwc2_readl(hsotg, HCFG);
3595                                 hcfg |= HCFG_DESCDMA;
3596                                 dwc2_writel(hsotg, hcfg, HCFG);
3597                                 hsotg->new_connection = false;
3598                         }
3599                 }
3600
3601                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3602                 *(__le32 *)buf = cpu_to_le32(port_status);
3603                 break;
3604
3605         case SetHubFeature:
3606                 dev_dbg(hsotg->dev, "SetHubFeature\n");
3607                 /* No HUB features supported */
3608                 break;
3609
3610         case SetPortFeature:
3611                 dev_dbg(hsotg->dev, "SetPortFeature\n");
3612                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3613                         goto error;
3614
3615                 if (!hsotg->flags.b.port_connect_status) {
3616                         /*
3617                          * The port is disconnected, which means the core is
3618                          * either in device mode or it soon will be. Just
3619                          * return without doing anything since the port
3620                          * register can't be written if the core is in device
3621                          * mode.
3622                          */
3623                         break;
3624                 }
3625
3626                 switch (wvalue) {
3627                 case USB_PORT_FEAT_SUSPEND:
3628                         dev_dbg(hsotg->dev,
3629                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3630                         if (windex != hsotg->otg_port)
3631                                 goto error;
3632                         if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION)
3633                                 dwc2_enter_hibernation(hsotg, 1);
3634                         else
3635                                 dwc2_port_suspend(hsotg, windex);
3636                         break;
3637
3638                 case USB_PORT_FEAT_POWER:
3639                         dev_dbg(hsotg->dev,
3640                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3641                         hprt0 = dwc2_read_hprt0(hsotg);
3642                         pwr = hprt0 & HPRT0_PWR;
3643                         hprt0 |= HPRT0_PWR;
3644                         dwc2_writel(hsotg, hprt0, HPRT0);
3645                         if (!pwr)
3646                                 dwc2_vbus_supply_init(hsotg);
3647                         break;
3648
3649                 case USB_PORT_FEAT_RESET:
3650                         if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION &&
3651                             hsotg->hibernated)
3652                                 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3653                         hprt0 = dwc2_read_hprt0(hsotg);
3654                         dev_dbg(hsotg->dev,
3655                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3656                         pcgctl = dwc2_readl(hsotg, PCGCTL);
3657                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3658                         dwc2_writel(hsotg, pcgctl, PCGCTL);
3659                         /* ??? Original driver does this */
3660                         dwc2_writel(hsotg, 0, PCGCTL);
3661
3662                         hprt0 = dwc2_read_hprt0(hsotg);
3663                         pwr = hprt0 & HPRT0_PWR;
3664                         /* Clear suspend bit if resetting from suspend state */
3665                         hprt0 &= ~HPRT0_SUSP;
3666
3667                         /*
3668                          * When B-Host the Port reset bit is set in the Start
3669                          * HCD Callback function, so that the reset is started
3670                          * within 1ms of the HNP success interrupt
3671                          */
3672                         if (!dwc2_hcd_is_b_host(hsotg)) {
3673                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
3674                                 dev_dbg(hsotg->dev,
3675                                         "In host mode, hprt0=%08x\n", hprt0);
3676                                 dwc2_writel(hsotg, hprt0, HPRT0);
3677                                 if (!pwr)
3678                                         dwc2_vbus_supply_init(hsotg);
3679                         }
3680
3681                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3682                         msleep(50);
3683                         hprt0 &= ~HPRT0_RST;
3684                         dwc2_writel(hsotg, hprt0, HPRT0);
3685                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
3686                         break;
3687
3688                 case USB_PORT_FEAT_INDICATOR:
3689                         dev_dbg(hsotg->dev,
3690                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3691                         /* Not supported */
3692                         break;
3693
3694                 case USB_PORT_FEAT_TEST:
3695                         hprt0 = dwc2_read_hprt0(hsotg);
3696                         dev_dbg(hsotg->dev,
3697                                 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3698                         hprt0 &= ~HPRT0_TSTCTL_MASK;
3699                         hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3700                         dwc2_writel(hsotg, hprt0, HPRT0);
3701                         break;
3702
3703                 default:
3704                         retval = -EINVAL;
3705                         dev_err(hsotg->dev,
3706                                 "SetPortFeature %1xh unknown or unsupported\n",
3707                                 wvalue);
3708                         break;
3709                 }
3710                 break;
3711
3712         default:
3713 error:
3714                 retval = -EINVAL;
3715                 dev_dbg(hsotg->dev,
3716                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3717                         typereq, windex, wvalue);
3718                 break;
3719         }
3720
3721         return retval;
3722 }
3723
3724 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3725 {
3726         int retval;
3727
3728         if (port != 1)
3729                 return -EINVAL;
3730
3731         retval = (hsotg->flags.b.port_connect_status_change ||
3732                   hsotg->flags.b.port_reset_change ||
3733                   hsotg->flags.b.port_enable_change ||
3734                   hsotg->flags.b.port_suspend_change ||
3735                   hsotg->flags.b.port_over_current_change);
3736
3737         if (retval) {
3738                 dev_dbg(hsotg->dev,
3739                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3740                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
3741                         hsotg->flags.b.port_connect_status_change);
3742                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
3743                         hsotg->flags.b.port_reset_change);
3744                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
3745                         hsotg->flags.b.port_enable_change);
3746                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
3747                         hsotg->flags.b.port_suspend_change);
3748                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
3749                         hsotg->flags.b.port_over_current_change);
3750         }
3751
3752         return retval;
3753 }
3754
3755 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3756 {
3757         u32 hfnum = dwc2_readl(hsotg, HFNUM);
3758
3759 #ifdef DWC2_DEBUG_SOF
3760         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3761                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3762 #endif
3763         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3764 }
3765
3766 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3767 {
3768         u32 hprt = dwc2_readl(hsotg, HPRT0);
3769         u32 hfir = dwc2_readl(hsotg, HFIR);
3770         u32 hfnum = dwc2_readl(hsotg, HFNUM);
3771         unsigned int us_per_frame;
3772         unsigned int frame_number;
3773         unsigned int remaining;
3774         unsigned int interval;
3775         unsigned int phy_clks;
3776
3777         /* High speed has 125 us per (micro) frame; others are 1 ms per */
3778         us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3779
3780         /* Extract fields */
3781         frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3782         remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3783         interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3784
3785         /*
3786          * Number of phy clocks since the last tick of the frame number after
3787          * "us" has passed.
3788          */
3789         phy_clks = (interval - remaining) +
3790                    DIV_ROUND_UP(interval * us, us_per_frame);
3791
3792         return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3793 }
3794
3795 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3796 {
3797         return hsotg->op_state == OTG_STATE_B_HOST;
3798 }
3799
3800 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3801                                                int iso_desc_count,
3802                                                gfp_t mem_flags)
3803 {
3804         struct dwc2_hcd_urb *urb;
3805
3806         urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags);
3807         if (urb)
3808                 urb->packet_count = iso_desc_count;
3809         return urb;
3810 }
3811
3812 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3813                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
3814                                       u8 ep_num, u8 ep_type, u8 ep_dir,
3815                                       u16 maxp, u16 maxp_mult)
3816 {
3817         if (dbg_perio() ||
3818             ep_type == USB_ENDPOINT_XFER_BULK ||
3819             ep_type == USB_ENDPOINT_XFER_CONTROL)
3820                 dev_vdbg(hsotg->dev,
3821                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, maxp=%d (%d mult)\n",
3822                          dev_addr, ep_num, ep_dir, ep_type, maxp, maxp_mult);
3823         urb->pipe_info.dev_addr = dev_addr;
3824         urb->pipe_info.ep_num = ep_num;
3825         urb->pipe_info.pipe_type = ep_type;
3826         urb->pipe_info.pipe_dir = ep_dir;
3827         urb->pipe_info.maxp = maxp;
3828         urb->pipe_info.maxp_mult = maxp_mult;
3829 }
3830
3831 /*
3832  * NOTE: This function will be removed once the peripheral controller code
3833  * is integrated and the driver is stable
3834  */
3835 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3836 {
3837 #ifdef DEBUG
3838         struct dwc2_host_chan *chan;
3839         struct dwc2_hcd_urb *urb;
3840         struct dwc2_qtd *qtd;
3841         int num_channels;
3842         u32 np_tx_status;
3843         u32 p_tx_status;
3844         int i;
3845
3846         num_channels = hsotg->params.host_channels;
3847         dev_dbg(hsotg->dev, "\n");
3848         dev_dbg(hsotg->dev,
3849                 "************************************************************\n");
3850         dev_dbg(hsotg->dev, "HCD State:\n");
3851         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
3852
3853         for (i = 0; i < num_channels; i++) {
3854                 chan = hsotg->hc_ptr_array[i];
3855                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
3856                 dev_dbg(hsotg->dev,
3857                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3858                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
3859                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
3860                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
3861                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
3862                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
3863                         chan->data_pid_start);
3864                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
3865                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
3866                         chan->xfer_started);
3867                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
3868                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
3869                         (unsigned long)chan->xfer_dma);
3870                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
3871                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
3872                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
3873                         chan->halt_on_queue);
3874                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
3875                         chan->halt_pending);
3876                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
3877                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
3878                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
3879                         chan->complete_split);
3880                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
3881                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
3882                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
3883                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
3884                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
3885
3886                 if (chan->xfer_started) {
3887                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3888
3889                         hfnum = dwc2_readl(hsotg, HFNUM);
3890                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
3891                         hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
3892                         hcint = dwc2_readl(hsotg, HCINT(i));
3893                         hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
3894                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
3895                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
3896                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
3897                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
3898                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
3899                 }
3900
3901                 if (!(chan->xfer_started && chan->qh))
3902                         continue;
3903
3904                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
3905                         if (!qtd->in_process)
3906                                 break;
3907                         urb = qtd->urb;
3908                         dev_dbg(hsotg->dev, "    URB Info:\n");
3909                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
3910                                 qtd, urb);
3911                         if (urb) {
3912                                 dev_dbg(hsotg->dev,
3913                                         "      Dev: %d, EP: %d %s\n",
3914                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
3915                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
3916                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
3917                                         "IN" : "OUT");
3918                                 dev_dbg(hsotg->dev,
3919                                         "      Max packet size: %d (%d mult)\n",
3920                                         dwc2_hcd_get_maxp(&urb->pipe_info),
3921                                         dwc2_hcd_get_maxp_mult(&urb->pipe_info));
3922                                 dev_dbg(hsotg->dev,
3923                                         "      transfer_buffer: %p\n",
3924                                         urb->buf);
3925                                 dev_dbg(hsotg->dev,
3926                                         "      transfer_dma: %08lx\n",
3927                                         (unsigned long)urb->dma);
3928                                 dev_dbg(hsotg->dev,
3929                                         "      transfer_buffer_length: %d\n",
3930                                         urb->length);
3931                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
3932                                         urb->actual_length);
3933                         }
3934                 }
3935         }
3936
3937         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
3938                 hsotg->non_periodic_channels);
3939         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
3940                 hsotg->periodic_channels);
3941         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
3942         np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
3943         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
3944                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3945         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
3946                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3947         p_tx_status = dwc2_readl(hsotg, HPTXSTS);
3948         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
3949                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3950         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
3951                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3952         dwc2_dump_global_registers(hsotg);
3953         dwc2_dump_host_registers(hsotg);
3954         dev_dbg(hsotg->dev,
3955                 "************************************************************\n");
3956         dev_dbg(hsotg->dev, "\n");
3957 #endif
3958 }
3959
3960 struct wrapper_priv_data {
3961         struct dwc2_hsotg *hsotg;
3962 };
3963
3964 /* Gets the dwc2_hsotg from a usb_hcd */
3965 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
3966 {
3967         struct wrapper_priv_data *p;
3968
3969         p = (struct wrapper_priv_data *)&hcd->hcd_priv;
3970         return p->hsotg;
3971 }
3972
3973 /**
3974  * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
3975  *
3976  * This will get the dwc2_tt structure (and ttport) associated with the given
3977  * context (which is really just a struct urb pointer).
3978  *
3979  * The first time this is called for a given TT we allocate memory for our
3980  * structure.  When everyone is done and has called dwc2_host_put_tt_info()
3981  * then the refcount for the structure will go to 0 and we'll free it.
3982  *
3983  * @hsotg:     The HCD state structure for the DWC OTG controller.
3984  * @context:   The priv pointer from a struct dwc2_hcd_urb.
3985  * @mem_flags: Flags for allocating memory.
3986  * @ttport:    We'll return this device's port number here.  That's used to
3987  *             reference into the bitmap if we're on a multi_tt hub.
3988  *
3989  * Return: a pointer to a struct dwc2_tt.  Don't forget to call
3990  *         dwc2_host_put_tt_info()!  Returns NULL upon memory alloc failure.
3991  */
3992
3993 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
3994                                       gfp_t mem_flags, int *ttport)
3995 {
3996         struct urb *urb = context;
3997         struct dwc2_tt *dwc_tt = NULL;
3998
3999         if (urb->dev->tt) {
4000                 *ttport = urb->dev->ttport;
4001
4002                 dwc_tt = urb->dev->tt->hcpriv;
4003                 if (!dwc_tt) {
4004                         size_t bitmap_size;
4005
4006                         /*
4007                          * For single_tt we need one schedule.  For multi_tt
4008                          * we need one per port.
4009                          */
4010                         bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4011                                       sizeof(dwc_tt->periodic_bitmaps[0]);
4012                         if (urb->dev->tt->multi)
4013                                 bitmap_size *= urb->dev->tt->hub->maxchild;
4014
4015                         dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4016                                          mem_flags);
4017                         if (!dwc_tt)
4018                                 return NULL;
4019
4020                         dwc_tt->usb_tt = urb->dev->tt;
4021                         dwc_tt->usb_tt->hcpriv = dwc_tt;
4022                 }
4023
4024                 dwc_tt->refcount++;
4025         }
4026
4027         return dwc_tt;
4028 }
4029
4030 /**
4031  * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4032  *
4033  * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4034  * of the structure are done.
4035  *
4036  * It's OK to call this with NULL.
4037  *
4038  * @hsotg:     The HCD state structure for the DWC OTG controller.
4039  * @dwc_tt:    The pointer returned by dwc2_host_get_tt_info.
4040  */
4041 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4042 {
4043         /* Model kfree and make put of NULL a no-op */
4044         if (!dwc_tt)
4045                 return;
4046
4047         WARN_ON(dwc_tt->refcount < 1);
4048
4049         dwc_tt->refcount--;
4050         if (!dwc_tt->refcount) {
4051                 dwc_tt->usb_tt->hcpriv = NULL;
4052                 kfree(dwc_tt);
4053         }
4054 }
4055
4056 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4057 {
4058         struct urb *urb = context;
4059
4060         return urb->dev->speed;
4061 }
4062
4063 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4064                                         struct urb *urb)
4065 {
4066         struct usb_bus *bus = hcd_to_bus(hcd);
4067
4068         if (urb->interval)
4069                 bus->bandwidth_allocated += bw / urb->interval;
4070         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4071                 bus->bandwidth_isoc_reqs++;
4072         else
4073                 bus->bandwidth_int_reqs++;
4074 }
4075
4076 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4077                                     struct urb *urb)
4078 {
4079         struct usb_bus *bus = hcd_to_bus(hcd);
4080
4081         if (urb->interval)
4082                 bus->bandwidth_allocated -= bw / urb->interval;
4083         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4084                 bus->bandwidth_isoc_reqs--;
4085         else
4086                 bus->bandwidth_int_reqs--;
4087 }
4088
4089 /*
4090  * Sets the final status of an URB and returns it to the upper layer. Any
4091  * required cleanup of the URB is performed.
4092  *
4093  * Must be called with interrupt disabled and spinlock held
4094  */
4095 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4096                         int status)
4097 {
4098         struct urb *urb;
4099         int i;
4100
4101         if (!qtd) {
4102                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4103                 return;
4104         }
4105
4106         if (!qtd->urb) {
4107                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4108                 return;
4109         }
4110
4111         urb = qtd->urb->priv;
4112         if (!urb) {
4113                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4114                 return;
4115         }
4116
4117         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4118
4119         if (dbg_urb(urb))
4120                 dev_vdbg(hsotg->dev,
4121                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4122                          __func__, urb, usb_pipedevice(urb->pipe),
4123                          usb_pipeendpoint(urb->pipe),
4124                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4125                          urb->actual_length);
4126
4127         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4128                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4129                 for (i = 0; i < urb->number_of_packets; ++i) {
4130                         urb->iso_frame_desc[i].actual_length =
4131                                 dwc2_hcd_urb_get_iso_desc_actual_length(
4132                                                 qtd->urb, i);
4133                         urb->iso_frame_desc[i].status =
4134                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4135                 }
4136         }
4137
4138         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4139                 for (i = 0; i < urb->number_of_packets; i++)
4140                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4141                                  i, urb->iso_frame_desc[i].status);
4142         }
4143
4144         urb->status = status;
4145         if (!status) {
4146                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4147                     urb->actual_length < urb->transfer_buffer_length)
4148                         urb->status = -EREMOTEIO;
4149         }
4150
4151         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4152             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4153                 struct usb_host_endpoint *ep = urb->ep;
4154
4155                 if (ep)
4156                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4157                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4158                                         urb);
4159         }
4160
4161         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4162         urb->hcpriv = NULL;
4163         kfree(qtd->urb);
4164         qtd->urb = NULL;
4165
4166         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4167 }
4168
4169 /*
4170  * Work queue function for starting the HCD when A-Cable is connected
4171  */
4172 static void dwc2_hcd_start_func(struct work_struct *work)
4173 {
4174         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4175                                                 start_work.work);
4176
4177         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4178         dwc2_host_start(hsotg);
4179 }
4180
4181 /*
4182  * Reset work queue function
4183  */
4184 static void dwc2_hcd_reset_func(struct work_struct *work)
4185 {
4186         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4187                                                 reset_work.work);
4188         unsigned long flags;
4189         u32 hprt0;
4190
4191         dev_dbg(hsotg->dev, "USB RESET function called\n");
4192
4193         spin_lock_irqsave(&hsotg->lock, flags);
4194
4195         hprt0 = dwc2_read_hprt0(hsotg);
4196         hprt0 &= ~HPRT0_RST;
4197         dwc2_writel(hsotg, hprt0, HPRT0);
4198         hsotg->flags.b.port_reset_change = 1;
4199
4200         spin_unlock_irqrestore(&hsotg->lock, flags);
4201 }
4202
4203 static void dwc2_hcd_phy_reset_func(struct work_struct *work)
4204 {
4205         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4206                                                 phy_reset_work);
4207         int ret;
4208
4209         ret = phy_reset(hsotg->phy);
4210         if (ret)
4211                 dev_warn(hsotg->dev, "PHY reset failed\n");
4212 }
4213
4214 /*
4215  * =========================================================================
4216  *  Linux HC Driver Functions
4217  * =========================================================================
4218  */
4219
4220 /*
4221  * Initializes the DWC_otg controller and its root hub and prepares it for host
4222  * mode operation. Activates the root port. Returns 0 on success and a negative
4223  * error code on failure.
4224  */
4225 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4226 {
4227         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4228         struct usb_bus *bus = hcd_to_bus(hcd);
4229         unsigned long flags;
4230         u32 hprt0;
4231         int ret;
4232
4233         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4234
4235         spin_lock_irqsave(&hsotg->lock, flags);
4236         hsotg->lx_state = DWC2_L0;
4237         hcd->state = HC_STATE_RUNNING;
4238         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4239
4240         if (dwc2_is_device_mode(hsotg)) {
4241                 spin_unlock_irqrestore(&hsotg->lock, flags);
4242                 return 0;       /* why 0 ?? */
4243         }
4244
4245         dwc2_hcd_reinit(hsotg);
4246
4247         hprt0 = dwc2_read_hprt0(hsotg);
4248         /* Has vbus power been turned on in dwc2_core_host_init ? */
4249         if (hprt0 & HPRT0_PWR) {
4250                 /* Enable external vbus supply before resuming root hub */
4251                 spin_unlock_irqrestore(&hsotg->lock, flags);
4252                 ret = dwc2_vbus_supply_init(hsotg);
4253                 if (ret)
4254                         return ret;
4255                 spin_lock_irqsave(&hsotg->lock, flags);
4256         }
4257
4258         /* Initialize and connect root hub if one is not already attached */
4259         if (bus->root_hub) {
4260                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4261                 /* Inform the HUB driver to resume */
4262                 usb_hcd_resume_root_hub(hcd);
4263         }
4264
4265         spin_unlock_irqrestore(&hsotg->lock, flags);
4266
4267         return 0;
4268 }
4269
4270 /*
4271  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4272  * stopped.
4273  */
4274 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4275 {
4276         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4277         unsigned long flags;
4278         u32 hprt0;
4279
4280         /* Turn off all host-specific interrupts */
4281         dwc2_disable_host_interrupts(hsotg);
4282
4283         /* Wait for interrupt processing to finish */
4284         synchronize_irq(hcd->irq);
4285
4286         spin_lock_irqsave(&hsotg->lock, flags);
4287         hprt0 = dwc2_read_hprt0(hsotg);
4288         /* Ensure hcd is disconnected */
4289         dwc2_hcd_disconnect(hsotg, true);
4290         dwc2_hcd_stop(hsotg);
4291         hsotg->lx_state = DWC2_L3;
4292         hcd->state = HC_STATE_HALT;
4293         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4294         spin_unlock_irqrestore(&hsotg->lock, flags);
4295
4296         /* keep balanced supply init/exit by checking HPRT0_PWR */
4297         if (hprt0 & HPRT0_PWR)
4298                 dwc2_vbus_supply_exit(hsotg);
4299
4300         usleep_range(1000, 3000);
4301 }
4302
4303 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4304 {
4305         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4306         unsigned long flags;
4307         int ret = 0;
4308         u32 hprt0;
4309         u32 pcgctl;
4310
4311         spin_lock_irqsave(&hsotg->lock, flags);
4312
4313         if (dwc2_is_device_mode(hsotg))
4314                 goto unlock;
4315
4316         if (hsotg->lx_state != DWC2_L0)
4317                 goto unlock;
4318
4319         if (!HCD_HW_ACCESSIBLE(hcd))
4320                 goto unlock;
4321
4322         if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4323                 goto unlock;
4324
4325         if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL)
4326                 goto skip_power_saving;
4327
4328         /*
4329          * Drive USB suspend and disable port Power
4330          * if usb bus is not suspended.
4331          */
4332         if (!hsotg->bus_suspended) {
4333                 hprt0 = dwc2_read_hprt0(hsotg);
4334                 if (hprt0 & HPRT0_CONNSTS) {
4335                         hprt0 |= HPRT0_SUSP;
4336                         if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL)
4337                                 hprt0 &= ~HPRT0_PWR;
4338                         dwc2_writel(hsotg, hprt0, HPRT0);
4339                 }
4340                 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4341                         spin_unlock_irqrestore(&hsotg->lock, flags);
4342                         dwc2_vbus_supply_exit(hsotg);
4343                         spin_lock_irqsave(&hsotg->lock, flags);
4344                 } else {
4345                         pcgctl = readl(hsotg->regs + PCGCTL);
4346                         pcgctl |= PCGCTL_STOPPCLK;
4347                         writel(pcgctl, hsotg->regs + PCGCTL);
4348                 }
4349         }
4350
4351         if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4352                 /* Enter partial_power_down */
4353                 ret = dwc2_enter_partial_power_down(hsotg);
4354                 if (ret) {
4355                         if (ret != -ENOTSUPP)
4356                                 dev_err(hsotg->dev,
4357                                         "enter partial_power_down failed\n");
4358                         goto skip_power_saving;
4359                 }
4360
4361                 /* After entering partial_power_down, hardware is no more accessible */
4362                 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4363         }
4364
4365         /* Ask phy to be suspended */
4366         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4367                 spin_unlock_irqrestore(&hsotg->lock, flags);
4368                 usb_phy_set_suspend(hsotg->uphy, true);
4369                 spin_lock_irqsave(&hsotg->lock, flags);
4370         }
4371
4372 skip_power_saving:
4373         hsotg->lx_state = DWC2_L2;
4374 unlock:
4375         spin_unlock_irqrestore(&hsotg->lock, flags);
4376
4377         return ret;
4378 }
4379
4380 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4381 {
4382         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4383         unsigned long flags;
4384         u32 pcgctl;
4385         int ret = 0;
4386
4387         spin_lock_irqsave(&hsotg->lock, flags);
4388
4389         if (dwc2_is_device_mode(hsotg))
4390                 goto unlock;
4391
4392         if (hsotg->lx_state != DWC2_L2)
4393                 goto unlock;
4394
4395         if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) {
4396                 hsotg->lx_state = DWC2_L0;
4397                 goto unlock;
4398         }
4399
4400         /*
4401          * Enable power if not already done.
4402          * This must not be spinlocked since duration
4403          * of this call is unknown.
4404          */
4405         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4406                 spin_unlock_irqrestore(&hsotg->lock, flags);
4407                 usb_phy_set_suspend(hsotg->uphy, false);
4408                 spin_lock_irqsave(&hsotg->lock, flags);
4409         }
4410
4411         if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4412                 /*
4413                  * Set HW accessible bit before powering on the controller
4414                  * since an interrupt may rise.
4415                  */
4416                 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4417
4418
4419                 /* Exit partial_power_down */
4420                 ret = dwc2_exit_partial_power_down(hsotg, true);
4421                 if (ret && (ret != -ENOTSUPP))
4422                         dev_err(hsotg->dev, "exit partial_power_down failed\n");
4423         } else {
4424                 pcgctl = readl(hsotg->regs + PCGCTL);
4425                 pcgctl &= ~PCGCTL_STOPPCLK;
4426                 writel(pcgctl, hsotg->regs + PCGCTL);
4427         }
4428
4429         hsotg->lx_state = DWC2_L0;
4430
4431         spin_unlock_irqrestore(&hsotg->lock, flags);
4432
4433         if (hsotg->bus_suspended) {
4434                 spin_lock_irqsave(&hsotg->lock, flags);
4435                 hsotg->flags.b.port_suspend_change = 1;
4436                 spin_unlock_irqrestore(&hsotg->lock, flags);
4437                 dwc2_port_resume(hsotg);
4438         } else {
4439                 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4440                         dwc2_vbus_supply_init(hsotg);
4441
4442                         /* Wait for controller to correctly update D+/D- level */
4443                         usleep_range(3000, 5000);
4444                 }
4445
4446                 /*
4447                  * Clear Port Enable and Port Status changes.
4448                  * Enable Port Power.
4449                  */
4450                 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4451                                 HPRT0_ENACHG, HPRT0);
4452                 /* Wait for controller to detect Port Connect */
4453                 usleep_range(5000, 7000);
4454         }
4455
4456         return ret;
4457 unlock:
4458         spin_unlock_irqrestore(&hsotg->lock, flags);
4459
4460         return ret;
4461 }
4462
4463 /* Returns the current frame number */
4464 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4465 {
4466         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4467
4468         return dwc2_hcd_get_frame_number(hsotg);
4469 }
4470
4471 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4472                                char *fn_name)
4473 {
4474 #ifdef VERBOSE_DEBUG
4475         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4476         char *pipetype = NULL;
4477         char *speed = NULL;
4478
4479         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4480         dev_vdbg(hsotg->dev, "  Device address: %d\n",
4481                  usb_pipedevice(urb->pipe));
4482         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
4483                  usb_pipeendpoint(urb->pipe),
4484                  usb_pipein(urb->pipe) ? "IN" : "OUT");
4485
4486         switch (usb_pipetype(urb->pipe)) {
4487         case PIPE_CONTROL:
4488                 pipetype = "CONTROL";
4489                 break;
4490         case PIPE_BULK:
4491                 pipetype = "BULK";
4492                 break;
4493         case PIPE_INTERRUPT:
4494                 pipetype = "INTERRUPT";
4495                 break;
4496         case PIPE_ISOCHRONOUS:
4497                 pipetype = "ISOCHRONOUS";
4498                 break;
4499         }
4500
4501         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
4502                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4503                  "IN" : "OUT");
4504
4505         switch (urb->dev->speed) {
4506         case USB_SPEED_HIGH:
4507                 speed = "HIGH";
4508                 break;
4509         case USB_SPEED_FULL:
4510                 speed = "FULL";
4511                 break;
4512         case USB_SPEED_LOW:
4513                 speed = "LOW";
4514                 break;
4515         default:
4516                 speed = "UNKNOWN";
4517                 break;
4518         }
4519
4520         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
4521         dev_vdbg(hsotg->dev, "  Max packet size: %d (%d mult)\n",
4522                  usb_endpoint_maxp(&urb->ep->desc),
4523                  usb_endpoint_maxp_mult(&urb->ep->desc));
4524
4525         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
4526                  urb->transfer_buffer_length);
4527         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
4528                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4529         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
4530                  urb->setup_packet, (unsigned long)urb->setup_dma);
4531         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
4532
4533         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4534                 int i;
4535
4536                 for (i = 0; i < urb->number_of_packets; i++) {
4537                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
4538                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
4539                                  urb->iso_frame_desc[i].offset,
4540                                  urb->iso_frame_desc[i].length);
4541                 }
4542         }
4543 #endif
4544 }
4545
4546 /*
4547  * Starts processing a USB transfer request specified by a USB Request Block
4548  * (URB). mem_flags indicates the type of memory allocation to use while
4549  * processing this URB.
4550  */
4551 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4552                                  gfp_t mem_flags)
4553 {
4554         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4555         struct usb_host_endpoint *ep = urb->ep;
4556         struct dwc2_hcd_urb *dwc2_urb;
4557         int i;
4558         int retval;
4559         int alloc_bandwidth = 0;
4560         u8 ep_type = 0;
4561         u32 tflags = 0;
4562         void *buf;
4563         unsigned long flags;
4564         struct dwc2_qh *qh;
4565         bool qh_allocated = false;
4566         struct dwc2_qtd *qtd;
4567
4568         if (dbg_urb(urb)) {
4569                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4570                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4571         }
4572
4573         if (!ep)
4574                 return -EINVAL;
4575
4576         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4577             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4578                 spin_lock_irqsave(&hsotg->lock, flags);
4579                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4580                         alloc_bandwidth = 1;
4581                 spin_unlock_irqrestore(&hsotg->lock, flags);
4582         }
4583
4584         switch (usb_pipetype(urb->pipe)) {
4585         case PIPE_CONTROL:
4586                 ep_type = USB_ENDPOINT_XFER_CONTROL;
4587                 break;
4588         case PIPE_ISOCHRONOUS:
4589                 ep_type = USB_ENDPOINT_XFER_ISOC;
4590                 break;
4591         case PIPE_BULK:
4592                 ep_type = USB_ENDPOINT_XFER_BULK;
4593                 break;
4594         case PIPE_INTERRUPT:
4595                 ep_type = USB_ENDPOINT_XFER_INT;
4596                 break;
4597         }
4598
4599         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4600                                       mem_flags);
4601         if (!dwc2_urb)
4602                 return -ENOMEM;
4603
4604         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4605                                   usb_pipeendpoint(urb->pipe), ep_type,
4606                                   usb_pipein(urb->pipe),
4607                                   usb_endpoint_maxp(&ep->desc),
4608                                   usb_endpoint_maxp_mult(&ep->desc));
4609
4610         buf = urb->transfer_buffer;
4611
4612         if (hcd_uses_dma(hcd)) {
4613                 if (!buf && (urb->transfer_dma & 3)) {
4614                         dev_err(hsotg->dev,
4615                                 "%s: unaligned transfer with no transfer_buffer",
4616                                 __func__);
4617                         retval = -EINVAL;
4618                         goto fail0;
4619                 }
4620         }
4621
4622         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4623                 tflags |= URB_GIVEBACK_ASAP;
4624         if (urb->transfer_flags & URB_ZERO_PACKET)
4625                 tflags |= URB_SEND_ZERO_PACKET;
4626
4627         dwc2_urb->priv = urb;
4628         dwc2_urb->buf = buf;
4629         dwc2_urb->dma = urb->transfer_dma;
4630         dwc2_urb->length = urb->transfer_buffer_length;
4631         dwc2_urb->setup_packet = urb->setup_packet;
4632         dwc2_urb->setup_dma = urb->setup_dma;
4633         dwc2_urb->flags = tflags;
4634         dwc2_urb->interval = urb->interval;
4635         dwc2_urb->status = -EINPROGRESS;
4636
4637         for (i = 0; i < urb->number_of_packets; ++i)
4638                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4639                                                  urb->iso_frame_desc[i].offset,
4640                                                  urb->iso_frame_desc[i].length);
4641
4642         urb->hcpriv = dwc2_urb;
4643         qh = (struct dwc2_qh *)ep->hcpriv;
4644         /* Create QH for the endpoint if it doesn't exist */
4645         if (!qh) {
4646                 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4647                 if (!qh) {
4648                         retval = -ENOMEM;
4649                         goto fail0;
4650                 }
4651                 ep->hcpriv = qh;
4652                 qh_allocated = true;
4653         }
4654
4655         qtd = kzalloc(sizeof(*qtd), mem_flags);
4656         if (!qtd) {
4657                 retval = -ENOMEM;
4658                 goto fail1;
4659         }
4660
4661         spin_lock_irqsave(&hsotg->lock, flags);
4662         retval = usb_hcd_link_urb_to_ep(hcd, urb);
4663         if (retval)
4664                 goto fail2;
4665
4666         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4667         if (retval)
4668                 goto fail3;
4669
4670         if (alloc_bandwidth) {
4671                 dwc2_allocate_bus_bandwidth(hcd,
4672                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4673                                 urb);
4674         }
4675
4676         spin_unlock_irqrestore(&hsotg->lock, flags);
4677
4678         return 0;
4679
4680 fail3:
4681         dwc2_urb->priv = NULL;
4682         usb_hcd_unlink_urb_from_ep(hcd, urb);
4683         if (qh_allocated && qh->channel && qh->channel->qh == qh)
4684                 qh->channel->qh = NULL;
4685 fail2:
4686         spin_unlock_irqrestore(&hsotg->lock, flags);
4687         urb->hcpriv = NULL;
4688         kfree(qtd);
4689 fail1:
4690         if (qh_allocated) {
4691                 struct dwc2_qtd *qtd2, *qtd2_tmp;
4692
4693                 ep->hcpriv = NULL;
4694                 dwc2_hcd_qh_unlink(hsotg, qh);
4695                 /* Free each QTD in the QH's QTD list */
4696                 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4697                                          qtd_list_entry)
4698                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4699                 dwc2_hcd_qh_free(hsotg, qh);
4700         }
4701 fail0:
4702         kfree(dwc2_urb);
4703
4704         return retval;
4705 }
4706
4707 /*
4708  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4709  */
4710 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4711                                  int status)
4712 {
4713         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4714         int rc;
4715         unsigned long flags;
4716
4717         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4718         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4719
4720         spin_lock_irqsave(&hsotg->lock, flags);
4721
4722         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4723         if (rc)
4724                 goto out;
4725
4726         if (!urb->hcpriv) {
4727                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4728                 goto out;
4729         }
4730
4731         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4732
4733         usb_hcd_unlink_urb_from_ep(hcd, urb);
4734
4735         kfree(urb->hcpriv);
4736         urb->hcpriv = NULL;
4737
4738         /* Higher layer software sets URB status */
4739         spin_unlock(&hsotg->lock);
4740         usb_hcd_giveback_urb(hcd, urb, status);
4741         spin_lock(&hsotg->lock);
4742
4743         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4744         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
4745 out:
4746         spin_unlock_irqrestore(&hsotg->lock, flags);
4747
4748         return rc;
4749 }
4750
4751 /*
4752  * Frees resources in the DWC_otg controller related to a given endpoint. Also
4753  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4754  * must already be dequeued.
4755  */
4756 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4757                                        struct usb_host_endpoint *ep)
4758 {
4759         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4760
4761         dev_dbg(hsotg->dev,
4762                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4763                 ep->desc.bEndpointAddress, ep->hcpriv);
4764         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4765 }
4766
4767 /*
4768  * Resets endpoint specific parameter values, in current version used to reset
4769  * the data toggle (as a WA). This function can be called from usb_clear_halt
4770  * routine.
4771  */
4772 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4773                                      struct usb_host_endpoint *ep)
4774 {
4775         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4776         unsigned long flags;
4777
4778         dev_dbg(hsotg->dev,
4779                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4780                 ep->desc.bEndpointAddress);
4781
4782         spin_lock_irqsave(&hsotg->lock, flags);
4783         dwc2_hcd_endpoint_reset(hsotg, ep);
4784         spin_unlock_irqrestore(&hsotg->lock, flags);
4785 }
4786
4787 /*
4788  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4789  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4790  * interrupt.
4791  *
4792  * This function is called by the USB core when an interrupt occurs
4793  */
4794 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4795 {
4796         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4797
4798         return dwc2_handle_hcd_intr(hsotg);
4799 }
4800
4801 /*
4802  * Creates Status Change bitmap for the root hub and root port. The bitmap is
4803  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4804  * is the status change indicator for the single root port. Returns 1 if either
4805  * change indicator is 1, otherwise returns 0.
4806  */
4807 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4808 {
4809         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4810
4811         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4812         return buf[0] != 0;
4813 }
4814
4815 /* Handles hub class-specific requests */
4816 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4817                                  u16 windex, char *buf, u16 wlength)
4818 {
4819         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4820                                           wvalue, windex, buf, wlength);
4821         return retval;
4822 }
4823
4824 /* Handles hub TT buffer clear completions */
4825 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4826                                                struct usb_host_endpoint *ep)
4827 {
4828         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4829         struct dwc2_qh *qh;
4830         unsigned long flags;
4831
4832         qh = ep->hcpriv;
4833         if (!qh)
4834                 return;
4835
4836         spin_lock_irqsave(&hsotg->lock, flags);
4837         qh->tt_buffer_dirty = 0;
4838
4839         if (hsotg->flags.b.port_connect_status)
4840                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4841
4842         spin_unlock_irqrestore(&hsotg->lock, flags);
4843 }
4844
4845 /*
4846  * HPRT0_SPD_HIGH_SPEED: high speed
4847  * HPRT0_SPD_FULL_SPEED: full speed
4848  */
4849 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4850 {
4851         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4852
4853         if (hsotg->params.speed == speed)
4854                 return;
4855
4856         hsotg->params.speed = speed;
4857         queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4858 }
4859
4860 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4861 {
4862         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4863
4864         if (!hsotg->params.change_speed_quirk)
4865                 return;
4866
4867         /*
4868          * On removal, set speed to default high-speed.
4869          */
4870         if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4871             udev->parent->speed < USB_SPEED_HIGH) {
4872                 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4873                 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4874         }
4875 }
4876
4877 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
4878 {
4879         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4880
4881         if (!hsotg->params.change_speed_quirk)
4882                 return 0;
4883
4884         if (udev->speed == USB_SPEED_HIGH) {
4885                 dev_info(hsotg->dev, "Set speed to high-speed\n");
4886                 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4887         } else if ((udev->speed == USB_SPEED_FULL ||
4888                                 udev->speed == USB_SPEED_LOW)) {
4889                 /*
4890                  * Change speed setting to full-speed if there's
4891                  * a full-speed or low-speed device plugged in.
4892                  */
4893                 dev_info(hsotg->dev, "Set speed to full-speed\n");
4894                 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
4895         }
4896
4897         return 0;
4898 }
4899
4900 static struct hc_driver dwc2_hc_driver = {
4901         .description = "dwc2_hsotg",
4902         .product_desc = "DWC OTG Controller",
4903         .hcd_priv_size = sizeof(struct wrapper_priv_data),
4904
4905         .irq = _dwc2_hcd_irq,
4906         .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
4907
4908         .start = _dwc2_hcd_start,
4909         .stop = _dwc2_hcd_stop,
4910         .urb_enqueue = _dwc2_hcd_urb_enqueue,
4911         .urb_dequeue = _dwc2_hcd_urb_dequeue,
4912         .endpoint_disable = _dwc2_hcd_endpoint_disable,
4913         .endpoint_reset = _dwc2_hcd_endpoint_reset,
4914         .get_frame_number = _dwc2_hcd_get_frame_number,
4915
4916         .hub_status_data = _dwc2_hcd_hub_status_data,
4917         .hub_control = _dwc2_hcd_hub_control,
4918         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
4919
4920         .bus_suspend = _dwc2_hcd_suspend,
4921         .bus_resume = _dwc2_hcd_resume,
4922
4923         .map_urb_for_dma        = dwc2_map_urb_for_dma,
4924         .unmap_urb_for_dma      = dwc2_unmap_urb_for_dma,
4925 };
4926
4927 /*
4928  * Frees secondary storage associated with the dwc2_hsotg structure contained
4929  * in the struct usb_hcd field
4930  */
4931 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4932 {
4933         u32 ahbcfg;
4934         u32 dctl;
4935         int i;
4936
4937         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4938
4939         /* Free memory for QH/QTD lists */
4940         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4941         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
4942         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4943         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4944         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4945         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
4946         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
4947
4948         /* Free memory for the host channels */
4949         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
4950                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
4951
4952                 if (chan) {
4953                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
4954                                 i, chan);
4955                         hsotg->hc_ptr_array[i] = NULL;
4956                         kfree(chan);
4957                 }
4958         }
4959
4960         if (hsotg->params.host_dma) {
4961                 if (hsotg->status_buf) {
4962                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
4963                                           hsotg->status_buf,
4964                                           hsotg->status_buf_dma);
4965                         hsotg->status_buf = NULL;
4966                 }
4967         } else {
4968                 kfree(hsotg->status_buf);
4969                 hsotg->status_buf = NULL;
4970         }
4971
4972         ahbcfg = dwc2_readl(hsotg, GAHBCFG);
4973
4974         /* Disable all interrupts */
4975         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
4976         dwc2_writel(hsotg, ahbcfg, GAHBCFG);
4977         dwc2_writel(hsotg, 0, GINTMSK);
4978
4979         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
4980                 dctl = dwc2_readl(hsotg, DCTL);
4981                 dctl |= DCTL_SFTDISCON;
4982                 dwc2_writel(hsotg, dctl, DCTL);
4983         }
4984
4985         if (hsotg->wq_otg) {
4986                 if (!cancel_work_sync(&hsotg->wf_otg))
4987                         flush_workqueue(hsotg->wq_otg);
4988                 destroy_workqueue(hsotg->wq_otg);
4989         }
4990
4991         cancel_work_sync(&hsotg->phy_reset_work);
4992
4993         del_timer(&hsotg->wkp_timer);
4994 }
4995
4996 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
4997 {
4998         /* Turn off all host-specific interrupts */
4999         dwc2_disable_host_interrupts(hsotg);
5000
5001         dwc2_hcd_free(hsotg);
5002 }
5003
5004 /*
5005  * Initializes the HCD. This function allocates memory for and initializes the
5006  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5007  * USB bus with the core and calls the hc_driver->start() function. It returns
5008  * a negative error on failure.
5009  */
5010 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5011 {
5012         struct platform_device *pdev = to_platform_device(hsotg->dev);
5013         struct resource *res;
5014         struct usb_hcd *hcd;
5015         struct dwc2_host_chan *channel;
5016         u32 hcfg;
5017         int i, num_channels;
5018         int retval;
5019
5020         if (usb_disabled())
5021                 return -ENODEV;
5022
5023         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5024
5025         retval = -ENOMEM;
5026
5027         hcfg = dwc2_readl(hsotg, HCFG);
5028         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5029
5030 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5031         hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5032                                          sizeof(*hsotg->frame_num_array),
5033                                          GFP_KERNEL);
5034         if (!hsotg->frame_num_array)
5035                 goto error1;
5036         hsotg->last_frame_num_array =
5037                 kcalloc(FRAME_NUM_ARRAY_SIZE,
5038                         sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5039         if (!hsotg->last_frame_num_array)
5040                 goto error1;
5041 #endif
5042         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5043
5044         /* Check if the bus driver or platform code has setup a dma_mask */
5045         if (hsotg->params.host_dma &&
5046             !hsotg->dev->dma_mask) {
5047                 dev_warn(hsotg->dev,
5048                          "dma_mask not set, disabling DMA\n");
5049                 hsotg->params.host_dma = false;
5050                 hsotg->params.dma_desc_enable = false;
5051         }
5052
5053         /* Set device flags indicating whether the HCD supports DMA */
5054         if (hsotg->params.host_dma) {
5055                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5056                         dev_warn(hsotg->dev, "can't set DMA mask\n");
5057                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5058                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5059         }
5060
5061         if (hsotg->params.change_speed_quirk) {
5062                 dwc2_hc_driver.free_dev = dwc2_free_dev;
5063                 dwc2_hc_driver.reset_device = dwc2_reset_device;
5064         }
5065
5066         if (hsotg->params.host_dma)
5067                 dwc2_hc_driver.flags |= HCD_DMA;
5068
5069         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5070         if (!hcd)
5071                 goto error1;
5072
5073         hcd->has_tt = 1;
5074
5075         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5076         hcd->rsrc_start = res->start;
5077         hcd->rsrc_len = resource_size(res);
5078
5079         ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5080         hsotg->priv = hcd;
5081
5082         /*
5083          * Disable the global interrupt until all the interrupt handlers are
5084          * installed
5085          */
5086         dwc2_disable_global_interrupts(hsotg);
5087
5088         /* Initialize the DWC_otg core, and select the Phy type */
5089         retval = dwc2_core_init(hsotg, true);
5090         if (retval)
5091                 goto error2;
5092
5093         /* Create new workqueue and init work */
5094         retval = -ENOMEM;
5095         hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5096         if (!hsotg->wq_otg) {
5097                 dev_err(hsotg->dev, "Failed to create workqueue\n");
5098                 goto error2;
5099         }
5100         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5101
5102         timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5103
5104         /* Initialize the non-periodic schedule */
5105         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5106         INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5107         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5108
5109         /* Initialize the periodic schedule */
5110         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5111         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5112         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5113         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5114
5115         INIT_LIST_HEAD(&hsotg->split_order);
5116
5117         /*
5118          * Create a host channel descriptor for each host channel implemented
5119          * in the controller. Initialize the channel descriptor array.
5120          */
5121         INIT_LIST_HEAD(&hsotg->free_hc_list);
5122         num_channels = hsotg->params.host_channels;
5123         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5124
5125         for (i = 0; i < num_channels; i++) {
5126                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5127                 if (!channel)
5128                         goto error3;
5129                 channel->hc_num = i;
5130                 INIT_LIST_HEAD(&channel->split_order_list_entry);
5131                 hsotg->hc_ptr_array[i] = channel;
5132         }
5133
5134         /* Initialize work */
5135         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5136         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5137         INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func);
5138
5139         /*
5140          * Allocate space for storing data on status transactions. Normally no
5141          * data is sent, but this space acts as a bit bucket. This must be
5142          * done after usb_add_hcd since that function allocates the DMA buffer
5143          * pool.
5144          */
5145         if (hsotg->params.host_dma)
5146                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5147                                         DWC2_HCD_STATUS_BUF_SIZE,
5148                                         &hsotg->status_buf_dma, GFP_KERNEL);
5149         else
5150                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5151                                           GFP_KERNEL);
5152
5153         if (!hsotg->status_buf)
5154                 goto error3;
5155
5156         /*
5157          * Create kmem caches to handle descriptor buffers in descriptor
5158          * DMA mode.
5159          * Alignment must be set to 512 bytes.
5160          */
5161         if (hsotg->params.dma_desc_enable ||
5162             hsotg->params.dma_desc_fs_enable) {
5163                 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5164                                 sizeof(struct dwc2_dma_desc) *
5165                                 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5166                                 NULL);
5167                 if (!hsotg->desc_gen_cache) {
5168                         dev_err(hsotg->dev,
5169                                 "unable to create dwc2 generic desc cache\n");
5170
5171                         /*
5172                          * Disable descriptor dma mode since it will not be
5173                          * usable.
5174                          */
5175                         hsotg->params.dma_desc_enable = false;
5176                         hsotg->params.dma_desc_fs_enable = false;
5177                 }
5178
5179                 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5180                                 sizeof(struct dwc2_dma_desc) *
5181                                 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5182                 if (!hsotg->desc_hsisoc_cache) {
5183                         dev_err(hsotg->dev,
5184                                 "unable to create dwc2 hs isoc desc cache\n");
5185
5186                         kmem_cache_destroy(hsotg->desc_gen_cache);
5187
5188                         /*
5189                          * Disable descriptor dma mode since it will not be
5190                          * usable.
5191                          */
5192                         hsotg->params.dma_desc_enable = false;
5193                         hsotg->params.dma_desc_fs_enable = false;
5194                 }
5195         }
5196
5197         if (hsotg->params.host_dma) {
5198                 /*
5199                  * Create kmem caches to handle non-aligned buffer
5200                  * in Buffer DMA mode.
5201                  */
5202                 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5203                                                 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5204                                                 SLAB_CACHE_DMA, NULL);
5205                 if (!hsotg->unaligned_cache)
5206                         dev_err(hsotg->dev,
5207                                 "unable to create dwc2 unaligned cache\n");
5208         }
5209
5210         hsotg->otg_port = 1;
5211         hsotg->frame_list = NULL;
5212         hsotg->frame_list_dma = 0;
5213         hsotg->periodic_qh_count = 0;
5214
5215         /* Initiate lx_state to L3 disconnected state */
5216         hsotg->lx_state = DWC2_L3;
5217
5218         hcd->self.otg_port = hsotg->otg_port;
5219
5220         /* Don't support SG list at this point */
5221         hcd->self.sg_tablesize = 0;
5222
5223         if (!IS_ERR_OR_NULL(hsotg->uphy))
5224                 otg_set_host(hsotg->uphy->otg, &hcd->self);
5225
5226         /*
5227          * Finish generic HCD initialization and start the HCD. This function
5228          * allocates the DMA buffer pool, registers the USB bus, requests the
5229          * IRQ line, and calls hcd_start method.
5230          */
5231         retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5232         if (retval < 0)
5233                 goto error4;
5234
5235         device_wakeup_enable(hcd->self.controller);
5236
5237         dwc2_hcd_dump_state(hsotg);
5238
5239         dwc2_enable_global_interrupts(hsotg);
5240
5241         return 0;
5242
5243 error4:
5244         kmem_cache_destroy(hsotg->unaligned_cache);
5245         kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5246         kmem_cache_destroy(hsotg->desc_gen_cache);
5247 error3:
5248         dwc2_hcd_release(hsotg);
5249 error2:
5250         usb_put_hcd(hcd);
5251 error1:
5252
5253 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5254         kfree(hsotg->last_frame_num_array);
5255         kfree(hsotg->frame_num_array);
5256 #endif
5257
5258         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5259         return retval;
5260 }
5261
5262 /*
5263  * Removes the HCD.
5264  * Frees memory and resources associated with the HCD and deregisters the bus.
5265  */
5266 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5267 {
5268         struct usb_hcd *hcd;
5269
5270         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5271
5272         hcd = dwc2_hsotg_to_hcd(hsotg);
5273         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5274
5275         if (!hcd) {
5276                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5277                         __func__);
5278                 return;
5279         }
5280
5281         if (!IS_ERR_OR_NULL(hsotg->uphy))
5282                 otg_set_host(hsotg->uphy->otg, NULL);
5283
5284         usb_remove_hcd(hcd);
5285         hsotg->priv = NULL;
5286
5287         kmem_cache_destroy(hsotg->unaligned_cache);
5288         kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5289         kmem_cache_destroy(hsotg->desc_gen_cache);
5290
5291         dwc2_hcd_release(hsotg);
5292         usb_put_hcd(hcd);
5293
5294 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5295         kfree(hsotg->last_frame_num_array);
5296         kfree(hsotg->frame_num_array);
5297 #endif
5298 }
5299
5300 /**
5301  * dwc2_backup_host_registers() - Backup controller host registers.
5302  * When suspending usb bus, registers needs to be backuped
5303  * if controller power is disabled once suspended.
5304  *
5305  * @hsotg: Programming view of the DWC_otg controller
5306  */
5307 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5308 {
5309         struct dwc2_hregs_backup *hr;
5310         int i;
5311
5312         dev_dbg(hsotg->dev, "%s\n", __func__);
5313
5314         /* Backup Host regs */
5315         hr = &hsotg->hr_backup;
5316         hr->hcfg = dwc2_readl(hsotg, HCFG);
5317         hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5318         for (i = 0; i < hsotg->params.host_channels; ++i)
5319                 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5320
5321         hr->hprt0 = dwc2_read_hprt0(hsotg);
5322         hr->hfir = dwc2_readl(hsotg, HFIR);
5323         hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5324         hr->valid = true;
5325
5326         return 0;
5327 }
5328
5329 /**
5330  * dwc2_restore_host_registers() - Restore controller host registers.
5331  * When resuming usb bus, device registers needs to be restored
5332  * if controller power were disabled.
5333  *
5334  * @hsotg: Programming view of the DWC_otg controller
5335  */
5336 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5337 {
5338         struct dwc2_hregs_backup *hr;
5339         int i;
5340
5341         dev_dbg(hsotg->dev, "%s\n", __func__);
5342
5343         /* Restore host regs */
5344         hr = &hsotg->hr_backup;
5345         if (!hr->valid) {
5346                 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5347                         __func__);
5348                 return -EINVAL;
5349         }
5350         hr->valid = false;
5351
5352         dwc2_writel(hsotg, hr->hcfg, HCFG);
5353         dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5354
5355         for (i = 0; i < hsotg->params.host_channels; ++i)
5356                 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5357
5358         dwc2_writel(hsotg, hr->hprt0, HPRT0);
5359         dwc2_writel(hsotg, hr->hfir, HFIR);
5360         dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5361         hsotg->frame_number = 0;
5362
5363         return 0;
5364 }
5365
5366 /**
5367  * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5368  *
5369  * @hsotg: Programming view of the DWC_otg controller
5370  */
5371 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5372 {
5373         unsigned long flags;
5374         int ret = 0;
5375         u32 hprt0;
5376         u32 pcgcctl;
5377         u32 gusbcfg;
5378         u32 gpwrdn;
5379
5380         dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5381         ret = dwc2_backup_global_registers(hsotg);
5382         if (ret) {
5383                 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5384                         __func__);
5385                 return ret;
5386         }
5387         ret = dwc2_backup_host_registers(hsotg);
5388         if (ret) {
5389                 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5390                         __func__);
5391                 return ret;
5392         }
5393
5394         /* Enter USB Suspend Mode */
5395         hprt0 = dwc2_readl(hsotg, HPRT0);
5396         hprt0 |= HPRT0_SUSP;
5397         hprt0 &= ~HPRT0_ENA;
5398         dwc2_writel(hsotg, hprt0, HPRT0);
5399
5400         /* Wait for the HPRT0.PrtSusp register field to be set */
5401         if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
5402                 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5403
5404         /*
5405          * We need to disable interrupts to prevent servicing of any IRQ
5406          * during going to hibernation
5407          */
5408         spin_lock_irqsave(&hsotg->lock, flags);
5409         hsotg->lx_state = DWC2_L2;
5410
5411         gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5412         if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5413                 /* ULPI interface */
5414                 /* Suspend the Phy Clock */
5415                 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5416                 pcgcctl |= PCGCTL_STOPPCLK;
5417                 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5418                 udelay(10);
5419
5420                 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5421                 gpwrdn |= GPWRDN_PMUACTV;
5422                 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5423                 udelay(10);
5424         } else {
5425                 /* UTMI+ Interface */
5426                 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5427                 gpwrdn |= GPWRDN_PMUACTV;
5428                 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5429                 udelay(10);
5430
5431                 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5432                 pcgcctl |= PCGCTL_STOPPCLK;
5433                 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5434                 udelay(10);
5435         }
5436
5437         /* Enable interrupts from wake up logic */
5438         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5439         gpwrdn |= GPWRDN_PMUINTSEL;
5440         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5441         udelay(10);
5442
5443         /* Unmask host mode interrupts in GPWRDN */
5444         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5445         gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5446         gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5447         gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5448         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5449         udelay(10);
5450
5451         /* Enable Power Down Clamp */
5452         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5453         gpwrdn |= GPWRDN_PWRDNCLMP;
5454         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5455         udelay(10);
5456
5457         /* Switch off VDD */
5458         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5459         gpwrdn |= GPWRDN_PWRDNSWTCH;
5460         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5461
5462         hsotg->hibernated = 1;
5463         hsotg->bus_suspended = 1;
5464         dev_dbg(hsotg->dev, "Host hibernation completed\n");
5465         spin_unlock_irqrestore(&hsotg->lock, flags);
5466         return ret;
5467 }
5468
5469 /*
5470  * dwc2_host_exit_hibernation()
5471  *
5472  * @hsotg: Programming view of the DWC_otg controller
5473  * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5474  * @param reset: indicates whether resume is initiated by Reset.
5475  *
5476  * Return: non-zero if failed to enter to hibernation.
5477  *
5478  * This function is for exiting from Host mode hibernation by
5479  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5480  */
5481 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5482                                int reset)
5483 {
5484         u32 gpwrdn;
5485         u32 hprt0;
5486         int ret = 0;
5487         struct dwc2_gregs_backup *gr;
5488         struct dwc2_hregs_backup *hr;
5489
5490         gr = &hsotg->gr_backup;
5491         hr = &hsotg->hr_backup;
5492
5493         dev_dbg(hsotg->dev,
5494                 "%s: called with rem_wakeup = %d reset = %d\n",
5495                 __func__, rem_wakeup, reset);
5496
5497         dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5498         hsotg->hibernated = 0;
5499
5500         /*
5501          * This step is not described in functional spec but if not wait for
5502          * this delay, mismatch interrupts occurred because just after restore
5503          * core is in Device mode(gintsts.curmode == 0)
5504          */
5505         mdelay(100);
5506
5507         /* Clear all pending interupts */
5508         dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5509
5510         /* De-assert Restore */
5511         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5512         gpwrdn &= ~GPWRDN_RESTORE;
5513         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5514         udelay(10);
5515
5516         /* Restore GUSBCFG, HCFG */
5517         dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5518         dwc2_writel(hsotg, hr->hcfg, HCFG);
5519
5520         /* De-assert Wakeup Logic */
5521         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5522         gpwrdn &= ~GPWRDN_PMUACTV;
5523         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5524         udelay(10);
5525
5526         hprt0 = hr->hprt0;
5527         hprt0 |= HPRT0_PWR;
5528         hprt0 &= ~HPRT0_ENA;
5529         hprt0 &= ~HPRT0_SUSP;
5530         dwc2_writel(hsotg, hprt0, HPRT0);
5531
5532         hprt0 = hr->hprt0;
5533         hprt0 |= HPRT0_PWR;
5534         hprt0 &= ~HPRT0_ENA;
5535         hprt0 &= ~HPRT0_SUSP;
5536
5537         if (reset) {
5538                 hprt0 |= HPRT0_RST;
5539                 dwc2_writel(hsotg, hprt0, HPRT0);
5540
5541                 /* Wait for Resume time and then program HPRT again */
5542                 mdelay(60);
5543                 hprt0 &= ~HPRT0_RST;
5544                 dwc2_writel(hsotg, hprt0, HPRT0);
5545         } else {
5546                 hprt0 |= HPRT0_RES;
5547                 dwc2_writel(hsotg, hprt0, HPRT0);
5548
5549                 /* Wait for Resume time and then program HPRT again */
5550                 mdelay(100);
5551                 hprt0 &= ~HPRT0_RES;
5552                 dwc2_writel(hsotg, hprt0, HPRT0);
5553         }
5554         /* Clear all interrupt status */
5555         hprt0 = dwc2_readl(hsotg, HPRT0);
5556         hprt0 |= HPRT0_CONNDET;
5557         hprt0 |= HPRT0_ENACHG;
5558         hprt0 &= ~HPRT0_ENA;
5559         dwc2_writel(hsotg, hprt0, HPRT0);
5560
5561         hprt0 = dwc2_readl(hsotg, HPRT0);
5562
5563         /* Clear all pending interupts */
5564         dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5565
5566         /* Restore global registers */
5567         ret = dwc2_restore_global_registers(hsotg);
5568         if (ret) {
5569                 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5570                         __func__);
5571                 return ret;
5572         }
5573
5574         /* Restore host registers */
5575         ret = dwc2_restore_host_registers(hsotg);
5576         if (ret) {
5577                 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5578                         __func__);
5579                 return ret;
5580         }
5581
5582         dwc2_hcd_rem_wakeup(hsotg);
5583
5584         hsotg->hibernated = 0;
5585         hsotg->bus_suspended = 0;
5586         hsotg->lx_state = DWC2_L0;
5587         dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
5588         return ret;
5589 }
5590
5591 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
5592 {
5593         struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub;
5594
5595         /* If the controller isn't allowed to wakeup then we can power off. */
5596         if (!device_may_wakeup(dwc2->dev))
5597                 return true;
5598
5599         /*
5600          * We don't want to power off the PHY if something under the
5601          * root hub has wakeup enabled.
5602          */
5603         if (usb_wakeup_enabled_descendants(root_hub))
5604                 return false;
5605
5606         /* No reason to keep the PHY powered, so allow poweroff */
5607         return true;
5608 }