1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/extcon-provider.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
30 #include <linux/usb/composite.h>
36 /* conversion functions */
37 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39 return container_of(req, struct dwc2_hsotg_req, req);
42 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
47 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49 return container_of(gadget, struct dwc2_hsotg, gadget);
52 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
57 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
62 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
66 return hsotg->eps_in[ep_index];
68 return hsotg->eps_out[ep_index];
71 /* forward declaration of functions */
72 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
78 * Return true if we're using DMA.
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
91 * g_using_dma is set depending on dts flag.
93 static inline bool using_dma(struct dwc2_hsotg *hsotg)
95 return hsotg->params.g_dma;
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
102 * Return true if we're using descriptor DMA.
104 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
106 return hsotg->params.g_dma_desc;
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
116 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
118 struct dwc2_hsotg *hsotg = hs_ep->parent;
119 u16 limit = DSTS_SOFFN_LIMIT;
121 if (hsotg->gadget.speed != USB_SPEED_HIGH)
124 hs_ep->target_frame += hs_ep->interval;
125 if (hs_ep->target_frame > limit) {
126 hs_ep->frame_overrun = true;
127 hs_ep->target_frame &= limit;
129 hs_ep->frame_overrun = false;
134 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
136 * @hs_ep: The endpoint.
138 * This function used in service interval based scheduling flow to calculate
139 * descriptor frame number filed value. For service interval mode frame
140 * number in descriptor should point to last (u)frame in the interval.
143 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
145 struct dwc2_hsotg *hsotg = hs_ep->parent;
146 u16 limit = DSTS_SOFFN_LIMIT;
148 if (hsotg->gadget.speed != USB_SPEED_HIGH)
151 if (hs_ep->target_frame)
152 hs_ep->target_frame -= 1;
154 hs_ep->target_frame = limit;
158 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
159 * @hsotg: The device state
160 * @ints: A bitmask of the interrupts to enable
162 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
164 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
167 new_gsintmsk = gsintmsk | ints;
169 if (new_gsintmsk != gsintmsk) {
170 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
171 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
176 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
177 * @hsotg: The device state
178 * @ints: A bitmask of the interrupts to enable
180 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
182 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
185 new_gsintmsk = gsintmsk & ~ints;
187 if (new_gsintmsk != gsintmsk)
188 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
192 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
193 * @hsotg: The device state
194 * @ep: The endpoint index
195 * @dir_in: True if direction is in.
196 * @en: The enable value, true to enable
198 * Set or clear the mask for an individual endpoint's interrupt
201 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
202 unsigned int ep, unsigned int dir_in,
212 local_irq_save(flags);
213 daint = dwc2_readl(hsotg, DAINTMSK);
218 dwc2_writel(hsotg, daint, DAINTMSK);
219 local_irq_restore(flags);
223 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
225 * @hsotg: Programming view of the DWC_otg controller
227 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
229 if (hsotg->hw_params.en_multiple_tx_fifo)
230 /* In dedicated FIFO mode we need count of IN EPs */
231 return hsotg->hw_params.num_dev_in_eps;
233 /* In shared FIFO mode we need count of Periodic IN EPs */
234 return hsotg->hw_params.num_dev_perio_in_ep;
238 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
239 * device mode TX FIFOs
241 * @hsotg: Programming view of the DWC_otg controller
243 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
249 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
250 hsotg->params.g_np_tx_fifo_size);
252 /* Get Endpoint Info Control block size in DWORDs. */
253 tx_addr_max = hsotg->hw_params.total_fifo_size;
255 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
256 if (tx_addr_max <= addr)
259 return tx_addr_max - addr;
263 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
265 * @hsotg: Programming view of the DWC_otg controller
268 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
273 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
274 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
275 gintsts2 &= gintmsk2;
277 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
278 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
279 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
280 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
285 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
288 * @hsotg: Programming view of the DWC_otg controller
290 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
295 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
297 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
300 return tx_fifo_depth;
302 return tx_fifo_depth / tx_fifo_count;
306 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
307 * @hsotg: The device instance.
309 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
316 u32 *txfsz = hsotg->params.g_tx_fifo_size;
318 /* Reset fifo map if not correctly cleared during previous session */
319 WARN_ON(hsotg->fifo_map);
322 /* set RX/NPTX FIFO sizes */
323 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
324 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
325 FIFOSIZE_STARTADDR_SHIFT) |
326 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
330 * arange all the rest of the TX FIFOs, as some versions of this
331 * block have overlapping default addresses. This also ensures
332 * that if the settings have been changed, then they are set to
336 /* start at the end of the GNPTXFSIZ, rounded up */
337 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
340 * Configure fifos sizes from provided configuration and assign
341 * them to endpoints dynamically according to maxpacket size value of
344 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
348 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
349 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
350 "insufficient fifo memory");
353 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
354 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
357 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
358 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
361 * according to p428 of the design guide, we need to ensure that
362 * all fifos are flushed before continuing
365 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
366 GRSTCTL_RXFFLSH, GRSTCTL);
368 /* wait until the fifos are both flushed */
371 val = dwc2_readl(hsotg, GRSTCTL);
373 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
376 if (--timeout == 0) {
378 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
386 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
390 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
391 * @ep: USB endpoint to allocate request for.
392 * @flags: Allocation flags
394 * Allocate a new USB request structure appropriate for the specified endpoint
396 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
399 struct dwc2_hsotg_req *req;
401 req = kzalloc(sizeof(*req), flags);
405 INIT_LIST_HEAD(&req->queue);
411 * is_ep_periodic - return true if the endpoint is in periodic mode.
412 * @hs_ep: The endpoint to query.
414 * Returns true if the endpoint is in periodic mode, meaning it is being
415 * used for an Interrupt or ISO transfer.
417 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
419 return hs_ep->periodic;
423 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
424 * @hsotg: The device state.
425 * @hs_ep: The endpoint for the request
426 * @hs_req: The request being processed.
428 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
429 * of a request to ensure the buffer is ready for access by the caller.
431 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
432 struct dwc2_hsotg_ep *hs_ep,
433 struct dwc2_hsotg_req *hs_req)
435 struct usb_request *req = &hs_req->req;
437 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
441 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
442 * for Control endpoint
443 * @hsotg: The device state.
445 * This function will allocate 4 descriptor chains for EP 0: 2 for
446 * Setup stage, per one for IN and OUT data/status transactions.
448 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
450 hsotg->setup_desc[0] =
451 dmam_alloc_coherent(hsotg->dev,
452 sizeof(struct dwc2_dma_desc),
453 &hsotg->setup_desc_dma[0],
455 if (!hsotg->setup_desc[0])
458 hsotg->setup_desc[1] =
459 dmam_alloc_coherent(hsotg->dev,
460 sizeof(struct dwc2_dma_desc),
461 &hsotg->setup_desc_dma[1],
463 if (!hsotg->setup_desc[1])
466 hsotg->ctrl_in_desc =
467 dmam_alloc_coherent(hsotg->dev,
468 sizeof(struct dwc2_dma_desc),
469 &hsotg->ctrl_in_desc_dma,
471 if (!hsotg->ctrl_in_desc)
474 hsotg->ctrl_out_desc =
475 dmam_alloc_coherent(hsotg->dev,
476 sizeof(struct dwc2_dma_desc),
477 &hsotg->ctrl_out_desc_dma,
479 if (!hsotg->ctrl_out_desc)
489 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
490 * @hsotg: The controller state.
491 * @hs_ep: The endpoint we're going to write for.
492 * @hs_req: The request to write data for.
494 * This is called when the TxFIFO has some space in it to hold a new
495 * transmission and we have something to give it. The actual setup of
496 * the data size is done elsewhere, so all we have to do is to actually
499 * The return value is zero if there is more space (or nothing was done)
500 * otherwise -ENOSPC is returned if the FIFO space was used up.
502 * This routine is only needed for PIO
504 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
505 struct dwc2_hsotg_ep *hs_ep,
506 struct dwc2_hsotg_req *hs_req)
508 bool periodic = is_ep_periodic(hs_ep);
509 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
510 int buf_pos = hs_req->req.actual;
511 int to_write = hs_ep->size_loaded;
517 to_write -= (buf_pos - hs_ep->last_load);
519 /* if there's nothing to write, get out early */
523 if (periodic && !hsotg->dedicated_fifos) {
524 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
529 * work out how much data was loaded so we can calculate
530 * how much data is left in the fifo.
533 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
536 * if shared fifo, we cannot write anything until the
537 * previous data has been completely sent.
539 if (hs_ep->fifo_load != 0) {
540 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
544 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
546 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
548 /* how much of the data has moved */
549 size_done = hs_ep->size_loaded - size_left;
551 /* how much data is left in the fifo */
552 can_write = hs_ep->fifo_load - size_done;
553 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
554 __func__, can_write);
556 can_write = hs_ep->fifo_size - can_write;
557 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
558 __func__, can_write);
560 if (can_write <= 0) {
561 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
564 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
565 can_write = dwc2_readl(hsotg,
566 DTXFSTS(hs_ep->fifo_index));
571 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
573 "%s: no queue slots available (0x%08x)\n",
576 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
580 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
581 can_write *= 4; /* fifo size is in 32bit quantities. */
584 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
586 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
587 __func__, gnptxsts, can_write, to_write, max_transfer);
590 * limit to 512 bytes of data, it seems at least on the non-periodic
591 * FIFO, requests of >512 cause the endpoint to get stuck with a
592 * fragment of the end of the transfer in it.
594 if (can_write > 512 && !periodic)
598 * limit the write to one max-packet size worth of data, but allow
599 * the transfer to return that it did not run out of fifo space
602 if (to_write > max_transfer) {
603 to_write = max_transfer;
605 /* it's needed only when we do not use dedicated fifos */
606 if (!hsotg->dedicated_fifos)
607 dwc2_hsotg_en_gsint(hsotg,
608 periodic ? GINTSTS_PTXFEMP :
612 /* see if we can write data */
614 if (to_write > can_write) {
615 to_write = can_write;
616 pkt_round = to_write % max_transfer;
619 * Round the write down to an
620 * exact number of packets.
622 * Note, we do not currently check to see if we can ever
623 * write a full packet or not to the FIFO.
627 to_write -= pkt_round;
630 * enable correct FIFO interrupt to alert us when there
634 /* it's needed only when we do not use dedicated fifos */
635 if (!hsotg->dedicated_fifos)
636 dwc2_hsotg_en_gsint(hsotg,
637 periodic ? GINTSTS_PTXFEMP :
641 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
642 to_write, hs_req->req.length, can_write, buf_pos);
647 hs_req->req.actual = buf_pos + to_write;
648 hs_ep->total_data += to_write;
651 hs_ep->fifo_load += to_write;
653 to_write = DIV_ROUND_UP(to_write, 4);
654 data = hs_req->req.buf + buf_pos;
656 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
658 return (to_write >= can_write) ? -ENOSPC : 0;
662 * get_ep_limit - get the maximum data legnth for this endpoint
663 * @hs_ep: The endpoint
665 * Return the maximum data that can be queued in one go on a given endpoint
666 * so that transfers that are too long can be split.
668 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
670 int index = hs_ep->index;
671 unsigned int maxsize;
675 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
676 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
680 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
685 /* we made the constant loading easier above by using +1 */
690 * constrain by packet count if maxpkts*pktsize is greater
691 * than the length register size.
694 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
695 maxsize = maxpkt * hs_ep->ep.maxpacket;
701 * dwc2_hsotg_read_frameno - read current frame number
702 * @hsotg: The device instance
704 * Return the current frame number
706 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
710 dsts = dwc2_readl(hsotg, DSTS);
711 dsts &= DSTS_SOFFN_MASK;
712 dsts >>= DSTS_SOFFN_SHIFT;
718 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
719 * DMA descriptor chain prepared for specific endpoint
720 * @hs_ep: The endpoint
722 * Return the maximum data that can be queued in one go on a given endpoint
723 * depending on its descriptor chain capacity so that transfers that
724 * are too long can be split.
726 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
728 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
729 int is_isoc = hs_ep->isochronous;
730 unsigned int maxsize;
731 u32 mps = hs_ep->ep.maxpacket;
732 int dir_in = hs_ep->dir_in;
735 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
736 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
737 MAX_DMA_DESC_NUM_HS_ISOC;
739 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
741 /* Interrupt OUT EP with mps not multiple of 4 */
743 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
744 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
750 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
751 * @hs_ep: The endpoint
752 * @mask: RX/TX bytes mask to be defined
754 * Returns maximum data payload for one descriptor after analyzing endpoint
756 * DMA descriptor transfer bytes limit depends on EP type:
758 * Isochronous - descriptor rx/tx bytes bitfield limit,
759 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
760 * have concatenations from various descriptors within one packet.
761 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
762 * to a single descriptor.
764 * Selects corresponding mask for RX/TX bytes as well.
766 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
768 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
769 u32 mps = hs_ep->ep.maxpacket;
770 int dir_in = hs_ep->dir_in;
773 if (!hs_ep->index && !dir_in) {
775 *mask = DEV_DMA_NBYTES_MASK;
776 } else if (hs_ep->isochronous) {
778 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
779 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
781 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
782 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
785 desc_size = DEV_DMA_NBYTES_LIMIT;
786 *mask = DEV_DMA_NBYTES_MASK;
788 /* Round down desc_size to be mps multiple */
789 desc_size -= desc_size % mps;
792 /* Interrupt OUT EP with mps not multiple of 4 */
794 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
796 *mask = DEV_DMA_NBYTES_MASK;
802 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
803 struct dwc2_dma_desc **desc,
808 int dir_in = hs_ep->dir_in;
809 u32 mps = hs_ep->ep.maxpacket;
815 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
817 hs_ep->desc_count = (len / maxsize) +
818 ((len % maxsize) ? 1 : 0);
820 hs_ep->desc_count = 1;
822 for (i = 0; i < hs_ep->desc_count; ++i) {
824 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
825 << DEV_DMA_BUFF_STS_SHIFT);
828 if (!hs_ep->index && !dir_in)
829 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
832 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
833 (*desc)->buf = dma_buff + offset;
839 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
842 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
843 ((hs_ep->send_zlp && true_last) ?
847 len << DEV_DMA_NBYTES_SHIFT & mask;
848 (*desc)->buf = dma_buff + offset;
851 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
852 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
853 << DEV_DMA_BUFF_STS_SHIFT);
859 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
860 * @hs_ep: The endpoint
861 * @ureq: Request to transfer
862 * @offset: offset in bytes
863 * @len: Length of the transfer
865 * This function will iterate over descriptor chain and fill its entries
866 * with corresponding information based on transfer data.
868 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
872 struct usb_request *ureq = NULL;
873 struct dwc2_dma_desc *desc = hs_ep->desc_list;
874 struct scatterlist *sg;
879 ureq = &hs_ep->req->req;
881 /* non-DMA sg buffer */
882 if (!ureq || !ureq->num_sgs) {
883 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
884 dma_buff, len, true);
889 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
890 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
891 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
893 desc_count += hs_ep->desc_count;
896 hs_ep->desc_count = desc_count;
900 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
901 * @hs_ep: The isochronous endpoint.
902 * @dma_buff: usb requests dma buffer.
903 * @len: usb request transfer length.
905 * Fills next free descriptor with the data of the arrived usb request,
906 * frame info, sets Last and IOC bits increments next_desc. If filled
907 * descriptor is not the first one, removes L bit from the previous descriptor
910 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
911 dma_addr_t dma_buff, unsigned int len)
913 struct dwc2_dma_desc *desc;
914 struct dwc2_hsotg *hsotg = hs_ep->parent;
919 dwc2_gadget_get_desc_params(hs_ep, &mask);
921 index = hs_ep->next_desc;
922 desc = &hs_ep->desc_list[index];
924 /* Check if descriptor chain full */
925 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
926 DEV_DMA_BUFF_STS_HREADY) {
927 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
931 /* Clear L bit of previous desc if more than one entries in the chain */
932 if (hs_ep->next_desc)
933 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
935 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
936 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
939 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
941 desc->buf = dma_buff;
942 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
943 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
947 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
950 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
951 DEV_DMA_ISOC_PID_MASK) |
952 ((len % hs_ep->ep.maxpacket) ?
954 ((hs_ep->target_frame <<
955 DEV_DMA_ISOC_FRNUM_SHIFT) &
956 DEV_DMA_ISOC_FRNUM_MASK);
959 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
960 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
962 /* Increment frame number by interval for IN */
964 dwc2_gadget_incr_frame_num(hs_ep);
966 /* Update index of last configured entry in the chain */
968 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
969 hs_ep->next_desc = 0;
975 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
976 * @hs_ep: The isochronous endpoint.
978 * Prepare descriptor chain for isochronous endpoints. Afterwards
979 * write DMA address to HW and enable the endpoint.
981 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
983 struct dwc2_hsotg *hsotg = hs_ep->parent;
984 struct dwc2_hsotg_req *hs_req, *treq;
985 int index = hs_ep->index;
991 struct dwc2_dma_desc *desc;
993 if (list_empty(&hs_ep->queue)) {
994 hs_ep->target_frame = TARGET_FRAME_INITIAL;
995 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
999 /* Initialize descriptor chain by Host Busy status */
1000 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1001 desc = &hs_ep->desc_list[i];
1003 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1004 << DEV_DMA_BUFF_STS_SHIFT);
1007 hs_ep->next_desc = 0;
1008 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1009 dma_addr_t dma_addr = hs_req->req.dma;
1011 if (hs_req->req.num_sgs) {
1012 WARN_ON(hs_req->req.num_sgs > 1);
1013 dma_addr = sg_dma_address(hs_req->req.sg);
1015 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1016 hs_req->req.length);
1021 hs_ep->compl_desc = 0;
1022 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1023 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1025 /* write descriptor chain address to control register */
1026 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1028 ctrl = dwc2_readl(hsotg, depctl);
1029 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1030 dwc2_writel(hsotg, ctrl, depctl);
1033 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1034 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1035 struct dwc2_hsotg_ep *hs_ep,
1036 struct dwc2_hsotg_req *hs_req,
1040 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1041 * @hsotg: The controller state.
1042 * @hs_ep: The endpoint to process a request for
1043 * @hs_req: The request to start.
1044 * @continuing: True if we are doing more for the current request.
1046 * Start the given request running by setting the endpoint registers
1047 * appropriately, and writing any data to the FIFOs.
1049 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1050 struct dwc2_hsotg_ep *hs_ep,
1051 struct dwc2_hsotg_req *hs_req,
1054 struct usb_request *ureq = &hs_req->req;
1055 int index = hs_ep->index;
1056 int dir_in = hs_ep->dir_in;
1061 unsigned int length;
1062 unsigned int packets;
1063 unsigned int maxreq;
1064 unsigned int dma_reg;
1067 if (hs_ep->req && !continuing) {
1068 dev_err(hsotg->dev, "%s: active request\n", __func__);
1071 } else if (hs_ep->req != hs_req && continuing) {
1073 "%s: continue different req\n", __func__);
1079 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1080 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1081 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1083 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1084 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1085 hs_ep->dir_in ? "in" : "out");
1087 /* If endpoint is stalled, we will restart request later */
1088 ctrl = dwc2_readl(hsotg, epctrl_reg);
1090 if (index && ctrl & DXEPCTL_STALL) {
1091 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1095 length = ureq->length - ureq->actual;
1096 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1097 ureq->length, ureq->actual);
1099 if (!using_desc_dma(hsotg))
1100 maxreq = get_ep_limit(hs_ep);
1102 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1104 if (length > maxreq) {
1105 int round = maxreq % hs_ep->ep.maxpacket;
1107 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1108 __func__, length, maxreq, round);
1110 /* round down to multiple of packets */
1118 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1120 packets = 1; /* send one packet if length is zero. */
1122 if (dir_in && index != 0)
1123 if (hs_ep->isochronous)
1124 epsize = DXEPTSIZ_MC(packets);
1126 epsize = DXEPTSIZ_MC(1);
1131 * zero length packet should be programmed on its own and should not
1132 * be counted in DIEPTSIZ.PktCnt with other packets.
1134 if (dir_in && ureq->zero && !continuing) {
1135 /* Test if zlp is actually required. */
1136 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1137 !(ureq->length % hs_ep->ep.maxpacket))
1138 hs_ep->send_zlp = 1;
1141 epsize |= DXEPTSIZ_PKTCNT(packets);
1142 epsize |= DXEPTSIZ_XFERSIZE(length);
1144 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1145 __func__, packets, length, ureq->length, epsize, epsize_reg);
1147 /* store the request as the current one we're doing */
1148 hs_ep->req = hs_req;
1150 if (using_desc_dma(hsotg)) {
1152 u32 mps = hs_ep->ep.maxpacket;
1154 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1158 else if (length % mps)
1159 length += (mps - (length % mps));
1163 offset = ureq->actual;
1165 /* Fill DDMA chain entries */
1166 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1169 /* write descriptor chain address to control register */
1170 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1172 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1173 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1175 /* write size / packets */
1176 dwc2_writel(hsotg, epsize, epsize_reg);
1178 if (using_dma(hsotg) && !continuing && (length != 0)) {
1180 * write DMA address to control register, buffer
1181 * already synced by dwc2_hsotg_ep_queue().
1184 dwc2_writel(hsotg, ureq->dma, dma_reg);
1186 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1187 __func__, &ureq->dma, dma_reg);
1191 if (hs_ep->isochronous) {
1192 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1193 if (hs_ep->interval == 1) {
1194 if (hs_ep->target_frame & 0x1)
1195 ctrl |= DXEPCTL_SETODDFR;
1197 ctrl |= DXEPCTL_SETEVENFR;
1199 ctrl |= DXEPCTL_CNAK;
1201 hs_req->req.frame_number = hs_ep->target_frame;
1202 hs_req->req.actual = 0;
1203 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1208 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1210 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1212 /* For Setup request do not clear NAK */
1213 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1214 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1216 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1217 dwc2_writel(hsotg, ctrl, epctrl_reg);
1220 * set these, it seems that DMA support increments past the end
1221 * of the packet buffer so we need to calculate the length from
1224 hs_ep->size_loaded = length;
1225 hs_ep->last_load = ureq->actual;
1227 if (dir_in && !using_dma(hsotg)) {
1228 /* set these anyway, we may need them for non-periodic in */
1229 hs_ep->fifo_load = 0;
1231 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1235 * Note, trying to clear the NAK here causes problems with transmit
1236 * on the S3C6400 ending up with the TXFIFO becoming full.
1239 /* check ep is enabled */
1240 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1242 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1243 index, dwc2_readl(hsotg, epctrl_reg));
1245 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1246 __func__, dwc2_readl(hsotg, epctrl_reg));
1248 /* enable ep interrupts */
1249 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1253 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1254 * @hsotg: The device state.
1255 * @hs_ep: The endpoint the request is on.
1256 * @req: The request being processed.
1258 * We've been asked to queue a request, so ensure that the memory buffer
1259 * is correctly setup for DMA. If we've been passed an extant DMA address
1260 * then ensure the buffer has been synced to memory. If our buffer has no
1261 * DMA memory, then we map the memory and mark our request to allow us to
1262 * cleanup on completion.
1264 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1265 struct dwc2_hsotg_ep *hs_ep,
1266 struct usb_request *req)
1270 hs_ep->map_dir = hs_ep->dir_in;
1271 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1278 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1279 __func__, req->buf, req->length);
1284 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1285 struct dwc2_hsotg_ep *hs_ep,
1286 struct dwc2_hsotg_req *hs_req)
1288 void *req_buf = hs_req->req.buf;
1290 /* If dma is not being used or buffer is aligned */
1291 if (!using_dma(hsotg) || !((long)req_buf & 3))
1294 WARN_ON(hs_req->saved_req_buf);
1296 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1297 hs_ep->ep.name, req_buf, hs_req->req.length);
1299 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1300 if (!hs_req->req.buf) {
1301 hs_req->req.buf = req_buf;
1303 "%s: unable to allocate memory for bounce buffer\n",
1308 /* Save actual buffer */
1309 hs_req->saved_req_buf = req_buf;
1312 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1317 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1318 struct dwc2_hsotg_ep *hs_ep,
1319 struct dwc2_hsotg_req *hs_req)
1321 /* If dma is not being used or buffer was aligned */
1322 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1325 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1326 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1328 /* Copy data from bounce buffer on successful out transfer */
1329 if (!hs_ep->dir_in && !hs_req->req.status)
1330 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1331 hs_req->req.actual);
1333 /* Free bounce buffer */
1334 kfree(hs_req->req.buf);
1336 hs_req->req.buf = hs_req->saved_req_buf;
1337 hs_req->saved_req_buf = NULL;
1341 * dwc2_gadget_target_frame_elapsed - Checks target frame
1342 * @hs_ep: The driver endpoint to check
1344 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1345 * corresponding transfer.
1347 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1349 struct dwc2_hsotg *hsotg = hs_ep->parent;
1350 u32 target_frame = hs_ep->target_frame;
1351 u32 current_frame = hsotg->frame_number;
1352 bool frame_overrun = hs_ep->frame_overrun;
1353 u16 limit = DSTS_SOFFN_LIMIT;
1355 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1358 if (!frame_overrun && current_frame >= target_frame)
1361 if (frame_overrun && current_frame >= target_frame &&
1362 ((current_frame - target_frame) < limit / 2))
1369 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1370 * @hsotg: The driver state
1371 * @hs_ep: the ep descriptor chain is for
1373 * Called to update EP0 structure's pointers depend on stage of
1376 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1377 struct dwc2_hsotg_ep *hs_ep)
1379 switch (hsotg->ep0_state) {
1380 case DWC2_EP0_SETUP:
1381 case DWC2_EP0_STATUS_OUT:
1382 hs_ep->desc_list = hsotg->setup_desc[0];
1383 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1385 case DWC2_EP0_DATA_IN:
1386 case DWC2_EP0_STATUS_IN:
1387 hs_ep->desc_list = hsotg->ctrl_in_desc;
1388 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1390 case DWC2_EP0_DATA_OUT:
1391 hs_ep->desc_list = hsotg->ctrl_out_desc;
1392 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1395 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1403 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1406 struct dwc2_hsotg_req *hs_req = our_req(req);
1407 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1408 struct dwc2_hsotg *hs = hs_ep->parent;
1415 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1416 ep->name, req, req->length, req->buf, req->no_interrupt,
1417 req->zero, req->short_not_ok);
1419 /* Prevent new request submission when controller is suspended */
1420 if (hs->lx_state != DWC2_L0) {
1421 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1426 /* initialise status of the request */
1427 INIT_LIST_HEAD(&hs_req->queue);
1429 req->status = -EINPROGRESS;
1431 /* Don't queue ISOC request if length greater than mps*mc */
1432 if (hs_ep->isochronous &&
1433 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1434 dev_err(hs->dev, "req length > maxpacket*mc\n");
1438 /* In DDMA mode for ISOC's don't queue request if length greater
1439 * than descriptor limits.
1441 if (using_desc_dma(hs) && hs_ep->isochronous) {
1442 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1443 if (hs_ep->dir_in && req->length > maxsize) {
1444 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1445 req->length, maxsize);
1449 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1450 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1451 req->length, hs_ep->ep.maxpacket);
1456 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1460 /* if we're using DMA, sync the buffers as necessary */
1461 if (using_dma(hs)) {
1462 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1466 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1467 if (using_desc_dma(hs) && !hs_ep->index) {
1468 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1473 first = list_empty(&hs_ep->queue);
1474 list_add_tail(&hs_req->queue, &hs_ep->queue);
1477 * Handle DDMA isochronous transfers separately - just add new entry
1478 * to the descriptor chain.
1479 * Transfer will be started once SW gets either one of NAK or
1480 * OutTknEpDis interrupts.
1482 if (using_desc_dma(hs) && hs_ep->isochronous) {
1483 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1484 dma_addr_t dma_addr = hs_req->req.dma;
1486 if (hs_req->req.num_sgs) {
1487 WARN_ON(hs_req->req.num_sgs > 1);
1488 dma_addr = sg_dma_address(hs_req->req.sg);
1490 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1491 hs_req->req.length);
1496 /* Change EP direction if status phase request is after data out */
1497 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1498 hs->ep0_state == DWC2_EP0_DATA_OUT)
1502 if (!hs_ep->isochronous) {
1503 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1507 /* Update current frame number value. */
1508 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1509 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1510 dwc2_gadget_incr_frame_num(hs_ep);
1511 /* Update current frame number value once more as it
1514 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1517 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1518 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1523 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1526 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1527 struct dwc2_hsotg *hs = hs_ep->parent;
1528 unsigned long flags;
1531 spin_lock_irqsave(&hs->lock, flags);
1532 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1533 spin_unlock_irqrestore(&hs->lock, flags);
1538 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1539 struct usb_request *req)
1541 struct dwc2_hsotg_req *hs_req = our_req(req);
1547 * dwc2_hsotg_complete_oursetup - setup completion callback
1548 * @ep: The endpoint the request was on.
1549 * @req: The request completed.
1551 * Called on completion of any requests the driver itself
1552 * submitted that need cleaning up.
1554 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1555 struct usb_request *req)
1557 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1558 struct dwc2_hsotg *hsotg = hs_ep->parent;
1560 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1562 dwc2_hsotg_ep_free_request(ep, req);
1566 * ep_from_windex - convert control wIndex value to endpoint
1567 * @hsotg: The driver state.
1568 * @windex: The control request wIndex field (in host order).
1570 * Convert the given wIndex into a pointer to an driver endpoint
1571 * structure, or return NULL if it is not a valid endpoint.
1573 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1576 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1577 int idx = windex & 0x7F;
1579 if (windex >= 0x100)
1582 if (idx > hsotg->num_of_eps)
1585 return index_to_ep(hsotg, idx, dir);
1589 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1590 * @hsotg: The driver state.
1591 * @testmode: requested usb test mode
1592 * Enable usb Test Mode requested by the Host.
1594 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1596 int dctl = dwc2_readl(hsotg, DCTL);
1598 dctl &= ~DCTL_TSTCTL_MASK;
1602 case USB_TEST_SE0_NAK:
1603 case USB_TEST_PACKET:
1604 case USB_TEST_FORCE_ENABLE:
1605 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1610 dwc2_writel(hsotg, dctl, DCTL);
1615 * dwc2_hsotg_send_reply - send reply to control request
1616 * @hsotg: The device state
1618 * @buff: Buffer for request
1619 * @length: Length of reply.
1621 * Create a request and queue it on the given endpoint. This is useful as
1622 * an internal method of sending replies to certain control requests, etc.
1624 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1625 struct dwc2_hsotg_ep *ep,
1629 struct usb_request *req;
1632 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1634 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1635 hsotg->ep0_reply = req;
1637 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1641 req->buf = hsotg->ep0_buff;
1642 req->length = length;
1644 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1648 req->complete = dwc2_hsotg_complete_oursetup;
1651 memcpy(req->buf, buff, length);
1653 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1655 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1663 * dwc2_hsotg_process_req_status - process request GET_STATUS
1664 * @hsotg: The device state
1665 * @ctrl: USB control request
1667 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1668 struct usb_ctrlrequest *ctrl)
1670 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1671 struct dwc2_hsotg_ep *ep;
1676 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1679 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1683 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1684 case USB_RECIP_DEVICE:
1685 status = hsotg->gadget.is_selfpowered <<
1686 USB_DEVICE_SELF_POWERED;
1687 status |= hsotg->remote_wakeup_allowed <<
1688 USB_DEVICE_REMOTE_WAKEUP;
1689 reply = cpu_to_le16(status);
1692 case USB_RECIP_INTERFACE:
1693 /* currently, the data result should be zero */
1694 reply = cpu_to_le16(0);
1697 case USB_RECIP_ENDPOINT:
1698 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1702 reply = cpu_to_le16(ep->halted ? 1 : 0);
1709 if (le16_to_cpu(ctrl->wLength) != 2)
1712 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1714 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1721 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1724 * get_ep_head - return the first request on the endpoint
1725 * @hs_ep: The controller endpoint to get
1727 * Get the first request on the endpoint.
1729 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1731 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1736 * dwc2_gadget_start_next_request - Starts next request from ep queue
1737 * @hs_ep: Endpoint structure
1739 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1740 * in its handler. Hence we need to unmask it here to be able to do
1741 * resynchronization.
1743 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1745 struct dwc2_hsotg *hsotg = hs_ep->parent;
1746 int dir_in = hs_ep->dir_in;
1747 struct dwc2_hsotg_req *hs_req;
1749 if (!list_empty(&hs_ep->queue)) {
1750 hs_req = get_ep_head(hs_ep);
1751 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1754 if (!hs_ep->isochronous)
1758 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1761 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1767 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1768 * @hsotg: The device state
1769 * @ctrl: USB control request
1771 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1772 struct usb_ctrlrequest *ctrl)
1774 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1775 struct dwc2_hsotg_req *hs_req;
1776 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1777 struct dwc2_hsotg_ep *ep;
1784 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1785 __func__, set ? "SET" : "CLEAR");
1787 wValue = le16_to_cpu(ctrl->wValue);
1788 wIndex = le16_to_cpu(ctrl->wIndex);
1789 recip = ctrl->bRequestType & USB_RECIP_MASK;
1792 case USB_RECIP_DEVICE:
1794 case USB_DEVICE_REMOTE_WAKEUP:
1796 hsotg->remote_wakeup_allowed = 1;
1798 hsotg->remote_wakeup_allowed = 0;
1801 case USB_DEVICE_TEST_MODE:
1802 if ((wIndex & 0xff) != 0)
1807 hsotg->test_mode = wIndex >> 8;
1813 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1816 "%s: failed to send reply\n", __func__);
1821 case USB_RECIP_ENDPOINT:
1822 ep = ep_from_windex(hsotg, wIndex);
1824 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1830 case USB_ENDPOINT_HALT:
1831 halted = ep->halted;
1834 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1836 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1839 "%s: failed to send reply\n", __func__);
1844 * we have to complete all requests for ep if it was
1845 * halted, and the halt was cleared by CLEAR_FEATURE
1848 if (!set && halted) {
1850 * If we have request in progress,
1856 list_del_init(&hs_req->queue);
1857 if (hs_req->req.complete) {
1858 spin_unlock(&hsotg->lock);
1859 usb_gadget_giveback_request(
1860 &ep->ep, &hs_req->req);
1861 spin_lock(&hsotg->lock);
1865 /* If we have pending request, then start it */
1867 dwc2_gadget_start_next_request(ep);
1882 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1885 * dwc2_hsotg_stall_ep0 - stall ep0
1886 * @hsotg: The device state
1888 * Set stall for ep0 as response for setup request.
1890 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1892 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1896 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1897 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1900 * DxEPCTL_Stall will be cleared by EP once it has
1901 * taken effect, so no need to clear later.
1904 ctrl = dwc2_readl(hsotg, reg);
1905 ctrl |= DXEPCTL_STALL;
1906 ctrl |= DXEPCTL_CNAK;
1907 dwc2_writel(hsotg, ctrl, reg);
1910 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1911 ctrl, reg, dwc2_readl(hsotg, reg));
1914 * complete won't be called, so we enqueue
1915 * setup request here
1917 dwc2_hsotg_enqueue_setup(hsotg);
1921 * dwc2_hsotg_process_control - process a control request
1922 * @hsotg: The device state
1923 * @ctrl: The control request received
1925 * The controller has received the SETUP phase of a control request, and
1926 * needs to work out what to do next (and whether to pass it on to the
1929 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1930 struct usb_ctrlrequest *ctrl)
1932 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1937 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1938 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1939 ctrl->wIndex, ctrl->wLength);
1941 if (ctrl->wLength == 0) {
1943 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1944 } else if (ctrl->bRequestType & USB_DIR_IN) {
1946 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1949 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1952 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1953 switch (ctrl->bRequest) {
1954 case USB_REQ_SET_ADDRESS:
1955 hsotg->connected = 1;
1956 dcfg = dwc2_readl(hsotg, DCFG);
1957 dcfg &= ~DCFG_DEVADDR_MASK;
1958 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1959 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1960 dwc2_writel(hsotg, dcfg, DCFG);
1962 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1964 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1967 case USB_REQ_GET_STATUS:
1968 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1971 case USB_REQ_CLEAR_FEATURE:
1972 case USB_REQ_SET_FEATURE:
1973 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1978 /* as a fallback, try delivering it to the driver to deal with */
1980 if (ret == 0 && hsotg->driver) {
1981 spin_unlock(&hsotg->lock);
1982 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1983 spin_lock(&hsotg->lock);
1985 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1988 hsotg->delayed_status = false;
1989 if (ret == USB_GADGET_DELAYED_STATUS)
1990 hsotg->delayed_status = true;
1993 * the request is either unhandlable, or is not formatted correctly
1994 * so respond with a STALL for the status stage to indicate failure.
1998 dwc2_hsotg_stall_ep0(hsotg);
2002 * dwc2_hsotg_complete_setup - completion of a setup transfer
2003 * @ep: The endpoint the request was on.
2004 * @req: The request completed.
2006 * Called on completion of any requests the driver itself submitted for
2009 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2010 struct usb_request *req)
2012 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2013 struct dwc2_hsotg *hsotg = hs_ep->parent;
2015 if (req->status < 0) {
2016 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2020 spin_lock(&hsotg->lock);
2021 if (req->actual == 0)
2022 dwc2_hsotg_enqueue_setup(hsotg);
2024 dwc2_hsotg_process_control(hsotg, req->buf);
2025 spin_unlock(&hsotg->lock);
2029 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2030 * @hsotg: The device state.
2032 * Enqueue a request on EP0 if necessary to received any SETUP packets
2033 * received from the host.
2035 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2037 struct usb_request *req = hsotg->ctrl_req;
2038 struct dwc2_hsotg_req *hs_req = our_req(req);
2041 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2045 req->buf = hsotg->ctrl_buff;
2046 req->complete = dwc2_hsotg_complete_setup;
2048 if (!list_empty(&hs_req->queue)) {
2049 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2053 hsotg->eps_out[0]->dir_in = 0;
2054 hsotg->eps_out[0]->send_zlp = 0;
2055 hsotg->ep0_state = DWC2_EP0_SETUP;
2057 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2059 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2061 * Don't think there's much we can do other than watch the
2067 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2068 struct dwc2_hsotg_ep *hs_ep)
2071 u8 index = hs_ep->index;
2072 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2073 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2076 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2079 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2081 if (using_desc_dma(hsotg)) {
2082 /* Not specific buffer needed for ep0 ZLP */
2083 dma_addr_t dma = hs_ep->desc_list_dma;
2086 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2088 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2090 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2091 DXEPTSIZ_XFERSIZE(0),
2095 ctrl = dwc2_readl(hsotg, epctl_reg);
2096 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2097 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2098 ctrl |= DXEPCTL_USBACTEP;
2099 dwc2_writel(hsotg, ctrl, epctl_reg);
2103 * dwc2_hsotg_complete_request - complete a request given to us
2104 * @hsotg: The device state.
2105 * @hs_ep: The endpoint the request was on.
2106 * @hs_req: The request to complete.
2107 * @result: The result code (0 => Ok, otherwise errno)
2109 * The given request has finished, so call the necessary completion
2110 * if it has one and then look to see if we can start a new request
2113 * Note, expects the ep to already be locked as appropriate.
2115 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2116 struct dwc2_hsotg_ep *hs_ep,
2117 struct dwc2_hsotg_req *hs_req,
2121 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2125 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2126 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2129 * only replace the status if we've not already set an error
2130 * from a previous transaction
2133 if (hs_req->req.status == -EINPROGRESS)
2134 hs_req->req.status = result;
2136 if (using_dma(hsotg))
2137 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2139 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2142 list_del_init(&hs_req->queue);
2145 * call the complete request with the locks off, just in case the
2146 * request tries to queue more work for this endpoint.
2149 if (hs_req->req.complete) {
2150 spin_unlock(&hsotg->lock);
2151 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2152 spin_lock(&hsotg->lock);
2155 /* In DDMA don't need to proceed to starting of next ISOC request */
2156 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2160 * Look to see if there is anything else to do. Note, the completion
2161 * of the previous request may have caused a new request to be started
2162 * so be careful when doing this.
2165 if (!hs_ep->req && result >= 0)
2166 dwc2_gadget_start_next_request(hs_ep);
2170 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2171 * @hs_ep: The endpoint the request was on.
2173 * Get first request from the ep queue, determine descriptor on which complete
2174 * happened. SW discovers which descriptor currently in use by HW, adjusts
2175 * dma_address and calculates index of completed descriptor based on the value
2176 * of DEPDMA register. Update actual length of request, giveback to gadget.
2178 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2180 struct dwc2_hsotg *hsotg = hs_ep->parent;
2181 struct dwc2_hsotg_req *hs_req;
2182 struct usb_request *ureq;
2186 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2188 /* Process only descriptors with buffer status set to DMA done */
2189 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2190 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2192 hs_req = get_ep_head(hs_ep);
2194 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2197 ureq = &hs_req->req;
2199 /* Check completion status */
2200 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2202 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2203 DEV_DMA_ISOC_RX_NBYTES_MASK;
2204 ureq->actual = ureq->length - ((desc_sts & mask) >>
2205 DEV_DMA_ISOC_NBYTES_SHIFT);
2207 /* Adjust actual len for ISOC Out if len is
2210 if (!hs_ep->dir_in && ureq->length & 0x3)
2211 ureq->actual += 4 - (ureq->length & 0x3);
2213 /* Set actual frame number for completed transfers */
2214 ureq->frame_number =
2215 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2216 DEV_DMA_ISOC_FRNUM_SHIFT;
2219 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2221 hs_ep->compl_desc++;
2222 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2223 hs_ep->compl_desc = 0;
2224 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2229 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2230 * @hs_ep: The isochronous endpoint.
2232 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2233 * interrupt. Reset target frame and next_desc to allow to start
2234 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2235 * interrupt for OUT direction.
2237 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2239 struct dwc2_hsotg *hsotg = hs_ep->parent;
2242 dwc2_flush_rx_fifo(hsotg);
2243 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2245 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2246 hs_ep->next_desc = 0;
2247 hs_ep->compl_desc = 0;
2251 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2252 * @hsotg: The device state.
2253 * @ep_idx: The endpoint index for the data
2254 * @size: The size of data in the fifo, in bytes
2256 * The FIFO status shows there is data to read from the FIFO for a given
2257 * endpoint, so sort out whether we need to read the data into a request
2258 * that has been made for that endpoint.
2260 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2262 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2263 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2269 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2273 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2274 __func__, size, ep_idx, epctl);
2276 /* dump the data from the FIFO, we've nothing we can do */
2277 for (ptr = 0; ptr < size; ptr += 4)
2278 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2284 read_ptr = hs_req->req.actual;
2285 max_req = hs_req->req.length - read_ptr;
2287 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2288 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2290 if (to_read > max_req) {
2292 * more data appeared than we where willing
2293 * to deal with in this request.
2296 /* currently we don't deal this */
2300 hs_ep->total_data += to_read;
2301 hs_req->req.actual += to_read;
2302 to_read = DIV_ROUND_UP(to_read, 4);
2305 * note, we might over-write the buffer end by 3 bytes depending on
2306 * alignment of the data.
2308 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2309 hs_req->req.buf + read_ptr, to_read);
2313 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2314 * @hsotg: The device instance
2315 * @dir_in: If IN zlp
2317 * Generate a zero-length IN packet request for terminating a SETUP
2320 * Note, since we don't write any data to the TxFIFO, then it is
2321 * currently believed that we do not need to wait for any space in
2324 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2326 /* eps_out[0] is used in both directions */
2327 hsotg->eps_out[0]->dir_in = dir_in;
2328 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2330 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2334 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2335 * @hs_ep - The endpoint on which transfer went
2337 * Iterate over endpoints descriptor chain and get info on bytes remained
2338 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2340 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2342 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2343 struct dwc2_hsotg *hsotg = hs_ep->parent;
2344 unsigned int bytes_rem = 0;
2345 unsigned int bytes_rem_correction = 0;
2346 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2349 u32 mps = hs_ep->ep.maxpacket;
2350 int dir_in = hs_ep->dir_in;
2355 /* Interrupt OUT EP with mps not multiple of 4 */
2357 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2358 bytes_rem_correction = 4 - (mps % 4);
2360 for (i = 0; i < hs_ep->desc_count; ++i) {
2361 status = desc->status;
2362 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2363 bytes_rem -= bytes_rem_correction;
2365 if (status & DEV_DMA_STS_MASK)
2366 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2367 i, status & DEV_DMA_STS_MASK);
2369 if (status & DEV_DMA_L)
2379 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2380 * @hsotg: The device instance
2381 * @epnum: The endpoint received from
2383 * The RXFIFO has delivered an OutDone event, which means that the data
2384 * transfer for an OUT endpoint has been completed, either by a short
2385 * packet or by the finish of a transfer.
2387 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2389 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2390 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2391 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2392 struct usb_request *req = &hs_req->req;
2393 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2397 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2401 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2402 dev_dbg(hsotg->dev, "zlp packet received\n");
2403 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2404 dwc2_hsotg_enqueue_setup(hsotg);
2408 if (using_desc_dma(hsotg))
2409 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2411 if (using_dma(hsotg)) {
2412 unsigned int size_done;
2415 * Calculate the size of the transfer by checking how much
2416 * is left in the endpoint size register and then working it
2417 * out from the amount we loaded for the transfer.
2419 * We need to do this as DMA pointers are always 32bit aligned
2420 * so may overshoot/undershoot the transfer.
2423 size_done = hs_ep->size_loaded - size_left;
2424 size_done += hs_ep->last_load;
2426 req->actual = size_done;
2429 /* if there is more request to do, schedule new transfer */
2430 if (req->actual < req->length && size_left == 0) {
2431 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2435 if (req->actual < req->length && req->short_not_ok) {
2436 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2437 __func__, req->actual, req->length);
2440 * todo - what should we return here? there's no one else
2441 * even bothering to check the status.
2445 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2446 if (!using_desc_dma(hsotg) && epnum == 0 &&
2447 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2448 /* Move to STATUS IN */
2449 if (!hsotg->delayed_status)
2450 dwc2_hsotg_ep0_zlp(hsotg, true);
2453 /* Set actual frame number for completed transfers */
2454 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2455 req->frame_number = hs_ep->target_frame;
2456 dwc2_gadget_incr_frame_num(hs_ep);
2459 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2463 * dwc2_hsotg_handle_rx - RX FIFO has data
2464 * @hsotg: The device instance
2466 * The IRQ handler has detected that the RX FIFO has some data in it
2467 * that requires processing, so find out what is in there and do the
2470 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2471 * chunks, so if you have x packets received on an endpoint you'll get x
2472 * FIFO events delivered, each with a packet's worth of data in it.
2474 * When using DMA, we should not be processing events from the RXFIFO
2475 * as the actual data should be sent to the memory directly and we turn
2476 * on the completion interrupts to get notifications of transfer completion.
2478 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2480 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2481 u32 epnum, status, size;
2483 WARN_ON(using_dma(hsotg));
2485 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2486 status = grxstsr & GRXSTS_PKTSTS_MASK;
2488 size = grxstsr & GRXSTS_BYTECNT_MASK;
2489 size >>= GRXSTS_BYTECNT_SHIFT;
2491 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2492 __func__, grxstsr, size, epnum);
2494 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2495 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2496 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2499 case GRXSTS_PKTSTS_OUTDONE:
2500 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2501 dwc2_hsotg_read_frameno(hsotg));
2503 if (!using_dma(hsotg))
2504 dwc2_hsotg_handle_outdone(hsotg, epnum);
2507 case GRXSTS_PKTSTS_SETUPDONE:
2509 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2510 dwc2_hsotg_read_frameno(hsotg),
2511 dwc2_readl(hsotg, DOEPCTL(0)));
2513 * Call dwc2_hsotg_handle_outdone here if it was not called from
2514 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2515 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2517 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2518 dwc2_hsotg_handle_outdone(hsotg, epnum);
2521 case GRXSTS_PKTSTS_OUTRX:
2522 dwc2_hsotg_rx_data(hsotg, epnum, size);
2525 case GRXSTS_PKTSTS_SETUPRX:
2527 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2528 dwc2_hsotg_read_frameno(hsotg),
2529 dwc2_readl(hsotg, DOEPCTL(0)));
2531 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2533 dwc2_hsotg_rx_data(hsotg, epnum, size);
2537 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2540 dwc2_hsotg_dump(hsotg);
2546 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2547 * @mps: The maximum packet size in bytes.
2549 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2553 return D0EPCTL_MPS_64;
2555 return D0EPCTL_MPS_32;
2557 return D0EPCTL_MPS_16;
2559 return D0EPCTL_MPS_8;
2562 /* bad max packet size, warn and return invalid result */
2568 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2569 * @hsotg: The driver state.
2570 * @ep: The index number of the endpoint
2571 * @mps: The maximum packet size in bytes
2572 * @mc: The multicount value
2573 * @dir_in: True if direction is in.
2575 * Configure the maximum packet size for the given endpoint, updating
2576 * the hardware control registers to reflect this.
2578 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2579 unsigned int ep, unsigned int mps,
2580 unsigned int mc, unsigned int dir_in)
2582 struct dwc2_hsotg_ep *hs_ep;
2585 hs_ep = index_to_ep(hsotg, ep, dir_in);
2590 u32 mps_bytes = mps;
2592 /* EP0 is a special case */
2593 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2596 hs_ep->ep.maxpacket = mps_bytes;
2604 hs_ep->ep.maxpacket = mps;
2608 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2609 reg &= ~DXEPCTL_MPS_MASK;
2611 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2613 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2614 reg &= ~DXEPCTL_MPS_MASK;
2616 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2622 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2626 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2627 * @hsotg: The driver state
2628 * @idx: The index for the endpoint (0..15)
2630 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2632 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2635 /* wait until the fifo is flushed */
2636 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2637 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2642 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2643 * @hsotg: The driver state
2644 * @hs_ep: The driver endpoint to check.
2646 * Check to see if there is a request that has data to send, and if so
2647 * make an attempt to write data into the FIFO.
2649 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2650 struct dwc2_hsotg_ep *hs_ep)
2652 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2654 if (!hs_ep->dir_in || !hs_req) {
2656 * if request is not enqueued, we disable interrupts
2657 * for endpoints, excepting ep0
2659 if (hs_ep->index != 0)
2660 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2665 if (hs_req->req.actual < hs_req->req.length) {
2666 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2668 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2675 * dwc2_hsotg_complete_in - complete IN transfer
2676 * @hsotg: The device state.
2677 * @hs_ep: The endpoint that has just completed.
2679 * An IN transfer has been completed, update the transfer's state and then
2680 * call the relevant completion routines.
2682 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2683 struct dwc2_hsotg_ep *hs_ep)
2685 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2686 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2687 int size_left, size_done;
2690 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2694 /* Finish ZLP handling for IN EP0 transactions */
2695 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2696 dev_dbg(hsotg->dev, "zlp packet sent\n");
2699 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2700 * changed to IN. Change back to complete OUT transfer request
2704 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2705 if (hsotg->test_mode) {
2708 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2710 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2712 dwc2_hsotg_stall_ep0(hsotg);
2716 dwc2_hsotg_enqueue_setup(hsotg);
2721 * Calculate the size of the transfer by checking how much is left
2722 * in the endpoint size register and then working it out from
2723 * the amount we loaded for the transfer.
2725 * We do this even for DMA, as the transfer may have incremented
2726 * past the end of the buffer (DMA transfers are always 32bit
2729 if (using_desc_dma(hsotg)) {
2730 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2732 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2735 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2738 size_done = hs_ep->size_loaded - size_left;
2739 size_done += hs_ep->last_load;
2741 if (hs_req->req.actual != size_done)
2742 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2743 __func__, hs_req->req.actual, size_done);
2745 hs_req->req.actual = size_done;
2746 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2747 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2749 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2750 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2751 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2755 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2756 if (hs_ep->send_zlp) {
2757 hs_ep->send_zlp = 0;
2758 if (!using_desc_dma(hsotg)) {
2759 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2760 /* transfer will be completed on next complete interrupt */
2765 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2766 /* Move to STATUS OUT */
2767 dwc2_hsotg_ep0_zlp(hsotg, false);
2771 /* Set actual frame number for completed transfers */
2772 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2773 hs_req->req.frame_number = hs_ep->target_frame;
2774 dwc2_gadget_incr_frame_num(hs_ep);
2777 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2781 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2782 * @hsotg: The device state.
2783 * @idx: Index of ep.
2784 * @dir_in: Endpoint direction 1-in 0-out.
2786 * Reads for endpoint with given index and direction, by masking
2787 * epint_reg with coresponding mask.
2789 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2790 unsigned int idx, int dir_in)
2792 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2793 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2798 mask = dwc2_readl(hsotg, epmsk_reg);
2799 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2800 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2801 mask |= DXEPINT_SETUP_RCVD;
2803 ints = dwc2_readl(hsotg, epint_reg);
2809 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2810 * @hs_ep: The endpoint on which interrupt is asserted.
2812 * This interrupt indicates that the endpoint has been disabled per the
2813 * application's request.
2815 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2816 * in case of ISOC completes current request.
2818 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2819 * request starts it.
2821 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2823 struct dwc2_hsotg *hsotg = hs_ep->parent;
2824 struct dwc2_hsotg_req *hs_req;
2825 unsigned char idx = hs_ep->index;
2826 int dir_in = hs_ep->dir_in;
2827 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2828 int dctl = dwc2_readl(hsotg, DCTL);
2830 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2833 int epctl = dwc2_readl(hsotg, epctl_reg);
2835 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2837 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2838 int dctl = dwc2_readl(hsotg, DCTL);
2840 dctl |= DCTL_CGNPINNAK;
2841 dwc2_writel(hsotg, dctl, DCTL);
2845 if (dctl & DCTL_GOUTNAKSTS) {
2846 dctl |= DCTL_CGOUTNAK;
2847 dwc2_writel(hsotg, dctl, DCTL);
2851 if (!hs_ep->isochronous)
2854 if (list_empty(&hs_ep->queue)) {
2855 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2861 hs_req = get_ep_head(hs_ep);
2863 hs_req->req.frame_number = hs_ep->target_frame;
2864 hs_req->req.actual = 0;
2865 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2868 dwc2_gadget_incr_frame_num(hs_ep);
2869 /* Update current frame number value. */
2870 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2871 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2875 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2876 * @ep: The endpoint on which interrupt is asserted.
2878 * This is starting point for ISOC-OUT transfer, synchronization done with
2879 * first out token received from host while corresponding EP is disabled.
2881 * Device does not know initial frame in which out token will come. For this
2882 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2883 * getting this interrupt SW starts calculation for next transfer frame.
2885 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2887 struct dwc2_hsotg *hsotg = ep->parent;
2888 struct dwc2_hsotg_req *hs_req;
2889 int dir_in = ep->dir_in;
2891 if (dir_in || !ep->isochronous)
2894 if (using_desc_dma(hsotg)) {
2895 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2896 /* Start first ISO Out */
2897 ep->target_frame = hsotg->frame_number;
2898 dwc2_gadget_start_isoc_ddma(ep);
2903 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2906 ep->target_frame = hsotg->frame_number;
2907 if (ep->interval > 1) {
2908 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2909 if (ep->target_frame & 0x1)
2910 ctrl |= DXEPCTL_SETODDFR;
2912 ctrl |= DXEPCTL_SETEVENFR;
2914 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2918 while (dwc2_gadget_target_frame_elapsed(ep)) {
2919 hs_req = get_ep_head(ep);
2921 hs_req->req.frame_number = ep->target_frame;
2922 hs_req->req.actual = 0;
2923 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2926 dwc2_gadget_incr_frame_num(ep);
2927 /* Update current frame number value. */
2928 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2932 dwc2_gadget_start_next_request(ep);
2936 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2937 struct dwc2_hsotg_ep *hs_ep);
2940 * dwc2_gadget_handle_nak - handle NAK interrupt
2941 * @hs_ep: The endpoint on which interrupt is asserted.
2943 * This is starting point for ISOC-IN transfer, synchronization done with
2944 * first IN token received from host while corresponding EP is disabled.
2946 * Device does not know when first one token will arrive from host. On first
2947 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2948 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2949 * sent in response to that as there was no data in FIFO. SW is basing on this
2950 * interrupt to obtain frame in which token has come and then based on the
2951 * interval calculates next frame for transfer.
2953 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2955 struct dwc2_hsotg *hsotg = hs_ep->parent;
2956 struct dwc2_hsotg_req *hs_req;
2957 int dir_in = hs_ep->dir_in;
2960 if (!dir_in || !hs_ep->isochronous)
2963 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2965 if (using_desc_dma(hsotg)) {
2966 hs_ep->target_frame = hsotg->frame_number;
2967 dwc2_gadget_incr_frame_num(hs_ep);
2969 /* In service interval mode target_frame must
2970 * be set to last (u)frame of the service interval.
2972 if (hsotg->params.service_interval) {
2973 /* Set target_frame to the first (u)frame of
2974 * the service interval
2976 hs_ep->target_frame &= ~hs_ep->interval + 1;
2978 /* Set target_frame to the last (u)frame of
2979 * the service interval
2981 dwc2_gadget_incr_frame_num(hs_ep);
2982 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2985 dwc2_gadget_start_isoc_ddma(hs_ep);
2989 hs_ep->target_frame = hsotg->frame_number;
2990 if (hs_ep->interval > 1) {
2991 u32 ctrl = dwc2_readl(hsotg,
2992 DIEPCTL(hs_ep->index));
2993 if (hs_ep->target_frame & 0x1)
2994 ctrl |= DXEPCTL_SETODDFR;
2996 ctrl |= DXEPCTL_SETEVENFR;
2998 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
3002 if (using_desc_dma(hsotg))
3005 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3006 if (ctrl & DXEPCTL_EPENA)
3007 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3009 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3011 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3012 hs_req = get_ep_head(hs_ep);
3014 hs_req->req.frame_number = hs_ep->target_frame;
3015 hs_req->req.actual = 0;
3016 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3019 dwc2_gadget_incr_frame_num(hs_ep);
3020 /* Update current frame number value. */
3021 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3025 dwc2_gadget_start_next_request(hs_ep);
3029 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3030 * @hsotg: The driver state
3031 * @idx: The index for the endpoint (0..15)
3032 * @dir_in: Set if this is an IN endpoint
3034 * Process and clear any interrupt pending for an individual endpoint
3036 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3039 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3040 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3041 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3042 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3045 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3047 /* Clear endpoint interrupts */
3048 dwc2_writel(hsotg, ints, epint_reg);
3051 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3052 __func__, idx, dir_in ? "in" : "out");
3056 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3057 __func__, idx, dir_in ? "in" : "out", ints);
3059 /* Don't process XferCompl interrupt if it is a setup packet */
3060 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3061 ints &= ~DXEPINT_XFERCOMPL;
3064 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3065 * stage and xfercomplete was generated without SETUP phase done
3066 * interrupt. SW should parse received setup packet only after host's
3067 * exit from setup phase of control transfer.
3069 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3070 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3071 ints &= ~DXEPINT_XFERCOMPL;
3073 if (ints & DXEPINT_XFERCOMPL) {
3075 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3076 __func__, dwc2_readl(hsotg, epctl_reg),
3077 dwc2_readl(hsotg, epsiz_reg));
3079 /* In DDMA handle isochronous requests separately */
3080 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3081 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3082 } else if (dir_in) {
3084 * We get OutDone from the FIFO, so we only
3085 * need to look at completing IN requests here
3086 * if operating slave mode
3088 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3089 dwc2_hsotg_complete_in(hsotg, hs_ep);
3091 if (idx == 0 && !hs_ep->req)
3092 dwc2_hsotg_enqueue_setup(hsotg);
3093 } else if (using_dma(hsotg)) {
3095 * We're using DMA, we need to fire an OutDone here
3096 * as we ignore the RXFIFO.
3098 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3099 dwc2_hsotg_handle_outdone(hsotg, idx);
3103 if (ints & DXEPINT_EPDISBLD)
3104 dwc2_gadget_handle_ep_disabled(hs_ep);
3106 if (ints & DXEPINT_OUTTKNEPDIS)
3107 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3109 if (ints & DXEPINT_NAKINTRPT)
3110 dwc2_gadget_handle_nak(hs_ep);
3112 if (ints & DXEPINT_AHBERR)
3113 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3115 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3116 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3118 if (using_dma(hsotg) && idx == 0) {
3120 * this is the notification we've received a
3121 * setup packet. In non-DMA mode we'd get this
3122 * from the RXFIFO, instead we need to process
3129 dwc2_hsotg_handle_outdone(hsotg, 0);
3133 if (ints & DXEPINT_STSPHSERCVD) {
3134 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3136 /* Safety check EP0 state when STSPHSERCVD asserted */
3137 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3138 /* Move to STATUS IN for DDMA */
3139 if (using_desc_dma(hsotg)) {
3140 if (!hsotg->delayed_status)
3141 dwc2_hsotg_ep0_zlp(hsotg, true);
3143 /* In case of 3 stage Control Write with delayed
3144 * status, when Status IN transfer started
3145 * before STSPHSERCVD asserted, NAKSTS bit not
3146 * cleared by CNAK in dwc2_hsotg_start_req()
3147 * function. Clear now NAKSTS to allow complete
3150 dwc2_set_bit(hsotg, DIEPCTL(0),
3157 if (ints & DXEPINT_BACK2BACKSETUP)
3158 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3160 if (ints & DXEPINT_BNAINTR) {
3161 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3162 if (hs_ep->isochronous)
3163 dwc2_gadget_handle_isoc_bna(hs_ep);
3166 if (dir_in && !hs_ep->isochronous) {
3167 /* not sure if this is important, but we'll clear it anyway */
3168 if (ints & DXEPINT_INTKNTXFEMP) {
3169 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3173 /* this probably means something bad is happening */
3174 if (ints & DXEPINT_INTKNEPMIS) {
3175 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3179 /* FIFO has space or is empty (see GAHBCFG) */
3180 if (hsotg->dedicated_fifos &&
3181 ints & DXEPINT_TXFEMP) {
3182 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3184 if (!using_dma(hsotg))
3185 dwc2_hsotg_trytx(hsotg, hs_ep);
3191 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3192 * @hsotg: The device state.
3194 * Handle updating the device settings after the enumeration phase has
3197 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3199 u32 dsts = dwc2_readl(hsotg, DSTS);
3200 int ep0_mps = 0, ep_mps = 8;
3203 * This should signal the finish of the enumeration phase
3204 * of the USB handshaking, so we should now know what rate
3208 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3211 * note, since we're limited by the size of transfer on EP0, and
3212 * it seems IN transfers must be a even number of packets we do
3213 * not advertise a 64byte MPS on EP0.
3216 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3217 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3218 case DSTS_ENUMSPD_FS:
3219 case DSTS_ENUMSPD_FS48:
3220 hsotg->gadget.speed = USB_SPEED_FULL;
3221 ep0_mps = EP0_MPS_LIMIT;
3225 case DSTS_ENUMSPD_HS:
3226 hsotg->gadget.speed = USB_SPEED_HIGH;
3227 ep0_mps = EP0_MPS_LIMIT;
3231 case DSTS_ENUMSPD_LS:
3232 hsotg->gadget.speed = USB_SPEED_LOW;
3236 * note, we don't actually support LS in this driver at the
3237 * moment, and the documentation seems to imply that it isn't
3238 * supported by the PHYs on some of the devices.
3242 dev_info(hsotg->dev, "new device is %s\n",
3243 usb_speed_string(hsotg->gadget.speed));
3246 * we should now know the maximum packet size for an
3247 * endpoint, so set the endpoints to a default value.
3252 /* Initialize ep0 for both in and out directions */
3253 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3254 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3255 for (i = 1; i < hsotg->num_of_eps; i++) {
3256 if (hsotg->eps_in[i])
3257 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3259 if (hsotg->eps_out[i])
3260 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3265 /* ensure after enumeration our EP0 is active */
3267 dwc2_hsotg_enqueue_setup(hsotg);
3269 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3270 dwc2_readl(hsotg, DIEPCTL0),
3271 dwc2_readl(hsotg, DOEPCTL0));
3275 * kill_all_requests - remove all requests from the endpoint's queue
3276 * @hsotg: The device state.
3277 * @ep: The endpoint the requests may be on.
3278 * @result: The result code to use.
3280 * Go through the requests on the given endpoint and mark them
3281 * completed with the given result code.
3283 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3284 struct dwc2_hsotg_ep *ep,
3291 while (!list_empty(&ep->queue)) {
3292 struct dwc2_hsotg_req *req = get_ep_head(ep);
3294 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3297 if (!hsotg->dedicated_fifos)
3299 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3300 if (size < ep->fifo_size)
3301 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3305 * dwc2_hsotg_disconnect - disconnect service
3306 * @hsotg: The device state.
3308 * The device has been disconnected. Remove all current
3309 * transactions and signal the gadget driver that this
3312 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3316 if (!hsotg->connected)
3319 hsotg->connected = 0;
3320 hsotg->test_mode = 0;
3322 /* all endpoints should be shutdown */
3323 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3324 if (hsotg->eps_in[ep])
3325 kill_all_requests(hsotg, hsotg->eps_in[ep],
3327 if (hsotg->eps_out[ep])
3328 kill_all_requests(hsotg, hsotg->eps_out[ep],
3332 call_gadget(hsotg, disconnect);
3333 hsotg->lx_state = DWC2_L3;
3335 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3339 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3340 * @hsotg: The device state:
3341 * @periodic: True if this is a periodic FIFO interrupt
3343 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3345 struct dwc2_hsotg_ep *ep;
3348 /* look through for any more data to transmit */
3349 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3350 ep = index_to_ep(hsotg, epno, 1);
3358 if ((periodic && !ep->periodic) ||
3359 (!periodic && ep->periodic))
3362 ret = dwc2_hsotg_trytx(hsotg, ep);
3368 /* IRQ flags which will trigger a retry around the IRQ loop */
3369 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3373 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3375 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3376 * @hsotg: The device state
3377 * @is_usb_reset: Usb resetting flag
3379 * Issue a soft reset to the core, and await the core finishing it.
3381 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3390 /* Kill any ep0 requests as controller will be reinitialized */
3391 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3393 if (!is_usb_reset) {
3394 if (dwc2_core_reset(hsotg, true))
3397 /* all endpoints should be shutdown */
3398 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3399 if (hsotg->eps_in[ep])
3400 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3401 if (hsotg->eps_out[ep])
3402 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3407 * we must now enable ep0 ready for host detection and then
3408 * set configuration.
3411 /* keep other bits untouched (so e.g. forced modes are not lost) */
3412 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3413 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3414 usbcfg |= GUSBCFG_TOUTCAL(7);
3416 /* remove the HNP/SRP and set the PHY */
3417 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3418 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3420 dwc2_phy_init(hsotg, true);
3422 dwc2_hsotg_init_fifo(hsotg);
3425 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3427 dcfg |= DCFG_EPMISCNT(1);
3429 switch (hsotg->params.speed) {
3430 case DWC2_SPEED_PARAM_LOW:
3431 dcfg |= DCFG_DEVSPD_LS;
3433 case DWC2_SPEED_PARAM_FULL:
3434 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3435 dcfg |= DCFG_DEVSPD_FS48;
3437 dcfg |= DCFG_DEVSPD_FS;
3440 dcfg |= DCFG_DEVSPD_HS;
3443 if (hsotg->params.ipg_isoc_en)
3444 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3446 dwc2_writel(hsotg, dcfg, DCFG);
3448 /* Clear any pending OTG interrupts */
3449 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3451 /* Clear any pending interrupts */
3452 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3453 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3454 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3455 GINTSTS_USBRST | GINTSTS_RESETDET |
3456 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3457 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3458 GINTSTS_LPMTRANRCVD;
3460 if (!using_desc_dma(hsotg))
3461 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3463 if (!hsotg->params.external_id_pin_ctl)
3464 intmsk |= GINTSTS_CONIDSTSCHNG;
3466 dwc2_writel(hsotg, intmsk, GINTMSK);
3468 if (using_dma(hsotg)) {
3469 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3470 hsotg->params.ahbcfg,
3473 /* Set DDMA mode support in the core if needed */
3474 if (using_desc_dma(hsotg))
3475 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3478 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3479 (GAHBCFG_NP_TXF_EMP_LVL |
3480 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3481 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3485 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3486 * when we have no data to transfer. Otherwise we get being flooded by
3490 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3491 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3492 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3493 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3497 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3498 * DMA mode we may need this and StsPhseRcvd.
3500 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3501 DOEPMSK_STSPHSERCVDMSK) : 0) |
3502 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3506 /* Enable BNA interrupt for DDMA */
3507 if (using_desc_dma(hsotg)) {
3508 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3509 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3512 /* Enable Service Interval mode if supported */
3513 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3514 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3516 dwc2_writel(hsotg, 0, DAINTMSK);
3518 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3519 dwc2_readl(hsotg, DIEPCTL0),
3520 dwc2_readl(hsotg, DOEPCTL0));
3522 /* enable in and out endpoint interrupts */
3523 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3526 * Enable the RXFIFO when in slave mode, as this is how we collect
3527 * the data. In DMA mode, we get events from the FIFO but also
3528 * things we cannot process, so do not use it.
3530 if (!using_dma(hsotg))
3531 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3533 /* Enable interrupts for EP0 in and out */
3534 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3535 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3537 if (!is_usb_reset) {
3538 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3539 udelay(10); /* see openiboot */
3540 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3543 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3546 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3547 * writing to the EPCTL register..
3550 /* set to read 1 8byte packet */
3551 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3552 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3554 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3555 DXEPCTL_CNAK | DXEPCTL_EPENA |
3559 /* enable, but don't activate EP0in */
3560 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3561 DXEPCTL_USBACTEP, DIEPCTL0);
3563 /* clear global NAKs */
3564 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3566 val |= DCTL_SFTDISCON;
3567 dwc2_set_bit(hsotg, DCTL, val);
3569 /* configure the core to support LPM */
3570 dwc2_gadget_init_lpm(hsotg);
3572 /* program GREFCLK register if needed */
3573 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3574 dwc2_gadget_program_ref_clk(hsotg);
3576 /* must be at-least 3ms to allow bus to see disconnect */
3579 hsotg->lx_state = DWC2_L0;
3581 dwc2_hsotg_enqueue_setup(hsotg);
3583 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3584 dwc2_readl(hsotg, DIEPCTL0),
3585 dwc2_readl(hsotg, DOEPCTL0));
3588 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3590 /* set the soft-disconnect bit */
3591 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3594 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3596 /* remove the soft-disconnect and let's go */
3597 if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3598 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3602 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3603 * @hsotg: The device state:
3605 * This interrupt indicates one of the following conditions occurred while
3606 * transmitting an ISOC transaction.
3607 * - Corrupted IN Token for ISOC EP.
3608 * - Packet not complete in FIFO.
3610 * The following actions will be taken:
3611 * - Determine the EP
3612 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3614 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3616 struct dwc2_hsotg_ep *hs_ep;
3621 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3623 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3625 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3626 hs_ep = hsotg->eps_in[idx];
3627 /* Proceed only unmasked ISOC EPs */
3628 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3631 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3632 if ((epctrl & DXEPCTL_EPENA) &&
3633 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3634 epctrl |= DXEPCTL_SNAK;
3635 epctrl |= DXEPCTL_EPDIS;
3636 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3640 /* Clear interrupt */
3641 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3645 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3646 * @hsotg: The device state:
3648 * This interrupt indicates one of the following conditions occurred while
3649 * transmitting an ISOC transaction.
3650 * - Corrupted OUT Token for ISOC EP.
3651 * - Packet not complete in FIFO.
3653 * The following actions will be taken:
3654 * - Determine the EP
3655 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3657 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3663 struct dwc2_hsotg_ep *hs_ep;
3666 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3668 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3669 daintmsk >>= DAINT_OUTEP_SHIFT;
3671 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3672 hs_ep = hsotg->eps_out[idx];
3673 /* Proceed only unmasked ISOC EPs */
3674 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3677 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3678 if ((epctrl & DXEPCTL_EPENA) &&
3679 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3680 /* Unmask GOUTNAKEFF interrupt */
3681 gintmsk = dwc2_readl(hsotg, GINTMSK);
3682 gintmsk |= GINTSTS_GOUTNAKEFF;
3683 dwc2_writel(hsotg, gintmsk, GINTMSK);
3685 gintsts = dwc2_readl(hsotg, GINTSTS);
3686 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3687 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3693 /* Clear interrupt */
3694 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3698 * dwc2_hsotg_irq - handle device interrupt
3699 * @irq: The IRQ number triggered
3700 * @pw: The pw value when registered the handler.
3702 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3704 struct dwc2_hsotg *hsotg = pw;
3705 int retry_count = 8;
3709 if (!dwc2_is_device_mode(hsotg))
3712 spin_lock(&hsotg->lock);
3714 gintsts = dwc2_readl(hsotg, GINTSTS);
3715 gintmsk = dwc2_readl(hsotg, GINTMSK);
3717 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3718 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3722 if (gintsts & GINTSTS_RESETDET) {
3723 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3725 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3727 /* This event must be used only if controller is suspended */
3728 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3729 dwc2_exit_partial_power_down(hsotg, 0, true);
3731 hsotg->lx_state = DWC2_L0;
3734 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3735 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3736 u32 connected = hsotg->connected;
3738 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3739 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3740 dwc2_readl(hsotg, GNPTXSTS));
3742 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3744 /* Report disconnection if it is not already done. */
3745 dwc2_hsotg_disconnect(hsotg);
3747 /* Reset device address to zero */
3748 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3750 if (usb_status & GOTGCTL_BSESVLD && connected)
3751 dwc2_hsotg_core_init_disconnected(hsotg, true);
3754 if (gintsts & GINTSTS_ENUMDONE) {
3755 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3757 dwc2_hsotg_irq_enumdone(hsotg);
3760 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3761 u32 daint = dwc2_readl(hsotg, DAINT);
3762 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3763 u32 daint_out, daint_in;
3767 daint_out = daint >> DAINT_OUTEP_SHIFT;
3768 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3770 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3772 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3773 ep++, daint_out >>= 1) {
3775 dwc2_hsotg_epint(hsotg, ep, 0);
3778 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3779 ep++, daint_in >>= 1) {
3781 dwc2_hsotg_epint(hsotg, ep, 1);
3785 /* check both FIFOs */
3787 if (gintsts & GINTSTS_NPTXFEMP) {
3788 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3791 * Disable the interrupt to stop it happening again
3792 * unless one of these endpoint routines decides that
3793 * it needs re-enabling
3796 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3797 dwc2_hsotg_irq_fifoempty(hsotg, false);
3800 if (gintsts & GINTSTS_PTXFEMP) {
3801 dev_dbg(hsotg->dev, "PTxFEmp\n");
3803 /* See note in GINTSTS_NPTxFEmp */
3805 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3806 dwc2_hsotg_irq_fifoempty(hsotg, true);
3809 if (gintsts & GINTSTS_RXFLVL) {
3811 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3812 * we need to retry dwc2_hsotg_handle_rx if this is still
3816 dwc2_hsotg_handle_rx(hsotg);
3819 if (gintsts & GINTSTS_ERLYSUSP) {
3820 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3821 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3825 * these next two seem to crop-up occasionally causing the core
3826 * to shutdown the USB transfer, so try clearing them and logging
3830 if (gintsts & GINTSTS_GOUTNAKEFF) {
3835 struct dwc2_hsotg_ep *hs_ep;
3837 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3838 daintmsk >>= DAINT_OUTEP_SHIFT;
3839 /* Mask this interrupt */
3840 gintmsk = dwc2_readl(hsotg, GINTMSK);
3841 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3842 dwc2_writel(hsotg, gintmsk, GINTMSK);
3844 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3845 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3846 hs_ep = hsotg->eps_out[idx];
3847 /* Proceed only unmasked ISOC EPs */
3848 if (BIT(idx) & ~daintmsk)
3851 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3854 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3855 epctrl |= DXEPCTL_SNAK;
3856 epctrl |= DXEPCTL_EPDIS;
3857 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3862 if (hs_ep->halted) {
3863 if (!(epctrl & DXEPCTL_EPENA))
3864 epctrl |= DXEPCTL_EPENA;
3865 epctrl |= DXEPCTL_EPDIS;
3866 epctrl |= DXEPCTL_STALL;
3867 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3871 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3874 if (gintsts & GINTSTS_GINNAKEFF) {
3875 dev_info(hsotg->dev, "GINNakEff triggered\n");
3877 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3879 dwc2_hsotg_dump(hsotg);
3882 if (gintsts & GINTSTS_INCOMPL_SOIN)
3883 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3885 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3886 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3889 * if we've had fifo events, we should try and go around the
3890 * loop again to see if there's any point in returning yet.
3893 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3896 /* Check WKUP_ALERT interrupt*/
3897 if (hsotg->params.service_interval)
3898 dwc2_gadget_wkup_alert_handler(hsotg);
3900 spin_unlock(&hsotg->lock);
3905 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3906 struct dwc2_hsotg_ep *hs_ep)
3911 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3912 DOEPCTL(hs_ep->index);
3913 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3914 DOEPINT(hs_ep->index);
3916 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3919 if (hs_ep->dir_in) {
3920 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3921 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3922 /* Wait for Nak effect */
3923 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3924 DXEPINT_INEPNAKEFF, 100))
3925 dev_warn(hsotg->dev,
3926 "%s: timeout DIEPINT.NAKEFF\n",
3929 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3930 /* Wait for Nak effect */
3931 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3932 GINTSTS_GINNAKEFF, 100))
3933 dev_warn(hsotg->dev,
3934 "%s: timeout GINTSTS.GINNAKEFF\n",
3938 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3939 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3941 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3942 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3944 if (!using_dma(hsotg)) {
3945 /* Wait for GINTSTS_RXFLVL interrupt */
3946 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3947 GINTSTS_RXFLVL, 100)) {
3948 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3952 * Pop GLOBAL OUT NAK status packet from RxFIFO
3953 * to assert GOUTNAKEFF interrupt
3955 dwc2_readl(hsotg, GRXSTSP);
3959 /* Wait for global nak to take effect */
3960 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3961 GINTSTS_GOUTNAKEFF, 100))
3962 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3967 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3969 /* Wait for ep to be disabled */
3970 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3971 dev_warn(hsotg->dev,
3972 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3974 /* Clear EPDISBLD interrupt */
3975 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3977 if (hs_ep->dir_in) {
3978 unsigned short fifo_index;
3980 if (hsotg->dedicated_fifos || hs_ep->periodic)
3981 fifo_index = hs_ep->fifo_index;
3986 dwc2_flush_tx_fifo(hsotg, fifo_index);
3988 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3989 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3990 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3993 /* Remove global NAKs */
3994 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3999 * dwc2_hsotg_ep_enable - enable the given endpoint
4000 * @ep: The USB endpint to configure
4001 * @desc: The USB endpoint descriptor to configure with.
4003 * This is called from the USB gadget code's usb_ep_enable().
4005 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
4006 const struct usb_endpoint_descriptor *desc)
4008 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4009 struct dwc2_hsotg *hsotg = hs_ep->parent;
4010 unsigned long flags;
4011 unsigned int index = hs_ep->index;
4017 unsigned int dir_in;
4018 unsigned int i, val, size;
4020 unsigned char ep_type;
4024 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4025 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4026 desc->wMaxPacketSize, desc->bInterval);
4028 /* not to be called for EP0 */
4030 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4034 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4035 if (dir_in != hs_ep->dir_in) {
4036 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4040 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4041 mps = usb_endpoint_maxp(desc);
4042 mc = usb_endpoint_maxp_mult(desc);
4044 /* ISOC IN in DDMA supported bInterval up to 10 */
4045 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4046 dir_in && desc->bInterval > 10) {
4048 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4052 /* High bandwidth ISOC OUT in DDMA not supported */
4053 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4054 !dir_in && mc > 1) {
4056 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4060 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4062 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4063 epctrl = dwc2_readl(hsotg, epctrl_reg);
4065 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4066 __func__, epctrl, epctrl_reg);
4068 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4069 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4071 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4073 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4074 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4075 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4076 desc_num * sizeof(struct dwc2_dma_desc),
4077 &hs_ep->desc_list_dma, GFP_ATOMIC);
4078 if (!hs_ep->desc_list) {
4084 spin_lock_irqsave(&hsotg->lock, flags);
4086 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4087 epctrl |= DXEPCTL_MPS(mps);
4090 * mark the endpoint as active, otherwise the core may ignore
4091 * transactions entirely for this endpoint
4093 epctrl |= DXEPCTL_USBACTEP;
4095 /* update the endpoint state */
4096 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4098 /* default, set to non-periodic */
4099 hs_ep->isochronous = 0;
4100 hs_ep->periodic = 0;
4103 hs_ep->interval = desc->bInterval;
4106 case USB_ENDPOINT_XFER_ISOC:
4107 epctrl |= DXEPCTL_EPTYPE_ISO;
4108 epctrl |= DXEPCTL_SETEVENFR;
4109 hs_ep->isochronous = 1;
4110 hs_ep->interval = 1 << (desc->bInterval - 1);
4111 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4112 hs_ep->next_desc = 0;
4113 hs_ep->compl_desc = 0;
4115 hs_ep->periodic = 1;
4116 mask = dwc2_readl(hsotg, DIEPMSK);
4117 mask |= DIEPMSK_NAKMSK;
4118 dwc2_writel(hsotg, mask, DIEPMSK);
4120 epctrl |= DXEPCTL_SNAK;
4121 mask = dwc2_readl(hsotg, DOEPMSK);
4122 mask |= DOEPMSK_OUTTKNEPDISMSK;
4123 dwc2_writel(hsotg, mask, DOEPMSK);
4127 case USB_ENDPOINT_XFER_BULK:
4128 epctrl |= DXEPCTL_EPTYPE_BULK;
4131 case USB_ENDPOINT_XFER_INT:
4133 hs_ep->periodic = 1;
4135 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4136 hs_ep->interval = 1 << (desc->bInterval - 1);
4138 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4141 case USB_ENDPOINT_XFER_CONTROL:
4142 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4147 * if the hardware has dedicated fifos, we must give each IN EP
4148 * a unique tx-fifo even if it is non-periodic.
4150 if (dir_in && hsotg->dedicated_fifos) {
4151 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4153 u32 fifo_size = UINT_MAX;
4155 size = hs_ep->ep.maxpacket * hs_ep->mc;
4156 for (i = 1; i <= fifo_count; ++i) {
4157 if (hsotg->fifo_map & (1 << i))
4159 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4160 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4163 /* Search for smallest acceptable fifo */
4164 if (val < fifo_size) {
4171 "%s: No suitable fifo found\n", __func__);
4175 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4176 hsotg->fifo_map |= 1 << fifo_index;
4177 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4178 hs_ep->fifo_index = fifo_index;
4179 hs_ep->fifo_size = fifo_size;
4182 /* for non control endpoints, set PID to D0 */
4183 if (index && !hs_ep->isochronous)
4184 epctrl |= DXEPCTL_SETD0PID;
4186 /* WA for Full speed ISOC IN in DDMA mode.
4187 * By Clear NAK status of EP, core will send ZLP
4188 * to IN token and assert NAK interrupt relying
4189 * on TxFIFO status only
4192 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4193 hs_ep->isochronous && dir_in) {
4194 /* The WA applies only to core versions from 2.72a
4195 * to 4.00a (including both). Also for FS_IOT_1.00a
4198 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4200 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4201 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4202 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4203 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4204 epctrl |= DXEPCTL_CNAK;
4207 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4210 dwc2_writel(hsotg, epctrl, epctrl_reg);
4211 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4212 __func__, dwc2_readl(hsotg, epctrl_reg));
4214 /* enable the endpoint interrupt */
4215 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4218 spin_unlock_irqrestore(&hsotg->lock, flags);
4221 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4222 dmam_free_coherent(hsotg->dev, desc_num *
4223 sizeof(struct dwc2_dma_desc),
4224 hs_ep->desc_list, hs_ep->desc_list_dma);
4225 hs_ep->desc_list = NULL;
4232 * dwc2_hsotg_ep_disable - disable given endpoint
4233 * @ep: The endpoint to disable.
4235 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4237 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4238 struct dwc2_hsotg *hsotg = hs_ep->parent;
4239 int dir_in = hs_ep->dir_in;
4240 int index = hs_ep->index;
4244 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4246 if (ep == &hsotg->eps_out[0]->ep) {
4247 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4251 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4252 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4256 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4258 ctrl = dwc2_readl(hsotg, epctrl_reg);
4260 if (ctrl & DXEPCTL_EPENA)
4261 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4263 ctrl &= ~DXEPCTL_EPENA;
4264 ctrl &= ~DXEPCTL_USBACTEP;
4265 ctrl |= DXEPCTL_SNAK;
4267 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4268 dwc2_writel(hsotg, ctrl, epctrl_reg);
4270 /* disable endpoint interrupts */
4271 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4273 /* terminate all requests with shutdown */
4274 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4276 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4277 hs_ep->fifo_index = 0;
4278 hs_ep->fifo_size = 0;
4283 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4285 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4286 struct dwc2_hsotg *hsotg = hs_ep->parent;
4287 unsigned long flags;
4290 spin_lock_irqsave(&hsotg->lock, flags);
4291 ret = dwc2_hsotg_ep_disable(ep);
4292 spin_unlock_irqrestore(&hsotg->lock, flags);
4297 * on_list - check request is on the given endpoint
4298 * @ep: The endpoint to check.
4299 * @test: The request to test if it is on the endpoint.
4301 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4303 struct dwc2_hsotg_req *req, *treq;
4305 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4314 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4315 * @ep: The endpoint to dequeue.
4316 * @req: The request to be removed from a queue.
4318 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4320 struct dwc2_hsotg_req *hs_req = our_req(req);
4321 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4322 struct dwc2_hsotg *hs = hs_ep->parent;
4323 unsigned long flags;
4325 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4327 spin_lock_irqsave(&hs->lock, flags);
4329 if (!on_list(hs_ep, hs_req)) {
4330 spin_unlock_irqrestore(&hs->lock, flags);
4334 /* Dequeue already started request */
4335 if (req == &hs_ep->req->req)
4336 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4338 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4339 spin_unlock_irqrestore(&hs->lock, flags);
4345 * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
4346 * @ep: The endpoint to be wedged.
4349 static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
4351 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4352 struct dwc2_hsotg *hs = hs_ep->parent;
4354 unsigned long flags;
4357 spin_lock_irqsave(&hs->lock, flags);
4359 ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
4360 spin_unlock_irqrestore(&hs->lock, flags);
4366 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4367 * @ep: The endpoint to set halt.
4368 * @value: Set or unset the halt.
4369 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4370 * the endpoint is busy processing requests.
4372 * We need to stall the endpoint immediately if request comes from set_feature
4373 * protocol command handler.
4375 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4377 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4378 struct dwc2_hsotg *hs = hs_ep->parent;
4379 int index = hs_ep->index;
4384 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4388 dwc2_hsotg_stall_ep0(hs);
4391 "%s: can't clear halt on ep0\n", __func__);
4395 if (hs_ep->isochronous) {
4396 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4400 if (!now && value && !list_empty(&hs_ep->queue)) {
4401 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4406 if (hs_ep->dir_in) {
4407 epreg = DIEPCTL(index);
4408 epctl = dwc2_readl(hs, epreg);
4411 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4412 if (epctl & DXEPCTL_EPENA)
4413 epctl |= DXEPCTL_EPDIS;
4415 epctl &= ~DXEPCTL_STALL;
4417 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4418 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4419 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4420 epctl |= DXEPCTL_SETD0PID;
4422 dwc2_writel(hs, epctl, epreg);
4424 epreg = DOEPCTL(index);
4425 epctl = dwc2_readl(hs, epreg);
4428 /* Unmask GOUTNAKEFF interrupt */
4429 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4431 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4432 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4433 // STALL bit will be set in GOUTNAKEFF interrupt handler
4435 epctl &= ~DXEPCTL_STALL;
4437 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4438 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4439 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4440 epctl |= DXEPCTL_SETD0PID;
4441 dwc2_writel(hs, epctl, epreg);
4445 hs_ep->halted = value;
4450 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4451 * @ep: The endpoint to set halt.
4452 * @value: Set or unset the halt.
4454 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4456 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4457 struct dwc2_hsotg *hs = hs_ep->parent;
4458 unsigned long flags;
4461 spin_lock_irqsave(&hs->lock, flags);
4462 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4463 spin_unlock_irqrestore(&hs->lock, flags);
4468 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4469 .enable = dwc2_hsotg_ep_enable,
4470 .disable = dwc2_hsotg_ep_disable_lock,
4471 .alloc_request = dwc2_hsotg_ep_alloc_request,
4472 .free_request = dwc2_hsotg_ep_free_request,
4473 .queue = dwc2_hsotg_ep_queue_lock,
4474 .dequeue = dwc2_hsotg_ep_dequeue,
4475 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4476 .set_wedge = dwc2_gadget_ep_set_wedge,
4477 /* note, don't believe we have any call for the fifo routines */
4481 * dwc2_hsotg_init - initialize the usb core
4482 * @hsotg: The driver state
4484 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4486 /* unmask subset of endpoint interrupts */
4488 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4489 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4492 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4493 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4496 dwc2_writel(hsotg, 0, DAINTMSK);
4498 /* Be in disconnected state until gadget is registered */
4499 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4503 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4504 dwc2_readl(hsotg, GRXFSIZ),
4505 dwc2_readl(hsotg, GNPTXFSIZ));
4507 dwc2_hsotg_init_fifo(hsotg);
4509 if (using_dma(hsotg))
4510 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4514 * dwc2_hsotg_udc_start - prepare the udc for work
4515 * @gadget: The usb gadget state
4516 * @driver: The usb gadget driver
4518 * Perform initialization to prepare udc device and driver
4521 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4522 struct usb_gadget_driver *driver)
4524 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4525 unsigned long flags;
4529 pr_err("%s: called with no device\n", __func__);
4534 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4538 if (driver->max_speed < USB_SPEED_FULL)
4539 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4541 if (!driver->setup) {
4542 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4546 WARN_ON(hsotg->driver);
4548 hsotg->driver = driver;
4549 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4550 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4552 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4553 dwc2_force_mode(hsotg, false);
4554 ret = dwc2_lowlevel_hw_enable(hsotg);
4559 if (!IS_ERR_OR_NULL(hsotg->uphy))
4560 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4562 spin_lock_irqsave(&hsotg->lock, flags);
4563 if (dwc2_hw_is_device(hsotg)) {
4564 dwc2_hsotg_init(hsotg);
4565 dwc2_hsotg_core_init_disconnected(hsotg, false);
4569 spin_unlock_irqrestore(&hsotg->lock, flags);
4571 gadget->sg_supported = using_desc_dma(hsotg);
4572 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4577 hsotg->driver = NULL;
4582 * dwc2_hsotg_udc_stop - stop the udc
4583 * @gadget: The usb gadget state
4585 * Stop udc hw block and stay tunned for future transmissions
4587 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4589 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4590 unsigned long flags;
4596 /* all endpoints should be shutdown */
4597 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4598 if (hsotg->eps_in[ep])
4599 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4600 if (hsotg->eps_out[ep])
4601 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4604 spin_lock_irqsave(&hsotg->lock, flags);
4606 hsotg->driver = NULL;
4607 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4610 spin_unlock_irqrestore(&hsotg->lock, flags);
4612 if (!IS_ERR_OR_NULL(hsotg->uphy))
4613 otg_set_peripheral(hsotg->uphy->otg, NULL);
4615 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4616 dwc2_lowlevel_hw_disable(hsotg);
4622 * dwc2_hsotg_gadget_getframe - read the frame number
4623 * @gadget: The usb gadget state
4625 * Read the {micro} frame number
4627 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4629 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4633 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4634 * @gadget: The usb gadget state
4635 * @is_selfpowered: Whether the device is self-powered
4637 * Set if the device is self or bus powered.
4639 static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4642 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4643 unsigned long flags;
4645 spin_lock_irqsave(&hsotg->lock, flags);
4646 gadget->is_selfpowered = !!is_selfpowered;
4647 spin_unlock_irqrestore(&hsotg->lock, flags);
4653 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4654 * @gadget: The usb gadget state
4655 * @is_on: Current state of the USB PHY
4657 * Connect/Disconnect the USB PHY pullup
4659 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4661 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4662 unsigned long flags;
4664 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4667 /* Don't modify pullup state while in host mode */
4668 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4669 hsotg->enabled = is_on;
4673 spin_lock_irqsave(&hsotg->lock, flags);
4676 dwc2_hsotg_core_init_disconnected(hsotg, false);
4677 /* Enable ACG feature in device mode,if supported */
4678 dwc2_enable_acg(hsotg);
4679 dwc2_hsotg_core_connect(hsotg);
4681 dwc2_hsotg_core_disconnect(hsotg);
4682 dwc2_hsotg_disconnect(hsotg);
4686 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4687 spin_unlock_irqrestore(&hsotg->lock, flags);
4692 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4694 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4695 unsigned long flags;
4697 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4698 spin_lock_irqsave(&hsotg->lock, flags);
4701 * If controller is in partial power down state, it must exit from
4702 * that state before being initialized / de-initialized
4704 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4706 * No need to check the return value as
4707 * registers are not being restored.
4709 dwc2_exit_partial_power_down(hsotg, 0, false);
4712 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4714 dwc2_hsotg_core_init_disconnected(hsotg, false);
4715 if (hsotg->enabled) {
4716 /* Enable ACG feature in device mode,if supported */
4717 dwc2_enable_acg(hsotg);
4718 dwc2_hsotg_core_connect(hsotg);
4721 dwc2_hsotg_core_disconnect(hsotg);
4722 dwc2_hsotg_disconnect(hsotg);
4725 spin_unlock_irqrestore(&hsotg->lock, flags);
4730 * dwc2_hsotg_vbus_draw - report bMaxPower field
4731 * @gadget: The usb gadget state
4732 * @mA: Amount of current
4734 * Report how much power the device may consume to the phy.
4736 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4738 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4740 if (IS_ERR_OR_NULL(hsotg->uphy))
4742 return usb_phy_set_power(hsotg->uphy, mA);
4745 static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
4747 struct dwc2_hsotg *hsotg = to_hsotg(g);
4748 unsigned long flags;
4750 spin_lock_irqsave(&hsotg->lock, flags);
4752 case USB_SPEED_HIGH:
4753 hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
4755 case USB_SPEED_FULL:
4756 hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
4759 hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
4762 dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
4764 spin_unlock_irqrestore(&hsotg->lock, flags);
4767 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4768 .get_frame = dwc2_hsotg_gadget_getframe,
4769 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4770 .udc_start = dwc2_hsotg_udc_start,
4771 .udc_stop = dwc2_hsotg_udc_stop,
4772 .pullup = dwc2_hsotg_pullup,
4773 .udc_set_speed = dwc2_gadget_set_speed,
4774 .vbus_session = dwc2_hsotg_vbus_session,
4775 .vbus_draw = dwc2_hsotg_vbus_draw,
4779 * dwc2_hsotg_initep - initialise a single endpoint
4780 * @hsotg: The device state.
4781 * @hs_ep: The endpoint to be initialised.
4782 * @epnum: The endpoint number
4783 * @dir_in: True if direction is in.
4785 * Initialise the given endpoint (as part of the probe and device state
4786 * creation) to give to the gadget driver. Setup the endpoint name, any
4787 * direction information and other state that may be required.
4789 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4790 struct dwc2_hsotg_ep *hs_ep,
4803 hs_ep->dir_in = dir_in;
4804 hs_ep->index = epnum;
4806 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4808 INIT_LIST_HEAD(&hs_ep->queue);
4809 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4811 /* add to the list of endpoints known by the gadget driver */
4813 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4815 hs_ep->parent = hsotg;
4816 hs_ep->ep.name = hs_ep->name;
4818 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4819 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4821 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4822 epnum ? 1024 : EP0_MPS_LIMIT);
4823 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4826 hs_ep->ep.caps.type_control = true;
4828 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4829 hs_ep->ep.caps.type_iso = true;
4830 hs_ep->ep.caps.type_bulk = true;
4832 hs_ep->ep.caps.type_int = true;
4836 hs_ep->ep.caps.dir_in = true;
4838 hs_ep->ep.caps.dir_out = true;
4841 * if we're using dma, we need to set the next-endpoint pointer
4842 * to be something valid.
4845 if (using_dma(hsotg)) {
4846 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4849 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4851 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4856 * dwc2_hsotg_hw_cfg - read HW configuration registers
4857 * @hsotg: Programming view of the DWC_otg controller
4859 * Read the USB core HW configuration registers
4861 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4867 /* check hardware configuration */
4869 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4872 hsotg->num_of_eps++;
4874 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4875 sizeof(struct dwc2_hsotg_ep),
4877 if (!hsotg->eps_in[0])
4879 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4880 hsotg->eps_out[0] = hsotg->eps_in[0];
4882 cfg = hsotg->hw_params.dev_ep_dirs;
4883 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4885 /* Direction in or both */
4886 if (!(ep_type & 2)) {
4887 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4888 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4889 if (!hsotg->eps_in[i])
4892 /* Direction out or both */
4893 if (!(ep_type & 1)) {
4894 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4895 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4896 if (!hsotg->eps_out[i])
4901 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4902 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4904 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4906 hsotg->dedicated_fifos ? "dedicated" : "shared",
4912 * dwc2_hsotg_dump - dump state of the udc
4913 * @hsotg: Programming view of the DWC_otg controller
4916 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4919 struct device *dev = hsotg->dev;
4923 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4924 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4925 dwc2_readl(hsotg, DIEPMSK));
4927 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4928 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4930 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4931 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4933 /* show periodic fifo settings */
4935 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4936 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4937 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4938 val >> FIFOSIZE_DEPTH_SHIFT,
4939 val & FIFOSIZE_STARTADDR_MASK);
4942 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4944 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4945 dwc2_readl(hsotg, DIEPCTL(idx)),
4946 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4947 dwc2_readl(hsotg, DIEPDMA(idx)));
4949 val = dwc2_readl(hsotg, DOEPCTL(idx));
4951 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4952 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4953 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4954 dwc2_readl(hsotg, DOEPDMA(idx)));
4957 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4958 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4963 * dwc2_gadget_init - init function for gadget
4964 * @hsotg: Programming view of the DWC_otg controller
4967 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4969 struct device *dev = hsotg->dev;
4973 /* Dump fifo information */
4974 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4975 hsotg->params.g_np_tx_fifo_size);
4976 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4978 switch (hsotg->params.speed) {
4979 case DWC2_SPEED_PARAM_LOW:
4980 hsotg->gadget.max_speed = USB_SPEED_LOW;
4982 case DWC2_SPEED_PARAM_FULL:
4983 hsotg->gadget.max_speed = USB_SPEED_FULL;
4986 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4990 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4991 hsotg->gadget.name = dev_name(dev);
4992 hsotg->gadget.otg_caps = &hsotg->params.otg_caps;
4993 hsotg->remote_wakeup_allowed = 0;
4995 if (hsotg->params.lpm)
4996 hsotg->gadget.lpm_capable = true;
4998 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4999 hsotg->gadget.is_otg = 1;
5000 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
5001 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
5003 ret = dwc2_hsotg_hw_cfg(hsotg);
5005 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
5009 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
5010 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5011 if (!hsotg->ctrl_buff)
5014 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
5015 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5016 if (!hsotg->ep0_buff)
5019 if (using_desc_dma(hsotg)) {
5020 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
5025 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
5026 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
5028 dev_err(dev, "cannot claim IRQ for gadget\n");
5032 /* hsotg->num_of_eps holds number of EPs other than ep0 */
5034 if (hsotg->num_of_eps == 0) {
5035 dev_err(dev, "wrong number of EPs (zero)\n");
5039 /* setup endpoint information */
5041 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
5042 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
5044 /* allocate EP0 request */
5046 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
5048 if (!hsotg->ctrl_req) {
5049 dev_err(dev, "failed to allocate ctrl req\n");
5053 /* initialise the endpoints now the core has been initialised */
5054 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
5055 if (hsotg->eps_in[epnum])
5056 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
5058 if (hsotg->eps_out[epnum])
5059 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5063 dwc2_hsotg_dump(hsotg);
5065 #if IS_ENABLED(CONFIG_EXTCON)
5066 if (hsotg->params.g_extcon_always_on) {
5067 struct extcon_dev *edev;
5068 static const unsigned int supported_cable[] = {
5073 edev = devm_extcon_dev_allocate(dev, supported_cable);
5075 return PTR_ERR(edev);
5077 ret = devm_extcon_dev_register(dev, edev);
5081 extcon_set_state_sync(edev, EXTCON_USB, true);
5088 * dwc2_hsotg_remove - remove function for hsotg driver
5089 * @hsotg: Programming view of the DWC_otg controller
5092 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5094 usb_del_gadget_udc(&hsotg->gadget);
5095 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5100 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5102 unsigned long flags;
5104 if (hsotg->lx_state != DWC2_L0)
5107 if (hsotg->driver) {
5110 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5111 hsotg->driver->driver.name);
5113 spin_lock_irqsave(&hsotg->lock, flags);
5115 dwc2_hsotg_core_disconnect(hsotg);
5116 dwc2_hsotg_disconnect(hsotg);
5117 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5118 spin_unlock_irqrestore(&hsotg->lock, flags);
5120 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
5121 if (hsotg->eps_in[ep])
5122 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5123 if (hsotg->eps_out[ep])
5124 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5131 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5133 unsigned long flags;
5135 if (hsotg->lx_state == DWC2_L2)
5138 if (hsotg->driver) {
5139 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5140 hsotg->driver->driver.name);
5142 spin_lock_irqsave(&hsotg->lock, flags);
5143 dwc2_hsotg_core_init_disconnected(hsotg, false);
5144 if (hsotg->enabled) {
5145 /* Enable ACG feature in device mode,if supported */
5146 dwc2_enable_acg(hsotg);
5147 dwc2_hsotg_core_connect(hsotg);
5149 spin_unlock_irqrestore(&hsotg->lock, flags);
5156 * dwc2_backup_device_registers() - Backup controller device registers.
5157 * When suspending usb bus, registers needs to be backuped
5158 * if controller power is disabled once suspended.
5160 * @hsotg: Programming view of the DWC_otg controller
5162 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5164 struct dwc2_dregs_backup *dr;
5167 dev_dbg(hsotg->dev, "%s\n", __func__);
5169 /* Backup dev regs */
5170 dr = &hsotg->dr_backup;
5172 dr->dcfg = dwc2_readl(hsotg, DCFG);
5173 dr->dctl = dwc2_readl(hsotg, DCTL);
5174 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5175 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5176 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5178 for (i = 0; i < hsotg->num_of_eps; i++) {
5180 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5182 /* Ensure DATA PID is correctly configured */
5183 if (dr->diepctl[i] & DXEPCTL_DPID)
5184 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5186 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5188 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5189 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5191 /* Backup OUT EPs */
5192 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5194 /* Ensure DATA PID is correctly configured */
5195 if (dr->doepctl[i] & DXEPCTL_DPID)
5196 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5198 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5200 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5201 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5202 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5209 * dwc2_restore_device_registers() - Restore controller device registers.
5210 * When resuming usb bus, device registers needs to be restored
5211 * if controller power were disabled.
5213 * @hsotg: Programming view of the DWC_otg controller
5214 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5216 * Return: 0 if successful, negative error code otherwise
5218 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5220 struct dwc2_dregs_backup *dr;
5223 dev_dbg(hsotg->dev, "%s\n", __func__);
5225 /* Restore dev regs */
5226 dr = &hsotg->dr_backup;
5228 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5235 dwc2_writel(hsotg, dr->dctl, DCTL);
5237 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5238 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5239 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5241 for (i = 0; i < hsotg->num_of_eps; i++) {
5242 /* Restore IN EPs */
5243 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5244 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5245 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5246 /** WA for enabled EPx's IN in DDMA mode. On entering to
5247 * hibernation wrong value read and saved from DIEPDMAx,
5248 * as result BNA interrupt asserted on hibernation exit
5249 * by restoring from saved area.
5251 if (using_desc_dma(hsotg) &&
5252 (dr->diepctl[i] & DXEPCTL_EPENA))
5253 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5254 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5255 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5256 /* Restore OUT EPs */
5257 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5258 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5259 * hibernation wrong value read and saved from DOEPDMAx,
5260 * as result BNA interrupt asserted on hibernation exit
5261 * by restoring from saved area.
5263 if (using_desc_dma(hsotg) &&
5264 (dr->doepctl[i] & DXEPCTL_EPENA))
5265 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5266 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5267 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5274 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5276 * @hsotg: Programming view of DWC_otg controller
5279 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5283 if (!hsotg->params.lpm)
5286 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5287 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5288 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5289 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5290 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5291 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5292 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5293 dwc2_writel(hsotg, val, GLPMCFG);
5294 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5296 /* Unmask WKUP_ALERT Interrupt */
5297 if (hsotg->params.service_interval)
5298 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5302 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5304 * @hsotg: Programming view of DWC_otg controller
5307 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5311 val |= GREFCLK_REF_CLK_MODE;
5312 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5313 val |= hsotg->params.sof_cnt_wkup_alert <<
5314 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5316 dwc2_writel(hsotg, val, GREFCLK);
5317 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5321 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5323 * @hsotg: Programming view of the DWC_otg controller
5325 * Return non-zero if failed to enter to hibernation.
5327 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5332 /* Change to L2(suspend) state */
5333 hsotg->lx_state = DWC2_L2;
5334 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5335 ret = dwc2_backup_global_registers(hsotg);
5337 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5341 ret = dwc2_backup_device_registers(hsotg);
5343 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5348 gpwrdn = GPWRDN_PWRDNRSTN;
5349 gpwrdn |= GPWRDN_PMUACTV;
5350 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5353 /* Set flag to indicate that we are in hibernation */
5354 hsotg->hibernated = 1;
5356 /* Enable interrupts from wake up logic */
5357 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5358 gpwrdn |= GPWRDN_PMUINTSEL;
5359 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5362 /* Unmask device mode interrupts in GPWRDN */
5363 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5364 gpwrdn |= GPWRDN_RST_DET_MSK;
5365 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5366 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5367 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5370 /* Enable Power Down Clamp */
5371 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5372 gpwrdn |= GPWRDN_PWRDNCLMP;
5373 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5376 /* Switch off VDD */
5377 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5378 gpwrdn |= GPWRDN_PWRDNSWTCH;
5379 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5382 /* Save gpwrdn register for further usage if stschng interrupt */
5383 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5384 dev_dbg(hsotg->dev, "Hibernation completed\n");
5390 * dwc2_gadget_exit_hibernation()
5391 * This function is for exiting from Device mode hibernation by host initiated
5392 * resume/reset and device initiated remote-wakeup.
5394 * @hsotg: Programming view of the DWC_otg controller
5395 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5396 * @reset: indicates whether resume is initiated by Reset.
5398 * Return non-zero if failed to exit from hibernation.
5400 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5401 int rem_wakeup, int reset)
5407 struct dwc2_gregs_backup *gr;
5408 struct dwc2_dregs_backup *dr;
5410 gr = &hsotg->gr_backup;
5411 dr = &hsotg->dr_backup;
5413 if (!hsotg->hibernated) {
5414 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5418 "%s: called with rem_wakeup = %d reset = %d\n",
5419 __func__, rem_wakeup, reset);
5421 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5424 /* Clear all pending interupts */
5425 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5428 /* De-assert Restore */
5429 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5430 gpwrdn &= ~GPWRDN_RESTORE;
5431 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5435 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5436 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5437 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5440 /* Restore GUSBCFG, DCFG and DCTL */
5441 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5442 dwc2_writel(hsotg, dr->dcfg, DCFG);
5443 dwc2_writel(hsotg, dr->dctl, DCTL);
5445 /* On USB Reset, reset device address to zero */
5447 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5449 /* De-assert Wakeup Logic */
5450 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5451 gpwrdn &= ~GPWRDN_PMUACTV;
5452 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5456 /* Start Remote Wakeup Signaling */
5457 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5460 /* Set Device programming done bit */
5461 dctl = dwc2_readl(hsotg, DCTL);
5462 dctl |= DCTL_PWRONPRGDONE;
5463 dwc2_writel(hsotg, dctl, DCTL);
5465 /* Wait for interrupts which must be cleared */
5467 /* Clear all pending interupts */
5468 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5470 /* Restore global registers */
5471 ret = dwc2_restore_global_registers(hsotg);
5473 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5478 /* Restore device registers */
5479 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5481 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5488 dctl = dwc2_readl(hsotg, DCTL);
5489 dctl &= ~DCTL_RMTWKUPSIG;
5490 dwc2_writel(hsotg, dctl, DCTL);
5493 hsotg->hibernated = 0;
5494 hsotg->lx_state = DWC2_L0;
5495 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5501 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5504 * @hsotg: Programming view of the DWC_otg controller
5506 * Return: non-zero if failed to enter device partial power down.
5508 * This function is for entering device mode partial power down.
5510 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5515 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5517 /* Backup all registers */
5518 ret = dwc2_backup_global_registers(hsotg);
5520 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5525 ret = dwc2_backup_device_registers(hsotg);
5527 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5533 * Clear any pending interrupts since dwc2 will not be able to
5534 * clear them after entering partial_power_down.
5536 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5538 /* Put the controller in low power state */
5539 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5541 pcgcctl |= PCGCTL_PWRCLMP;
5542 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5545 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5546 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5549 pcgcctl |= PCGCTL_STOPPCLK;
5550 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5552 /* Set in_ppd flag to 1 as here core enters suspend. */
5554 hsotg->lx_state = DWC2_L2;
5556 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5562 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5565 * @hsotg: Programming view of the DWC_otg controller
5566 * @restore: indicates whether need to restore the registers or not.
5568 * Return: non-zero if failed to exit device partial power down.
5570 * This function is for exiting from device mode partial power down.
5572 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5577 struct dwc2_dregs_backup *dr;
5580 dr = &hsotg->dr_backup;
5582 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5584 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5585 pcgcctl &= ~PCGCTL_STOPPCLK;
5586 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5588 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5589 pcgcctl &= ~PCGCTL_PWRCLMP;
5590 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5592 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5593 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5594 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5598 ret = dwc2_restore_global_registers(hsotg);
5600 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5605 dwc2_writel(hsotg, dr->dcfg, DCFG);
5607 ret = dwc2_restore_device_registers(hsotg, 0);
5609 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5615 /* Set the Power-On Programming done bit */
5616 dctl = dwc2_readl(hsotg, DCTL);
5617 dctl |= DCTL_PWRONPRGDONE;
5618 dwc2_writel(hsotg, dctl, DCTL);
5620 /* Set in_ppd flag to 0 as here core exits from suspend. */
5622 hsotg->lx_state = DWC2_L0;
5624 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5629 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5631 * @hsotg: Programming view of the DWC_otg controller
5633 * Return: non-zero if failed to enter device partial power down.
5635 * This function is for entering device mode clock gating.
5637 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5641 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5643 /* Set the Phy Clock bit as suspend is received. */
5644 pcgctl = dwc2_readl(hsotg, PCGCTL);
5645 pcgctl |= PCGCTL_STOPPCLK;
5646 dwc2_writel(hsotg, pcgctl, PCGCTL);
5649 /* Set the Gate hclk as suspend is received. */
5650 pcgctl = dwc2_readl(hsotg, PCGCTL);
5651 pcgctl |= PCGCTL_GATEHCLK;
5652 dwc2_writel(hsotg, pcgctl, PCGCTL);
5655 hsotg->lx_state = DWC2_L2;
5656 hsotg->bus_suspended = true;
5660 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5662 * @hsotg: Programming view of the DWC_otg controller
5663 * @rem_wakeup: indicates whether remote wake up is enabled.
5665 * This function is for exiting from device mode clock gating.
5667 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5672 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5674 /* Clear the Gate hclk. */
5675 pcgctl = dwc2_readl(hsotg, PCGCTL);
5676 pcgctl &= ~PCGCTL_GATEHCLK;
5677 dwc2_writel(hsotg, pcgctl, PCGCTL);
5680 /* Phy Clock bit. */
5681 pcgctl = dwc2_readl(hsotg, PCGCTL);
5682 pcgctl &= ~PCGCTL_STOPPCLK;
5683 dwc2_writel(hsotg, pcgctl, PCGCTL);
5687 /* Set Remote Wakeup Signaling */
5688 dctl = dwc2_readl(hsotg, DCTL);
5689 dctl |= DCTL_RMTWKUPSIG;
5690 dwc2_writel(hsotg, dctl, DCTL);
5693 /* Change to L0 state */
5694 call_gadget(hsotg, resume);
5695 hsotg->lx_state = DWC2_L0;
5696 hsotg->bus_suspended = false;