1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
26 #include <linux/extcon-provider.h>
28 #include <linux/usb/ch9.h>
29 #include <linux/usb/gadget.h>
30 #include <linux/usb/phy.h>
31 #include <linux/usb/composite.h>
37 /* conversion functions */
38 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
40 return container_of(req, struct dwc2_hsotg_req, req);
43 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
48 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
50 return container_of(gadget, struct dwc2_hsotg, gadget);
53 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
55 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
58 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
60 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
63 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
67 return hsotg->eps_in[ep_index];
69 return hsotg->eps_out[ep_index];
72 /* forward declaration of functions */
73 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
79 * Return true if we're using DMA.
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
92 * g_using_dma is set depending on dts flag.
94 static inline bool using_dma(struct dwc2_hsotg *hsotg)
96 return hsotg->params.g_dma;
100 * using_desc_dma - return the descriptor DMA status of the driver.
101 * @hsotg: The driver state.
103 * Return true if we're using descriptor DMA.
105 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
107 return hsotg->params.g_dma_desc;
111 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
112 * @hs_ep: The endpoint
114 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
115 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
117 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
119 struct dwc2_hsotg *hsotg = hs_ep->parent;
120 u16 limit = DSTS_SOFFN_LIMIT;
122 if (hsotg->gadget.speed != USB_SPEED_HIGH)
125 hs_ep->target_frame += hs_ep->interval;
126 if (hs_ep->target_frame > limit) {
127 hs_ep->frame_overrun = true;
128 hs_ep->target_frame &= limit;
130 hs_ep->frame_overrun = false;
135 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
137 * @hs_ep: The endpoint.
139 * This function used in service interval based scheduling flow to calculate
140 * descriptor frame number filed value. For service interval mode frame
141 * number in descriptor should point to last (u)frame in the interval.
144 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
146 struct dwc2_hsotg *hsotg = hs_ep->parent;
147 u16 limit = DSTS_SOFFN_LIMIT;
149 if (hsotg->gadget.speed != USB_SPEED_HIGH)
152 if (hs_ep->target_frame)
153 hs_ep->target_frame -= 1;
155 hs_ep->target_frame = limit;
159 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
160 * @hsotg: The device state
161 * @ints: A bitmask of the interrupts to enable
163 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
165 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
168 new_gsintmsk = gsintmsk | ints;
170 if (new_gsintmsk != gsintmsk) {
171 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
172 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
177 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
178 * @hsotg: The device state
179 * @ints: A bitmask of the interrupts to enable
181 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
183 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
186 new_gsintmsk = gsintmsk & ~ints;
188 if (new_gsintmsk != gsintmsk)
189 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
193 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
194 * @hsotg: The device state
195 * @ep: The endpoint index
196 * @dir_in: True if direction is in.
197 * @en: The enable value, true to enable
199 * Set or clear the mask for an individual endpoint's interrupt
202 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
203 unsigned int ep, unsigned int dir_in,
213 local_irq_save(flags);
214 daint = dwc2_readl(hsotg, DAINTMSK);
219 dwc2_writel(hsotg, daint, DAINTMSK);
220 local_irq_restore(flags);
224 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
226 * @hsotg: Programming view of the DWC_otg controller
228 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
230 if (hsotg->hw_params.en_multiple_tx_fifo)
231 /* In dedicated FIFO mode we need count of IN EPs */
232 return hsotg->hw_params.num_dev_in_eps;
234 /* In shared FIFO mode we need count of Periodic IN EPs */
235 return hsotg->hw_params.num_dev_perio_in_ep;
239 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
240 * device mode TX FIFOs
242 * @hsotg: Programming view of the DWC_otg controller
244 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
250 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
251 hsotg->params.g_np_tx_fifo_size);
253 /* Get Endpoint Info Control block size in DWORDs. */
254 tx_addr_max = hsotg->hw_params.total_fifo_size;
256 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
257 if (tx_addr_max <= addr)
260 return tx_addr_max - addr;
264 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
266 * @hsotg: Programming view of the DWC_otg controller
269 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
274 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
275 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
276 gintsts2 &= gintmsk2;
278 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
279 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
280 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
281 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
286 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
289 * @hsotg: Programming view of the DWC_otg controller
291 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
296 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
298 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
301 return tx_fifo_depth;
303 return tx_fifo_depth / tx_fifo_count;
307 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
308 * @hsotg: The device instance.
310 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
317 u32 *txfsz = hsotg->params.g_tx_fifo_size;
319 /* Reset fifo map if not correctly cleared during previous session */
320 WARN_ON(hsotg->fifo_map);
323 /* set RX/NPTX FIFO sizes */
324 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
325 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
326 FIFOSIZE_STARTADDR_SHIFT) |
327 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
331 * arange all the rest of the TX FIFOs, as some versions of this
332 * block have overlapping default addresses. This also ensures
333 * that if the settings have been changed, then they are set to
337 /* start at the end of the GNPTXFSIZ, rounded up */
338 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
341 * Configure fifos sizes from provided configuration and assign
342 * them to endpoints dynamically according to maxpacket size value of
345 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
349 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
350 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
351 "insufficient fifo memory");
354 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
355 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
358 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
359 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
362 * according to p428 of the design guide, we need to ensure that
363 * all fifos are flushed before continuing
366 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
367 GRSTCTL_RXFFLSH, GRSTCTL);
369 /* wait until the fifos are both flushed */
372 val = dwc2_readl(hsotg, GRSTCTL);
374 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
377 if (--timeout == 0) {
379 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
387 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
391 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
392 * @ep: USB endpoint to allocate request for.
393 * @flags: Allocation flags
395 * Allocate a new USB request structure appropriate for the specified endpoint
397 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
400 struct dwc2_hsotg_req *req;
402 req = kzalloc(sizeof(*req), flags);
406 INIT_LIST_HEAD(&req->queue);
412 * is_ep_periodic - return true if the endpoint is in periodic mode.
413 * @hs_ep: The endpoint to query.
415 * Returns true if the endpoint is in periodic mode, meaning it is being
416 * used for an Interrupt or ISO transfer.
418 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
420 return hs_ep->periodic;
424 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
425 * @hsotg: The device state.
426 * @hs_ep: The endpoint for the request
427 * @hs_req: The request being processed.
429 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
430 * of a request to ensure the buffer is ready for access by the caller.
432 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
433 struct dwc2_hsotg_ep *hs_ep,
434 struct dwc2_hsotg_req *hs_req)
436 struct usb_request *req = &hs_req->req;
438 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
442 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
443 * for Control endpoint
444 * @hsotg: The device state.
446 * This function will allocate 4 descriptor chains for EP 0: 2 for
447 * Setup stage, per one for IN and OUT data/status transactions.
449 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
451 hsotg->setup_desc[0] =
452 dmam_alloc_coherent(hsotg->dev,
453 sizeof(struct dwc2_dma_desc),
454 &hsotg->setup_desc_dma[0],
456 if (!hsotg->setup_desc[0])
459 hsotg->setup_desc[1] =
460 dmam_alloc_coherent(hsotg->dev,
461 sizeof(struct dwc2_dma_desc),
462 &hsotg->setup_desc_dma[1],
464 if (!hsotg->setup_desc[1])
467 hsotg->ctrl_in_desc =
468 dmam_alloc_coherent(hsotg->dev,
469 sizeof(struct dwc2_dma_desc),
470 &hsotg->ctrl_in_desc_dma,
472 if (!hsotg->ctrl_in_desc)
475 hsotg->ctrl_out_desc =
476 dmam_alloc_coherent(hsotg->dev,
477 sizeof(struct dwc2_dma_desc),
478 &hsotg->ctrl_out_desc_dma,
480 if (!hsotg->ctrl_out_desc)
490 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
491 * @hsotg: The controller state.
492 * @hs_ep: The endpoint we're going to write for.
493 * @hs_req: The request to write data for.
495 * This is called when the TxFIFO has some space in it to hold a new
496 * transmission and we have something to give it. The actual setup of
497 * the data size is done elsewhere, so all we have to do is to actually
500 * The return value is zero if there is more space (or nothing was done)
501 * otherwise -ENOSPC is returned if the FIFO space was used up.
503 * This routine is only needed for PIO
505 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
506 struct dwc2_hsotg_ep *hs_ep,
507 struct dwc2_hsotg_req *hs_req)
509 bool periodic = is_ep_periodic(hs_ep);
510 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
511 int buf_pos = hs_req->req.actual;
512 int to_write = hs_ep->size_loaded;
518 to_write -= (buf_pos - hs_ep->last_load);
520 /* if there's nothing to write, get out early */
524 if (periodic && !hsotg->dedicated_fifos) {
525 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
530 * work out how much data was loaded so we can calculate
531 * how much data is left in the fifo.
534 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
537 * if shared fifo, we cannot write anything until the
538 * previous data has been completely sent.
540 if (hs_ep->fifo_load != 0) {
541 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
545 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
547 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
549 /* how much of the data has moved */
550 size_done = hs_ep->size_loaded - size_left;
552 /* how much data is left in the fifo */
553 can_write = hs_ep->fifo_load - size_done;
554 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
555 __func__, can_write);
557 can_write = hs_ep->fifo_size - can_write;
558 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
559 __func__, can_write);
561 if (can_write <= 0) {
562 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
565 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
566 can_write = dwc2_readl(hsotg,
567 DTXFSTS(hs_ep->fifo_index));
572 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
574 "%s: no queue slots available (0x%08x)\n",
577 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
581 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
582 can_write *= 4; /* fifo size is in 32bit quantities. */
585 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
587 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
588 __func__, gnptxsts, can_write, to_write, max_transfer);
591 * limit to 512 bytes of data, it seems at least on the non-periodic
592 * FIFO, requests of >512 cause the endpoint to get stuck with a
593 * fragment of the end of the transfer in it.
595 if (can_write > 512 && !periodic)
599 * limit the write to one max-packet size worth of data, but allow
600 * the transfer to return that it did not run out of fifo space
603 if (to_write > max_transfer) {
604 to_write = max_transfer;
606 /* it's needed only when we do not use dedicated fifos */
607 if (!hsotg->dedicated_fifos)
608 dwc2_hsotg_en_gsint(hsotg,
609 periodic ? GINTSTS_PTXFEMP :
613 /* see if we can write data */
615 if (to_write > can_write) {
616 to_write = can_write;
617 pkt_round = to_write % max_transfer;
620 * Round the write down to an
621 * exact number of packets.
623 * Note, we do not currently check to see if we can ever
624 * write a full packet or not to the FIFO.
628 to_write -= pkt_round;
631 * enable correct FIFO interrupt to alert us when there
635 /* it's needed only when we do not use dedicated fifos */
636 if (!hsotg->dedicated_fifos)
637 dwc2_hsotg_en_gsint(hsotg,
638 periodic ? GINTSTS_PTXFEMP :
642 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
643 to_write, hs_req->req.length, can_write, buf_pos);
648 hs_req->req.actual = buf_pos + to_write;
649 hs_ep->total_data += to_write;
652 hs_ep->fifo_load += to_write;
654 to_write = DIV_ROUND_UP(to_write, 4);
655 data = hs_req->req.buf + buf_pos;
657 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
659 return (to_write >= can_write) ? -ENOSPC : 0;
663 * get_ep_limit - get the maximum data legnth for this endpoint
664 * @hs_ep: The endpoint
666 * Return the maximum data that can be queued in one go on a given endpoint
667 * so that transfers that are too long can be split.
669 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
671 int index = hs_ep->index;
672 unsigned int maxsize;
676 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
677 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
681 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
686 /* we made the constant loading easier above by using +1 */
691 * constrain by packet count if maxpkts*pktsize is greater
692 * than the length register size.
695 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
696 maxsize = maxpkt * hs_ep->ep.maxpacket;
702 * dwc2_hsotg_read_frameno - read current frame number
703 * @hsotg: The device instance
705 * Return the current frame number
707 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
711 dsts = dwc2_readl(hsotg, DSTS);
712 dsts &= DSTS_SOFFN_MASK;
713 dsts >>= DSTS_SOFFN_SHIFT;
719 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
720 * DMA descriptor chain prepared for specific endpoint
721 * @hs_ep: The endpoint
723 * Return the maximum data that can be queued in one go on a given endpoint
724 * depending on its descriptor chain capacity so that transfers that
725 * are too long can be split.
727 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
729 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
730 int is_isoc = hs_ep->isochronous;
731 unsigned int maxsize;
732 u32 mps = hs_ep->ep.maxpacket;
733 int dir_in = hs_ep->dir_in;
736 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
737 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
738 MAX_DMA_DESC_NUM_HS_ISOC;
740 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
742 /* Interrupt OUT EP with mps not multiple of 4 */
744 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
745 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
751 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
752 * @hs_ep: The endpoint
753 * @mask: RX/TX bytes mask to be defined
755 * Returns maximum data payload for one descriptor after analyzing endpoint
757 * DMA descriptor transfer bytes limit depends on EP type:
759 * Isochronous - descriptor rx/tx bytes bitfield limit,
760 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
761 * have concatenations from various descriptors within one packet.
762 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
763 * to a single descriptor.
765 * Selects corresponding mask for RX/TX bytes as well.
767 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
769 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
770 u32 mps = hs_ep->ep.maxpacket;
771 int dir_in = hs_ep->dir_in;
774 if (!hs_ep->index && !dir_in) {
776 *mask = DEV_DMA_NBYTES_MASK;
777 } else if (hs_ep->isochronous) {
779 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
780 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
782 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
783 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
786 desc_size = DEV_DMA_NBYTES_LIMIT;
787 *mask = DEV_DMA_NBYTES_MASK;
789 /* Round down desc_size to be mps multiple */
790 desc_size -= desc_size % mps;
793 /* Interrupt OUT EP with mps not multiple of 4 */
795 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
797 *mask = DEV_DMA_NBYTES_MASK;
803 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
804 struct dwc2_dma_desc **desc,
809 int dir_in = hs_ep->dir_in;
810 u32 mps = hs_ep->ep.maxpacket;
816 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
818 hs_ep->desc_count = (len / maxsize) +
819 ((len % maxsize) ? 1 : 0);
821 hs_ep->desc_count = 1;
823 for (i = 0; i < hs_ep->desc_count; ++i) {
825 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
826 << DEV_DMA_BUFF_STS_SHIFT);
829 if (!hs_ep->index && !dir_in)
830 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
833 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
834 (*desc)->buf = dma_buff + offset;
840 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
843 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
844 ((hs_ep->send_zlp && true_last) ?
848 len << DEV_DMA_NBYTES_SHIFT & mask;
849 (*desc)->buf = dma_buff + offset;
852 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
853 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
854 << DEV_DMA_BUFF_STS_SHIFT);
860 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
861 * @hs_ep: The endpoint
862 * @ureq: Request to transfer
863 * @offset: offset in bytes
864 * @len: Length of the transfer
866 * This function will iterate over descriptor chain and fill its entries
867 * with corresponding information based on transfer data.
869 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
873 struct usb_request *ureq = NULL;
874 struct dwc2_dma_desc *desc = hs_ep->desc_list;
875 struct scatterlist *sg;
880 ureq = &hs_ep->req->req;
882 /* non-DMA sg buffer */
883 if (!ureq || !ureq->num_sgs) {
884 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
885 dma_buff, len, true);
890 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
891 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
892 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
894 desc_count += hs_ep->desc_count;
897 hs_ep->desc_count = desc_count;
901 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
902 * @hs_ep: The isochronous endpoint.
903 * @dma_buff: usb requests dma buffer.
904 * @len: usb request transfer length.
906 * Fills next free descriptor with the data of the arrived usb request,
907 * frame info, sets Last and IOC bits increments next_desc. If filled
908 * descriptor is not the first one, removes L bit from the previous descriptor
911 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
912 dma_addr_t dma_buff, unsigned int len)
914 struct dwc2_dma_desc *desc;
915 struct dwc2_hsotg *hsotg = hs_ep->parent;
920 dwc2_gadget_get_desc_params(hs_ep, &mask);
922 index = hs_ep->next_desc;
923 desc = &hs_ep->desc_list[index];
925 /* Check if descriptor chain full */
926 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
927 DEV_DMA_BUFF_STS_HREADY) {
928 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
932 /* Clear L bit of previous desc if more than one entries in the chain */
933 if (hs_ep->next_desc)
934 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
936 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
937 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
940 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
942 desc->buf = dma_buff;
943 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
944 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
948 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
951 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
952 DEV_DMA_ISOC_PID_MASK) |
953 ((len % hs_ep->ep.maxpacket) ?
955 ((hs_ep->target_frame <<
956 DEV_DMA_ISOC_FRNUM_SHIFT) &
957 DEV_DMA_ISOC_FRNUM_MASK);
960 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
961 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
963 /* Increment frame number by interval for IN */
965 dwc2_gadget_incr_frame_num(hs_ep);
967 /* Update index of last configured entry in the chain */
969 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
970 hs_ep->next_desc = 0;
976 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
977 * @hs_ep: The isochronous endpoint.
979 * Prepare descriptor chain for isochronous endpoints. Afterwards
980 * write DMA address to HW and enable the endpoint.
982 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
984 struct dwc2_hsotg *hsotg = hs_ep->parent;
985 struct dwc2_hsotg_req *hs_req, *treq;
986 int index = hs_ep->index;
992 struct dwc2_dma_desc *desc;
994 if (list_empty(&hs_ep->queue)) {
995 hs_ep->target_frame = TARGET_FRAME_INITIAL;
996 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
1000 /* Initialize descriptor chain by Host Busy status */
1001 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1002 desc = &hs_ep->desc_list[i];
1004 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1005 << DEV_DMA_BUFF_STS_SHIFT);
1008 hs_ep->next_desc = 0;
1009 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1010 dma_addr_t dma_addr = hs_req->req.dma;
1012 if (hs_req->req.num_sgs) {
1013 WARN_ON(hs_req->req.num_sgs > 1);
1014 dma_addr = sg_dma_address(hs_req->req.sg);
1016 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1017 hs_req->req.length);
1022 hs_ep->compl_desc = 0;
1023 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1024 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1026 /* write descriptor chain address to control register */
1027 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1029 ctrl = dwc2_readl(hsotg, depctl);
1030 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1031 dwc2_writel(hsotg, ctrl, depctl);
1034 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1035 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1036 struct dwc2_hsotg_ep *hs_ep,
1037 struct dwc2_hsotg_req *hs_req,
1041 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1042 * @hsotg: The controller state.
1043 * @hs_ep: The endpoint to process a request for
1044 * @hs_req: The request to start.
1045 * @continuing: True if we are doing more for the current request.
1047 * Start the given request running by setting the endpoint registers
1048 * appropriately, and writing any data to the FIFOs.
1050 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1051 struct dwc2_hsotg_ep *hs_ep,
1052 struct dwc2_hsotg_req *hs_req,
1055 struct usb_request *ureq = &hs_req->req;
1056 int index = hs_ep->index;
1057 int dir_in = hs_ep->dir_in;
1062 unsigned int length;
1063 unsigned int packets;
1064 unsigned int maxreq;
1065 unsigned int dma_reg;
1068 if (hs_ep->req && !continuing) {
1069 dev_err(hsotg->dev, "%s: active request\n", __func__);
1072 } else if (hs_ep->req != hs_req && continuing) {
1074 "%s: continue different req\n", __func__);
1080 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1081 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1082 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1084 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1085 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1086 hs_ep->dir_in ? "in" : "out");
1088 /* If endpoint is stalled, we will restart request later */
1089 ctrl = dwc2_readl(hsotg, epctrl_reg);
1091 if (index && ctrl & DXEPCTL_STALL) {
1092 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1096 length = ureq->length - ureq->actual;
1097 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1098 ureq->length, ureq->actual);
1100 if (!using_desc_dma(hsotg))
1101 maxreq = get_ep_limit(hs_ep);
1103 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1105 if (length > maxreq) {
1106 int round = maxreq % hs_ep->ep.maxpacket;
1108 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1109 __func__, length, maxreq, round);
1111 /* round down to multiple of packets */
1119 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1121 packets = 1; /* send one packet if length is zero. */
1123 if (dir_in && index != 0)
1124 if (hs_ep->isochronous)
1125 epsize = DXEPTSIZ_MC(packets);
1127 epsize = DXEPTSIZ_MC(1);
1132 * zero length packet should be programmed on its own and should not
1133 * be counted in DIEPTSIZ.PktCnt with other packets.
1135 if (dir_in && ureq->zero && !continuing) {
1136 /* Test if zlp is actually required. */
1137 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1138 !(ureq->length % hs_ep->ep.maxpacket))
1139 hs_ep->send_zlp = 1;
1142 epsize |= DXEPTSIZ_PKTCNT(packets);
1143 epsize |= DXEPTSIZ_XFERSIZE(length);
1145 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1146 __func__, packets, length, ureq->length, epsize, epsize_reg);
1148 /* store the request as the current one we're doing */
1149 hs_ep->req = hs_req;
1151 if (using_desc_dma(hsotg)) {
1153 u32 mps = hs_ep->ep.maxpacket;
1155 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1159 else if (length % mps)
1160 length += (mps - (length % mps));
1164 offset = ureq->actual;
1166 /* Fill DDMA chain entries */
1167 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1170 /* write descriptor chain address to control register */
1171 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1173 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1174 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1176 /* write size / packets */
1177 dwc2_writel(hsotg, epsize, epsize_reg);
1179 if (using_dma(hsotg) && !continuing && (length != 0)) {
1181 * write DMA address to control register, buffer
1182 * already synced by dwc2_hsotg_ep_queue().
1185 dwc2_writel(hsotg, ureq->dma, dma_reg);
1187 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1188 __func__, &ureq->dma, dma_reg);
1192 if (hs_ep->isochronous) {
1193 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1194 if (hs_ep->interval == 1) {
1195 if (hs_ep->target_frame & 0x1)
1196 ctrl |= DXEPCTL_SETODDFR;
1198 ctrl |= DXEPCTL_SETEVENFR;
1200 ctrl |= DXEPCTL_CNAK;
1202 hs_req->req.frame_number = hs_ep->target_frame;
1203 hs_req->req.actual = 0;
1204 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1209 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1211 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1213 /* For Setup request do not clear NAK */
1214 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1215 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1217 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1218 dwc2_writel(hsotg, ctrl, epctrl_reg);
1221 * set these, it seems that DMA support increments past the end
1222 * of the packet buffer so we need to calculate the length from
1225 hs_ep->size_loaded = length;
1226 hs_ep->last_load = ureq->actual;
1228 if (dir_in && !using_dma(hsotg)) {
1229 /* set these anyway, we may need them for non-periodic in */
1230 hs_ep->fifo_load = 0;
1232 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1236 * Note, trying to clear the NAK here causes problems with transmit
1237 * on the S3C6400 ending up with the TXFIFO becoming full.
1240 /* check ep is enabled */
1241 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1243 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1244 index, dwc2_readl(hsotg, epctrl_reg));
1246 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1247 __func__, dwc2_readl(hsotg, epctrl_reg));
1249 /* enable ep interrupts */
1250 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1254 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1255 * @hsotg: The device state.
1256 * @hs_ep: The endpoint the request is on.
1257 * @req: The request being processed.
1259 * We've been asked to queue a request, so ensure that the memory buffer
1260 * is correctly setup for DMA. If we've been passed an extant DMA address
1261 * then ensure the buffer has been synced to memory. If our buffer has no
1262 * DMA memory, then we map the memory and mark our request to allow us to
1263 * cleanup on completion.
1265 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1266 struct dwc2_hsotg_ep *hs_ep,
1267 struct usb_request *req)
1271 hs_ep->map_dir = hs_ep->dir_in;
1272 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1279 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1280 __func__, req->buf, req->length);
1285 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1286 struct dwc2_hsotg_ep *hs_ep,
1287 struct dwc2_hsotg_req *hs_req)
1289 void *req_buf = hs_req->req.buf;
1291 /* If dma is not being used or buffer is aligned */
1292 if (!using_dma(hsotg) || !((long)req_buf & 3))
1295 WARN_ON(hs_req->saved_req_buf);
1297 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1298 hs_ep->ep.name, req_buf, hs_req->req.length);
1300 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1301 if (!hs_req->req.buf) {
1302 hs_req->req.buf = req_buf;
1304 "%s: unable to allocate memory for bounce buffer\n",
1309 /* Save actual buffer */
1310 hs_req->saved_req_buf = req_buf;
1313 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1318 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1319 struct dwc2_hsotg_ep *hs_ep,
1320 struct dwc2_hsotg_req *hs_req)
1322 /* If dma is not being used or buffer was aligned */
1323 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1326 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1327 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1329 /* Copy data from bounce buffer on successful out transfer */
1330 if (!hs_ep->dir_in && !hs_req->req.status)
1331 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1332 hs_req->req.actual);
1334 /* Free bounce buffer */
1335 kfree(hs_req->req.buf);
1337 hs_req->req.buf = hs_req->saved_req_buf;
1338 hs_req->saved_req_buf = NULL;
1342 * dwc2_gadget_target_frame_elapsed - Checks target frame
1343 * @hs_ep: The driver endpoint to check
1345 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1346 * corresponding transfer.
1348 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1350 struct dwc2_hsotg *hsotg = hs_ep->parent;
1351 u32 target_frame = hs_ep->target_frame;
1352 u32 current_frame = hsotg->frame_number;
1353 bool frame_overrun = hs_ep->frame_overrun;
1354 u16 limit = DSTS_SOFFN_LIMIT;
1356 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1359 if (!frame_overrun && current_frame >= target_frame)
1362 if (frame_overrun && current_frame >= target_frame &&
1363 ((current_frame - target_frame) < limit / 2))
1370 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1371 * @hsotg: The driver state
1372 * @hs_ep: the ep descriptor chain is for
1374 * Called to update EP0 structure's pointers depend on stage of
1377 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1378 struct dwc2_hsotg_ep *hs_ep)
1380 switch (hsotg->ep0_state) {
1381 case DWC2_EP0_SETUP:
1382 case DWC2_EP0_STATUS_OUT:
1383 hs_ep->desc_list = hsotg->setup_desc[0];
1384 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1386 case DWC2_EP0_DATA_IN:
1387 case DWC2_EP0_STATUS_IN:
1388 hs_ep->desc_list = hsotg->ctrl_in_desc;
1389 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1391 case DWC2_EP0_DATA_OUT:
1392 hs_ep->desc_list = hsotg->ctrl_out_desc;
1393 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1396 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1404 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1407 struct dwc2_hsotg_req *hs_req = our_req(req);
1408 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1409 struct dwc2_hsotg *hs = hs_ep->parent;
1416 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1417 ep->name, req, req->length, req->buf, req->no_interrupt,
1418 req->zero, req->short_not_ok);
1420 /* Prevent new request submission when controller is suspended */
1421 if (hs->lx_state != DWC2_L0) {
1422 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1427 /* initialise status of the request */
1428 INIT_LIST_HEAD(&hs_req->queue);
1430 req->status = -EINPROGRESS;
1432 /* Don't queue ISOC request if length greater than mps*mc */
1433 if (hs_ep->isochronous &&
1434 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1435 dev_err(hs->dev, "req length > maxpacket*mc\n");
1439 /* In DDMA mode for ISOC's don't queue request if length greater
1440 * than descriptor limits.
1442 if (using_desc_dma(hs) && hs_ep->isochronous) {
1443 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1444 if (hs_ep->dir_in && req->length > maxsize) {
1445 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1446 req->length, maxsize);
1450 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1451 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1452 req->length, hs_ep->ep.maxpacket);
1457 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1461 /* if we're using DMA, sync the buffers as necessary */
1462 if (using_dma(hs)) {
1463 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1467 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1468 if (using_desc_dma(hs) && !hs_ep->index) {
1469 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1474 first = list_empty(&hs_ep->queue);
1475 list_add_tail(&hs_req->queue, &hs_ep->queue);
1478 * Handle DDMA isochronous transfers separately - just add new entry
1479 * to the descriptor chain.
1480 * Transfer will be started once SW gets either one of NAK or
1481 * OutTknEpDis interrupts.
1483 if (using_desc_dma(hs) && hs_ep->isochronous) {
1484 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1485 dma_addr_t dma_addr = hs_req->req.dma;
1487 if (hs_req->req.num_sgs) {
1488 WARN_ON(hs_req->req.num_sgs > 1);
1489 dma_addr = sg_dma_address(hs_req->req.sg);
1491 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1492 hs_req->req.length);
1497 /* Change EP direction if status phase request is after data out */
1498 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1499 hs->ep0_state == DWC2_EP0_DATA_OUT)
1503 if (!hs_ep->isochronous) {
1504 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1508 /* Update current frame number value. */
1509 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1510 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1511 dwc2_gadget_incr_frame_num(hs_ep);
1512 /* Update current frame number value once more as it
1515 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1518 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1519 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1524 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1527 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1528 struct dwc2_hsotg *hs = hs_ep->parent;
1529 unsigned long flags;
1532 spin_lock_irqsave(&hs->lock, flags);
1533 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1534 spin_unlock_irqrestore(&hs->lock, flags);
1539 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1540 struct usb_request *req)
1542 struct dwc2_hsotg_req *hs_req = our_req(req);
1548 * dwc2_hsotg_complete_oursetup - setup completion callback
1549 * @ep: The endpoint the request was on.
1550 * @req: The request completed.
1552 * Called on completion of any requests the driver itself
1553 * submitted that need cleaning up.
1555 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1556 struct usb_request *req)
1558 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1559 struct dwc2_hsotg *hsotg = hs_ep->parent;
1561 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1563 dwc2_hsotg_ep_free_request(ep, req);
1567 * ep_from_windex - convert control wIndex value to endpoint
1568 * @hsotg: The driver state.
1569 * @windex: The control request wIndex field (in host order).
1571 * Convert the given wIndex into a pointer to an driver endpoint
1572 * structure, or return NULL if it is not a valid endpoint.
1574 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1577 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1578 int idx = windex & 0x7F;
1580 if (windex >= 0x100)
1583 if (idx > hsotg->num_of_eps)
1586 return index_to_ep(hsotg, idx, dir);
1590 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1591 * @hsotg: The driver state.
1592 * @testmode: requested usb test mode
1593 * Enable usb Test Mode requested by the Host.
1595 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1597 int dctl = dwc2_readl(hsotg, DCTL);
1599 dctl &= ~DCTL_TSTCTL_MASK;
1603 case USB_TEST_SE0_NAK:
1604 case USB_TEST_PACKET:
1605 case USB_TEST_FORCE_ENABLE:
1606 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1611 dwc2_writel(hsotg, dctl, DCTL);
1616 * dwc2_hsotg_send_reply - send reply to control request
1617 * @hsotg: The device state
1619 * @buff: Buffer for request
1620 * @length: Length of reply.
1622 * Create a request and queue it on the given endpoint. This is useful as
1623 * an internal method of sending replies to certain control requests, etc.
1625 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1626 struct dwc2_hsotg_ep *ep,
1630 struct usb_request *req;
1633 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1635 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1636 hsotg->ep0_reply = req;
1638 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1642 req->buf = hsotg->ep0_buff;
1643 req->length = length;
1645 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1649 req->complete = dwc2_hsotg_complete_oursetup;
1652 memcpy(req->buf, buff, length);
1654 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1656 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1664 * dwc2_hsotg_process_req_status - process request GET_STATUS
1665 * @hsotg: The device state
1666 * @ctrl: USB control request
1668 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1669 struct usb_ctrlrequest *ctrl)
1671 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1672 struct dwc2_hsotg_ep *ep;
1677 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1680 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1684 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1685 case USB_RECIP_DEVICE:
1686 status = hsotg->gadget.is_selfpowered <<
1687 USB_DEVICE_SELF_POWERED;
1688 status |= hsotg->remote_wakeup_allowed <<
1689 USB_DEVICE_REMOTE_WAKEUP;
1690 reply = cpu_to_le16(status);
1693 case USB_RECIP_INTERFACE:
1694 /* currently, the data result should be zero */
1695 reply = cpu_to_le16(0);
1698 case USB_RECIP_ENDPOINT:
1699 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1703 reply = cpu_to_le16(ep->halted ? 1 : 0);
1710 if (le16_to_cpu(ctrl->wLength) != 2)
1713 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1715 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1722 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1725 * get_ep_head - return the first request on the endpoint
1726 * @hs_ep: The controller endpoint to get
1728 * Get the first request on the endpoint.
1730 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1732 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1737 * dwc2_gadget_start_next_request - Starts next request from ep queue
1738 * @hs_ep: Endpoint structure
1740 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1741 * in its handler. Hence we need to unmask it here to be able to do
1742 * resynchronization.
1744 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1746 struct dwc2_hsotg *hsotg = hs_ep->parent;
1747 int dir_in = hs_ep->dir_in;
1748 struct dwc2_hsotg_req *hs_req;
1750 if (!list_empty(&hs_ep->queue)) {
1751 hs_req = get_ep_head(hs_ep);
1752 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1755 if (!hs_ep->isochronous)
1759 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1762 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1768 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1769 * @hsotg: The device state
1770 * @ctrl: USB control request
1772 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1773 struct usb_ctrlrequest *ctrl)
1775 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1776 struct dwc2_hsotg_req *hs_req;
1777 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1778 struct dwc2_hsotg_ep *ep;
1785 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1786 __func__, set ? "SET" : "CLEAR");
1788 wValue = le16_to_cpu(ctrl->wValue);
1789 wIndex = le16_to_cpu(ctrl->wIndex);
1790 recip = ctrl->bRequestType & USB_RECIP_MASK;
1793 case USB_RECIP_DEVICE:
1795 case USB_DEVICE_REMOTE_WAKEUP:
1797 hsotg->remote_wakeup_allowed = 1;
1799 hsotg->remote_wakeup_allowed = 0;
1802 case USB_DEVICE_TEST_MODE:
1803 if ((wIndex & 0xff) != 0)
1808 hsotg->test_mode = wIndex >> 8;
1814 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1817 "%s: failed to send reply\n", __func__);
1822 case USB_RECIP_ENDPOINT:
1823 ep = ep_from_windex(hsotg, wIndex);
1825 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1831 case USB_ENDPOINT_HALT:
1832 halted = ep->halted;
1835 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1837 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1840 "%s: failed to send reply\n", __func__);
1845 * we have to complete all requests for ep if it was
1846 * halted, and the halt was cleared by CLEAR_FEATURE
1849 if (!set && halted) {
1851 * If we have request in progress,
1857 list_del_init(&hs_req->queue);
1858 if (hs_req->req.complete) {
1859 spin_unlock(&hsotg->lock);
1860 usb_gadget_giveback_request(
1861 &ep->ep, &hs_req->req);
1862 spin_lock(&hsotg->lock);
1866 /* If we have pending request, then start it */
1868 dwc2_gadget_start_next_request(ep);
1883 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1886 * dwc2_hsotg_stall_ep0 - stall ep0
1887 * @hsotg: The device state
1889 * Set stall for ep0 as response for setup request.
1891 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1893 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1897 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1898 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1901 * DxEPCTL_Stall will be cleared by EP once it has
1902 * taken effect, so no need to clear later.
1905 ctrl = dwc2_readl(hsotg, reg);
1906 ctrl |= DXEPCTL_STALL;
1907 ctrl |= DXEPCTL_CNAK;
1908 dwc2_writel(hsotg, ctrl, reg);
1911 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1912 ctrl, reg, dwc2_readl(hsotg, reg));
1915 * complete won't be called, so we enqueue
1916 * setup request here
1918 dwc2_hsotg_enqueue_setup(hsotg);
1922 * dwc2_hsotg_process_control - process a control request
1923 * @hsotg: The device state
1924 * @ctrl: The control request received
1926 * The controller has received the SETUP phase of a control request, and
1927 * needs to work out what to do next (and whether to pass it on to the
1930 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1931 struct usb_ctrlrequest *ctrl)
1933 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1938 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1939 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1940 ctrl->wIndex, ctrl->wLength);
1942 if (ctrl->wLength == 0) {
1944 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1945 } else if (ctrl->bRequestType & USB_DIR_IN) {
1947 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1950 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1953 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1954 switch (ctrl->bRequest) {
1955 case USB_REQ_SET_ADDRESS:
1956 hsotg->connected = 1;
1957 dcfg = dwc2_readl(hsotg, DCFG);
1958 dcfg &= ~DCFG_DEVADDR_MASK;
1959 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1960 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1961 dwc2_writel(hsotg, dcfg, DCFG);
1963 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1965 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1968 case USB_REQ_GET_STATUS:
1969 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1972 case USB_REQ_CLEAR_FEATURE:
1973 case USB_REQ_SET_FEATURE:
1974 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1979 /* as a fallback, try delivering it to the driver to deal with */
1981 if (ret == 0 && hsotg->driver) {
1982 spin_unlock(&hsotg->lock);
1983 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1984 spin_lock(&hsotg->lock);
1986 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1989 hsotg->delayed_status = false;
1990 if (ret == USB_GADGET_DELAYED_STATUS)
1991 hsotg->delayed_status = true;
1994 * the request is either unhandlable, or is not formatted correctly
1995 * so respond with a STALL for the status stage to indicate failure.
1999 dwc2_hsotg_stall_ep0(hsotg);
2003 * dwc2_hsotg_complete_setup - completion of a setup transfer
2004 * @ep: The endpoint the request was on.
2005 * @req: The request completed.
2007 * Called on completion of any requests the driver itself submitted for
2010 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2011 struct usb_request *req)
2013 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2014 struct dwc2_hsotg *hsotg = hs_ep->parent;
2016 if (req->status < 0) {
2017 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2021 spin_lock(&hsotg->lock);
2022 if (req->actual == 0)
2023 dwc2_hsotg_enqueue_setup(hsotg);
2025 dwc2_hsotg_process_control(hsotg, req->buf);
2026 spin_unlock(&hsotg->lock);
2030 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2031 * @hsotg: The device state.
2033 * Enqueue a request on EP0 if necessary to received any SETUP packets
2034 * received from the host.
2036 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2038 struct usb_request *req = hsotg->ctrl_req;
2039 struct dwc2_hsotg_req *hs_req = our_req(req);
2042 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2046 req->buf = hsotg->ctrl_buff;
2047 req->complete = dwc2_hsotg_complete_setup;
2049 if (!list_empty(&hs_req->queue)) {
2050 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2054 hsotg->eps_out[0]->dir_in = 0;
2055 hsotg->eps_out[0]->send_zlp = 0;
2056 hsotg->ep0_state = DWC2_EP0_SETUP;
2058 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2060 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2062 * Don't think there's much we can do other than watch the
2068 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2069 struct dwc2_hsotg_ep *hs_ep)
2072 u8 index = hs_ep->index;
2073 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2074 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2077 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2080 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2082 if (using_desc_dma(hsotg)) {
2083 /* Not specific buffer needed for ep0 ZLP */
2084 dma_addr_t dma = hs_ep->desc_list_dma;
2087 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2089 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2091 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2092 DXEPTSIZ_XFERSIZE(0),
2096 ctrl = dwc2_readl(hsotg, epctl_reg);
2097 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2098 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2099 ctrl |= DXEPCTL_USBACTEP;
2100 dwc2_writel(hsotg, ctrl, epctl_reg);
2104 * dwc2_hsotg_complete_request - complete a request given to us
2105 * @hsotg: The device state.
2106 * @hs_ep: The endpoint the request was on.
2107 * @hs_req: The request to complete.
2108 * @result: The result code (0 => Ok, otherwise errno)
2110 * The given request has finished, so call the necessary completion
2111 * if it has one and then look to see if we can start a new request
2114 * Note, expects the ep to already be locked as appropriate.
2116 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2117 struct dwc2_hsotg_ep *hs_ep,
2118 struct dwc2_hsotg_req *hs_req,
2122 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2126 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2127 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2130 * only replace the status if we've not already set an error
2131 * from a previous transaction
2134 if (hs_req->req.status == -EINPROGRESS)
2135 hs_req->req.status = result;
2137 if (using_dma(hsotg))
2138 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2140 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2143 list_del_init(&hs_req->queue);
2146 * call the complete request with the locks off, just in case the
2147 * request tries to queue more work for this endpoint.
2150 if (hs_req->req.complete) {
2151 spin_unlock(&hsotg->lock);
2152 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2153 spin_lock(&hsotg->lock);
2156 /* In DDMA don't need to proceed to starting of next ISOC request */
2157 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2161 * Look to see if there is anything else to do. Note, the completion
2162 * of the previous request may have caused a new request to be started
2163 * so be careful when doing this.
2166 if (!hs_ep->req && result >= 0)
2167 dwc2_gadget_start_next_request(hs_ep);
2171 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2172 * @hs_ep: The endpoint the request was on.
2174 * Get first request from the ep queue, determine descriptor on which complete
2175 * happened. SW discovers which descriptor currently in use by HW, adjusts
2176 * dma_address and calculates index of completed descriptor based on the value
2177 * of DEPDMA register. Update actual length of request, giveback to gadget.
2179 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2181 struct dwc2_hsotg *hsotg = hs_ep->parent;
2182 struct dwc2_hsotg_req *hs_req;
2183 struct usb_request *ureq;
2187 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2189 /* Process only descriptors with buffer status set to DMA done */
2190 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2191 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2193 hs_req = get_ep_head(hs_ep);
2195 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2198 ureq = &hs_req->req;
2200 /* Check completion status */
2201 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2203 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2204 DEV_DMA_ISOC_RX_NBYTES_MASK;
2205 ureq->actual = ureq->length - ((desc_sts & mask) >>
2206 DEV_DMA_ISOC_NBYTES_SHIFT);
2208 /* Adjust actual len for ISOC Out if len is
2211 if (!hs_ep->dir_in && ureq->length & 0x3)
2212 ureq->actual += 4 - (ureq->length & 0x3);
2214 /* Set actual frame number for completed transfers */
2215 ureq->frame_number =
2216 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2217 DEV_DMA_ISOC_FRNUM_SHIFT;
2220 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2222 hs_ep->compl_desc++;
2223 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2224 hs_ep->compl_desc = 0;
2225 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2230 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2231 * @hs_ep: The isochronous endpoint.
2233 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2234 * interrupt. Reset target frame and next_desc to allow to start
2235 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2236 * interrupt for OUT direction.
2238 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2240 struct dwc2_hsotg *hsotg = hs_ep->parent;
2243 dwc2_flush_rx_fifo(hsotg);
2244 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2246 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2247 hs_ep->next_desc = 0;
2248 hs_ep->compl_desc = 0;
2252 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2253 * @hsotg: The device state.
2254 * @ep_idx: The endpoint index for the data
2255 * @size: The size of data in the fifo, in bytes
2257 * The FIFO status shows there is data to read from the FIFO for a given
2258 * endpoint, so sort out whether we need to read the data into a request
2259 * that has been made for that endpoint.
2261 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2263 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2264 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2270 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2274 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2275 __func__, size, ep_idx, epctl);
2277 /* dump the data from the FIFO, we've nothing we can do */
2278 for (ptr = 0; ptr < size; ptr += 4)
2279 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2285 read_ptr = hs_req->req.actual;
2286 max_req = hs_req->req.length - read_ptr;
2288 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2289 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2291 if (to_read > max_req) {
2293 * more data appeared than we where willing
2294 * to deal with in this request.
2297 /* currently we don't deal this */
2301 hs_ep->total_data += to_read;
2302 hs_req->req.actual += to_read;
2303 to_read = DIV_ROUND_UP(to_read, 4);
2306 * note, we might over-write the buffer end by 3 bytes depending on
2307 * alignment of the data.
2309 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2310 hs_req->req.buf + read_ptr, to_read);
2314 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2315 * @hsotg: The device instance
2316 * @dir_in: If IN zlp
2318 * Generate a zero-length IN packet request for terminating a SETUP
2321 * Note, since we don't write any data to the TxFIFO, then it is
2322 * currently believed that we do not need to wait for any space in
2325 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2327 /* eps_out[0] is used in both directions */
2328 hsotg->eps_out[0]->dir_in = dir_in;
2329 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2331 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2335 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2336 * @hs_ep - The endpoint on which transfer went
2338 * Iterate over endpoints descriptor chain and get info on bytes remained
2339 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2341 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2343 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2344 struct dwc2_hsotg *hsotg = hs_ep->parent;
2345 unsigned int bytes_rem = 0;
2346 unsigned int bytes_rem_correction = 0;
2347 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2350 u32 mps = hs_ep->ep.maxpacket;
2351 int dir_in = hs_ep->dir_in;
2356 /* Interrupt OUT EP with mps not multiple of 4 */
2358 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2359 bytes_rem_correction = 4 - (mps % 4);
2361 for (i = 0; i < hs_ep->desc_count; ++i) {
2362 status = desc->status;
2363 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2364 bytes_rem -= bytes_rem_correction;
2366 if (status & DEV_DMA_STS_MASK)
2367 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2368 i, status & DEV_DMA_STS_MASK);
2370 if (status & DEV_DMA_L)
2380 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2381 * @hsotg: The device instance
2382 * @epnum: The endpoint received from
2384 * The RXFIFO has delivered an OutDone event, which means that the data
2385 * transfer for an OUT endpoint has been completed, either by a short
2386 * packet or by the finish of a transfer.
2388 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2390 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2391 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2392 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2393 struct usb_request *req = &hs_req->req;
2394 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2398 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2402 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2403 dev_dbg(hsotg->dev, "zlp packet received\n");
2404 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2405 dwc2_hsotg_enqueue_setup(hsotg);
2409 if (using_desc_dma(hsotg))
2410 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2412 if (using_dma(hsotg)) {
2413 unsigned int size_done;
2416 * Calculate the size of the transfer by checking how much
2417 * is left in the endpoint size register and then working it
2418 * out from the amount we loaded for the transfer.
2420 * We need to do this as DMA pointers are always 32bit aligned
2421 * so may overshoot/undershoot the transfer.
2424 size_done = hs_ep->size_loaded - size_left;
2425 size_done += hs_ep->last_load;
2427 req->actual = size_done;
2430 /* if there is more request to do, schedule new transfer */
2431 if (req->actual < req->length && size_left == 0) {
2432 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2436 if (req->actual < req->length && req->short_not_ok) {
2437 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2438 __func__, req->actual, req->length);
2441 * todo - what should we return here? there's no one else
2442 * even bothering to check the status.
2446 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2447 if (!using_desc_dma(hsotg) && epnum == 0 &&
2448 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2449 /* Move to STATUS IN */
2450 if (!hsotg->delayed_status)
2451 dwc2_hsotg_ep0_zlp(hsotg, true);
2454 /* Set actual frame number for completed transfers */
2455 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2456 req->frame_number = hs_ep->target_frame;
2457 dwc2_gadget_incr_frame_num(hs_ep);
2460 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2464 * dwc2_hsotg_handle_rx - RX FIFO has data
2465 * @hsotg: The device instance
2467 * The IRQ handler has detected that the RX FIFO has some data in it
2468 * that requires processing, so find out what is in there and do the
2471 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2472 * chunks, so if you have x packets received on an endpoint you'll get x
2473 * FIFO events delivered, each with a packet's worth of data in it.
2475 * When using DMA, we should not be processing events from the RXFIFO
2476 * as the actual data should be sent to the memory directly and we turn
2477 * on the completion interrupts to get notifications of transfer completion.
2479 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2481 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2482 u32 epnum, status, size;
2484 WARN_ON(using_dma(hsotg));
2486 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2487 status = grxstsr & GRXSTS_PKTSTS_MASK;
2489 size = grxstsr & GRXSTS_BYTECNT_MASK;
2490 size >>= GRXSTS_BYTECNT_SHIFT;
2492 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2493 __func__, grxstsr, size, epnum);
2495 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2496 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2497 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2500 case GRXSTS_PKTSTS_OUTDONE:
2501 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2502 dwc2_hsotg_read_frameno(hsotg));
2504 if (!using_dma(hsotg))
2505 dwc2_hsotg_handle_outdone(hsotg, epnum);
2508 case GRXSTS_PKTSTS_SETUPDONE:
2510 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2511 dwc2_hsotg_read_frameno(hsotg),
2512 dwc2_readl(hsotg, DOEPCTL(0)));
2514 * Call dwc2_hsotg_handle_outdone here if it was not called from
2515 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2516 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2518 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2519 dwc2_hsotg_handle_outdone(hsotg, epnum);
2522 case GRXSTS_PKTSTS_OUTRX:
2523 dwc2_hsotg_rx_data(hsotg, epnum, size);
2526 case GRXSTS_PKTSTS_SETUPRX:
2528 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2529 dwc2_hsotg_read_frameno(hsotg),
2530 dwc2_readl(hsotg, DOEPCTL(0)));
2532 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2534 dwc2_hsotg_rx_data(hsotg, epnum, size);
2538 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2541 dwc2_hsotg_dump(hsotg);
2547 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2548 * @mps: The maximum packet size in bytes.
2550 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2554 return D0EPCTL_MPS_64;
2556 return D0EPCTL_MPS_32;
2558 return D0EPCTL_MPS_16;
2560 return D0EPCTL_MPS_8;
2563 /* bad max packet size, warn and return invalid result */
2569 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2570 * @hsotg: The driver state.
2571 * @ep: The index number of the endpoint
2572 * @mps: The maximum packet size in bytes
2573 * @mc: The multicount value
2574 * @dir_in: True if direction is in.
2576 * Configure the maximum packet size for the given endpoint, updating
2577 * the hardware control registers to reflect this.
2579 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2580 unsigned int ep, unsigned int mps,
2581 unsigned int mc, unsigned int dir_in)
2583 struct dwc2_hsotg_ep *hs_ep;
2586 hs_ep = index_to_ep(hsotg, ep, dir_in);
2591 u32 mps_bytes = mps;
2593 /* EP0 is a special case */
2594 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2597 hs_ep->ep.maxpacket = mps_bytes;
2605 hs_ep->ep.maxpacket = mps;
2609 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2610 reg &= ~DXEPCTL_MPS_MASK;
2612 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2614 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2615 reg &= ~DXEPCTL_MPS_MASK;
2617 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2623 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2627 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2628 * @hsotg: The driver state
2629 * @idx: The index for the endpoint (0..15)
2631 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2633 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2636 /* wait until the fifo is flushed */
2637 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2638 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2643 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2644 * @hsotg: The driver state
2645 * @hs_ep: The driver endpoint to check.
2647 * Check to see if there is a request that has data to send, and if so
2648 * make an attempt to write data into the FIFO.
2650 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2651 struct dwc2_hsotg_ep *hs_ep)
2653 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2655 if (!hs_ep->dir_in || !hs_req) {
2657 * if request is not enqueued, we disable interrupts
2658 * for endpoints, excepting ep0
2660 if (hs_ep->index != 0)
2661 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2666 if (hs_req->req.actual < hs_req->req.length) {
2667 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2669 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2676 * dwc2_hsotg_complete_in - complete IN transfer
2677 * @hsotg: The device state.
2678 * @hs_ep: The endpoint that has just completed.
2680 * An IN transfer has been completed, update the transfer's state and then
2681 * call the relevant completion routines.
2683 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2684 struct dwc2_hsotg_ep *hs_ep)
2686 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2687 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2688 int size_left, size_done;
2691 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2695 /* Finish ZLP handling for IN EP0 transactions */
2696 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2697 dev_dbg(hsotg->dev, "zlp packet sent\n");
2700 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2701 * changed to IN. Change back to complete OUT transfer request
2705 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2706 if (hsotg->test_mode) {
2709 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2711 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2713 dwc2_hsotg_stall_ep0(hsotg);
2717 dwc2_hsotg_enqueue_setup(hsotg);
2722 * Calculate the size of the transfer by checking how much is left
2723 * in the endpoint size register and then working it out from
2724 * the amount we loaded for the transfer.
2726 * We do this even for DMA, as the transfer may have incremented
2727 * past the end of the buffer (DMA transfers are always 32bit
2730 if (using_desc_dma(hsotg)) {
2731 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2733 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2736 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2739 size_done = hs_ep->size_loaded - size_left;
2740 size_done += hs_ep->last_load;
2742 if (hs_req->req.actual != size_done)
2743 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2744 __func__, hs_req->req.actual, size_done);
2746 hs_req->req.actual = size_done;
2747 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2748 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2750 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2751 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2752 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2756 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2757 if (hs_ep->send_zlp) {
2758 hs_ep->send_zlp = 0;
2759 if (!using_desc_dma(hsotg)) {
2760 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2761 /* transfer will be completed on next complete interrupt */
2766 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2767 /* Move to STATUS OUT */
2768 dwc2_hsotg_ep0_zlp(hsotg, false);
2772 /* Set actual frame number for completed transfers */
2773 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2774 hs_req->req.frame_number = hs_ep->target_frame;
2775 dwc2_gadget_incr_frame_num(hs_ep);
2778 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2782 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2783 * @hsotg: The device state.
2784 * @idx: Index of ep.
2785 * @dir_in: Endpoint direction 1-in 0-out.
2787 * Reads for endpoint with given index and direction, by masking
2788 * epint_reg with coresponding mask.
2790 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2791 unsigned int idx, int dir_in)
2793 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2794 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2799 mask = dwc2_readl(hsotg, epmsk_reg);
2800 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2801 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2802 mask |= DXEPINT_SETUP_RCVD;
2804 ints = dwc2_readl(hsotg, epint_reg);
2810 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2811 * @hs_ep: The endpoint on which interrupt is asserted.
2813 * This interrupt indicates that the endpoint has been disabled per the
2814 * application's request.
2816 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2817 * in case of ISOC completes current request.
2819 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2820 * request starts it.
2822 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2824 struct dwc2_hsotg *hsotg = hs_ep->parent;
2825 struct dwc2_hsotg_req *hs_req;
2826 unsigned char idx = hs_ep->index;
2827 int dir_in = hs_ep->dir_in;
2828 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2829 int dctl = dwc2_readl(hsotg, DCTL);
2831 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2834 int epctl = dwc2_readl(hsotg, epctl_reg);
2836 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2838 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2839 int dctl = dwc2_readl(hsotg, DCTL);
2841 dctl |= DCTL_CGNPINNAK;
2842 dwc2_writel(hsotg, dctl, DCTL);
2846 if (dctl & DCTL_GOUTNAKSTS) {
2847 dctl |= DCTL_CGOUTNAK;
2848 dwc2_writel(hsotg, dctl, DCTL);
2852 if (!hs_ep->isochronous)
2855 if (list_empty(&hs_ep->queue)) {
2856 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2862 hs_req = get_ep_head(hs_ep);
2864 hs_req->req.frame_number = hs_ep->target_frame;
2865 hs_req->req.actual = 0;
2866 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2869 dwc2_gadget_incr_frame_num(hs_ep);
2870 /* Update current frame number value. */
2871 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2872 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2876 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2877 * @ep: The endpoint on which interrupt is asserted.
2879 * This is starting point for ISOC-OUT transfer, synchronization done with
2880 * first out token received from host while corresponding EP is disabled.
2882 * Device does not know initial frame in which out token will come. For this
2883 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2884 * getting this interrupt SW starts calculation for next transfer frame.
2886 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2888 struct dwc2_hsotg *hsotg = ep->parent;
2889 struct dwc2_hsotg_req *hs_req;
2890 int dir_in = ep->dir_in;
2892 if (dir_in || !ep->isochronous)
2895 if (using_desc_dma(hsotg)) {
2896 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2897 /* Start first ISO Out */
2898 ep->target_frame = hsotg->frame_number;
2899 dwc2_gadget_start_isoc_ddma(ep);
2904 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2907 ep->target_frame = hsotg->frame_number;
2908 if (ep->interval > 1) {
2909 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2910 if (ep->target_frame & 0x1)
2911 ctrl |= DXEPCTL_SETODDFR;
2913 ctrl |= DXEPCTL_SETEVENFR;
2915 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2919 while (dwc2_gadget_target_frame_elapsed(ep)) {
2920 hs_req = get_ep_head(ep);
2922 hs_req->req.frame_number = ep->target_frame;
2923 hs_req->req.actual = 0;
2924 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2927 dwc2_gadget_incr_frame_num(ep);
2928 /* Update current frame number value. */
2929 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2933 dwc2_gadget_start_next_request(ep);
2937 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2938 struct dwc2_hsotg_ep *hs_ep);
2941 * dwc2_gadget_handle_nak - handle NAK interrupt
2942 * @hs_ep: The endpoint on which interrupt is asserted.
2944 * This is starting point for ISOC-IN transfer, synchronization done with
2945 * first IN token received from host while corresponding EP is disabled.
2947 * Device does not know when first one token will arrive from host. On first
2948 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2949 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2950 * sent in response to that as there was no data in FIFO. SW is basing on this
2951 * interrupt to obtain frame in which token has come and then based on the
2952 * interval calculates next frame for transfer.
2954 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2956 struct dwc2_hsotg *hsotg = hs_ep->parent;
2957 struct dwc2_hsotg_req *hs_req;
2958 int dir_in = hs_ep->dir_in;
2961 if (!dir_in || !hs_ep->isochronous)
2964 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2966 if (using_desc_dma(hsotg)) {
2967 hs_ep->target_frame = hsotg->frame_number;
2968 dwc2_gadget_incr_frame_num(hs_ep);
2970 /* In service interval mode target_frame must
2971 * be set to last (u)frame of the service interval.
2973 if (hsotg->params.service_interval) {
2974 /* Set target_frame to the first (u)frame of
2975 * the service interval
2977 hs_ep->target_frame &= ~hs_ep->interval + 1;
2979 /* Set target_frame to the last (u)frame of
2980 * the service interval
2982 dwc2_gadget_incr_frame_num(hs_ep);
2983 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2986 dwc2_gadget_start_isoc_ddma(hs_ep);
2990 hs_ep->target_frame = hsotg->frame_number;
2991 if (hs_ep->interval > 1) {
2992 u32 ctrl = dwc2_readl(hsotg,
2993 DIEPCTL(hs_ep->index));
2994 if (hs_ep->target_frame & 0x1)
2995 ctrl |= DXEPCTL_SETODDFR;
2997 ctrl |= DXEPCTL_SETEVENFR;
2999 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
3003 if (using_desc_dma(hsotg))
3006 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3007 if (ctrl & DXEPCTL_EPENA)
3008 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3010 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3012 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3013 hs_req = get_ep_head(hs_ep);
3015 hs_req->req.frame_number = hs_ep->target_frame;
3016 hs_req->req.actual = 0;
3017 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3020 dwc2_gadget_incr_frame_num(hs_ep);
3021 /* Update current frame number value. */
3022 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3026 dwc2_gadget_start_next_request(hs_ep);
3030 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3031 * @hsotg: The driver state
3032 * @idx: The index for the endpoint (0..15)
3033 * @dir_in: Set if this is an IN endpoint
3035 * Process and clear any interrupt pending for an individual endpoint
3037 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3040 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3041 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3042 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3043 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3046 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3048 /* Clear endpoint interrupts */
3049 dwc2_writel(hsotg, ints, epint_reg);
3052 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3053 __func__, idx, dir_in ? "in" : "out");
3057 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3058 __func__, idx, dir_in ? "in" : "out", ints);
3060 /* Don't process XferCompl interrupt if it is a setup packet */
3061 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3062 ints &= ~DXEPINT_XFERCOMPL;
3065 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3066 * stage and xfercomplete was generated without SETUP phase done
3067 * interrupt. SW should parse received setup packet only after host's
3068 * exit from setup phase of control transfer.
3070 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3071 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3072 ints &= ~DXEPINT_XFERCOMPL;
3074 if (ints & DXEPINT_XFERCOMPL) {
3076 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3077 __func__, dwc2_readl(hsotg, epctl_reg),
3078 dwc2_readl(hsotg, epsiz_reg));
3080 /* In DDMA handle isochronous requests separately */
3081 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3082 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3083 } else if (dir_in) {
3085 * We get OutDone from the FIFO, so we only
3086 * need to look at completing IN requests here
3087 * if operating slave mode
3089 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3090 dwc2_hsotg_complete_in(hsotg, hs_ep);
3092 if (idx == 0 && !hs_ep->req)
3093 dwc2_hsotg_enqueue_setup(hsotg);
3094 } else if (using_dma(hsotg)) {
3096 * We're using DMA, we need to fire an OutDone here
3097 * as we ignore the RXFIFO.
3099 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3100 dwc2_hsotg_handle_outdone(hsotg, idx);
3104 if (ints & DXEPINT_EPDISBLD)
3105 dwc2_gadget_handle_ep_disabled(hs_ep);
3107 if (ints & DXEPINT_OUTTKNEPDIS)
3108 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3110 if (ints & DXEPINT_NAKINTRPT)
3111 dwc2_gadget_handle_nak(hs_ep);
3113 if (ints & DXEPINT_AHBERR)
3114 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3116 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3117 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3119 if (using_dma(hsotg) && idx == 0) {
3121 * this is the notification we've received a
3122 * setup packet. In non-DMA mode we'd get this
3123 * from the RXFIFO, instead we need to process
3130 dwc2_hsotg_handle_outdone(hsotg, 0);
3134 if (ints & DXEPINT_STSPHSERCVD) {
3135 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3137 /* Safety check EP0 state when STSPHSERCVD asserted */
3138 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3139 /* Move to STATUS IN for DDMA */
3140 if (using_desc_dma(hsotg)) {
3141 if (!hsotg->delayed_status)
3142 dwc2_hsotg_ep0_zlp(hsotg, true);
3144 /* In case of 3 stage Control Write with delayed
3145 * status, when Status IN transfer started
3146 * before STSPHSERCVD asserted, NAKSTS bit not
3147 * cleared by CNAK in dwc2_hsotg_start_req()
3148 * function. Clear now NAKSTS to allow complete
3151 dwc2_set_bit(hsotg, DIEPCTL(0),
3158 if (ints & DXEPINT_BACK2BACKSETUP)
3159 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3161 if (ints & DXEPINT_BNAINTR) {
3162 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3163 if (hs_ep->isochronous)
3164 dwc2_gadget_handle_isoc_bna(hs_ep);
3167 if (dir_in && !hs_ep->isochronous) {
3168 /* not sure if this is important, but we'll clear it anyway */
3169 if (ints & DXEPINT_INTKNTXFEMP) {
3170 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3174 /* this probably means something bad is happening */
3175 if (ints & DXEPINT_INTKNEPMIS) {
3176 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3180 /* FIFO has space or is empty (see GAHBCFG) */
3181 if (hsotg->dedicated_fifos &&
3182 ints & DXEPINT_TXFEMP) {
3183 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3185 if (!using_dma(hsotg))
3186 dwc2_hsotg_trytx(hsotg, hs_ep);
3192 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3193 * @hsotg: The device state.
3195 * Handle updating the device settings after the enumeration phase has
3198 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3200 u32 dsts = dwc2_readl(hsotg, DSTS);
3201 int ep0_mps = 0, ep_mps = 8;
3204 * This should signal the finish of the enumeration phase
3205 * of the USB handshaking, so we should now know what rate
3209 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3212 * note, since we're limited by the size of transfer on EP0, and
3213 * it seems IN transfers must be a even number of packets we do
3214 * not advertise a 64byte MPS on EP0.
3217 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3218 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3219 case DSTS_ENUMSPD_FS:
3220 case DSTS_ENUMSPD_FS48:
3221 hsotg->gadget.speed = USB_SPEED_FULL;
3222 ep0_mps = EP0_MPS_LIMIT;
3226 case DSTS_ENUMSPD_HS:
3227 hsotg->gadget.speed = USB_SPEED_HIGH;
3228 ep0_mps = EP0_MPS_LIMIT;
3232 case DSTS_ENUMSPD_LS:
3233 hsotg->gadget.speed = USB_SPEED_LOW;
3237 * note, we don't actually support LS in this driver at the
3238 * moment, and the documentation seems to imply that it isn't
3239 * supported by the PHYs on some of the devices.
3243 dev_info(hsotg->dev, "new device is %s\n",
3244 usb_speed_string(hsotg->gadget.speed));
3247 * we should now know the maximum packet size for an
3248 * endpoint, so set the endpoints to a default value.
3253 /* Initialize ep0 for both in and out directions */
3254 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3255 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3256 for (i = 1; i < hsotg->num_of_eps; i++) {
3257 if (hsotg->eps_in[i])
3258 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3260 if (hsotg->eps_out[i])
3261 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3266 /* ensure after enumeration our EP0 is active */
3268 dwc2_hsotg_enqueue_setup(hsotg);
3270 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3271 dwc2_readl(hsotg, DIEPCTL0),
3272 dwc2_readl(hsotg, DOEPCTL0));
3276 * kill_all_requests - remove all requests from the endpoint's queue
3277 * @hsotg: The device state.
3278 * @ep: The endpoint the requests may be on.
3279 * @result: The result code to use.
3281 * Go through the requests on the given endpoint and mark them
3282 * completed with the given result code.
3284 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3285 struct dwc2_hsotg_ep *ep,
3292 while (!list_empty(&ep->queue)) {
3293 struct dwc2_hsotg_req *req = get_ep_head(ep);
3295 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3298 if (!hsotg->dedicated_fifos)
3300 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3301 if (size < ep->fifo_size)
3302 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3306 * dwc2_hsotg_disconnect - disconnect service
3307 * @hsotg: The device state.
3309 * The device has been disconnected. Remove all current
3310 * transactions and signal the gadget driver that this
3313 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3317 if (!hsotg->connected)
3320 hsotg->connected = 0;
3321 hsotg->test_mode = 0;
3323 /* all endpoints should be shutdown */
3324 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3325 if (hsotg->eps_in[ep])
3326 kill_all_requests(hsotg, hsotg->eps_in[ep],
3328 if (hsotg->eps_out[ep])
3329 kill_all_requests(hsotg, hsotg->eps_out[ep],
3333 call_gadget(hsotg, disconnect);
3334 hsotg->lx_state = DWC2_L3;
3336 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3340 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3341 * @hsotg: The device state:
3342 * @periodic: True if this is a periodic FIFO interrupt
3344 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3346 struct dwc2_hsotg_ep *ep;
3349 /* look through for any more data to transmit */
3350 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3351 ep = index_to_ep(hsotg, epno, 1);
3359 if ((periodic && !ep->periodic) ||
3360 (!periodic && ep->periodic))
3363 ret = dwc2_hsotg_trytx(hsotg, ep);
3369 /* IRQ flags which will trigger a retry around the IRQ loop */
3370 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3374 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3376 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3377 * @hsotg: The device state
3378 * @is_usb_reset: Usb resetting flag
3380 * Issue a soft reset to the core, and await the core finishing it.
3382 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3391 /* Kill any ep0 requests as controller will be reinitialized */
3392 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3394 if (!is_usb_reset) {
3395 if (dwc2_core_reset(hsotg, true))
3398 /* all endpoints should be shutdown */
3399 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3400 if (hsotg->eps_in[ep])
3401 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3402 if (hsotg->eps_out[ep])
3403 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3408 * we must now enable ep0 ready for host detection and then
3409 * set configuration.
3412 /* keep other bits untouched (so e.g. forced modes are not lost) */
3413 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3414 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3415 usbcfg |= GUSBCFG_TOUTCAL(7);
3417 /* remove the HNP/SRP and set the PHY */
3418 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3419 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3421 dwc2_phy_init(hsotg, true);
3423 dwc2_hsotg_init_fifo(hsotg);
3426 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3428 dcfg |= DCFG_EPMISCNT(1);
3430 switch (hsotg->params.speed) {
3431 case DWC2_SPEED_PARAM_LOW:
3432 dcfg |= DCFG_DEVSPD_LS;
3434 case DWC2_SPEED_PARAM_FULL:
3435 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3436 dcfg |= DCFG_DEVSPD_FS48;
3438 dcfg |= DCFG_DEVSPD_FS;
3441 dcfg |= DCFG_DEVSPD_HS;
3444 if (hsotg->params.ipg_isoc_en)
3445 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3447 dwc2_writel(hsotg, dcfg, DCFG);
3449 /* Clear any pending OTG interrupts */
3450 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3452 /* Clear any pending interrupts */
3453 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3454 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3455 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3456 GINTSTS_USBRST | GINTSTS_RESETDET |
3457 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3458 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3459 GINTSTS_LPMTRANRCVD;
3461 if (!using_desc_dma(hsotg))
3462 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3464 if (!hsotg->params.external_id_pin_ctl)
3465 intmsk |= GINTSTS_CONIDSTSCHNG;
3467 dwc2_writel(hsotg, intmsk, GINTMSK);
3469 if (using_dma(hsotg)) {
3470 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3471 hsotg->params.ahbcfg,
3474 /* Set DDMA mode support in the core if needed */
3475 if (using_desc_dma(hsotg))
3476 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3479 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3480 (GAHBCFG_NP_TXF_EMP_LVL |
3481 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3482 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3486 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3487 * when we have no data to transfer. Otherwise we get being flooded by
3491 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3492 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3493 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3494 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3498 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3499 * DMA mode we may need this and StsPhseRcvd.
3501 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3502 DOEPMSK_STSPHSERCVDMSK) : 0) |
3503 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3507 /* Enable BNA interrupt for DDMA */
3508 if (using_desc_dma(hsotg)) {
3509 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3510 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3513 /* Enable Service Interval mode if supported */
3514 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3515 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3517 dwc2_writel(hsotg, 0, DAINTMSK);
3519 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3520 dwc2_readl(hsotg, DIEPCTL0),
3521 dwc2_readl(hsotg, DOEPCTL0));
3523 /* enable in and out endpoint interrupts */
3524 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3527 * Enable the RXFIFO when in slave mode, as this is how we collect
3528 * the data. In DMA mode, we get events from the FIFO but also
3529 * things we cannot process, so do not use it.
3531 if (!using_dma(hsotg))
3532 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3534 /* Enable interrupts for EP0 in and out */
3535 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3536 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3538 if (!is_usb_reset) {
3539 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3540 udelay(10); /* see openiboot */
3541 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3544 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3547 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3548 * writing to the EPCTL register..
3551 /* set to read 1 8byte packet */
3552 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3553 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3555 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3556 DXEPCTL_CNAK | DXEPCTL_EPENA |
3560 /* enable, but don't activate EP0in */
3561 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3562 DXEPCTL_USBACTEP, DIEPCTL0);
3564 /* clear global NAKs */
3565 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3567 val |= DCTL_SFTDISCON;
3568 dwc2_set_bit(hsotg, DCTL, val);
3570 /* configure the core to support LPM */
3571 dwc2_gadget_init_lpm(hsotg);
3573 /* program GREFCLK register if needed */
3574 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3575 dwc2_gadget_program_ref_clk(hsotg);
3577 /* must be at-least 3ms to allow bus to see disconnect */
3580 hsotg->lx_state = DWC2_L0;
3582 dwc2_hsotg_enqueue_setup(hsotg);
3584 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3585 dwc2_readl(hsotg, DIEPCTL0),
3586 dwc2_readl(hsotg, DOEPCTL0));
3589 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3591 /* set the soft-disconnect bit */
3592 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3595 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3597 /* remove the soft-disconnect and let's go */
3598 if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3599 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3603 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3604 * @hsotg: The device state:
3606 * This interrupt indicates one of the following conditions occurred while
3607 * transmitting an ISOC transaction.
3608 * - Corrupted IN Token for ISOC EP.
3609 * - Packet not complete in FIFO.
3611 * The following actions will be taken:
3612 * - Determine the EP
3613 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3615 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3617 struct dwc2_hsotg_ep *hs_ep;
3622 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3624 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3626 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3627 hs_ep = hsotg->eps_in[idx];
3628 /* Proceed only unmasked ISOC EPs */
3629 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3632 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3633 if ((epctrl & DXEPCTL_EPENA) &&
3634 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3635 epctrl |= DXEPCTL_SNAK;
3636 epctrl |= DXEPCTL_EPDIS;
3637 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3641 /* Clear interrupt */
3642 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3646 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3647 * @hsotg: The device state:
3649 * This interrupt indicates one of the following conditions occurred while
3650 * transmitting an ISOC transaction.
3651 * - Corrupted OUT Token for ISOC EP.
3652 * - Packet not complete in FIFO.
3654 * The following actions will be taken:
3655 * - Determine the EP
3656 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3658 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3664 struct dwc2_hsotg_ep *hs_ep;
3667 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3669 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3670 daintmsk >>= DAINT_OUTEP_SHIFT;
3672 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3673 hs_ep = hsotg->eps_out[idx];
3674 /* Proceed only unmasked ISOC EPs */
3675 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3678 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3679 if ((epctrl & DXEPCTL_EPENA) &&
3680 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3681 /* Unmask GOUTNAKEFF interrupt */
3682 gintmsk = dwc2_readl(hsotg, GINTMSK);
3683 gintmsk |= GINTSTS_GOUTNAKEFF;
3684 dwc2_writel(hsotg, gintmsk, GINTMSK);
3686 gintsts = dwc2_readl(hsotg, GINTSTS);
3687 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3688 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3694 /* Clear interrupt */
3695 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3699 * dwc2_hsotg_irq - handle device interrupt
3700 * @irq: The IRQ number triggered
3701 * @pw: The pw value when registered the handler.
3703 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3705 struct dwc2_hsotg *hsotg = pw;
3706 int retry_count = 8;
3710 if (!dwc2_is_device_mode(hsotg))
3713 spin_lock(&hsotg->lock);
3715 gintsts = dwc2_readl(hsotg, GINTSTS);
3716 gintmsk = dwc2_readl(hsotg, GINTMSK);
3718 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3719 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3723 if (gintsts & GINTSTS_RESETDET) {
3724 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3726 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3728 /* This event must be used only if controller is suspended */
3729 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3730 dwc2_exit_partial_power_down(hsotg, 0, true);
3732 hsotg->lx_state = DWC2_L0;
3735 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3736 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3737 u32 connected = hsotg->connected;
3739 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3740 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3741 dwc2_readl(hsotg, GNPTXSTS));
3743 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3745 /* Report disconnection if it is not already done. */
3746 dwc2_hsotg_disconnect(hsotg);
3748 /* Reset device address to zero */
3749 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3751 if (usb_status & GOTGCTL_BSESVLD && connected)
3752 dwc2_hsotg_core_init_disconnected(hsotg, true);
3755 if (gintsts & GINTSTS_ENUMDONE) {
3756 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3758 dwc2_hsotg_irq_enumdone(hsotg);
3761 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3762 u32 daint = dwc2_readl(hsotg, DAINT);
3763 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3764 u32 daint_out, daint_in;
3768 daint_out = daint >> DAINT_OUTEP_SHIFT;
3769 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3771 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3773 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3774 ep++, daint_out >>= 1) {
3776 dwc2_hsotg_epint(hsotg, ep, 0);
3779 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3780 ep++, daint_in >>= 1) {
3782 dwc2_hsotg_epint(hsotg, ep, 1);
3786 /* check both FIFOs */
3788 if (gintsts & GINTSTS_NPTXFEMP) {
3789 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3792 * Disable the interrupt to stop it happening again
3793 * unless one of these endpoint routines decides that
3794 * it needs re-enabling
3797 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3798 dwc2_hsotg_irq_fifoempty(hsotg, false);
3801 if (gintsts & GINTSTS_PTXFEMP) {
3802 dev_dbg(hsotg->dev, "PTxFEmp\n");
3804 /* See note in GINTSTS_NPTxFEmp */
3806 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3807 dwc2_hsotg_irq_fifoempty(hsotg, true);
3810 if (gintsts & GINTSTS_RXFLVL) {
3812 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3813 * we need to retry dwc2_hsotg_handle_rx if this is still
3817 dwc2_hsotg_handle_rx(hsotg);
3820 if (gintsts & GINTSTS_ERLYSUSP) {
3821 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3822 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3826 * these next two seem to crop-up occasionally causing the core
3827 * to shutdown the USB transfer, so try clearing them and logging
3831 if (gintsts & GINTSTS_GOUTNAKEFF) {
3836 struct dwc2_hsotg_ep *hs_ep;
3838 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3839 daintmsk >>= DAINT_OUTEP_SHIFT;
3840 /* Mask this interrupt */
3841 gintmsk = dwc2_readl(hsotg, GINTMSK);
3842 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3843 dwc2_writel(hsotg, gintmsk, GINTMSK);
3845 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3846 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3847 hs_ep = hsotg->eps_out[idx];
3848 /* Proceed only unmasked ISOC EPs */
3849 if (BIT(idx) & ~daintmsk)
3852 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3855 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3856 epctrl |= DXEPCTL_SNAK;
3857 epctrl |= DXEPCTL_EPDIS;
3858 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3863 if (hs_ep->halted) {
3864 if (!(epctrl & DXEPCTL_EPENA))
3865 epctrl |= DXEPCTL_EPENA;
3866 epctrl |= DXEPCTL_EPDIS;
3867 epctrl |= DXEPCTL_STALL;
3868 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3872 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3875 if (gintsts & GINTSTS_GINNAKEFF) {
3876 dev_info(hsotg->dev, "GINNakEff triggered\n");
3878 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3880 dwc2_hsotg_dump(hsotg);
3883 if (gintsts & GINTSTS_INCOMPL_SOIN)
3884 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3886 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3887 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3890 * if we've had fifo events, we should try and go around the
3891 * loop again to see if there's any point in returning yet.
3894 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3897 /* Check WKUP_ALERT interrupt*/
3898 if (hsotg->params.service_interval)
3899 dwc2_gadget_wkup_alert_handler(hsotg);
3901 spin_unlock(&hsotg->lock);
3906 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3907 struct dwc2_hsotg_ep *hs_ep)
3912 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3913 DOEPCTL(hs_ep->index);
3914 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3915 DOEPINT(hs_ep->index);
3917 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3920 if (hs_ep->dir_in) {
3921 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3922 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3923 /* Wait for Nak effect */
3924 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3925 DXEPINT_INEPNAKEFF, 100))
3926 dev_warn(hsotg->dev,
3927 "%s: timeout DIEPINT.NAKEFF\n",
3930 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3931 /* Wait for Nak effect */
3932 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3933 GINTSTS_GINNAKEFF, 100))
3934 dev_warn(hsotg->dev,
3935 "%s: timeout GINTSTS.GINNAKEFF\n",
3939 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3940 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3942 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3943 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3945 if (!using_dma(hsotg)) {
3946 /* Wait for GINTSTS_RXFLVL interrupt */
3947 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3948 GINTSTS_RXFLVL, 100)) {
3949 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3953 * Pop GLOBAL OUT NAK status packet from RxFIFO
3954 * to assert GOUTNAKEFF interrupt
3956 dwc2_readl(hsotg, GRXSTSP);
3960 /* Wait for global nak to take effect */
3961 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3962 GINTSTS_GOUTNAKEFF, 100))
3963 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3968 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3970 /* Wait for ep to be disabled */
3971 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3972 dev_warn(hsotg->dev,
3973 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3975 /* Clear EPDISBLD interrupt */
3976 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3978 if (hs_ep->dir_in) {
3979 unsigned short fifo_index;
3981 if (hsotg->dedicated_fifos || hs_ep->periodic)
3982 fifo_index = hs_ep->fifo_index;
3987 dwc2_flush_tx_fifo(hsotg, fifo_index);
3989 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3990 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3991 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3994 /* Remove global NAKs */
3995 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
4000 * dwc2_hsotg_ep_enable - enable the given endpoint
4001 * @ep: The USB endpint to configure
4002 * @desc: The USB endpoint descriptor to configure with.
4004 * This is called from the USB gadget code's usb_ep_enable().
4006 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
4007 const struct usb_endpoint_descriptor *desc)
4009 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4010 struct dwc2_hsotg *hsotg = hs_ep->parent;
4011 unsigned long flags;
4012 unsigned int index = hs_ep->index;
4018 unsigned int dir_in;
4019 unsigned int i, val, size;
4021 unsigned char ep_type;
4025 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4026 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4027 desc->wMaxPacketSize, desc->bInterval);
4029 /* not to be called for EP0 */
4031 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4035 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4036 if (dir_in != hs_ep->dir_in) {
4037 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4041 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4042 mps = usb_endpoint_maxp(desc);
4043 mc = usb_endpoint_maxp_mult(desc);
4045 /* ISOC IN in DDMA supported bInterval up to 10 */
4046 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4047 dir_in && desc->bInterval > 10) {
4049 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4053 /* High bandwidth ISOC OUT in DDMA not supported */
4054 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4055 !dir_in && mc > 1) {
4057 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4061 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4063 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4064 epctrl = dwc2_readl(hsotg, epctrl_reg);
4066 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4067 __func__, epctrl, epctrl_reg);
4069 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4070 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4072 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4074 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4075 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4076 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4077 desc_num * sizeof(struct dwc2_dma_desc),
4078 &hs_ep->desc_list_dma, GFP_ATOMIC);
4079 if (!hs_ep->desc_list) {
4085 spin_lock_irqsave(&hsotg->lock, flags);
4087 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4088 epctrl |= DXEPCTL_MPS(mps);
4091 * mark the endpoint as active, otherwise the core may ignore
4092 * transactions entirely for this endpoint
4094 epctrl |= DXEPCTL_USBACTEP;
4096 /* update the endpoint state */
4097 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4099 /* default, set to non-periodic */
4100 hs_ep->isochronous = 0;
4101 hs_ep->periodic = 0;
4104 hs_ep->interval = desc->bInterval;
4107 case USB_ENDPOINT_XFER_ISOC:
4108 epctrl |= DXEPCTL_EPTYPE_ISO;
4109 epctrl |= DXEPCTL_SETEVENFR;
4110 hs_ep->isochronous = 1;
4111 hs_ep->interval = 1 << (desc->bInterval - 1);
4112 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4113 hs_ep->next_desc = 0;
4114 hs_ep->compl_desc = 0;
4116 hs_ep->periodic = 1;
4117 mask = dwc2_readl(hsotg, DIEPMSK);
4118 mask |= DIEPMSK_NAKMSK;
4119 dwc2_writel(hsotg, mask, DIEPMSK);
4121 epctrl |= DXEPCTL_SNAK;
4122 mask = dwc2_readl(hsotg, DOEPMSK);
4123 mask |= DOEPMSK_OUTTKNEPDISMSK;
4124 dwc2_writel(hsotg, mask, DOEPMSK);
4128 case USB_ENDPOINT_XFER_BULK:
4129 epctrl |= DXEPCTL_EPTYPE_BULK;
4132 case USB_ENDPOINT_XFER_INT:
4134 hs_ep->periodic = 1;
4136 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4137 hs_ep->interval = 1 << (desc->bInterval - 1);
4139 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4142 case USB_ENDPOINT_XFER_CONTROL:
4143 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4148 * if the hardware has dedicated fifos, we must give each IN EP
4149 * a unique tx-fifo even if it is non-periodic.
4151 if (dir_in && hsotg->dedicated_fifos) {
4152 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4154 u32 fifo_size = UINT_MAX;
4156 size = hs_ep->ep.maxpacket * hs_ep->mc;
4157 for (i = 1; i <= fifo_count; ++i) {
4158 if (hsotg->fifo_map & (1 << i))
4160 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4161 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4164 /* Search for smallest acceptable fifo */
4165 if (val < fifo_size) {
4172 "%s: No suitable fifo found\n", __func__);
4176 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4177 hsotg->fifo_map |= 1 << fifo_index;
4178 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4179 hs_ep->fifo_index = fifo_index;
4180 hs_ep->fifo_size = fifo_size;
4183 /* for non control endpoints, set PID to D0 */
4184 if (index && !hs_ep->isochronous)
4185 epctrl |= DXEPCTL_SETD0PID;
4187 /* WA for Full speed ISOC IN in DDMA mode.
4188 * By Clear NAK status of EP, core will send ZLP
4189 * to IN token and assert NAK interrupt relying
4190 * on TxFIFO status only
4193 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4194 hs_ep->isochronous && dir_in) {
4195 /* The WA applies only to core versions from 2.72a
4196 * to 4.00a (including both). Also for FS_IOT_1.00a
4199 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4201 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4202 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4203 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4204 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4205 epctrl |= DXEPCTL_CNAK;
4208 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4211 dwc2_writel(hsotg, epctrl, epctrl_reg);
4212 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4213 __func__, dwc2_readl(hsotg, epctrl_reg));
4215 /* enable the endpoint interrupt */
4216 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4219 spin_unlock_irqrestore(&hsotg->lock, flags);
4222 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4223 dmam_free_coherent(hsotg->dev, desc_num *
4224 sizeof(struct dwc2_dma_desc),
4225 hs_ep->desc_list, hs_ep->desc_list_dma);
4226 hs_ep->desc_list = NULL;
4233 * dwc2_hsotg_ep_disable - disable given endpoint
4234 * @ep: The endpoint to disable.
4236 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4238 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4239 struct dwc2_hsotg *hsotg = hs_ep->parent;
4240 int dir_in = hs_ep->dir_in;
4241 int index = hs_ep->index;
4245 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4247 if (ep == &hsotg->eps_out[0]->ep) {
4248 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4252 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4253 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4257 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4259 ctrl = dwc2_readl(hsotg, epctrl_reg);
4261 if (ctrl & DXEPCTL_EPENA)
4262 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4264 ctrl &= ~DXEPCTL_EPENA;
4265 ctrl &= ~DXEPCTL_USBACTEP;
4266 ctrl |= DXEPCTL_SNAK;
4268 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4269 dwc2_writel(hsotg, ctrl, epctrl_reg);
4271 /* disable endpoint interrupts */
4272 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4274 /* terminate all requests with shutdown */
4275 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4277 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4278 hs_ep->fifo_index = 0;
4279 hs_ep->fifo_size = 0;
4284 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4286 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4287 struct dwc2_hsotg *hsotg = hs_ep->parent;
4288 unsigned long flags;
4291 spin_lock_irqsave(&hsotg->lock, flags);
4292 ret = dwc2_hsotg_ep_disable(ep);
4293 spin_unlock_irqrestore(&hsotg->lock, flags);
4298 * on_list - check request is on the given endpoint
4299 * @ep: The endpoint to check.
4300 * @test: The request to test if it is on the endpoint.
4302 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4304 struct dwc2_hsotg_req *req, *treq;
4306 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4315 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4316 * @ep: The endpoint to dequeue.
4317 * @req: The request to be removed from a queue.
4319 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4321 struct dwc2_hsotg_req *hs_req = our_req(req);
4322 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4323 struct dwc2_hsotg *hs = hs_ep->parent;
4324 unsigned long flags;
4326 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4328 spin_lock_irqsave(&hs->lock, flags);
4330 if (!on_list(hs_ep, hs_req)) {
4331 spin_unlock_irqrestore(&hs->lock, flags);
4335 /* Dequeue already started request */
4336 if (req == &hs_ep->req->req)
4337 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4339 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4340 spin_unlock_irqrestore(&hs->lock, flags);
4346 * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
4347 * @ep: The endpoint to be wedged.
4350 static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
4352 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4353 struct dwc2_hsotg *hs = hs_ep->parent;
4355 unsigned long flags;
4358 spin_lock_irqsave(&hs->lock, flags);
4360 ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
4361 spin_unlock_irqrestore(&hs->lock, flags);
4367 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4368 * @ep: The endpoint to set halt.
4369 * @value: Set or unset the halt.
4370 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4371 * the endpoint is busy processing requests.
4373 * We need to stall the endpoint immediately if request comes from set_feature
4374 * protocol command handler.
4376 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4378 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4379 struct dwc2_hsotg *hs = hs_ep->parent;
4380 int index = hs_ep->index;
4385 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4389 dwc2_hsotg_stall_ep0(hs);
4392 "%s: can't clear halt on ep0\n", __func__);
4396 if (hs_ep->isochronous) {
4397 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4401 if (!now && value && !list_empty(&hs_ep->queue)) {
4402 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4407 if (hs_ep->dir_in) {
4408 epreg = DIEPCTL(index);
4409 epctl = dwc2_readl(hs, epreg);
4412 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4413 if (epctl & DXEPCTL_EPENA)
4414 epctl |= DXEPCTL_EPDIS;
4416 epctl &= ~DXEPCTL_STALL;
4418 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4419 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4420 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4421 epctl |= DXEPCTL_SETD0PID;
4423 dwc2_writel(hs, epctl, epreg);
4425 epreg = DOEPCTL(index);
4426 epctl = dwc2_readl(hs, epreg);
4429 /* Unmask GOUTNAKEFF interrupt */
4430 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4432 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4433 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4434 // STALL bit will be set in GOUTNAKEFF interrupt handler
4436 epctl &= ~DXEPCTL_STALL;
4438 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4439 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4440 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4441 epctl |= DXEPCTL_SETD0PID;
4442 dwc2_writel(hs, epctl, epreg);
4446 hs_ep->halted = value;
4451 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4452 * @ep: The endpoint to set halt.
4453 * @value: Set or unset the halt.
4455 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4457 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4458 struct dwc2_hsotg *hs = hs_ep->parent;
4459 unsigned long flags;
4462 spin_lock_irqsave(&hs->lock, flags);
4463 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4464 spin_unlock_irqrestore(&hs->lock, flags);
4469 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4470 .enable = dwc2_hsotg_ep_enable,
4471 .disable = dwc2_hsotg_ep_disable_lock,
4472 .alloc_request = dwc2_hsotg_ep_alloc_request,
4473 .free_request = dwc2_hsotg_ep_free_request,
4474 .queue = dwc2_hsotg_ep_queue_lock,
4475 .dequeue = dwc2_hsotg_ep_dequeue,
4476 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4477 .set_wedge = dwc2_gadget_ep_set_wedge,
4478 /* note, don't believe we have any call for the fifo routines */
4482 * dwc2_hsotg_init - initialize the usb core
4483 * @hsotg: The driver state
4485 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4487 /* unmask subset of endpoint interrupts */
4489 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4490 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4493 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4494 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4497 dwc2_writel(hsotg, 0, DAINTMSK);
4499 /* Be in disconnected state until gadget is registered */
4500 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4504 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4505 dwc2_readl(hsotg, GRXFSIZ),
4506 dwc2_readl(hsotg, GNPTXFSIZ));
4508 dwc2_hsotg_init_fifo(hsotg);
4510 if (using_dma(hsotg))
4511 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4515 * dwc2_hsotg_udc_start - prepare the udc for work
4516 * @gadget: The usb gadget state
4517 * @driver: The usb gadget driver
4519 * Perform initialization to prepare udc device and driver
4522 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4523 struct usb_gadget_driver *driver)
4525 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4526 unsigned long flags;
4530 pr_err("%s: called with no device\n", __func__);
4535 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4539 if (driver->max_speed < USB_SPEED_FULL)
4540 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4542 if (!driver->setup) {
4543 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4547 WARN_ON(hsotg->driver);
4549 hsotg->driver = driver;
4550 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4551 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4553 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4554 dwc2_force_mode(hsotg, false);
4555 ret = dwc2_lowlevel_hw_enable(hsotg);
4560 if (!IS_ERR_OR_NULL(hsotg->uphy))
4561 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4563 spin_lock_irqsave(&hsotg->lock, flags);
4564 if (dwc2_hw_is_device(hsotg)) {
4565 dwc2_hsotg_init(hsotg);
4566 dwc2_hsotg_core_init_disconnected(hsotg, false);
4570 spin_unlock_irqrestore(&hsotg->lock, flags);
4572 gadget->sg_supported = using_desc_dma(hsotg);
4573 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4578 hsotg->driver = NULL;
4583 * dwc2_hsotg_udc_stop - stop the udc
4584 * @gadget: The usb gadget state
4586 * Stop udc hw block and stay tunned for future transmissions
4588 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4590 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4591 unsigned long flags;
4597 /* all endpoints should be shutdown */
4598 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4599 if (hsotg->eps_in[ep])
4600 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4601 if (hsotg->eps_out[ep])
4602 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4605 spin_lock_irqsave(&hsotg->lock, flags);
4607 hsotg->driver = NULL;
4608 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4611 spin_unlock_irqrestore(&hsotg->lock, flags);
4613 if (!IS_ERR_OR_NULL(hsotg->uphy))
4614 otg_set_peripheral(hsotg->uphy->otg, NULL);
4616 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4617 dwc2_lowlevel_hw_disable(hsotg);
4623 * dwc2_hsotg_gadget_getframe - read the frame number
4624 * @gadget: The usb gadget state
4626 * Read the {micro} frame number
4628 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4630 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4634 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4635 * @gadget: The usb gadget state
4636 * @is_selfpowered: Whether the device is self-powered
4638 * Set if the device is self or bus powered.
4640 static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4643 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4644 unsigned long flags;
4646 spin_lock_irqsave(&hsotg->lock, flags);
4647 gadget->is_selfpowered = !!is_selfpowered;
4648 spin_unlock_irqrestore(&hsotg->lock, flags);
4654 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4655 * @gadget: The usb gadget state
4656 * @is_on: Current state of the USB PHY
4658 * Connect/Disconnect the USB PHY pullup
4660 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4662 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4663 unsigned long flags;
4665 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4668 /* Don't modify pullup state while in host mode */
4669 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4670 hsotg->enabled = is_on;
4674 spin_lock_irqsave(&hsotg->lock, flags);
4677 dwc2_hsotg_core_init_disconnected(hsotg, false);
4678 /* Enable ACG feature in device mode,if supported */
4679 dwc2_enable_acg(hsotg);
4680 dwc2_hsotg_core_connect(hsotg);
4682 dwc2_hsotg_core_disconnect(hsotg);
4683 dwc2_hsotg_disconnect(hsotg);
4687 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4688 spin_unlock_irqrestore(&hsotg->lock, flags);
4693 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4695 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4696 unsigned long flags;
4698 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4699 spin_lock_irqsave(&hsotg->lock, flags);
4702 * If controller is in partial power down state, it must exit from
4703 * that state before being initialized / de-initialized
4705 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4707 * No need to check the return value as
4708 * registers are not being restored.
4710 dwc2_exit_partial_power_down(hsotg, 0, false);
4713 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4715 dwc2_hsotg_core_init_disconnected(hsotg, false);
4716 if (hsotg->enabled) {
4717 /* Enable ACG feature in device mode,if supported */
4718 dwc2_enable_acg(hsotg);
4719 dwc2_hsotg_core_connect(hsotg);
4722 dwc2_hsotg_core_disconnect(hsotg);
4723 dwc2_hsotg_disconnect(hsotg);
4726 spin_unlock_irqrestore(&hsotg->lock, flags);
4731 * dwc2_hsotg_vbus_draw - report bMaxPower field
4732 * @gadget: The usb gadget state
4733 * @mA: Amount of current
4735 * Report how much power the device may consume to the phy.
4737 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4739 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4741 if (IS_ERR_OR_NULL(hsotg->uphy))
4743 return usb_phy_set_power(hsotg->uphy, mA);
4746 static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
4748 struct dwc2_hsotg *hsotg = to_hsotg(g);
4749 unsigned long flags;
4751 spin_lock_irqsave(&hsotg->lock, flags);
4753 case USB_SPEED_HIGH:
4754 hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
4756 case USB_SPEED_FULL:
4757 hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
4760 hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
4763 dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
4765 spin_unlock_irqrestore(&hsotg->lock, flags);
4768 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4769 .get_frame = dwc2_hsotg_gadget_getframe,
4770 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4771 .udc_start = dwc2_hsotg_udc_start,
4772 .udc_stop = dwc2_hsotg_udc_stop,
4773 .pullup = dwc2_hsotg_pullup,
4774 .udc_set_speed = dwc2_gadget_set_speed,
4775 .vbus_session = dwc2_hsotg_vbus_session,
4776 .vbus_draw = dwc2_hsotg_vbus_draw,
4780 * dwc2_hsotg_initep - initialise a single endpoint
4781 * @hsotg: The device state.
4782 * @hs_ep: The endpoint to be initialised.
4783 * @epnum: The endpoint number
4784 * @dir_in: True if direction is in.
4786 * Initialise the given endpoint (as part of the probe and device state
4787 * creation) to give to the gadget driver. Setup the endpoint name, any
4788 * direction information and other state that may be required.
4790 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4791 struct dwc2_hsotg_ep *hs_ep,
4804 hs_ep->dir_in = dir_in;
4805 hs_ep->index = epnum;
4807 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4809 INIT_LIST_HEAD(&hs_ep->queue);
4810 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4812 /* add to the list of endpoints known by the gadget driver */
4814 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4816 hs_ep->parent = hsotg;
4817 hs_ep->ep.name = hs_ep->name;
4819 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4820 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4822 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4823 epnum ? 1024 : EP0_MPS_LIMIT);
4824 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4827 hs_ep->ep.caps.type_control = true;
4829 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4830 hs_ep->ep.caps.type_iso = true;
4831 hs_ep->ep.caps.type_bulk = true;
4833 hs_ep->ep.caps.type_int = true;
4837 hs_ep->ep.caps.dir_in = true;
4839 hs_ep->ep.caps.dir_out = true;
4842 * if we're using dma, we need to set the next-endpoint pointer
4843 * to be something valid.
4846 if (using_dma(hsotg)) {
4847 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4850 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4852 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4857 * dwc2_hsotg_hw_cfg - read HW configuration registers
4858 * @hsotg: Programming view of the DWC_otg controller
4860 * Read the USB core HW configuration registers
4862 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4868 /* check hardware configuration */
4870 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4873 hsotg->num_of_eps++;
4875 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4876 sizeof(struct dwc2_hsotg_ep),
4878 if (!hsotg->eps_in[0])
4880 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4881 hsotg->eps_out[0] = hsotg->eps_in[0];
4883 cfg = hsotg->hw_params.dev_ep_dirs;
4884 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4886 /* Direction in or both */
4887 if (!(ep_type & 2)) {
4888 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4889 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4890 if (!hsotg->eps_in[i])
4893 /* Direction out or both */
4894 if (!(ep_type & 1)) {
4895 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4896 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4897 if (!hsotg->eps_out[i])
4902 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4903 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4905 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4907 hsotg->dedicated_fifos ? "dedicated" : "shared",
4913 * dwc2_hsotg_dump - dump state of the udc
4914 * @hsotg: Programming view of the DWC_otg controller
4917 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4920 struct device *dev = hsotg->dev;
4924 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4925 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4926 dwc2_readl(hsotg, DIEPMSK));
4928 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4929 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4931 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4932 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4934 /* show periodic fifo settings */
4936 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4937 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4938 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4939 val >> FIFOSIZE_DEPTH_SHIFT,
4940 val & FIFOSIZE_STARTADDR_MASK);
4943 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4945 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4946 dwc2_readl(hsotg, DIEPCTL(idx)),
4947 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4948 dwc2_readl(hsotg, DIEPDMA(idx)));
4950 val = dwc2_readl(hsotg, DOEPCTL(idx));
4952 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4953 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4954 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4955 dwc2_readl(hsotg, DOEPDMA(idx)));
4958 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4959 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4964 * dwc2_gadget_init - init function for gadget
4965 * @hsotg: Programming view of the DWC_otg controller
4968 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4970 struct device *dev = hsotg->dev;
4974 /* Dump fifo information */
4975 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4976 hsotg->params.g_np_tx_fifo_size);
4977 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4979 switch (hsotg->params.speed) {
4980 case DWC2_SPEED_PARAM_LOW:
4981 hsotg->gadget.max_speed = USB_SPEED_LOW;
4983 case DWC2_SPEED_PARAM_FULL:
4984 hsotg->gadget.max_speed = USB_SPEED_FULL;
4987 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4991 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4992 hsotg->gadget.name = dev_name(dev);
4993 hsotg->remote_wakeup_allowed = 0;
4995 if (hsotg->params.lpm)
4996 hsotg->gadget.lpm_capable = true;
4998 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4999 hsotg->gadget.is_otg = 1;
5000 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
5001 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
5003 ret = dwc2_hsotg_hw_cfg(hsotg);
5005 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
5009 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
5010 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5011 if (!hsotg->ctrl_buff)
5014 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
5015 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5016 if (!hsotg->ep0_buff)
5019 if (using_desc_dma(hsotg)) {
5020 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
5025 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
5026 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
5028 dev_err(dev, "cannot claim IRQ for gadget\n");
5032 /* hsotg->num_of_eps holds number of EPs other than ep0 */
5034 if (hsotg->num_of_eps == 0) {
5035 dev_err(dev, "wrong number of EPs (zero)\n");
5039 /* setup endpoint information */
5041 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
5042 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
5044 /* allocate EP0 request */
5046 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
5048 if (!hsotg->ctrl_req) {
5049 dev_err(dev, "failed to allocate ctrl req\n");
5053 /* initialise the endpoints now the core has been initialised */
5054 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
5055 if (hsotg->eps_in[epnum])
5056 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
5058 if (hsotg->eps_out[epnum])
5059 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5063 hsotg->gadget.quirk_ep_out_aligned_size = true;
5064 dwc2_hsotg_dump(hsotg);
5066 #if IS_ENABLED(CONFIG_EXTCON)
5067 if (hsotg->params.g_extcon_always_on) {
5068 struct extcon_dev *edev;
5069 static const unsigned int supported_cable[] = {
5074 edev = devm_extcon_dev_allocate(dev, supported_cable);
5076 return PTR_ERR(edev);
5078 ret = devm_extcon_dev_register(dev, edev);
5082 extcon_set_state_sync(edev, EXTCON_USB, true);
5089 * dwc2_hsotg_remove - remove function for hsotg driver
5090 * @hsotg: Programming view of the DWC_otg controller
5093 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5095 usb_del_gadget_udc(&hsotg->gadget);
5096 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5101 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5103 unsigned long flags;
5105 if (hsotg->lx_state != DWC2_L0)
5108 if (hsotg->driver) {
5111 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5112 hsotg->driver->driver.name);
5114 spin_lock_irqsave(&hsotg->lock, flags);
5116 dwc2_hsotg_core_disconnect(hsotg);
5117 dwc2_hsotg_disconnect(hsotg);
5118 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5119 spin_unlock_irqrestore(&hsotg->lock, flags);
5121 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
5122 if (hsotg->eps_in[ep])
5123 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5124 if (hsotg->eps_out[ep])
5125 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5132 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5134 unsigned long flags;
5136 if (hsotg->lx_state == DWC2_L2)
5139 if (hsotg->driver) {
5140 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5141 hsotg->driver->driver.name);
5143 spin_lock_irqsave(&hsotg->lock, flags);
5144 dwc2_hsotg_core_init_disconnected(hsotg, false);
5145 if (hsotg->enabled) {
5146 /* Enable ACG feature in device mode,if supported */
5147 dwc2_enable_acg(hsotg);
5148 dwc2_hsotg_core_connect(hsotg);
5150 spin_unlock_irqrestore(&hsotg->lock, flags);
5157 * dwc2_backup_device_registers() - Backup controller device registers.
5158 * When suspending usb bus, registers needs to be backuped
5159 * if controller power is disabled once suspended.
5161 * @hsotg: Programming view of the DWC_otg controller
5163 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5165 struct dwc2_dregs_backup *dr;
5168 dev_dbg(hsotg->dev, "%s\n", __func__);
5170 /* Backup dev regs */
5171 dr = &hsotg->dr_backup;
5173 dr->dcfg = dwc2_readl(hsotg, DCFG);
5174 dr->dctl = dwc2_readl(hsotg, DCTL);
5175 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5176 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5177 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5179 for (i = 0; i < hsotg->num_of_eps; i++) {
5181 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5183 /* Ensure DATA PID is correctly configured */
5184 if (dr->diepctl[i] & DXEPCTL_DPID)
5185 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5187 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5189 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5190 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5192 /* Backup OUT EPs */
5193 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5195 /* Ensure DATA PID is correctly configured */
5196 if (dr->doepctl[i] & DXEPCTL_DPID)
5197 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5199 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5201 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5202 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5203 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5210 * dwc2_restore_device_registers() - Restore controller device registers.
5211 * When resuming usb bus, device registers needs to be restored
5212 * if controller power were disabled.
5214 * @hsotg: Programming view of the DWC_otg controller
5215 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5217 * Return: 0 if successful, negative error code otherwise
5219 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5221 struct dwc2_dregs_backup *dr;
5224 dev_dbg(hsotg->dev, "%s\n", __func__);
5226 /* Restore dev regs */
5227 dr = &hsotg->dr_backup;
5229 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5236 dwc2_writel(hsotg, dr->dctl, DCTL);
5238 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5239 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5240 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5242 for (i = 0; i < hsotg->num_of_eps; i++) {
5243 /* Restore IN EPs */
5244 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5245 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5246 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5247 /** WA for enabled EPx's IN in DDMA mode. On entering to
5248 * hibernation wrong value read and saved from DIEPDMAx,
5249 * as result BNA interrupt asserted on hibernation exit
5250 * by restoring from saved area.
5252 if (hsotg->params.g_dma_desc &&
5253 (dr->diepctl[i] & DXEPCTL_EPENA))
5254 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5255 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5256 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5257 /* Restore OUT EPs */
5258 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5259 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5260 * hibernation wrong value read and saved from DOEPDMAx,
5261 * as result BNA interrupt asserted on hibernation exit
5262 * by restoring from saved area.
5264 if (hsotg->params.g_dma_desc &&
5265 (dr->doepctl[i] & DXEPCTL_EPENA))
5266 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5267 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5268 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5275 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5277 * @hsotg: Programming view of DWC_otg controller
5280 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5284 if (!hsotg->params.lpm)
5287 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5288 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5289 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5290 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5291 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5292 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5293 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5294 dwc2_writel(hsotg, val, GLPMCFG);
5295 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5297 /* Unmask WKUP_ALERT Interrupt */
5298 if (hsotg->params.service_interval)
5299 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5303 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5305 * @hsotg: Programming view of DWC_otg controller
5308 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5312 val |= GREFCLK_REF_CLK_MODE;
5313 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5314 val |= hsotg->params.sof_cnt_wkup_alert <<
5315 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5317 dwc2_writel(hsotg, val, GREFCLK);
5318 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5322 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5324 * @hsotg: Programming view of the DWC_otg controller
5326 * Return non-zero if failed to enter to hibernation.
5328 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5333 /* Change to L2(suspend) state */
5334 hsotg->lx_state = DWC2_L2;
5335 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5336 ret = dwc2_backup_global_registers(hsotg);
5338 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5342 ret = dwc2_backup_device_registers(hsotg);
5344 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5349 gpwrdn = GPWRDN_PWRDNRSTN;
5350 gpwrdn |= GPWRDN_PMUACTV;
5351 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5354 /* Set flag to indicate that we are in hibernation */
5355 hsotg->hibernated = 1;
5357 /* Enable interrupts from wake up logic */
5358 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5359 gpwrdn |= GPWRDN_PMUINTSEL;
5360 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5363 /* Unmask device mode interrupts in GPWRDN */
5364 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5365 gpwrdn |= GPWRDN_RST_DET_MSK;
5366 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5367 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5368 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5371 /* Enable Power Down Clamp */
5372 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5373 gpwrdn |= GPWRDN_PWRDNCLMP;
5374 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5377 /* Switch off VDD */
5378 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5379 gpwrdn |= GPWRDN_PWRDNSWTCH;
5380 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5383 /* Save gpwrdn register for further usage if stschng interrupt */
5384 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5385 dev_dbg(hsotg->dev, "Hibernation completed\n");
5391 * dwc2_gadget_exit_hibernation()
5392 * This function is for exiting from Device mode hibernation by host initiated
5393 * resume/reset and device initiated remote-wakeup.
5395 * @hsotg: Programming view of the DWC_otg controller
5396 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5397 * @reset: indicates whether resume is initiated by Reset.
5399 * Return non-zero if failed to exit from hibernation.
5401 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5402 int rem_wakeup, int reset)
5408 struct dwc2_gregs_backup *gr;
5409 struct dwc2_dregs_backup *dr;
5411 gr = &hsotg->gr_backup;
5412 dr = &hsotg->dr_backup;
5414 if (!hsotg->hibernated) {
5415 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5419 "%s: called with rem_wakeup = %d reset = %d\n",
5420 __func__, rem_wakeup, reset);
5422 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5425 /* Clear all pending interupts */
5426 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5429 /* De-assert Restore */
5430 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5431 gpwrdn &= ~GPWRDN_RESTORE;
5432 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5436 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5437 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5438 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5441 /* Restore GUSBCFG, DCFG and DCTL */
5442 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5443 dwc2_writel(hsotg, dr->dcfg, DCFG);
5444 dwc2_writel(hsotg, dr->dctl, DCTL);
5446 /* On USB Reset, reset device address to zero */
5448 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5450 /* De-assert Wakeup Logic */
5451 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5452 gpwrdn &= ~GPWRDN_PMUACTV;
5453 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5457 /* Start Remote Wakeup Signaling */
5458 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5461 /* Set Device programming done bit */
5462 dctl = dwc2_readl(hsotg, DCTL);
5463 dctl |= DCTL_PWRONPRGDONE;
5464 dwc2_writel(hsotg, dctl, DCTL);
5466 /* Wait for interrupts which must be cleared */
5468 /* Clear all pending interupts */
5469 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5471 /* Restore global registers */
5472 ret = dwc2_restore_global_registers(hsotg);
5474 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5479 /* Restore device registers */
5480 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5482 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5489 dctl = dwc2_readl(hsotg, DCTL);
5490 dctl &= ~DCTL_RMTWKUPSIG;
5491 dwc2_writel(hsotg, dctl, DCTL);
5494 hsotg->hibernated = 0;
5495 hsotg->lx_state = DWC2_L0;
5496 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5502 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5505 * @hsotg: Programming view of the DWC_otg controller
5507 * Return: non-zero if failed to enter device partial power down.
5509 * This function is for entering device mode partial power down.
5511 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5516 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5518 /* Backup all registers */
5519 ret = dwc2_backup_global_registers(hsotg);
5521 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5526 ret = dwc2_backup_device_registers(hsotg);
5528 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5534 * Clear any pending interrupts since dwc2 will not be able to
5535 * clear them after entering partial_power_down.
5537 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5539 /* Put the controller in low power state */
5540 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5542 pcgcctl |= PCGCTL_PWRCLMP;
5543 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5546 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5547 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5550 pcgcctl |= PCGCTL_STOPPCLK;
5551 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5553 /* Set in_ppd flag to 1 as here core enters suspend. */
5555 hsotg->lx_state = DWC2_L2;
5557 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5563 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5566 * @hsotg: Programming view of the DWC_otg controller
5567 * @restore: indicates whether need to restore the registers or not.
5569 * Return: non-zero if failed to exit device partial power down.
5571 * This function is for exiting from device mode partial power down.
5573 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5578 struct dwc2_dregs_backup *dr;
5581 dr = &hsotg->dr_backup;
5583 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5585 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5586 pcgcctl &= ~PCGCTL_STOPPCLK;
5587 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5589 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5590 pcgcctl &= ~PCGCTL_PWRCLMP;
5591 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5593 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5594 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5595 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5599 ret = dwc2_restore_global_registers(hsotg);
5601 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5606 dwc2_writel(hsotg, dr->dcfg, DCFG);
5608 ret = dwc2_restore_device_registers(hsotg, 0);
5610 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5616 /* Set the Power-On Programming done bit */
5617 dctl = dwc2_readl(hsotg, DCTL);
5618 dctl |= DCTL_PWRONPRGDONE;
5619 dwc2_writel(hsotg, dctl, DCTL);
5621 /* Set in_ppd flag to 0 as here core exits from suspend. */
5623 hsotg->lx_state = DWC2_L0;
5625 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5630 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5632 * @hsotg: Programming view of the DWC_otg controller
5634 * Return: non-zero if failed to enter device partial power down.
5636 * This function is for entering device mode clock gating.
5638 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5642 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5644 /* Set the Phy Clock bit as suspend is received. */
5645 pcgctl = dwc2_readl(hsotg, PCGCTL);
5646 pcgctl |= PCGCTL_STOPPCLK;
5647 dwc2_writel(hsotg, pcgctl, PCGCTL);
5650 /* Set the Gate hclk as suspend is received. */
5651 pcgctl = dwc2_readl(hsotg, PCGCTL);
5652 pcgctl |= PCGCTL_GATEHCLK;
5653 dwc2_writel(hsotg, pcgctl, PCGCTL);
5656 hsotg->lx_state = DWC2_L2;
5657 hsotg->bus_suspended = true;
5661 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5663 * @hsotg: Programming view of the DWC_otg controller
5664 * @rem_wakeup: indicates whether remote wake up is enabled.
5666 * This function is for exiting from device mode clock gating.
5668 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5673 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5675 /* Clear the Gate hclk. */
5676 pcgctl = dwc2_readl(hsotg, PCGCTL);
5677 pcgctl &= ~PCGCTL_GATEHCLK;
5678 dwc2_writel(hsotg, pcgctl, PCGCTL);
5681 /* Phy Clock bit. */
5682 pcgctl = dwc2_readl(hsotg, PCGCTL);
5683 pcgctl &= ~PCGCTL_STOPPCLK;
5684 dwc2_writel(hsotg, pcgctl, PCGCTL);
5688 /* Set Remote Wakeup Signaling */
5689 dctl = dwc2_readl(hsotg, DCTL);
5690 dctl |= DCTL_RMTWKUPSIG;
5691 dwc2_writel(hsotg, dctl, DCTL);
5694 /* Change to L0 state */
5695 call_gadget(hsotg, resume);
5696 hsotg->lx_state = DWC2_L0;
5697 hsotg->bus_suspended = false;