1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
30 #include <linux/usb/composite.h>
36 /* conversion functions */
37 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39 return container_of(req, struct dwc2_hsotg_req, req);
42 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
47 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49 return container_of(gadget, struct dwc2_hsotg, gadget);
52 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
57 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
62 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
66 return hsotg->eps_in[ep_index];
68 return hsotg->eps_out[ep_index];
71 /* forward declaration of functions */
72 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
78 * Return true if we're using DMA.
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
91 * g_using_dma is set depending on dts flag.
93 static inline bool using_dma(struct dwc2_hsotg *hsotg)
95 return hsotg->params.g_dma;
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
102 * Return true if we're using descriptor DMA.
104 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
106 return hsotg->params.g_dma_desc;
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
116 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
118 hs_ep->target_frame += hs_ep->interval;
119 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
120 hs_ep->frame_overrun = true;
121 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
123 hs_ep->frame_overrun = false;
128 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
130 * @hs_ep: The endpoint.
132 * This function used in service interval based scheduling flow to calculate
133 * descriptor frame number filed value. For service interval mode frame
134 * number in descriptor should point to last (u)frame in the interval.
137 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
139 if (hs_ep->target_frame)
140 hs_ep->target_frame -= 1;
142 hs_ep->target_frame = DSTS_SOFFN_LIMIT;
146 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
147 * @hsotg: The device state
148 * @ints: A bitmask of the interrupts to enable
150 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
152 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
155 new_gsintmsk = gsintmsk | ints;
157 if (new_gsintmsk != gsintmsk) {
158 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
159 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
164 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
165 * @hsotg: The device state
166 * @ints: A bitmask of the interrupts to enable
168 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
170 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
173 new_gsintmsk = gsintmsk & ~ints;
175 if (new_gsintmsk != gsintmsk)
176 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
180 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
181 * @hsotg: The device state
182 * @ep: The endpoint index
183 * @dir_in: True if direction is in.
184 * @en: The enable value, true to enable
186 * Set or clear the mask for an individual endpoint's interrupt
189 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
190 unsigned int ep, unsigned int dir_in,
200 local_irq_save(flags);
201 daint = dwc2_readl(hsotg, DAINTMSK);
206 dwc2_writel(hsotg, daint, DAINTMSK);
207 local_irq_restore(flags);
211 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
213 * @hsotg: Programming view of the DWC_otg controller
215 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
217 if (hsotg->hw_params.en_multiple_tx_fifo)
218 /* In dedicated FIFO mode we need count of IN EPs */
219 return hsotg->hw_params.num_dev_in_eps;
221 /* In shared FIFO mode we need count of Periodic IN EPs */
222 return hsotg->hw_params.num_dev_perio_in_ep;
226 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
227 * device mode TX FIFOs
229 * @hsotg: Programming view of the DWC_otg controller
231 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
237 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
238 hsotg->params.g_np_tx_fifo_size);
240 /* Get Endpoint Info Control block size in DWORDs. */
241 tx_addr_max = hsotg->hw_params.total_fifo_size;
243 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
244 if (tx_addr_max <= addr)
247 return tx_addr_max - addr;
251 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
253 * @hsotg: Programming view of the DWC_otg controller
256 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
261 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
262 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
263 gintsts2 &= gintmsk2;
265 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
266 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
267 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
268 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
273 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
276 * @hsotg: Programming view of the DWC_otg controller
278 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
283 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
285 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
288 return tx_fifo_depth;
290 return tx_fifo_depth / tx_fifo_count;
294 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
295 * @hsotg: The device instance.
297 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
304 u32 *txfsz = hsotg->params.g_tx_fifo_size;
306 /* Reset fifo map if not correctly cleared during previous session */
307 WARN_ON(hsotg->fifo_map);
310 /* set RX/NPTX FIFO sizes */
311 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
312 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
313 FIFOSIZE_STARTADDR_SHIFT) |
314 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
318 * arange all the rest of the TX FIFOs, as some versions of this
319 * block have overlapping default addresses. This also ensures
320 * that if the settings have been changed, then they are set to
324 /* start at the end of the GNPTXFSIZ, rounded up */
325 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
328 * Configure fifos sizes from provided configuration and assign
329 * them to endpoints dynamically according to maxpacket size value of
332 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
336 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
337 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
338 "insufficient fifo memory");
341 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
342 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
345 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
346 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
349 * according to p428 of the design guide, we need to ensure that
350 * all fifos are flushed before continuing
353 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
354 GRSTCTL_RXFFLSH, GRSTCTL);
356 /* wait until the fifos are both flushed */
359 val = dwc2_readl(hsotg, GRSTCTL);
361 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
364 if (--timeout == 0) {
366 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
374 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
378 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
379 * @ep: USB endpoint to allocate request for.
380 * @flags: Allocation flags
382 * Allocate a new USB request structure appropriate for the specified endpoint
384 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
387 struct dwc2_hsotg_req *req;
389 req = kzalloc(sizeof(*req), flags);
393 INIT_LIST_HEAD(&req->queue);
399 * is_ep_periodic - return true if the endpoint is in periodic mode.
400 * @hs_ep: The endpoint to query.
402 * Returns true if the endpoint is in periodic mode, meaning it is being
403 * used for an Interrupt or ISO transfer.
405 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
407 return hs_ep->periodic;
411 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
412 * @hsotg: The device state.
413 * @hs_ep: The endpoint for the request
414 * @hs_req: The request being processed.
416 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
417 * of a request to ensure the buffer is ready for access by the caller.
419 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
420 struct dwc2_hsotg_ep *hs_ep,
421 struct dwc2_hsotg_req *hs_req)
423 struct usb_request *req = &hs_req->req;
425 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
429 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
430 * for Control endpoint
431 * @hsotg: The device state.
433 * This function will allocate 4 descriptor chains for EP 0: 2 for
434 * Setup stage, per one for IN and OUT data/status transactions.
436 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
438 hsotg->setup_desc[0] =
439 dmam_alloc_coherent(hsotg->dev,
440 sizeof(struct dwc2_dma_desc),
441 &hsotg->setup_desc_dma[0],
443 if (!hsotg->setup_desc[0])
446 hsotg->setup_desc[1] =
447 dmam_alloc_coherent(hsotg->dev,
448 sizeof(struct dwc2_dma_desc),
449 &hsotg->setup_desc_dma[1],
451 if (!hsotg->setup_desc[1])
454 hsotg->ctrl_in_desc =
455 dmam_alloc_coherent(hsotg->dev,
456 sizeof(struct dwc2_dma_desc),
457 &hsotg->ctrl_in_desc_dma,
459 if (!hsotg->ctrl_in_desc)
462 hsotg->ctrl_out_desc =
463 dmam_alloc_coherent(hsotg->dev,
464 sizeof(struct dwc2_dma_desc),
465 &hsotg->ctrl_out_desc_dma,
467 if (!hsotg->ctrl_out_desc)
477 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
478 * @hsotg: The controller state.
479 * @hs_ep: The endpoint we're going to write for.
480 * @hs_req: The request to write data for.
482 * This is called when the TxFIFO has some space in it to hold a new
483 * transmission and we have something to give it. The actual setup of
484 * the data size is done elsewhere, so all we have to do is to actually
487 * The return value is zero if there is more space (or nothing was done)
488 * otherwise -ENOSPC is returned if the FIFO space was used up.
490 * This routine is only needed for PIO
492 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
493 struct dwc2_hsotg_ep *hs_ep,
494 struct dwc2_hsotg_req *hs_req)
496 bool periodic = is_ep_periodic(hs_ep);
497 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
498 int buf_pos = hs_req->req.actual;
499 int to_write = hs_ep->size_loaded;
505 to_write -= (buf_pos - hs_ep->last_load);
507 /* if there's nothing to write, get out early */
511 if (periodic && !hsotg->dedicated_fifos) {
512 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
517 * work out how much data was loaded so we can calculate
518 * how much data is left in the fifo.
521 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
524 * if shared fifo, we cannot write anything until the
525 * previous data has been completely sent.
527 if (hs_ep->fifo_load != 0) {
528 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
532 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
534 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
536 /* how much of the data has moved */
537 size_done = hs_ep->size_loaded - size_left;
539 /* how much data is left in the fifo */
540 can_write = hs_ep->fifo_load - size_done;
541 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
542 __func__, can_write);
544 can_write = hs_ep->fifo_size - can_write;
545 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
546 __func__, can_write);
548 if (can_write <= 0) {
549 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
552 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
553 can_write = dwc2_readl(hsotg,
554 DTXFSTS(hs_ep->fifo_index));
559 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
561 "%s: no queue slots available (0x%08x)\n",
564 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
568 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
569 can_write *= 4; /* fifo size is in 32bit quantities. */
572 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
574 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
575 __func__, gnptxsts, can_write, to_write, max_transfer);
578 * limit to 512 bytes of data, it seems at least on the non-periodic
579 * FIFO, requests of >512 cause the endpoint to get stuck with a
580 * fragment of the end of the transfer in it.
582 if (can_write > 512 && !periodic)
586 * limit the write to one max-packet size worth of data, but allow
587 * the transfer to return that it did not run out of fifo space
590 if (to_write > max_transfer) {
591 to_write = max_transfer;
593 /* it's needed only when we do not use dedicated fifos */
594 if (!hsotg->dedicated_fifos)
595 dwc2_hsotg_en_gsint(hsotg,
596 periodic ? GINTSTS_PTXFEMP :
600 /* see if we can write data */
602 if (to_write > can_write) {
603 to_write = can_write;
604 pkt_round = to_write % max_transfer;
607 * Round the write down to an
608 * exact number of packets.
610 * Note, we do not currently check to see if we can ever
611 * write a full packet or not to the FIFO.
615 to_write -= pkt_round;
618 * enable correct FIFO interrupt to alert us when there
622 /* it's needed only when we do not use dedicated fifos */
623 if (!hsotg->dedicated_fifos)
624 dwc2_hsotg_en_gsint(hsotg,
625 periodic ? GINTSTS_PTXFEMP :
629 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
630 to_write, hs_req->req.length, can_write, buf_pos);
635 hs_req->req.actual = buf_pos + to_write;
636 hs_ep->total_data += to_write;
639 hs_ep->fifo_load += to_write;
641 to_write = DIV_ROUND_UP(to_write, 4);
642 data = hs_req->req.buf + buf_pos;
644 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
646 return (to_write >= can_write) ? -ENOSPC : 0;
650 * get_ep_limit - get the maximum data legnth for this endpoint
651 * @hs_ep: The endpoint
653 * Return the maximum data that can be queued in one go on a given endpoint
654 * so that transfers that are too long can be split.
656 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
658 int index = hs_ep->index;
659 unsigned int maxsize;
663 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
664 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
668 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
673 /* we made the constant loading easier above by using +1 */
678 * constrain by packet count if maxpkts*pktsize is greater
679 * than the length register size.
682 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
683 maxsize = maxpkt * hs_ep->ep.maxpacket;
689 * dwc2_hsotg_read_frameno - read current frame number
690 * @hsotg: The device instance
692 * Return the current frame number
694 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
698 dsts = dwc2_readl(hsotg, DSTS);
699 dsts &= DSTS_SOFFN_MASK;
700 dsts >>= DSTS_SOFFN_SHIFT;
706 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
707 * DMA descriptor chain prepared for specific endpoint
708 * @hs_ep: The endpoint
710 * Return the maximum data that can be queued in one go on a given endpoint
711 * depending on its descriptor chain capacity so that transfers that
712 * are too long can be split.
714 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
716 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
717 int is_isoc = hs_ep->isochronous;
718 unsigned int maxsize;
719 u32 mps = hs_ep->ep.maxpacket;
720 int dir_in = hs_ep->dir_in;
723 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
724 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
725 MAX_DMA_DESC_NUM_HS_ISOC;
727 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
729 /* Interrupt OUT EP with mps not multiple of 4 */
731 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
732 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
738 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
739 * @hs_ep: The endpoint
740 * @mask: RX/TX bytes mask to be defined
742 * Returns maximum data payload for one descriptor after analyzing endpoint
744 * DMA descriptor transfer bytes limit depends on EP type:
746 * Isochronous - descriptor rx/tx bytes bitfield limit,
747 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
748 * have concatenations from various descriptors within one packet.
749 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
750 * to a single descriptor.
752 * Selects corresponding mask for RX/TX bytes as well.
754 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
756 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
757 u32 mps = hs_ep->ep.maxpacket;
758 int dir_in = hs_ep->dir_in;
761 if (!hs_ep->index && !dir_in) {
763 *mask = DEV_DMA_NBYTES_MASK;
764 } else if (hs_ep->isochronous) {
766 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
767 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
769 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
770 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
773 desc_size = DEV_DMA_NBYTES_LIMIT;
774 *mask = DEV_DMA_NBYTES_MASK;
776 /* Round down desc_size to be mps multiple */
777 desc_size -= desc_size % mps;
780 /* Interrupt OUT EP with mps not multiple of 4 */
782 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
784 *mask = DEV_DMA_NBYTES_MASK;
790 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
791 struct dwc2_dma_desc **desc,
796 int dir_in = hs_ep->dir_in;
797 u32 mps = hs_ep->ep.maxpacket;
803 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
805 hs_ep->desc_count = (len / maxsize) +
806 ((len % maxsize) ? 1 : 0);
808 hs_ep->desc_count = 1;
810 for (i = 0; i < hs_ep->desc_count; ++i) {
812 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
813 << DEV_DMA_BUFF_STS_SHIFT);
816 if (!hs_ep->index && !dir_in)
817 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
820 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
821 (*desc)->buf = dma_buff + offset;
827 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
830 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
831 ((hs_ep->send_zlp && true_last) ?
835 len << DEV_DMA_NBYTES_SHIFT & mask;
836 (*desc)->buf = dma_buff + offset;
839 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
840 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
841 << DEV_DMA_BUFF_STS_SHIFT);
847 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
848 * @hs_ep: The endpoint
849 * @ureq: Request to transfer
850 * @offset: offset in bytes
851 * @len: Length of the transfer
853 * This function will iterate over descriptor chain and fill its entries
854 * with corresponding information based on transfer data.
856 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
860 struct usb_request *ureq = NULL;
861 struct dwc2_dma_desc *desc = hs_ep->desc_list;
862 struct scatterlist *sg;
867 ureq = &hs_ep->req->req;
869 /* non-DMA sg buffer */
870 if (!ureq || !ureq->num_sgs) {
871 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
872 dma_buff, len, true);
877 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
878 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
879 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
881 desc_count += hs_ep->desc_count;
884 hs_ep->desc_count = desc_count;
888 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
889 * @hs_ep: The isochronous endpoint.
890 * @dma_buff: usb requests dma buffer.
891 * @len: usb request transfer length.
893 * Fills next free descriptor with the data of the arrived usb request,
894 * frame info, sets Last and IOC bits increments next_desc. If filled
895 * descriptor is not the first one, removes L bit from the previous descriptor
898 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
899 dma_addr_t dma_buff, unsigned int len)
901 struct dwc2_dma_desc *desc;
902 struct dwc2_hsotg *hsotg = hs_ep->parent;
907 dwc2_gadget_get_desc_params(hs_ep, &mask);
909 index = hs_ep->next_desc;
910 desc = &hs_ep->desc_list[index];
912 /* Check if descriptor chain full */
913 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
914 DEV_DMA_BUFF_STS_HREADY) {
915 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
919 /* Clear L bit of previous desc if more than one entries in the chain */
920 if (hs_ep->next_desc)
921 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
923 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
924 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
927 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
929 desc->buf = dma_buff;
930 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
931 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
935 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
938 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
939 DEV_DMA_ISOC_PID_MASK) |
940 ((len % hs_ep->ep.maxpacket) ?
942 ((hs_ep->target_frame <<
943 DEV_DMA_ISOC_FRNUM_SHIFT) &
944 DEV_DMA_ISOC_FRNUM_MASK);
947 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
948 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
950 /* Increment frame number by interval for IN */
952 dwc2_gadget_incr_frame_num(hs_ep);
954 /* Update index of last configured entry in the chain */
956 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
957 hs_ep->next_desc = 0;
963 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
964 * @hs_ep: The isochronous endpoint.
966 * Prepare descriptor chain for isochronous endpoints. Afterwards
967 * write DMA address to HW and enable the endpoint.
969 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
971 struct dwc2_hsotg *hsotg = hs_ep->parent;
972 struct dwc2_hsotg_req *hs_req, *treq;
973 int index = hs_ep->index;
979 struct dwc2_dma_desc *desc;
981 if (list_empty(&hs_ep->queue)) {
982 hs_ep->target_frame = TARGET_FRAME_INITIAL;
983 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
987 /* Initialize descriptor chain by Host Busy status */
988 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
989 desc = &hs_ep->desc_list[i];
991 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
992 << DEV_DMA_BUFF_STS_SHIFT);
995 hs_ep->next_desc = 0;
996 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
997 dma_addr_t dma_addr = hs_req->req.dma;
999 if (hs_req->req.num_sgs) {
1000 WARN_ON(hs_req->req.num_sgs > 1);
1001 dma_addr = sg_dma_address(hs_req->req.sg);
1003 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1004 hs_req->req.length);
1009 hs_ep->compl_desc = 0;
1010 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1011 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1013 /* write descriptor chain address to control register */
1014 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1016 ctrl = dwc2_readl(hsotg, depctl);
1017 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1018 dwc2_writel(hsotg, ctrl, depctl);
1022 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1023 * @hsotg: The controller state.
1024 * @hs_ep: The endpoint to process a request for
1025 * @hs_req: The request to start.
1026 * @continuing: True if we are doing more for the current request.
1028 * Start the given request running by setting the endpoint registers
1029 * appropriately, and writing any data to the FIFOs.
1031 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1032 struct dwc2_hsotg_ep *hs_ep,
1033 struct dwc2_hsotg_req *hs_req,
1036 struct usb_request *ureq = &hs_req->req;
1037 int index = hs_ep->index;
1038 int dir_in = hs_ep->dir_in;
1043 unsigned int length;
1044 unsigned int packets;
1045 unsigned int maxreq;
1046 unsigned int dma_reg;
1049 if (hs_ep->req && !continuing) {
1050 dev_err(hsotg->dev, "%s: active request\n", __func__);
1053 } else if (hs_ep->req != hs_req && continuing) {
1055 "%s: continue different req\n", __func__);
1061 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1062 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1063 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1065 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1066 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1067 hs_ep->dir_in ? "in" : "out");
1069 /* If endpoint is stalled, we will restart request later */
1070 ctrl = dwc2_readl(hsotg, epctrl_reg);
1072 if (index && ctrl & DXEPCTL_STALL) {
1073 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1077 length = ureq->length - ureq->actual;
1078 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1079 ureq->length, ureq->actual);
1081 if (!using_desc_dma(hsotg))
1082 maxreq = get_ep_limit(hs_ep);
1084 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1086 if (length > maxreq) {
1087 int round = maxreq % hs_ep->ep.maxpacket;
1089 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1090 __func__, length, maxreq, round);
1092 /* round down to multiple of packets */
1100 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1102 packets = 1; /* send one packet if length is zero. */
1104 if (dir_in && index != 0)
1105 if (hs_ep->isochronous)
1106 epsize = DXEPTSIZ_MC(packets);
1108 epsize = DXEPTSIZ_MC(1);
1113 * zero length packet should be programmed on its own and should not
1114 * be counted in DIEPTSIZ.PktCnt with other packets.
1116 if (dir_in && ureq->zero && !continuing) {
1117 /* Test if zlp is actually required. */
1118 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1119 !(ureq->length % hs_ep->ep.maxpacket))
1120 hs_ep->send_zlp = 1;
1123 epsize |= DXEPTSIZ_PKTCNT(packets);
1124 epsize |= DXEPTSIZ_XFERSIZE(length);
1126 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1127 __func__, packets, length, ureq->length, epsize, epsize_reg);
1129 /* store the request as the current one we're doing */
1130 hs_ep->req = hs_req;
1132 if (using_desc_dma(hsotg)) {
1134 u32 mps = hs_ep->ep.maxpacket;
1136 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1140 else if (length % mps)
1141 length += (mps - (length % mps));
1145 offset = ureq->actual;
1147 /* Fill DDMA chain entries */
1148 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1151 /* write descriptor chain address to control register */
1152 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1154 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1155 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1157 /* write size / packets */
1158 dwc2_writel(hsotg, epsize, epsize_reg);
1160 if (using_dma(hsotg) && !continuing && (length != 0)) {
1162 * write DMA address to control register, buffer
1163 * already synced by dwc2_hsotg_ep_queue().
1166 dwc2_writel(hsotg, ureq->dma, dma_reg);
1168 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1169 __func__, &ureq->dma, dma_reg);
1173 if (hs_ep->isochronous && hs_ep->interval == 1) {
1174 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1175 dwc2_gadget_incr_frame_num(hs_ep);
1177 if (hs_ep->target_frame & 0x1)
1178 ctrl |= DXEPCTL_SETODDFR;
1180 ctrl |= DXEPCTL_SETEVENFR;
1183 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1185 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1187 /* For Setup request do not clear NAK */
1188 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1189 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1191 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1192 dwc2_writel(hsotg, ctrl, epctrl_reg);
1195 * set these, it seems that DMA support increments past the end
1196 * of the packet buffer so we need to calculate the length from
1199 hs_ep->size_loaded = length;
1200 hs_ep->last_load = ureq->actual;
1202 if (dir_in && !using_dma(hsotg)) {
1203 /* set these anyway, we may need them for non-periodic in */
1204 hs_ep->fifo_load = 0;
1206 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1210 * Note, trying to clear the NAK here causes problems with transmit
1211 * on the S3C6400 ending up with the TXFIFO becoming full.
1214 /* check ep is enabled */
1215 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1217 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1218 index, dwc2_readl(hsotg, epctrl_reg));
1220 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1221 __func__, dwc2_readl(hsotg, epctrl_reg));
1223 /* enable ep interrupts */
1224 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1228 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1229 * @hsotg: The device state.
1230 * @hs_ep: The endpoint the request is on.
1231 * @req: The request being processed.
1233 * We've been asked to queue a request, so ensure that the memory buffer
1234 * is correctly setup for DMA. If we've been passed an extant DMA address
1235 * then ensure the buffer has been synced to memory. If our buffer has no
1236 * DMA memory, then we map the memory and mark our request to allow us to
1237 * cleanup on completion.
1239 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1240 struct dwc2_hsotg_ep *hs_ep,
1241 struct usb_request *req)
1245 hs_ep->map_dir = hs_ep->dir_in;
1246 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1253 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1254 __func__, req->buf, req->length);
1259 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1260 struct dwc2_hsotg_ep *hs_ep,
1261 struct dwc2_hsotg_req *hs_req)
1263 void *req_buf = hs_req->req.buf;
1265 /* If dma is not being used or buffer is aligned */
1266 if (!using_dma(hsotg) || !((long)req_buf & 3))
1269 WARN_ON(hs_req->saved_req_buf);
1271 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1272 hs_ep->ep.name, req_buf, hs_req->req.length);
1274 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1275 if (!hs_req->req.buf) {
1276 hs_req->req.buf = req_buf;
1278 "%s: unable to allocate memory for bounce buffer\n",
1283 /* Save actual buffer */
1284 hs_req->saved_req_buf = req_buf;
1287 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1292 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1293 struct dwc2_hsotg_ep *hs_ep,
1294 struct dwc2_hsotg_req *hs_req)
1296 /* If dma is not being used or buffer was aligned */
1297 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1300 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1301 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1303 /* Copy data from bounce buffer on successful out transfer */
1304 if (!hs_ep->dir_in && !hs_req->req.status)
1305 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1306 hs_req->req.actual);
1308 /* Free bounce buffer */
1309 kfree(hs_req->req.buf);
1311 hs_req->req.buf = hs_req->saved_req_buf;
1312 hs_req->saved_req_buf = NULL;
1316 * dwc2_gadget_target_frame_elapsed - Checks target frame
1317 * @hs_ep: The driver endpoint to check
1319 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1320 * corresponding transfer.
1322 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1324 struct dwc2_hsotg *hsotg = hs_ep->parent;
1325 u32 target_frame = hs_ep->target_frame;
1326 u32 current_frame = hsotg->frame_number;
1327 bool frame_overrun = hs_ep->frame_overrun;
1329 if (!frame_overrun && current_frame >= target_frame)
1332 if (frame_overrun && current_frame >= target_frame &&
1333 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1340 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1341 * @hsotg: The driver state
1342 * @hs_ep: the ep descriptor chain is for
1344 * Called to update EP0 structure's pointers depend on stage of
1347 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1348 struct dwc2_hsotg_ep *hs_ep)
1350 switch (hsotg->ep0_state) {
1351 case DWC2_EP0_SETUP:
1352 case DWC2_EP0_STATUS_OUT:
1353 hs_ep->desc_list = hsotg->setup_desc[0];
1354 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1356 case DWC2_EP0_DATA_IN:
1357 case DWC2_EP0_STATUS_IN:
1358 hs_ep->desc_list = hsotg->ctrl_in_desc;
1359 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1361 case DWC2_EP0_DATA_OUT:
1362 hs_ep->desc_list = hsotg->ctrl_out_desc;
1363 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1366 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1374 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1377 struct dwc2_hsotg_req *hs_req = our_req(req);
1378 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1379 struct dwc2_hsotg *hs = hs_ep->parent;
1386 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1387 ep->name, req, req->length, req->buf, req->no_interrupt,
1388 req->zero, req->short_not_ok);
1390 /* Prevent new request submission when controller is suspended */
1391 if (hs->lx_state != DWC2_L0) {
1392 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1397 /* initialise status of the request */
1398 INIT_LIST_HEAD(&hs_req->queue);
1400 req->status = -EINPROGRESS;
1402 /* Don't queue ISOC request if length greater than mps*mc */
1403 if (hs_ep->isochronous &&
1404 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1405 dev_err(hs->dev, "req length > maxpacket*mc\n");
1409 /* In DDMA mode for ISOC's don't queue request if length greater
1410 * than descriptor limits.
1412 if (using_desc_dma(hs) && hs_ep->isochronous) {
1413 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1414 if (hs_ep->dir_in && req->length > maxsize) {
1415 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1416 req->length, maxsize);
1420 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1421 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1422 req->length, hs_ep->ep.maxpacket);
1427 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1431 /* if we're using DMA, sync the buffers as necessary */
1432 if (using_dma(hs)) {
1433 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1437 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1438 if (using_desc_dma(hs) && !hs_ep->index) {
1439 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1444 first = list_empty(&hs_ep->queue);
1445 list_add_tail(&hs_req->queue, &hs_ep->queue);
1448 * Handle DDMA isochronous transfers separately - just add new entry
1449 * to the descriptor chain.
1450 * Transfer will be started once SW gets either one of NAK or
1451 * OutTknEpDis interrupts.
1453 if (using_desc_dma(hs) && hs_ep->isochronous) {
1454 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1455 dma_addr_t dma_addr = hs_req->req.dma;
1457 if (hs_req->req.num_sgs) {
1458 WARN_ON(hs_req->req.num_sgs > 1);
1459 dma_addr = sg_dma_address(hs_req->req.sg);
1461 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1462 hs_req->req.length);
1467 /* Change EP direction if status phase request is after data out */
1468 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1469 hs->ep0_state == DWC2_EP0_DATA_OUT)
1473 if (!hs_ep->isochronous) {
1474 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1478 /* Update current frame number value. */
1479 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1480 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1481 dwc2_gadget_incr_frame_num(hs_ep);
1482 /* Update current frame number value once more as it
1485 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1488 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1489 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1494 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1497 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1498 struct dwc2_hsotg *hs = hs_ep->parent;
1499 unsigned long flags;
1502 spin_lock_irqsave(&hs->lock, flags);
1503 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1504 spin_unlock_irqrestore(&hs->lock, flags);
1509 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1510 struct usb_request *req)
1512 struct dwc2_hsotg_req *hs_req = our_req(req);
1518 * dwc2_hsotg_complete_oursetup - setup completion callback
1519 * @ep: The endpoint the request was on.
1520 * @req: The request completed.
1522 * Called on completion of any requests the driver itself
1523 * submitted that need cleaning up.
1525 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1526 struct usb_request *req)
1528 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1529 struct dwc2_hsotg *hsotg = hs_ep->parent;
1531 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1533 dwc2_hsotg_ep_free_request(ep, req);
1537 * ep_from_windex - convert control wIndex value to endpoint
1538 * @hsotg: The driver state.
1539 * @windex: The control request wIndex field (in host order).
1541 * Convert the given wIndex into a pointer to an driver endpoint
1542 * structure, or return NULL if it is not a valid endpoint.
1544 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1547 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1548 int idx = windex & 0x7F;
1550 if (windex >= 0x100)
1553 if (idx > hsotg->num_of_eps)
1556 return index_to_ep(hsotg, idx, dir);
1560 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1561 * @hsotg: The driver state.
1562 * @testmode: requested usb test mode
1563 * Enable usb Test Mode requested by the Host.
1565 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1567 int dctl = dwc2_readl(hsotg, DCTL);
1569 dctl &= ~DCTL_TSTCTL_MASK;
1573 case USB_TEST_SE0_NAK:
1574 case USB_TEST_PACKET:
1575 case USB_TEST_FORCE_ENABLE:
1576 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1581 dwc2_writel(hsotg, dctl, DCTL);
1586 * dwc2_hsotg_send_reply - send reply to control request
1587 * @hsotg: The device state
1589 * @buff: Buffer for request
1590 * @length: Length of reply.
1592 * Create a request and queue it on the given endpoint. This is useful as
1593 * an internal method of sending replies to certain control requests, etc.
1595 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1596 struct dwc2_hsotg_ep *ep,
1600 struct usb_request *req;
1603 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1605 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1606 hsotg->ep0_reply = req;
1608 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1612 req->buf = hsotg->ep0_buff;
1613 req->length = length;
1615 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1619 req->complete = dwc2_hsotg_complete_oursetup;
1622 memcpy(req->buf, buff, length);
1624 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1626 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1634 * dwc2_hsotg_process_req_status - process request GET_STATUS
1635 * @hsotg: The device state
1636 * @ctrl: USB control request
1638 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1639 struct usb_ctrlrequest *ctrl)
1641 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1642 struct dwc2_hsotg_ep *ep;
1647 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1650 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1654 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1655 case USB_RECIP_DEVICE:
1656 status = hsotg->gadget.is_selfpowered <<
1657 USB_DEVICE_SELF_POWERED;
1658 status |= hsotg->remote_wakeup_allowed <<
1659 USB_DEVICE_REMOTE_WAKEUP;
1660 reply = cpu_to_le16(status);
1663 case USB_RECIP_INTERFACE:
1664 /* currently, the data result should be zero */
1665 reply = cpu_to_le16(0);
1668 case USB_RECIP_ENDPOINT:
1669 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1673 reply = cpu_to_le16(ep->halted ? 1 : 0);
1680 if (le16_to_cpu(ctrl->wLength) != 2)
1683 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1685 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1692 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1695 * get_ep_head - return the first request on the endpoint
1696 * @hs_ep: The controller endpoint to get
1698 * Get the first request on the endpoint.
1700 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1702 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1707 * dwc2_gadget_start_next_request - Starts next request from ep queue
1708 * @hs_ep: Endpoint structure
1710 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1711 * in its handler. Hence we need to unmask it here to be able to do
1712 * resynchronization.
1714 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1717 struct dwc2_hsotg *hsotg = hs_ep->parent;
1718 int dir_in = hs_ep->dir_in;
1719 struct dwc2_hsotg_req *hs_req;
1720 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1722 if (!list_empty(&hs_ep->queue)) {
1723 hs_req = get_ep_head(hs_ep);
1724 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1727 if (!hs_ep->isochronous)
1731 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1734 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1736 mask = dwc2_readl(hsotg, epmsk_reg);
1737 mask |= DOEPMSK_OUTTKNEPDISMSK;
1738 dwc2_writel(hsotg, mask, epmsk_reg);
1743 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1744 * @hsotg: The device state
1745 * @ctrl: USB control request
1747 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1748 struct usb_ctrlrequest *ctrl)
1750 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1751 struct dwc2_hsotg_req *hs_req;
1752 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1753 struct dwc2_hsotg_ep *ep;
1760 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1761 __func__, set ? "SET" : "CLEAR");
1763 wValue = le16_to_cpu(ctrl->wValue);
1764 wIndex = le16_to_cpu(ctrl->wIndex);
1765 recip = ctrl->bRequestType & USB_RECIP_MASK;
1768 case USB_RECIP_DEVICE:
1770 case USB_DEVICE_REMOTE_WAKEUP:
1772 hsotg->remote_wakeup_allowed = 1;
1774 hsotg->remote_wakeup_allowed = 0;
1777 case USB_DEVICE_TEST_MODE:
1778 if ((wIndex & 0xff) != 0)
1783 hsotg->test_mode = wIndex >> 8;
1789 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1792 "%s: failed to send reply\n", __func__);
1797 case USB_RECIP_ENDPOINT:
1798 ep = ep_from_windex(hsotg, wIndex);
1800 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1806 case USB_ENDPOINT_HALT:
1807 halted = ep->halted;
1810 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1812 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1815 "%s: failed to send reply\n", __func__);
1820 * we have to complete all requests for ep if it was
1821 * halted, and the halt was cleared by CLEAR_FEATURE
1824 if (!set && halted) {
1826 * If we have request in progress,
1832 list_del_init(&hs_req->queue);
1833 if (hs_req->req.complete) {
1834 spin_unlock(&hsotg->lock);
1835 usb_gadget_giveback_request(
1836 &ep->ep, &hs_req->req);
1837 spin_lock(&hsotg->lock);
1841 /* If we have pending request, then start it */
1843 dwc2_gadget_start_next_request(ep);
1858 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1861 * dwc2_hsotg_stall_ep0 - stall ep0
1862 * @hsotg: The device state
1864 * Set stall for ep0 as response for setup request.
1866 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1868 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1872 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1873 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1876 * DxEPCTL_Stall will be cleared by EP once it has
1877 * taken effect, so no need to clear later.
1880 ctrl = dwc2_readl(hsotg, reg);
1881 ctrl |= DXEPCTL_STALL;
1882 ctrl |= DXEPCTL_CNAK;
1883 dwc2_writel(hsotg, ctrl, reg);
1886 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1887 ctrl, reg, dwc2_readl(hsotg, reg));
1890 * complete won't be called, so we enqueue
1891 * setup request here
1893 dwc2_hsotg_enqueue_setup(hsotg);
1897 * dwc2_hsotg_process_control - process a control request
1898 * @hsotg: The device state
1899 * @ctrl: The control request received
1901 * The controller has received the SETUP phase of a control request, and
1902 * needs to work out what to do next (and whether to pass it on to the
1905 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1906 struct usb_ctrlrequest *ctrl)
1908 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1913 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1914 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1915 ctrl->wIndex, ctrl->wLength);
1917 if (ctrl->wLength == 0) {
1919 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1920 } else if (ctrl->bRequestType & USB_DIR_IN) {
1922 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1925 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1928 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1929 switch (ctrl->bRequest) {
1930 case USB_REQ_SET_ADDRESS:
1931 hsotg->connected = 1;
1932 dcfg = dwc2_readl(hsotg, DCFG);
1933 dcfg &= ~DCFG_DEVADDR_MASK;
1934 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1935 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1936 dwc2_writel(hsotg, dcfg, DCFG);
1938 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1940 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1943 case USB_REQ_GET_STATUS:
1944 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1947 case USB_REQ_CLEAR_FEATURE:
1948 case USB_REQ_SET_FEATURE:
1949 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1954 /* as a fallback, try delivering it to the driver to deal with */
1956 if (ret == 0 && hsotg->driver) {
1957 spin_unlock(&hsotg->lock);
1958 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1959 spin_lock(&hsotg->lock);
1961 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1964 hsotg->delayed_status = false;
1965 if (ret == USB_GADGET_DELAYED_STATUS)
1966 hsotg->delayed_status = true;
1969 * the request is either unhandlable, or is not formatted correctly
1970 * so respond with a STALL for the status stage to indicate failure.
1974 dwc2_hsotg_stall_ep0(hsotg);
1978 * dwc2_hsotg_complete_setup - completion of a setup transfer
1979 * @ep: The endpoint the request was on.
1980 * @req: The request completed.
1982 * Called on completion of any requests the driver itself submitted for
1985 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1986 struct usb_request *req)
1988 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1989 struct dwc2_hsotg *hsotg = hs_ep->parent;
1991 if (req->status < 0) {
1992 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1996 spin_lock(&hsotg->lock);
1997 if (req->actual == 0)
1998 dwc2_hsotg_enqueue_setup(hsotg);
2000 dwc2_hsotg_process_control(hsotg, req->buf);
2001 spin_unlock(&hsotg->lock);
2005 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2006 * @hsotg: The device state.
2008 * Enqueue a request on EP0 if necessary to received any SETUP packets
2009 * received from the host.
2011 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2013 struct usb_request *req = hsotg->ctrl_req;
2014 struct dwc2_hsotg_req *hs_req = our_req(req);
2017 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2021 req->buf = hsotg->ctrl_buff;
2022 req->complete = dwc2_hsotg_complete_setup;
2024 if (!list_empty(&hs_req->queue)) {
2025 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2029 hsotg->eps_out[0]->dir_in = 0;
2030 hsotg->eps_out[0]->send_zlp = 0;
2031 hsotg->ep0_state = DWC2_EP0_SETUP;
2033 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2035 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2037 * Don't think there's much we can do other than watch the
2043 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2044 struct dwc2_hsotg_ep *hs_ep)
2047 u8 index = hs_ep->index;
2048 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2049 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2052 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2055 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2057 if (using_desc_dma(hsotg)) {
2058 /* Not specific buffer needed for ep0 ZLP */
2059 dma_addr_t dma = hs_ep->desc_list_dma;
2062 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2064 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2066 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2067 DXEPTSIZ_XFERSIZE(0),
2071 ctrl = dwc2_readl(hsotg, epctl_reg);
2072 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2073 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2074 ctrl |= DXEPCTL_USBACTEP;
2075 dwc2_writel(hsotg, ctrl, epctl_reg);
2079 * dwc2_hsotg_complete_request - complete a request given to us
2080 * @hsotg: The device state.
2081 * @hs_ep: The endpoint the request was on.
2082 * @hs_req: The request to complete.
2083 * @result: The result code (0 => Ok, otherwise errno)
2085 * The given request has finished, so call the necessary completion
2086 * if it has one and then look to see if we can start a new request
2089 * Note, expects the ep to already be locked as appropriate.
2091 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2092 struct dwc2_hsotg_ep *hs_ep,
2093 struct dwc2_hsotg_req *hs_req,
2097 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2101 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2102 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2105 * only replace the status if we've not already set an error
2106 * from a previous transaction
2109 if (hs_req->req.status == -EINPROGRESS)
2110 hs_req->req.status = result;
2112 if (using_dma(hsotg))
2113 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2115 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2118 list_del_init(&hs_req->queue);
2121 * call the complete request with the locks off, just in case the
2122 * request tries to queue more work for this endpoint.
2125 if (hs_req->req.complete) {
2126 spin_unlock(&hsotg->lock);
2127 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2128 spin_lock(&hsotg->lock);
2131 /* In DDMA don't need to proceed to starting of next ISOC request */
2132 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2136 * Look to see if there is anything else to do. Note, the completion
2137 * of the previous request may have caused a new request to be started
2138 * so be careful when doing this.
2141 if (!hs_ep->req && result >= 0)
2142 dwc2_gadget_start_next_request(hs_ep);
2146 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2147 * @hs_ep: The endpoint the request was on.
2149 * Get first request from the ep queue, determine descriptor on which complete
2150 * happened. SW discovers which descriptor currently in use by HW, adjusts
2151 * dma_address and calculates index of completed descriptor based on the value
2152 * of DEPDMA register. Update actual length of request, giveback to gadget.
2154 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2156 struct dwc2_hsotg *hsotg = hs_ep->parent;
2157 struct dwc2_hsotg_req *hs_req;
2158 struct usb_request *ureq;
2162 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2164 /* Process only descriptors with buffer status set to DMA done */
2165 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2166 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2168 hs_req = get_ep_head(hs_ep);
2170 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2173 ureq = &hs_req->req;
2175 /* Check completion status */
2176 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2178 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2179 DEV_DMA_ISOC_RX_NBYTES_MASK;
2180 ureq->actual = ureq->length - ((desc_sts & mask) >>
2181 DEV_DMA_ISOC_NBYTES_SHIFT);
2183 /* Adjust actual len for ISOC Out if len is
2186 if (!hs_ep->dir_in && ureq->length & 0x3)
2187 ureq->actual += 4 - (ureq->length & 0x3);
2189 /* Set actual frame number for completed transfers */
2190 ureq->frame_number =
2191 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2192 DEV_DMA_ISOC_FRNUM_SHIFT;
2195 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2197 hs_ep->compl_desc++;
2198 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2199 hs_ep->compl_desc = 0;
2200 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2205 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2206 * @hs_ep: The isochronous endpoint.
2208 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2209 * interrupt. Reset target frame and next_desc to allow to start
2210 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2211 * interrupt for OUT direction.
2213 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2215 struct dwc2_hsotg *hsotg = hs_ep->parent;
2218 dwc2_flush_rx_fifo(hsotg);
2219 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2221 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2222 hs_ep->next_desc = 0;
2223 hs_ep->compl_desc = 0;
2227 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2228 * @hsotg: The device state.
2229 * @ep_idx: The endpoint index for the data
2230 * @size: The size of data in the fifo, in bytes
2232 * The FIFO status shows there is data to read from the FIFO for a given
2233 * endpoint, so sort out whether we need to read the data into a request
2234 * that has been made for that endpoint.
2236 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2238 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2239 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2245 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2249 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2250 __func__, size, ep_idx, epctl);
2252 /* dump the data from the FIFO, we've nothing we can do */
2253 for (ptr = 0; ptr < size; ptr += 4)
2254 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2260 read_ptr = hs_req->req.actual;
2261 max_req = hs_req->req.length - read_ptr;
2263 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2264 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2266 if (to_read > max_req) {
2268 * more data appeared than we where willing
2269 * to deal with in this request.
2272 /* currently we don't deal this */
2276 hs_ep->total_data += to_read;
2277 hs_req->req.actual += to_read;
2278 to_read = DIV_ROUND_UP(to_read, 4);
2281 * note, we might over-write the buffer end by 3 bytes depending on
2282 * alignment of the data.
2284 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2285 hs_req->req.buf + read_ptr, to_read);
2289 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2290 * @hsotg: The device instance
2291 * @dir_in: If IN zlp
2293 * Generate a zero-length IN packet request for terminating a SETUP
2296 * Note, since we don't write any data to the TxFIFO, then it is
2297 * currently believed that we do not need to wait for any space in
2300 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2302 /* eps_out[0] is used in both directions */
2303 hsotg->eps_out[0]->dir_in = dir_in;
2304 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2306 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2309 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2314 ctrl = dwc2_readl(hsotg, epctl_reg);
2315 if (ctrl & DXEPCTL_EOFRNUM)
2316 ctrl |= DXEPCTL_SETEVENFR;
2318 ctrl |= DXEPCTL_SETODDFR;
2319 dwc2_writel(hsotg, ctrl, epctl_reg);
2323 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2324 * @hs_ep - The endpoint on which transfer went
2326 * Iterate over endpoints descriptor chain and get info on bytes remained
2327 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2329 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2331 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2332 struct dwc2_hsotg *hsotg = hs_ep->parent;
2333 unsigned int bytes_rem = 0;
2334 unsigned int bytes_rem_correction = 0;
2335 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2338 u32 mps = hs_ep->ep.maxpacket;
2339 int dir_in = hs_ep->dir_in;
2344 /* Interrupt OUT EP with mps not multiple of 4 */
2346 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2347 bytes_rem_correction = 4 - (mps % 4);
2349 for (i = 0; i < hs_ep->desc_count; ++i) {
2350 status = desc->status;
2351 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2352 bytes_rem -= bytes_rem_correction;
2354 if (status & DEV_DMA_STS_MASK)
2355 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2356 i, status & DEV_DMA_STS_MASK);
2358 if (status & DEV_DMA_L)
2368 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2369 * @hsotg: The device instance
2370 * @epnum: The endpoint received from
2372 * The RXFIFO has delivered an OutDone event, which means that the data
2373 * transfer for an OUT endpoint has been completed, either by a short
2374 * packet or by the finish of a transfer.
2376 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2378 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2379 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2380 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2381 struct usb_request *req = &hs_req->req;
2382 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2386 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2390 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2391 dev_dbg(hsotg->dev, "zlp packet received\n");
2392 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2393 dwc2_hsotg_enqueue_setup(hsotg);
2397 if (using_desc_dma(hsotg))
2398 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2400 if (using_dma(hsotg)) {
2401 unsigned int size_done;
2404 * Calculate the size of the transfer by checking how much
2405 * is left in the endpoint size register and then working it
2406 * out from the amount we loaded for the transfer.
2408 * We need to do this as DMA pointers are always 32bit aligned
2409 * so may overshoot/undershoot the transfer.
2412 size_done = hs_ep->size_loaded - size_left;
2413 size_done += hs_ep->last_load;
2415 req->actual = size_done;
2418 /* if there is more request to do, schedule new transfer */
2419 if (req->actual < req->length && size_left == 0) {
2420 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2424 if (req->actual < req->length && req->short_not_ok) {
2425 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2426 __func__, req->actual, req->length);
2429 * todo - what should we return here? there's no one else
2430 * even bothering to check the status.
2434 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2435 if (!using_desc_dma(hsotg) && epnum == 0 &&
2436 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2437 /* Move to STATUS IN */
2438 if (!hsotg->delayed_status)
2439 dwc2_hsotg_ep0_zlp(hsotg, true);
2443 * Slave mode OUT transfers do not go through XferComplete so
2444 * adjust the ISOC parity here.
2446 if (!using_dma(hsotg)) {
2447 if (hs_ep->isochronous && hs_ep->interval == 1)
2448 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2449 else if (hs_ep->isochronous && hs_ep->interval > 1)
2450 dwc2_gadget_incr_frame_num(hs_ep);
2453 /* Set actual frame number for completed transfers */
2454 if (!using_desc_dma(hsotg) && hs_ep->isochronous)
2455 req->frame_number = hsotg->frame_number;
2457 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2461 * dwc2_hsotg_handle_rx - RX FIFO has data
2462 * @hsotg: The device instance
2464 * The IRQ handler has detected that the RX FIFO has some data in it
2465 * that requires processing, so find out what is in there and do the
2468 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2469 * chunks, so if you have x packets received on an endpoint you'll get x
2470 * FIFO events delivered, each with a packet's worth of data in it.
2472 * When using DMA, we should not be processing events from the RXFIFO
2473 * as the actual data should be sent to the memory directly and we turn
2474 * on the completion interrupts to get notifications of transfer completion.
2476 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2478 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2479 u32 epnum, status, size;
2481 WARN_ON(using_dma(hsotg));
2483 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2484 status = grxstsr & GRXSTS_PKTSTS_MASK;
2486 size = grxstsr & GRXSTS_BYTECNT_MASK;
2487 size >>= GRXSTS_BYTECNT_SHIFT;
2489 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2490 __func__, grxstsr, size, epnum);
2492 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2493 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2494 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2497 case GRXSTS_PKTSTS_OUTDONE:
2498 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2499 dwc2_hsotg_read_frameno(hsotg));
2501 if (!using_dma(hsotg))
2502 dwc2_hsotg_handle_outdone(hsotg, epnum);
2505 case GRXSTS_PKTSTS_SETUPDONE:
2507 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2508 dwc2_hsotg_read_frameno(hsotg),
2509 dwc2_readl(hsotg, DOEPCTL(0)));
2511 * Call dwc2_hsotg_handle_outdone here if it was not called from
2512 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2513 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2515 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2516 dwc2_hsotg_handle_outdone(hsotg, epnum);
2519 case GRXSTS_PKTSTS_OUTRX:
2520 dwc2_hsotg_rx_data(hsotg, epnum, size);
2523 case GRXSTS_PKTSTS_SETUPRX:
2525 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2526 dwc2_hsotg_read_frameno(hsotg),
2527 dwc2_readl(hsotg, DOEPCTL(0)));
2529 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2531 dwc2_hsotg_rx_data(hsotg, epnum, size);
2535 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2538 dwc2_hsotg_dump(hsotg);
2544 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2545 * @mps: The maximum packet size in bytes.
2547 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2551 return D0EPCTL_MPS_64;
2553 return D0EPCTL_MPS_32;
2555 return D0EPCTL_MPS_16;
2557 return D0EPCTL_MPS_8;
2560 /* bad max packet size, warn and return invalid result */
2566 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2567 * @hsotg: The driver state.
2568 * @ep: The index number of the endpoint
2569 * @mps: The maximum packet size in bytes
2570 * @mc: The multicount value
2571 * @dir_in: True if direction is in.
2573 * Configure the maximum packet size for the given endpoint, updating
2574 * the hardware control registers to reflect this.
2576 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2577 unsigned int ep, unsigned int mps,
2578 unsigned int mc, unsigned int dir_in)
2580 struct dwc2_hsotg_ep *hs_ep;
2583 hs_ep = index_to_ep(hsotg, ep, dir_in);
2588 u32 mps_bytes = mps;
2590 /* EP0 is a special case */
2591 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2594 hs_ep->ep.maxpacket = mps_bytes;
2602 hs_ep->ep.maxpacket = mps;
2606 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2607 reg &= ~DXEPCTL_MPS_MASK;
2609 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2611 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2612 reg &= ~DXEPCTL_MPS_MASK;
2614 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2620 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2624 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2625 * @hsotg: The driver state
2626 * @idx: The index for the endpoint (0..15)
2628 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2630 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2633 /* wait until the fifo is flushed */
2634 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2635 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2640 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2641 * @hsotg: The driver state
2642 * @hs_ep: The driver endpoint to check.
2644 * Check to see if there is a request that has data to send, and if so
2645 * make an attempt to write data into the FIFO.
2647 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2648 struct dwc2_hsotg_ep *hs_ep)
2650 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2652 if (!hs_ep->dir_in || !hs_req) {
2654 * if request is not enqueued, we disable interrupts
2655 * for endpoints, excepting ep0
2657 if (hs_ep->index != 0)
2658 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2663 if (hs_req->req.actual < hs_req->req.length) {
2664 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2666 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2673 * dwc2_hsotg_complete_in - complete IN transfer
2674 * @hsotg: The device state.
2675 * @hs_ep: The endpoint that has just completed.
2677 * An IN transfer has been completed, update the transfer's state and then
2678 * call the relevant completion routines.
2680 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2681 struct dwc2_hsotg_ep *hs_ep)
2683 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2684 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2685 int size_left, size_done;
2688 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2692 /* Finish ZLP handling for IN EP0 transactions */
2693 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2694 dev_dbg(hsotg->dev, "zlp packet sent\n");
2697 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2698 * changed to IN. Change back to complete OUT transfer request
2702 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2703 if (hsotg->test_mode) {
2706 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2708 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2710 dwc2_hsotg_stall_ep0(hsotg);
2714 dwc2_hsotg_enqueue_setup(hsotg);
2719 * Calculate the size of the transfer by checking how much is left
2720 * in the endpoint size register and then working it out from
2721 * the amount we loaded for the transfer.
2723 * We do this even for DMA, as the transfer may have incremented
2724 * past the end of the buffer (DMA transfers are always 32bit
2727 if (using_desc_dma(hsotg)) {
2728 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2730 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2733 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2736 size_done = hs_ep->size_loaded - size_left;
2737 size_done += hs_ep->last_load;
2739 if (hs_req->req.actual != size_done)
2740 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2741 __func__, hs_req->req.actual, size_done);
2743 hs_req->req.actual = size_done;
2744 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2745 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2747 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2748 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2749 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2753 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2754 if (hs_ep->send_zlp) {
2755 hs_ep->send_zlp = 0;
2756 if (!using_desc_dma(hsotg)) {
2757 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2758 /* transfer will be completed on next complete interrupt */
2763 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2764 /* Move to STATUS OUT */
2765 dwc2_hsotg_ep0_zlp(hsotg, false);
2769 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2773 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2774 * @hsotg: The device state.
2775 * @idx: Index of ep.
2776 * @dir_in: Endpoint direction 1-in 0-out.
2778 * Reads for endpoint with given index and direction, by masking
2779 * epint_reg with coresponding mask.
2781 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2782 unsigned int idx, int dir_in)
2784 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2785 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2790 mask = dwc2_readl(hsotg, epmsk_reg);
2791 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2792 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2793 mask |= DXEPINT_SETUP_RCVD;
2795 ints = dwc2_readl(hsotg, epint_reg);
2801 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2802 * @hs_ep: The endpoint on which interrupt is asserted.
2804 * This interrupt indicates that the endpoint has been disabled per the
2805 * application's request.
2807 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2808 * in case of ISOC completes current request.
2810 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2811 * request starts it.
2813 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2815 struct dwc2_hsotg *hsotg = hs_ep->parent;
2816 struct dwc2_hsotg_req *hs_req;
2817 unsigned char idx = hs_ep->index;
2818 int dir_in = hs_ep->dir_in;
2819 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2820 int dctl = dwc2_readl(hsotg, DCTL);
2822 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2825 int epctl = dwc2_readl(hsotg, epctl_reg);
2827 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2829 if (hs_ep->isochronous) {
2830 dwc2_hsotg_complete_in(hsotg, hs_ep);
2834 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2835 int dctl = dwc2_readl(hsotg, DCTL);
2837 dctl |= DCTL_CGNPINNAK;
2838 dwc2_writel(hsotg, dctl, DCTL);
2843 if (dctl & DCTL_GOUTNAKSTS) {
2844 dctl |= DCTL_CGOUTNAK;
2845 dwc2_writel(hsotg, dctl, DCTL);
2848 if (!hs_ep->isochronous)
2851 if (list_empty(&hs_ep->queue)) {
2852 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2858 hs_req = get_ep_head(hs_ep);
2860 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2862 dwc2_gadget_incr_frame_num(hs_ep);
2863 /* Update current frame number value. */
2864 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2865 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2867 dwc2_gadget_start_next_request(hs_ep);
2871 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2872 * @ep: The endpoint on which interrupt is asserted.
2874 * This is starting point for ISOC-OUT transfer, synchronization done with
2875 * first out token received from host while corresponding EP is disabled.
2877 * Device does not know initial frame in which out token will come. For this
2878 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2879 * getting this interrupt SW starts calculation for next transfer frame.
2881 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2883 struct dwc2_hsotg *hsotg = ep->parent;
2884 int dir_in = ep->dir_in;
2887 if (dir_in || !ep->isochronous)
2890 if (using_desc_dma(hsotg)) {
2891 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2892 /* Start first ISO Out */
2893 ep->target_frame = hsotg->frame_number;
2894 dwc2_gadget_start_isoc_ddma(ep);
2899 if (ep->interval > 1 &&
2900 ep->target_frame == TARGET_FRAME_INITIAL) {
2903 ep->target_frame = hsotg->frame_number;
2904 dwc2_gadget_incr_frame_num(ep);
2906 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2907 if (ep->target_frame & 0x1)
2908 ctrl |= DXEPCTL_SETODDFR;
2910 ctrl |= DXEPCTL_SETEVENFR;
2912 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2915 dwc2_gadget_start_next_request(ep);
2916 doepmsk = dwc2_readl(hsotg, DOEPMSK);
2917 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2918 dwc2_writel(hsotg, doepmsk, DOEPMSK);
2922 * dwc2_gadget_handle_nak - handle NAK interrupt
2923 * @hs_ep: The endpoint on which interrupt is asserted.
2925 * This is starting point for ISOC-IN transfer, synchronization done with
2926 * first IN token received from host while corresponding EP is disabled.
2928 * Device does not know when first one token will arrive from host. On first
2929 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2930 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2931 * sent in response to that as there was no data in FIFO. SW is basing on this
2932 * interrupt to obtain frame in which token has come and then based on the
2933 * interval calculates next frame for transfer.
2935 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2937 struct dwc2_hsotg *hsotg = hs_ep->parent;
2938 int dir_in = hs_ep->dir_in;
2940 if (!dir_in || !hs_ep->isochronous)
2943 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2945 if (using_desc_dma(hsotg)) {
2946 hs_ep->target_frame = hsotg->frame_number;
2947 dwc2_gadget_incr_frame_num(hs_ep);
2949 /* In service interval mode target_frame must
2950 * be set to last (u)frame of the service interval.
2952 if (hsotg->params.service_interval) {
2953 /* Set target_frame to the first (u)frame of
2954 * the service interval
2956 hs_ep->target_frame &= ~hs_ep->interval + 1;
2958 /* Set target_frame to the last (u)frame of
2959 * the service interval
2961 dwc2_gadget_incr_frame_num(hs_ep);
2962 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2965 dwc2_gadget_start_isoc_ddma(hs_ep);
2969 hs_ep->target_frame = hsotg->frame_number;
2970 if (hs_ep->interval > 1) {
2971 u32 ctrl = dwc2_readl(hsotg,
2972 DIEPCTL(hs_ep->index));
2973 if (hs_ep->target_frame & 0x1)
2974 ctrl |= DXEPCTL_SETODDFR;
2976 ctrl |= DXEPCTL_SETEVENFR;
2978 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2981 dwc2_hsotg_complete_request(hsotg, hs_ep,
2982 get_ep_head(hs_ep), 0);
2985 if (!using_desc_dma(hsotg))
2986 dwc2_gadget_incr_frame_num(hs_ep);
2990 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2991 * @hsotg: The driver state
2992 * @idx: The index for the endpoint (0..15)
2993 * @dir_in: Set if this is an IN endpoint
2995 * Process and clear any interrupt pending for an individual endpoint
2997 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3000 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3001 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3002 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3003 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3006 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3008 /* Clear endpoint interrupts */
3009 dwc2_writel(hsotg, ints, epint_reg);
3012 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3013 __func__, idx, dir_in ? "in" : "out");
3017 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3018 __func__, idx, dir_in ? "in" : "out", ints);
3020 /* Don't process XferCompl interrupt if it is a setup packet */
3021 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3022 ints &= ~DXEPINT_XFERCOMPL;
3025 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3026 * stage and xfercomplete was generated without SETUP phase done
3027 * interrupt. SW should parse received setup packet only after host's
3028 * exit from setup phase of control transfer.
3030 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3031 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3032 ints &= ~DXEPINT_XFERCOMPL;
3034 if (ints & DXEPINT_XFERCOMPL) {
3036 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3037 __func__, dwc2_readl(hsotg, epctl_reg),
3038 dwc2_readl(hsotg, epsiz_reg));
3040 /* In DDMA handle isochronous requests separately */
3041 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3042 /* XferCompl set along with BNA */
3043 if (!(ints & DXEPINT_BNAINTR))
3044 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3045 } else if (dir_in) {
3047 * We get OutDone from the FIFO, so we only
3048 * need to look at completing IN requests here
3049 * if operating slave mode
3051 if (hs_ep->isochronous && hs_ep->interval > 1)
3052 dwc2_gadget_incr_frame_num(hs_ep);
3054 dwc2_hsotg_complete_in(hsotg, hs_ep);
3055 if (ints & DXEPINT_NAKINTRPT)
3056 ints &= ~DXEPINT_NAKINTRPT;
3058 if (idx == 0 && !hs_ep->req)
3059 dwc2_hsotg_enqueue_setup(hsotg);
3060 } else if (using_dma(hsotg)) {
3062 * We're using DMA, we need to fire an OutDone here
3063 * as we ignore the RXFIFO.
3065 if (hs_ep->isochronous && hs_ep->interval > 1)
3066 dwc2_gadget_incr_frame_num(hs_ep);
3068 dwc2_hsotg_handle_outdone(hsotg, idx);
3072 if (ints & DXEPINT_EPDISBLD)
3073 dwc2_gadget_handle_ep_disabled(hs_ep);
3075 if (ints & DXEPINT_OUTTKNEPDIS)
3076 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3078 if (ints & DXEPINT_NAKINTRPT)
3079 dwc2_gadget_handle_nak(hs_ep);
3081 if (ints & DXEPINT_AHBERR)
3082 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3084 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3085 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3087 if (using_dma(hsotg) && idx == 0) {
3089 * this is the notification we've received a
3090 * setup packet. In non-DMA mode we'd get this
3091 * from the RXFIFO, instead we need to process
3098 dwc2_hsotg_handle_outdone(hsotg, 0);
3102 if (ints & DXEPINT_STSPHSERCVD) {
3103 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3105 /* Safety check EP0 state when STSPHSERCVD asserted */
3106 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3107 /* Move to STATUS IN for DDMA */
3108 if (using_desc_dma(hsotg)) {
3109 if (!hsotg->delayed_status)
3110 dwc2_hsotg_ep0_zlp(hsotg, true);
3112 /* In case of 3 stage Control Write with delayed
3113 * status, when Status IN transfer started
3114 * before STSPHSERCVD asserted, NAKSTS bit not
3115 * cleared by CNAK in dwc2_hsotg_start_req()
3116 * function. Clear now NAKSTS to allow complete
3119 dwc2_set_bit(hsotg, DIEPCTL(0),
3126 if (ints & DXEPINT_BACK2BACKSETUP)
3127 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3129 if (ints & DXEPINT_BNAINTR) {
3130 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3131 if (hs_ep->isochronous)
3132 dwc2_gadget_handle_isoc_bna(hs_ep);
3135 if (dir_in && !hs_ep->isochronous) {
3136 /* not sure if this is important, but we'll clear it anyway */
3137 if (ints & DXEPINT_INTKNTXFEMP) {
3138 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3142 /* this probably means something bad is happening */
3143 if (ints & DXEPINT_INTKNEPMIS) {
3144 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3148 /* FIFO has space or is empty (see GAHBCFG) */
3149 if (hsotg->dedicated_fifos &&
3150 ints & DXEPINT_TXFEMP) {
3151 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3153 if (!using_dma(hsotg))
3154 dwc2_hsotg_trytx(hsotg, hs_ep);
3160 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3161 * @hsotg: The device state.
3163 * Handle updating the device settings after the enumeration phase has
3166 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3168 u32 dsts = dwc2_readl(hsotg, DSTS);
3169 int ep0_mps = 0, ep_mps = 8;
3172 * This should signal the finish of the enumeration phase
3173 * of the USB handshaking, so we should now know what rate
3177 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3180 * note, since we're limited by the size of transfer on EP0, and
3181 * it seems IN transfers must be a even number of packets we do
3182 * not advertise a 64byte MPS on EP0.
3185 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3186 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3187 case DSTS_ENUMSPD_FS:
3188 case DSTS_ENUMSPD_FS48:
3189 hsotg->gadget.speed = USB_SPEED_FULL;
3190 ep0_mps = EP0_MPS_LIMIT;
3194 case DSTS_ENUMSPD_HS:
3195 hsotg->gadget.speed = USB_SPEED_HIGH;
3196 ep0_mps = EP0_MPS_LIMIT;
3200 case DSTS_ENUMSPD_LS:
3201 hsotg->gadget.speed = USB_SPEED_LOW;
3205 * note, we don't actually support LS in this driver at the
3206 * moment, and the documentation seems to imply that it isn't
3207 * supported by the PHYs on some of the devices.
3211 dev_info(hsotg->dev, "new device is %s\n",
3212 usb_speed_string(hsotg->gadget.speed));
3215 * we should now know the maximum packet size for an
3216 * endpoint, so set the endpoints to a default value.
3221 /* Initialize ep0 for both in and out directions */
3222 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3223 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3224 for (i = 1; i < hsotg->num_of_eps; i++) {
3225 if (hsotg->eps_in[i])
3226 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3228 if (hsotg->eps_out[i])
3229 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3234 /* ensure after enumeration our EP0 is active */
3236 dwc2_hsotg_enqueue_setup(hsotg);
3238 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3239 dwc2_readl(hsotg, DIEPCTL0),
3240 dwc2_readl(hsotg, DOEPCTL0));
3244 * kill_all_requests - remove all requests from the endpoint's queue
3245 * @hsotg: The device state.
3246 * @ep: The endpoint the requests may be on.
3247 * @result: The result code to use.
3249 * Go through the requests on the given endpoint and mark them
3250 * completed with the given result code.
3252 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3253 struct dwc2_hsotg_ep *ep,
3260 while (!list_empty(&ep->queue)) {
3261 struct dwc2_hsotg_req *req = get_ep_head(ep);
3263 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3266 if (!hsotg->dedicated_fifos)
3268 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3269 if (size < ep->fifo_size)
3270 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3274 * dwc2_hsotg_disconnect - disconnect service
3275 * @hsotg: The device state.
3277 * The device has been disconnected. Remove all current
3278 * transactions and signal the gadget driver that this
3281 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3285 if (!hsotg->connected)
3288 hsotg->connected = 0;
3289 hsotg->test_mode = 0;
3291 /* all endpoints should be shutdown */
3292 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3293 if (hsotg->eps_in[ep])
3294 kill_all_requests(hsotg, hsotg->eps_in[ep],
3296 if (hsotg->eps_out[ep])
3297 kill_all_requests(hsotg, hsotg->eps_out[ep],
3301 call_gadget(hsotg, disconnect);
3302 hsotg->lx_state = DWC2_L3;
3304 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3308 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3309 * @hsotg: The device state:
3310 * @periodic: True if this is a periodic FIFO interrupt
3312 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3314 struct dwc2_hsotg_ep *ep;
3317 /* look through for any more data to transmit */
3318 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3319 ep = index_to_ep(hsotg, epno, 1);
3327 if ((periodic && !ep->periodic) ||
3328 (!periodic && ep->periodic))
3331 ret = dwc2_hsotg_trytx(hsotg, ep);
3337 /* IRQ flags which will trigger a retry around the IRQ loop */
3338 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3342 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3344 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3345 * @hsotg: The device state
3346 * @is_usb_reset: Usb resetting flag
3348 * Issue a soft reset to the core, and await the core finishing it.
3350 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3359 /* Kill any ep0 requests as controller will be reinitialized */
3360 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3362 if (!is_usb_reset) {
3363 if (dwc2_core_reset(hsotg, true))
3366 /* all endpoints should be shutdown */
3367 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3368 if (hsotg->eps_in[ep])
3369 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3370 if (hsotg->eps_out[ep])
3371 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3376 * we must now enable ep0 ready for host detection and then
3377 * set configuration.
3380 /* keep other bits untouched (so e.g. forced modes are not lost) */
3381 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3382 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3383 usbcfg |= GUSBCFG_TOUTCAL(7);
3385 /* remove the HNP/SRP and set the PHY */
3386 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3387 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3389 dwc2_phy_init(hsotg, true);
3391 dwc2_hsotg_init_fifo(hsotg);
3394 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3396 dcfg |= DCFG_EPMISCNT(1);
3398 switch (hsotg->params.speed) {
3399 case DWC2_SPEED_PARAM_LOW:
3400 dcfg |= DCFG_DEVSPD_LS;
3402 case DWC2_SPEED_PARAM_FULL:
3403 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3404 dcfg |= DCFG_DEVSPD_FS48;
3406 dcfg |= DCFG_DEVSPD_FS;
3409 dcfg |= DCFG_DEVSPD_HS;
3412 if (hsotg->params.ipg_isoc_en)
3413 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3415 dwc2_writel(hsotg, dcfg, DCFG);
3417 /* Clear any pending OTG interrupts */
3418 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3420 /* Clear any pending interrupts */
3421 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3422 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3423 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3424 GINTSTS_USBRST | GINTSTS_RESETDET |
3425 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3426 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3427 GINTSTS_LPMTRANRCVD;
3429 if (!using_desc_dma(hsotg))
3430 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3432 if (!hsotg->params.external_id_pin_ctl)
3433 intmsk |= GINTSTS_CONIDSTSCHNG;
3435 dwc2_writel(hsotg, intmsk, GINTMSK);
3437 if (using_dma(hsotg)) {
3438 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3439 hsotg->params.ahbcfg,
3442 /* Set DDMA mode support in the core if needed */
3443 if (using_desc_dma(hsotg))
3444 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3447 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3448 (GAHBCFG_NP_TXF_EMP_LVL |
3449 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3450 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3454 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3455 * when we have no data to transfer. Otherwise we get being flooded by
3459 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3460 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3461 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3462 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3466 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3467 * DMA mode we may need this and StsPhseRcvd.
3469 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3470 DOEPMSK_STSPHSERCVDMSK) : 0) |
3471 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3475 /* Enable BNA interrupt for DDMA */
3476 if (using_desc_dma(hsotg)) {
3477 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3478 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3481 /* Enable Service Interval mode if supported */
3482 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3483 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3485 dwc2_writel(hsotg, 0, DAINTMSK);
3487 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3488 dwc2_readl(hsotg, DIEPCTL0),
3489 dwc2_readl(hsotg, DOEPCTL0));
3491 /* enable in and out endpoint interrupts */
3492 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3495 * Enable the RXFIFO when in slave mode, as this is how we collect
3496 * the data. In DMA mode, we get events from the FIFO but also
3497 * things we cannot process, so do not use it.
3499 if (!using_dma(hsotg))
3500 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3502 /* Enable interrupts for EP0 in and out */
3503 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3504 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3506 if (!is_usb_reset) {
3507 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3508 udelay(10); /* see openiboot */
3509 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3512 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3515 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3516 * writing to the EPCTL register..
3519 /* set to read 1 8byte packet */
3520 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3521 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3523 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3524 DXEPCTL_CNAK | DXEPCTL_EPENA |
3528 /* enable, but don't activate EP0in */
3529 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3530 DXEPCTL_USBACTEP, DIEPCTL0);
3532 /* clear global NAKs */
3533 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3535 val |= DCTL_SFTDISCON;
3536 dwc2_set_bit(hsotg, DCTL, val);
3538 /* configure the core to support LPM */
3539 dwc2_gadget_init_lpm(hsotg);
3541 /* program GREFCLK register if needed */
3542 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3543 dwc2_gadget_program_ref_clk(hsotg);
3545 /* must be at-least 3ms to allow bus to see disconnect */
3548 hsotg->lx_state = DWC2_L0;
3550 dwc2_hsotg_enqueue_setup(hsotg);
3552 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3553 dwc2_readl(hsotg, DIEPCTL0),
3554 dwc2_readl(hsotg, DOEPCTL0));
3557 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3559 /* set the soft-disconnect bit */
3560 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3563 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3565 /* remove the soft-disconnect and let's go */
3566 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3570 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3571 * @hsotg: The device state:
3573 * This interrupt indicates one of the following conditions occurred while
3574 * transmitting an ISOC transaction.
3575 * - Corrupted IN Token for ISOC EP.
3576 * - Packet not complete in FIFO.
3578 * The following actions will be taken:
3579 * - Determine the EP
3580 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3582 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3584 struct dwc2_hsotg_ep *hs_ep;
3589 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3591 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3593 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3594 hs_ep = hsotg->eps_in[idx];
3595 /* Proceed only unmasked ISOC EPs */
3596 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3599 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3600 if ((epctrl & DXEPCTL_EPENA) &&
3601 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3602 epctrl |= DXEPCTL_SNAK;
3603 epctrl |= DXEPCTL_EPDIS;
3604 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3608 /* Clear interrupt */
3609 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3613 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3614 * @hsotg: The device state:
3616 * This interrupt indicates one of the following conditions occurred while
3617 * transmitting an ISOC transaction.
3618 * - Corrupted OUT Token for ISOC EP.
3619 * - Packet not complete in FIFO.
3621 * The following actions will be taken:
3622 * - Determine the EP
3623 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3625 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3631 struct dwc2_hsotg_ep *hs_ep;
3634 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3636 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3637 daintmsk >>= DAINT_OUTEP_SHIFT;
3639 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3640 hs_ep = hsotg->eps_out[idx];
3641 /* Proceed only unmasked ISOC EPs */
3642 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3645 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3646 if ((epctrl & DXEPCTL_EPENA) &&
3647 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3648 /* Unmask GOUTNAKEFF interrupt */
3649 gintmsk = dwc2_readl(hsotg, GINTMSK);
3650 gintmsk |= GINTSTS_GOUTNAKEFF;
3651 dwc2_writel(hsotg, gintmsk, GINTMSK);
3653 gintsts = dwc2_readl(hsotg, GINTSTS);
3654 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3655 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3661 /* Clear interrupt */
3662 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3666 * dwc2_hsotg_irq - handle device interrupt
3667 * @irq: The IRQ number triggered
3668 * @pw: The pw value when registered the handler.
3670 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3672 struct dwc2_hsotg *hsotg = pw;
3673 int retry_count = 8;
3677 if (!dwc2_is_device_mode(hsotg))
3680 spin_lock(&hsotg->lock);
3682 gintsts = dwc2_readl(hsotg, GINTSTS);
3683 gintmsk = dwc2_readl(hsotg, GINTMSK);
3685 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3686 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3690 if (gintsts & GINTSTS_RESETDET) {
3691 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3693 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3695 /* This event must be used only if controller is suspended */
3696 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3697 dwc2_exit_partial_power_down(hsotg, 0, true);
3699 hsotg->lx_state = DWC2_L0;
3702 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3703 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3704 u32 connected = hsotg->connected;
3706 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3707 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3708 dwc2_readl(hsotg, GNPTXSTS));
3710 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3712 /* Report disconnection if it is not already done. */
3713 dwc2_hsotg_disconnect(hsotg);
3715 /* Reset device address to zero */
3716 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3718 if (usb_status & GOTGCTL_BSESVLD && connected)
3719 dwc2_hsotg_core_init_disconnected(hsotg, true);
3722 if (gintsts & GINTSTS_ENUMDONE) {
3723 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3725 dwc2_hsotg_irq_enumdone(hsotg);
3728 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3729 u32 daint = dwc2_readl(hsotg, DAINT);
3730 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3731 u32 daint_out, daint_in;
3735 daint_out = daint >> DAINT_OUTEP_SHIFT;
3736 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3738 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3740 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3741 ep++, daint_out >>= 1) {
3743 dwc2_hsotg_epint(hsotg, ep, 0);
3746 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3747 ep++, daint_in >>= 1) {
3749 dwc2_hsotg_epint(hsotg, ep, 1);
3753 /* check both FIFOs */
3755 if (gintsts & GINTSTS_NPTXFEMP) {
3756 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3759 * Disable the interrupt to stop it happening again
3760 * unless one of these endpoint routines decides that
3761 * it needs re-enabling
3764 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3765 dwc2_hsotg_irq_fifoempty(hsotg, false);
3768 if (gintsts & GINTSTS_PTXFEMP) {
3769 dev_dbg(hsotg->dev, "PTxFEmp\n");
3771 /* See note in GINTSTS_NPTxFEmp */
3773 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3774 dwc2_hsotg_irq_fifoempty(hsotg, true);
3777 if (gintsts & GINTSTS_RXFLVL) {
3779 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3780 * we need to retry dwc2_hsotg_handle_rx if this is still
3784 dwc2_hsotg_handle_rx(hsotg);
3787 if (gintsts & GINTSTS_ERLYSUSP) {
3788 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3789 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3793 * these next two seem to crop-up occasionally causing the core
3794 * to shutdown the USB transfer, so try clearing them and logging
3798 if (gintsts & GINTSTS_GOUTNAKEFF) {
3803 struct dwc2_hsotg_ep *hs_ep;
3805 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3806 daintmsk >>= DAINT_OUTEP_SHIFT;
3807 /* Mask this interrupt */
3808 gintmsk = dwc2_readl(hsotg, GINTMSK);
3809 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3810 dwc2_writel(hsotg, gintmsk, GINTMSK);
3812 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3813 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3814 hs_ep = hsotg->eps_out[idx];
3815 /* Proceed only unmasked ISOC EPs */
3816 if (BIT(idx) & ~daintmsk)
3819 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3822 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3823 epctrl |= DXEPCTL_SNAK;
3824 epctrl |= DXEPCTL_EPDIS;
3825 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3830 if (hs_ep->halted) {
3831 if (!(epctrl & DXEPCTL_EPENA))
3832 epctrl |= DXEPCTL_EPENA;
3833 epctrl |= DXEPCTL_EPDIS;
3834 epctrl |= DXEPCTL_STALL;
3835 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3839 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3842 if (gintsts & GINTSTS_GINNAKEFF) {
3843 dev_info(hsotg->dev, "GINNakEff triggered\n");
3845 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3847 dwc2_hsotg_dump(hsotg);
3850 if (gintsts & GINTSTS_INCOMPL_SOIN)
3851 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3853 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3854 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3857 * if we've had fifo events, we should try and go around the
3858 * loop again to see if there's any point in returning yet.
3861 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3864 /* Check WKUP_ALERT interrupt*/
3865 if (hsotg->params.service_interval)
3866 dwc2_gadget_wkup_alert_handler(hsotg);
3868 spin_unlock(&hsotg->lock);
3873 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3874 struct dwc2_hsotg_ep *hs_ep)
3879 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3880 DOEPCTL(hs_ep->index);
3881 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3882 DOEPINT(hs_ep->index);
3884 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3887 if (hs_ep->dir_in) {
3888 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3889 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3890 /* Wait for Nak effect */
3891 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3892 DXEPINT_INEPNAKEFF, 100))
3893 dev_warn(hsotg->dev,
3894 "%s: timeout DIEPINT.NAKEFF\n",
3897 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3898 /* Wait for Nak effect */
3899 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3900 GINTSTS_GINNAKEFF, 100))
3901 dev_warn(hsotg->dev,
3902 "%s: timeout GINTSTS.GINNAKEFF\n",
3906 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3907 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3909 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3910 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3912 if (!using_dma(hsotg)) {
3913 /* Wait for GINTSTS_RXFLVL interrupt */
3914 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3915 GINTSTS_RXFLVL, 100)) {
3916 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3920 * Pop GLOBAL OUT NAK status packet from RxFIFO
3921 * to assert GOUTNAKEFF interrupt
3923 dwc2_readl(hsotg, GRXSTSP);
3927 /* Wait for global nak to take effect */
3928 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3929 GINTSTS_GOUTNAKEFF, 100))
3930 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3935 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3937 /* Wait for ep to be disabled */
3938 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3939 dev_warn(hsotg->dev,
3940 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3942 /* Clear EPDISBLD interrupt */
3943 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3945 if (hs_ep->dir_in) {
3946 unsigned short fifo_index;
3948 if (hsotg->dedicated_fifos || hs_ep->periodic)
3949 fifo_index = hs_ep->fifo_index;
3954 dwc2_flush_tx_fifo(hsotg, fifo_index);
3956 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3957 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3958 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3961 /* Remove global NAKs */
3962 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3967 * dwc2_hsotg_ep_enable - enable the given endpoint
3968 * @ep: The USB endpint to configure
3969 * @desc: The USB endpoint descriptor to configure with.
3971 * This is called from the USB gadget code's usb_ep_enable().
3973 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3974 const struct usb_endpoint_descriptor *desc)
3976 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3977 struct dwc2_hsotg *hsotg = hs_ep->parent;
3978 unsigned long flags;
3979 unsigned int index = hs_ep->index;
3985 unsigned int dir_in;
3986 unsigned int i, val, size;
3988 unsigned char ep_type;
3992 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3993 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3994 desc->wMaxPacketSize, desc->bInterval);
3996 /* not to be called for EP0 */
3998 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4002 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4003 if (dir_in != hs_ep->dir_in) {
4004 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4008 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4009 mps = usb_endpoint_maxp(desc);
4010 mc = usb_endpoint_maxp_mult(desc);
4012 /* ISOC IN in DDMA supported bInterval up to 10 */
4013 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4014 dir_in && desc->bInterval > 10) {
4016 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4020 /* High bandwidth ISOC OUT in DDMA not supported */
4021 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4022 !dir_in && mc > 1) {
4024 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4028 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4030 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4031 epctrl = dwc2_readl(hsotg, epctrl_reg);
4033 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4034 __func__, epctrl, epctrl_reg);
4036 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4037 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4039 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4041 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4042 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4043 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4044 desc_num * sizeof(struct dwc2_dma_desc),
4045 &hs_ep->desc_list_dma, GFP_ATOMIC);
4046 if (!hs_ep->desc_list) {
4052 spin_lock_irqsave(&hsotg->lock, flags);
4054 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4055 epctrl |= DXEPCTL_MPS(mps);
4058 * mark the endpoint as active, otherwise the core may ignore
4059 * transactions entirely for this endpoint
4061 epctrl |= DXEPCTL_USBACTEP;
4063 /* update the endpoint state */
4064 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4066 /* default, set to non-periodic */
4067 hs_ep->isochronous = 0;
4068 hs_ep->periodic = 0;
4071 hs_ep->interval = desc->bInterval;
4074 case USB_ENDPOINT_XFER_ISOC:
4075 epctrl |= DXEPCTL_EPTYPE_ISO;
4076 epctrl |= DXEPCTL_SETEVENFR;
4077 hs_ep->isochronous = 1;
4078 hs_ep->interval = 1 << (desc->bInterval - 1);
4079 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4080 hs_ep->next_desc = 0;
4081 hs_ep->compl_desc = 0;
4083 hs_ep->periodic = 1;
4084 mask = dwc2_readl(hsotg, DIEPMSK);
4085 mask |= DIEPMSK_NAKMSK;
4086 dwc2_writel(hsotg, mask, DIEPMSK);
4088 mask = dwc2_readl(hsotg, DOEPMSK);
4089 mask |= DOEPMSK_OUTTKNEPDISMSK;
4090 dwc2_writel(hsotg, mask, DOEPMSK);
4094 case USB_ENDPOINT_XFER_BULK:
4095 epctrl |= DXEPCTL_EPTYPE_BULK;
4098 case USB_ENDPOINT_XFER_INT:
4100 hs_ep->periodic = 1;
4102 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4103 hs_ep->interval = 1 << (desc->bInterval - 1);
4105 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4108 case USB_ENDPOINT_XFER_CONTROL:
4109 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4114 * if the hardware has dedicated fifos, we must give each IN EP
4115 * a unique tx-fifo even if it is non-periodic.
4117 if (dir_in && hsotg->dedicated_fifos) {
4118 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4120 u32 fifo_size = UINT_MAX;
4122 size = hs_ep->ep.maxpacket * hs_ep->mc;
4123 for (i = 1; i <= fifo_count; ++i) {
4124 if (hsotg->fifo_map & (1 << i))
4126 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4127 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4130 /* Search for smallest acceptable fifo */
4131 if (val < fifo_size) {
4138 "%s: No suitable fifo found\n", __func__);
4142 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4143 hsotg->fifo_map |= 1 << fifo_index;
4144 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4145 hs_ep->fifo_index = fifo_index;
4146 hs_ep->fifo_size = fifo_size;
4149 /* for non control endpoints, set PID to D0 */
4150 if (index && !hs_ep->isochronous)
4151 epctrl |= DXEPCTL_SETD0PID;
4153 /* WA for Full speed ISOC IN in DDMA mode.
4154 * By Clear NAK status of EP, core will send ZLP
4155 * to IN token and assert NAK interrupt relying
4156 * on TxFIFO status only
4159 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4160 hs_ep->isochronous && dir_in) {
4161 /* The WA applies only to core versions from 2.72a
4162 * to 4.00a (including both). Also for FS_IOT_1.00a
4165 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4167 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4168 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4169 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4170 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4171 epctrl |= DXEPCTL_CNAK;
4174 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4177 dwc2_writel(hsotg, epctrl, epctrl_reg);
4178 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4179 __func__, dwc2_readl(hsotg, epctrl_reg));
4181 /* enable the endpoint interrupt */
4182 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4185 spin_unlock_irqrestore(&hsotg->lock, flags);
4188 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4189 dmam_free_coherent(hsotg->dev, desc_num *
4190 sizeof(struct dwc2_dma_desc),
4191 hs_ep->desc_list, hs_ep->desc_list_dma);
4192 hs_ep->desc_list = NULL;
4199 * dwc2_hsotg_ep_disable - disable given endpoint
4200 * @ep: The endpoint to disable.
4202 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4204 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4205 struct dwc2_hsotg *hsotg = hs_ep->parent;
4206 int dir_in = hs_ep->dir_in;
4207 int index = hs_ep->index;
4211 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4213 if (ep == &hsotg->eps_out[0]->ep) {
4214 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4218 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4219 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4223 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4225 ctrl = dwc2_readl(hsotg, epctrl_reg);
4227 if (ctrl & DXEPCTL_EPENA)
4228 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4230 ctrl &= ~DXEPCTL_EPENA;
4231 ctrl &= ~DXEPCTL_USBACTEP;
4232 ctrl |= DXEPCTL_SNAK;
4234 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4235 dwc2_writel(hsotg, ctrl, epctrl_reg);
4237 /* disable endpoint interrupts */
4238 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4240 /* terminate all requests with shutdown */
4241 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4243 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4244 hs_ep->fifo_index = 0;
4245 hs_ep->fifo_size = 0;
4250 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4252 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4253 struct dwc2_hsotg *hsotg = hs_ep->parent;
4254 unsigned long flags;
4257 spin_lock_irqsave(&hsotg->lock, flags);
4258 ret = dwc2_hsotg_ep_disable(ep);
4259 spin_unlock_irqrestore(&hsotg->lock, flags);
4264 * on_list - check request is on the given endpoint
4265 * @ep: The endpoint to check.
4266 * @test: The request to test if it is on the endpoint.
4268 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4270 struct dwc2_hsotg_req *req, *treq;
4272 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4281 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4282 * @ep: The endpoint to dequeue.
4283 * @req: The request to be removed from a queue.
4285 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4287 struct dwc2_hsotg_req *hs_req = our_req(req);
4288 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4289 struct dwc2_hsotg *hs = hs_ep->parent;
4290 unsigned long flags;
4292 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4294 spin_lock_irqsave(&hs->lock, flags);
4296 if (!on_list(hs_ep, hs_req)) {
4297 spin_unlock_irqrestore(&hs->lock, flags);
4301 /* Dequeue already started request */
4302 if (req == &hs_ep->req->req)
4303 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4305 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4306 spin_unlock_irqrestore(&hs->lock, flags);
4312 * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
4313 * @ep: The endpoint to be wedged.
4316 static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
4318 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4319 struct dwc2_hsotg *hs = hs_ep->parent;
4321 unsigned long flags;
4324 spin_lock_irqsave(&hs->lock, flags);
4326 ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
4327 spin_unlock_irqrestore(&hs->lock, flags);
4333 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4334 * @ep: The endpoint to set halt.
4335 * @value: Set or unset the halt.
4336 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4337 * the endpoint is busy processing requests.
4339 * We need to stall the endpoint immediately if request comes from set_feature
4340 * protocol command handler.
4342 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4344 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4345 struct dwc2_hsotg *hs = hs_ep->parent;
4346 int index = hs_ep->index;
4351 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4355 dwc2_hsotg_stall_ep0(hs);
4358 "%s: can't clear halt on ep0\n", __func__);
4362 if (hs_ep->isochronous) {
4363 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4367 if (!now && value && !list_empty(&hs_ep->queue)) {
4368 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4373 if (hs_ep->dir_in) {
4374 epreg = DIEPCTL(index);
4375 epctl = dwc2_readl(hs, epreg);
4378 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4379 if (epctl & DXEPCTL_EPENA)
4380 epctl |= DXEPCTL_EPDIS;
4382 epctl &= ~DXEPCTL_STALL;
4384 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4385 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4386 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4387 epctl |= DXEPCTL_SETD0PID;
4389 dwc2_writel(hs, epctl, epreg);
4391 epreg = DOEPCTL(index);
4392 epctl = dwc2_readl(hs, epreg);
4395 /* Unmask GOUTNAKEFF interrupt */
4396 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4398 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4399 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4400 // STALL bit will be set in GOUTNAKEFF interrupt handler
4402 epctl &= ~DXEPCTL_STALL;
4404 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4405 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4406 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4407 epctl |= DXEPCTL_SETD0PID;
4408 dwc2_writel(hs, epctl, epreg);
4412 hs_ep->halted = value;
4417 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4418 * @ep: The endpoint to set halt.
4419 * @value: Set or unset the halt.
4421 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4423 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4424 struct dwc2_hsotg *hs = hs_ep->parent;
4425 unsigned long flags;
4428 spin_lock_irqsave(&hs->lock, flags);
4429 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4430 spin_unlock_irqrestore(&hs->lock, flags);
4435 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4436 .enable = dwc2_hsotg_ep_enable,
4437 .disable = dwc2_hsotg_ep_disable_lock,
4438 .alloc_request = dwc2_hsotg_ep_alloc_request,
4439 .free_request = dwc2_hsotg_ep_free_request,
4440 .queue = dwc2_hsotg_ep_queue_lock,
4441 .dequeue = dwc2_hsotg_ep_dequeue,
4442 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4443 .set_wedge = dwc2_gadget_ep_set_wedge,
4444 /* note, don't believe we have any call for the fifo routines */
4448 * dwc2_hsotg_init - initialize the usb core
4449 * @hsotg: The driver state
4451 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4453 /* unmask subset of endpoint interrupts */
4455 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4456 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4459 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4460 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4463 dwc2_writel(hsotg, 0, DAINTMSK);
4465 /* Be in disconnected state until gadget is registered */
4466 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4470 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4471 dwc2_readl(hsotg, GRXFSIZ),
4472 dwc2_readl(hsotg, GNPTXFSIZ));
4474 dwc2_hsotg_init_fifo(hsotg);
4476 if (using_dma(hsotg))
4477 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4481 * dwc2_hsotg_udc_start - prepare the udc for work
4482 * @gadget: The usb gadget state
4483 * @driver: The usb gadget driver
4485 * Perform initialization to prepare udc device and driver
4488 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4489 struct usb_gadget_driver *driver)
4491 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4492 unsigned long flags;
4496 pr_err("%s: called with no device\n", __func__);
4501 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4505 if (driver->max_speed < USB_SPEED_FULL)
4506 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4508 if (!driver->setup) {
4509 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4513 WARN_ON(hsotg->driver);
4515 driver->driver.bus = NULL;
4516 hsotg->driver = driver;
4517 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4518 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4520 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4521 ret = dwc2_lowlevel_hw_enable(hsotg);
4526 if (!IS_ERR_OR_NULL(hsotg->uphy))
4527 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4529 spin_lock_irqsave(&hsotg->lock, flags);
4530 if (dwc2_hw_is_device(hsotg)) {
4531 dwc2_hsotg_init(hsotg);
4532 dwc2_hsotg_core_init_disconnected(hsotg, false);
4536 spin_unlock_irqrestore(&hsotg->lock, flags);
4538 gadget->sg_supported = using_desc_dma(hsotg);
4539 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4544 hsotg->driver = NULL;
4549 * dwc2_hsotg_udc_stop - stop the udc
4550 * @gadget: The usb gadget state
4552 * Stop udc hw block and stay tunned for future transmissions
4554 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4556 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4557 unsigned long flags;
4563 /* all endpoints should be shutdown */
4564 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4565 if (hsotg->eps_in[ep])
4566 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4567 if (hsotg->eps_out[ep])
4568 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4571 spin_lock_irqsave(&hsotg->lock, flags);
4573 hsotg->driver = NULL;
4574 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4577 spin_unlock_irqrestore(&hsotg->lock, flags);
4579 if (!IS_ERR_OR_NULL(hsotg->uphy))
4580 otg_set_peripheral(hsotg->uphy->otg, NULL);
4582 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4583 dwc2_lowlevel_hw_disable(hsotg);
4589 * dwc2_hsotg_gadget_getframe - read the frame number
4590 * @gadget: The usb gadget state
4592 * Read the {micro} frame number
4594 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4596 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4600 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4601 * @gadget: The usb gadget state
4602 * @is_selfpowered: Whether the device is self-powered
4604 * Set if the device is self or bus powered.
4606 static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4609 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4610 unsigned long flags;
4612 spin_lock_irqsave(&hsotg->lock, flags);
4613 gadget->is_selfpowered = !!is_selfpowered;
4614 spin_unlock_irqrestore(&hsotg->lock, flags);
4620 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4621 * @gadget: The usb gadget state
4622 * @is_on: Current state of the USB PHY
4624 * Connect/Disconnect the USB PHY pullup
4626 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4628 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4629 unsigned long flags;
4631 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4634 /* Don't modify pullup state while in host mode */
4635 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4636 hsotg->enabled = is_on;
4640 spin_lock_irqsave(&hsotg->lock, flags);
4643 dwc2_hsotg_core_init_disconnected(hsotg, false);
4644 /* Enable ACG feature in device mode,if supported */
4645 dwc2_enable_acg(hsotg);
4646 dwc2_hsotg_core_connect(hsotg);
4648 dwc2_hsotg_core_disconnect(hsotg);
4649 dwc2_hsotg_disconnect(hsotg);
4653 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4654 spin_unlock_irqrestore(&hsotg->lock, flags);
4659 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4661 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4662 unsigned long flags;
4664 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4665 spin_lock_irqsave(&hsotg->lock, flags);
4668 * If controller is in partial power down state, it must exit from
4669 * that state before being initialized / de-initialized
4671 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4673 * No need to check the return value as
4674 * registers are not being restored.
4676 dwc2_exit_partial_power_down(hsotg, 0, false);
4679 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4681 dwc2_hsotg_core_init_disconnected(hsotg, false);
4682 if (hsotg->enabled) {
4683 /* Enable ACG feature in device mode,if supported */
4684 dwc2_enable_acg(hsotg);
4685 dwc2_hsotg_core_connect(hsotg);
4688 dwc2_hsotg_core_disconnect(hsotg);
4689 dwc2_hsotg_disconnect(hsotg);
4692 spin_unlock_irqrestore(&hsotg->lock, flags);
4697 * dwc2_hsotg_vbus_draw - report bMaxPower field
4698 * @gadget: The usb gadget state
4699 * @mA: Amount of current
4701 * Report how much power the device may consume to the phy.
4703 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4705 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4707 if (IS_ERR_OR_NULL(hsotg->uphy))
4709 return usb_phy_set_power(hsotg->uphy, mA);
4712 static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
4714 struct dwc2_hsotg *hsotg = to_hsotg(g);
4715 unsigned long flags;
4717 spin_lock_irqsave(&hsotg->lock, flags);
4719 case USB_SPEED_HIGH:
4720 hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
4722 case USB_SPEED_FULL:
4723 hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
4726 hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
4729 dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
4731 spin_unlock_irqrestore(&hsotg->lock, flags);
4734 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4735 .get_frame = dwc2_hsotg_gadget_getframe,
4736 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4737 .udc_start = dwc2_hsotg_udc_start,
4738 .udc_stop = dwc2_hsotg_udc_stop,
4739 .pullup = dwc2_hsotg_pullup,
4740 .udc_set_speed = dwc2_gadget_set_speed,
4741 .vbus_session = dwc2_hsotg_vbus_session,
4742 .vbus_draw = dwc2_hsotg_vbus_draw,
4746 * dwc2_hsotg_initep - initialise a single endpoint
4747 * @hsotg: The device state.
4748 * @hs_ep: The endpoint to be initialised.
4749 * @epnum: The endpoint number
4750 * @dir_in: True if direction is in.
4752 * Initialise the given endpoint (as part of the probe and device state
4753 * creation) to give to the gadget driver. Setup the endpoint name, any
4754 * direction information and other state that may be required.
4756 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4757 struct dwc2_hsotg_ep *hs_ep,
4770 hs_ep->dir_in = dir_in;
4771 hs_ep->index = epnum;
4773 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4775 INIT_LIST_HEAD(&hs_ep->queue);
4776 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4778 /* add to the list of endpoints known by the gadget driver */
4780 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4782 hs_ep->parent = hsotg;
4783 hs_ep->ep.name = hs_ep->name;
4785 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4786 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4788 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4789 epnum ? 1024 : EP0_MPS_LIMIT);
4790 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4793 hs_ep->ep.caps.type_control = true;
4795 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4796 hs_ep->ep.caps.type_iso = true;
4797 hs_ep->ep.caps.type_bulk = true;
4799 hs_ep->ep.caps.type_int = true;
4803 hs_ep->ep.caps.dir_in = true;
4805 hs_ep->ep.caps.dir_out = true;
4808 * if we're using dma, we need to set the next-endpoint pointer
4809 * to be something valid.
4812 if (using_dma(hsotg)) {
4813 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4816 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4818 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4823 * dwc2_hsotg_hw_cfg - read HW configuration registers
4824 * @hsotg: Programming view of the DWC_otg controller
4826 * Read the USB core HW configuration registers
4828 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4834 /* check hardware configuration */
4836 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4839 hsotg->num_of_eps++;
4841 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4842 sizeof(struct dwc2_hsotg_ep),
4844 if (!hsotg->eps_in[0])
4846 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4847 hsotg->eps_out[0] = hsotg->eps_in[0];
4849 cfg = hsotg->hw_params.dev_ep_dirs;
4850 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4852 /* Direction in or both */
4853 if (!(ep_type & 2)) {
4854 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4855 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4856 if (!hsotg->eps_in[i])
4859 /* Direction out or both */
4860 if (!(ep_type & 1)) {
4861 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4862 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4863 if (!hsotg->eps_out[i])
4868 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4869 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4871 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4873 hsotg->dedicated_fifos ? "dedicated" : "shared",
4879 * dwc2_hsotg_dump - dump state of the udc
4880 * @hsotg: Programming view of the DWC_otg controller
4883 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4886 struct device *dev = hsotg->dev;
4890 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4891 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4892 dwc2_readl(hsotg, DIEPMSK));
4894 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4895 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4897 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4898 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4900 /* show periodic fifo settings */
4902 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4903 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4904 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4905 val >> FIFOSIZE_DEPTH_SHIFT,
4906 val & FIFOSIZE_STARTADDR_MASK);
4909 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4911 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4912 dwc2_readl(hsotg, DIEPCTL(idx)),
4913 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4914 dwc2_readl(hsotg, DIEPDMA(idx)));
4916 val = dwc2_readl(hsotg, DOEPCTL(idx));
4918 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4919 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4920 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4921 dwc2_readl(hsotg, DOEPDMA(idx)));
4924 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4925 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4930 * dwc2_gadget_init - init function for gadget
4931 * @hsotg: Programming view of the DWC_otg controller
4934 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4936 struct device *dev = hsotg->dev;
4940 /* Dump fifo information */
4941 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4942 hsotg->params.g_np_tx_fifo_size);
4943 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4945 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4946 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4947 hsotg->gadget.name = dev_name(dev);
4948 hsotg->remote_wakeup_allowed = 0;
4950 if (hsotg->params.lpm)
4951 hsotg->gadget.lpm_capable = true;
4953 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4954 hsotg->gadget.is_otg = 1;
4955 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4956 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4958 ret = dwc2_hsotg_hw_cfg(hsotg);
4960 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4964 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4965 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4966 if (!hsotg->ctrl_buff)
4969 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4970 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4971 if (!hsotg->ep0_buff)
4974 if (using_desc_dma(hsotg)) {
4975 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4980 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4981 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4983 dev_err(dev, "cannot claim IRQ for gadget\n");
4987 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4989 if (hsotg->num_of_eps == 0) {
4990 dev_err(dev, "wrong number of EPs (zero)\n");
4994 /* setup endpoint information */
4996 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4997 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4999 /* allocate EP0 request */
5001 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
5003 if (!hsotg->ctrl_req) {
5004 dev_err(dev, "failed to allocate ctrl req\n");
5008 /* initialise the endpoints now the core has been initialised */
5009 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
5010 if (hsotg->eps_in[epnum])
5011 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
5013 if (hsotg->eps_out[epnum])
5014 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5018 dwc2_hsotg_dump(hsotg);
5024 * dwc2_hsotg_remove - remove function for hsotg driver
5025 * @hsotg: Programming view of the DWC_otg controller
5028 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5030 usb_del_gadget_udc(&hsotg->gadget);
5031 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5036 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5038 unsigned long flags;
5040 if (hsotg->lx_state != DWC2_L0)
5043 if (hsotg->driver) {
5046 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5047 hsotg->driver->driver.name);
5049 spin_lock_irqsave(&hsotg->lock, flags);
5051 dwc2_hsotg_core_disconnect(hsotg);
5052 dwc2_hsotg_disconnect(hsotg);
5053 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5054 spin_unlock_irqrestore(&hsotg->lock, flags);
5056 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
5057 if (hsotg->eps_in[ep])
5058 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5059 if (hsotg->eps_out[ep])
5060 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5067 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5069 unsigned long flags;
5071 if (hsotg->lx_state == DWC2_L2)
5074 if (hsotg->driver) {
5075 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5076 hsotg->driver->driver.name);
5078 spin_lock_irqsave(&hsotg->lock, flags);
5079 dwc2_hsotg_core_init_disconnected(hsotg, false);
5080 if (hsotg->enabled) {
5081 /* Enable ACG feature in device mode,if supported */
5082 dwc2_enable_acg(hsotg);
5083 dwc2_hsotg_core_connect(hsotg);
5085 spin_unlock_irqrestore(&hsotg->lock, flags);
5092 * dwc2_backup_device_registers() - Backup controller device registers.
5093 * When suspending usb bus, registers needs to be backuped
5094 * if controller power is disabled once suspended.
5096 * @hsotg: Programming view of the DWC_otg controller
5098 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5100 struct dwc2_dregs_backup *dr;
5103 dev_dbg(hsotg->dev, "%s\n", __func__);
5105 /* Backup dev regs */
5106 dr = &hsotg->dr_backup;
5108 dr->dcfg = dwc2_readl(hsotg, DCFG);
5109 dr->dctl = dwc2_readl(hsotg, DCTL);
5110 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5111 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5112 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5114 for (i = 0; i < hsotg->num_of_eps; i++) {
5116 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5118 /* Ensure DATA PID is correctly configured */
5119 if (dr->diepctl[i] & DXEPCTL_DPID)
5120 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5122 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5124 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5125 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5127 /* Backup OUT EPs */
5128 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5130 /* Ensure DATA PID is correctly configured */
5131 if (dr->doepctl[i] & DXEPCTL_DPID)
5132 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5134 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5136 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5137 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5138 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5145 * dwc2_restore_device_registers() - Restore controller device registers.
5146 * When resuming usb bus, device registers needs to be restored
5147 * if controller power were disabled.
5149 * @hsotg: Programming view of the DWC_otg controller
5150 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5152 * Return: 0 if successful, negative error code otherwise
5154 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5156 struct dwc2_dregs_backup *dr;
5159 dev_dbg(hsotg->dev, "%s\n", __func__);
5161 /* Restore dev regs */
5162 dr = &hsotg->dr_backup;
5164 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5171 dwc2_writel(hsotg, dr->dctl, DCTL);
5173 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5174 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5175 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5177 for (i = 0; i < hsotg->num_of_eps; i++) {
5178 /* Restore IN EPs */
5179 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5180 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5181 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5182 /** WA for enabled EPx's IN in DDMA mode. On entering to
5183 * hibernation wrong value read and saved from DIEPDMAx,
5184 * as result BNA interrupt asserted on hibernation exit
5185 * by restoring from saved area.
5187 if (hsotg->params.g_dma_desc &&
5188 (dr->diepctl[i] & DXEPCTL_EPENA))
5189 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5190 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5191 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5192 /* Restore OUT EPs */
5193 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5194 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5195 * hibernation wrong value read and saved from DOEPDMAx,
5196 * as result BNA interrupt asserted on hibernation exit
5197 * by restoring from saved area.
5199 if (hsotg->params.g_dma_desc &&
5200 (dr->doepctl[i] & DXEPCTL_EPENA))
5201 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5202 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5203 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5210 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5212 * @hsotg: Programming view of DWC_otg controller
5215 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5219 if (!hsotg->params.lpm)
5222 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5223 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5224 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5225 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5226 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5227 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5228 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5229 dwc2_writel(hsotg, val, GLPMCFG);
5230 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5232 /* Unmask WKUP_ALERT Interrupt */
5233 if (hsotg->params.service_interval)
5234 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5238 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5240 * @hsotg: Programming view of DWC_otg controller
5243 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5247 val |= GREFCLK_REF_CLK_MODE;
5248 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5249 val |= hsotg->params.sof_cnt_wkup_alert <<
5250 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5252 dwc2_writel(hsotg, val, GREFCLK);
5253 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5257 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5259 * @hsotg: Programming view of the DWC_otg controller
5261 * Return non-zero if failed to enter to hibernation.
5263 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5268 /* Change to L2(suspend) state */
5269 hsotg->lx_state = DWC2_L2;
5270 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5271 ret = dwc2_backup_global_registers(hsotg);
5273 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5277 ret = dwc2_backup_device_registers(hsotg);
5279 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5284 gpwrdn = GPWRDN_PWRDNRSTN;
5285 gpwrdn |= GPWRDN_PMUACTV;
5286 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5289 /* Set flag to indicate that we are in hibernation */
5290 hsotg->hibernated = 1;
5292 /* Enable interrupts from wake up logic */
5293 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5294 gpwrdn |= GPWRDN_PMUINTSEL;
5295 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5298 /* Unmask device mode interrupts in GPWRDN */
5299 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5300 gpwrdn |= GPWRDN_RST_DET_MSK;
5301 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5302 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5303 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5306 /* Enable Power Down Clamp */
5307 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5308 gpwrdn |= GPWRDN_PWRDNCLMP;
5309 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5312 /* Switch off VDD */
5313 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5314 gpwrdn |= GPWRDN_PWRDNSWTCH;
5315 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5318 /* Save gpwrdn register for further usage if stschng interrupt */
5319 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5320 dev_dbg(hsotg->dev, "Hibernation completed\n");
5326 * dwc2_gadget_exit_hibernation()
5327 * This function is for exiting from Device mode hibernation by host initiated
5328 * resume/reset and device initiated remote-wakeup.
5330 * @hsotg: Programming view of the DWC_otg controller
5331 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5332 * @reset: indicates whether resume is initiated by Reset.
5334 * Return non-zero if failed to exit from hibernation.
5336 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5337 int rem_wakeup, int reset)
5343 struct dwc2_gregs_backup *gr;
5344 struct dwc2_dregs_backup *dr;
5346 gr = &hsotg->gr_backup;
5347 dr = &hsotg->dr_backup;
5349 if (!hsotg->hibernated) {
5350 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5354 "%s: called with rem_wakeup = %d reset = %d\n",
5355 __func__, rem_wakeup, reset);
5357 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5360 /* Clear all pending interupts */
5361 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5364 /* De-assert Restore */
5365 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5366 gpwrdn &= ~GPWRDN_RESTORE;
5367 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5371 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5372 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5373 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5376 /* Restore GUSBCFG, DCFG and DCTL */
5377 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5378 dwc2_writel(hsotg, dr->dcfg, DCFG);
5379 dwc2_writel(hsotg, dr->dctl, DCTL);
5381 /* On USB Reset, reset device address to zero */
5383 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5385 /* De-assert Wakeup Logic */
5386 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5387 gpwrdn &= ~GPWRDN_PMUACTV;
5388 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5392 /* Start Remote Wakeup Signaling */
5393 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5396 /* Set Device programming done bit */
5397 dctl = dwc2_readl(hsotg, DCTL);
5398 dctl |= DCTL_PWRONPRGDONE;
5399 dwc2_writel(hsotg, dctl, DCTL);
5401 /* Wait for interrupts which must be cleared */
5403 /* Clear all pending interupts */
5404 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5406 /* Restore global registers */
5407 ret = dwc2_restore_global_registers(hsotg);
5409 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5414 /* Restore device registers */
5415 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5417 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5424 dctl = dwc2_readl(hsotg, DCTL);
5425 dctl &= ~DCTL_RMTWKUPSIG;
5426 dwc2_writel(hsotg, dctl, DCTL);
5429 hsotg->hibernated = 0;
5430 hsotg->lx_state = DWC2_L0;
5431 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5437 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5440 * @hsotg: Programming view of the DWC_otg controller
5442 * Return: non-zero if failed to enter device partial power down.
5444 * This function is for entering device mode partial power down.
5446 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5451 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5453 /* Backup all registers */
5454 ret = dwc2_backup_global_registers(hsotg);
5456 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5461 ret = dwc2_backup_device_registers(hsotg);
5463 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5469 * Clear any pending interrupts since dwc2 will not be able to
5470 * clear them after entering partial_power_down.
5472 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5474 /* Put the controller in low power state */
5475 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5477 pcgcctl |= PCGCTL_PWRCLMP;
5478 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5481 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5482 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5485 pcgcctl |= PCGCTL_STOPPCLK;
5486 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5488 /* Set in_ppd flag to 1 as here core enters suspend. */
5490 hsotg->lx_state = DWC2_L2;
5492 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5498 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5501 * @hsotg: Programming view of the DWC_otg controller
5502 * @restore: indicates whether need to restore the registers or not.
5504 * Return: non-zero if failed to exit device partial power down.
5506 * This function is for exiting from device mode partial power down.
5508 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5513 struct dwc2_dregs_backup *dr;
5516 dr = &hsotg->dr_backup;
5518 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5520 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5521 pcgcctl &= ~PCGCTL_STOPPCLK;
5522 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5524 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5525 pcgcctl &= ~PCGCTL_PWRCLMP;
5526 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5528 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5529 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5530 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5534 ret = dwc2_restore_global_registers(hsotg);
5536 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5541 dwc2_writel(hsotg, dr->dcfg, DCFG);
5543 ret = dwc2_restore_device_registers(hsotg, 0);
5545 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5551 /* Set the Power-On Programming done bit */
5552 dctl = dwc2_readl(hsotg, DCTL);
5553 dctl |= DCTL_PWRONPRGDONE;
5554 dwc2_writel(hsotg, dctl, DCTL);
5556 /* Set in_ppd flag to 0 as here core exits from suspend. */
5558 hsotg->lx_state = DWC2_L0;
5560 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5565 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5567 * @hsotg: Programming view of the DWC_otg controller
5569 * Return: non-zero if failed to enter device partial power down.
5571 * This function is for entering device mode clock gating.
5573 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5577 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5579 /* Set the Phy Clock bit as suspend is received. */
5580 pcgctl = dwc2_readl(hsotg, PCGCTL);
5581 pcgctl |= PCGCTL_STOPPCLK;
5582 dwc2_writel(hsotg, pcgctl, PCGCTL);
5585 /* Set the Gate hclk as suspend is received. */
5586 pcgctl = dwc2_readl(hsotg, PCGCTL);
5587 pcgctl |= PCGCTL_GATEHCLK;
5588 dwc2_writel(hsotg, pcgctl, PCGCTL);
5591 hsotg->lx_state = DWC2_L2;
5592 hsotg->bus_suspended = true;
5596 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5598 * @hsotg: Programming view of the DWC_otg controller
5599 * @rem_wakeup: indicates whether remote wake up is enabled.
5601 * This function is for exiting from device mode clock gating.
5603 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5608 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5610 /* Clear the Gate hclk. */
5611 pcgctl = dwc2_readl(hsotg, PCGCTL);
5612 pcgctl &= ~PCGCTL_GATEHCLK;
5613 dwc2_writel(hsotg, pcgctl, PCGCTL);
5616 /* Phy Clock bit. */
5617 pcgctl = dwc2_readl(hsotg, PCGCTL);
5618 pcgctl &= ~PCGCTL_STOPPCLK;
5619 dwc2_writel(hsotg, pcgctl, PCGCTL);
5623 /* Set Remote Wakeup Signaling */
5624 dctl = dwc2_readl(hsotg, DCTL);
5625 dctl |= DCTL_RMTWKUPSIG;
5626 dwc2_writel(hsotg, dctl, DCTL);
5629 /* Change to L0 state */
5630 call_gadget(hsotg, resume);
5631 hsotg->lx_state = DWC2_L0;
5632 hsotg->bus_suspended = false;