1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
30 #include <linux/usb/composite.h>
36 /* conversion functions */
37 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39 return container_of(req, struct dwc2_hsotg_req, req);
42 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
47 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49 return container_of(gadget, struct dwc2_hsotg, gadget);
52 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
57 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
62 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
66 return hsotg->eps_in[ep_index];
68 return hsotg->eps_out[ep_index];
71 /* forward declaration of functions */
72 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
78 * Return true if we're using DMA.
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
91 * g_using_dma is set depending on dts flag.
93 static inline bool using_dma(struct dwc2_hsotg *hsotg)
95 return hsotg->params.g_dma;
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
102 * Return true if we're using descriptor DMA.
104 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
106 return hsotg->params.g_dma_desc;
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
116 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
118 struct dwc2_hsotg *hsotg = hs_ep->parent;
119 u16 limit = DSTS_SOFFN_LIMIT;
121 if (hsotg->gadget.speed != USB_SPEED_HIGH)
124 hs_ep->target_frame += hs_ep->interval;
125 if (hs_ep->target_frame > limit) {
126 hs_ep->frame_overrun = true;
127 hs_ep->target_frame &= limit;
129 hs_ep->frame_overrun = false;
134 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
136 * @hs_ep: The endpoint.
138 * This function used in service interval based scheduling flow to calculate
139 * descriptor frame number filed value. For service interval mode frame
140 * number in descriptor should point to last (u)frame in the interval.
143 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
145 struct dwc2_hsotg *hsotg = hs_ep->parent;
146 u16 limit = DSTS_SOFFN_LIMIT;
148 if (hsotg->gadget.speed != USB_SPEED_HIGH)
151 if (hs_ep->target_frame)
152 hs_ep->target_frame -= 1;
154 hs_ep->target_frame = limit;
158 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
159 * @hsotg: The device state
160 * @ints: A bitmask of the interrupts to enable
162 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
164 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
167 new_gsintmsk = gsintmsk | ints;
169 if (new_gsintmsk != gsintmsk) {
170 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
171 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
176 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
177 * @hsotg: The device state
178 * @ints: A bitmask of the interrupts to enable
180 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
182 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
185 new_gsintmsk = gsintmsk & ~ints;
187 if (new_gsintmsk != gsintmsk)
188 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
192 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
193 * @hsotg: The device state
194 * @ep: The endpoint index
195 * @dir_in: True if direction is in.
196 * @en: The enable value, true to enable
198 * Set or clear the mask for an individual endpoint's interrupt
201 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
202 unsigned int ep, unsigned int dir_in,
212 local_irq_save(flags);
213 daint = dwc2_readl(hsotg, DAINTMSK);
218 dwc2_writel(hsotg, daint, DAINTMSK);
219 local_irq_restore(flags);
223 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
225 * @hsotg: Programming view of the DWC_otg controller
227 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
229 if (hsotg->hw_params.en_multiple_tx_fifo)
230 /* In dedicated FIFO mode we need count of IN EPs */
231 return hsotg->hw_params.num_dev_in_eps;
233 /* In shared FIFO mode we need count of Periodic IN EPs */
234 return hsotg->hw_params.num_dev_perio_in_ep;
238 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
239 * device mode TX FIFOs
241 * @hsotg: Programming view of the DWC_otg controller
243 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
249 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
250 hsotg->params.g_np_tx_fifo_size);
252 /* Get Endpoint Info Control block size in DWORDs. */
253 tx_addr_max = hsotg->hw_params.total_fifo_size;
255 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
256 if (tx_addr_max <= addr)
259 return tx_addr_max - addr;
263 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
265 * @hsotg: Programming view of the DWC_otg controller
268 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
273 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
274 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
275 gintsts2 &= gintmsk2;
277 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
278 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
279 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
280 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
285 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
288 * @hsotg: Programming view of the DWC_otg controller
290 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
295 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
297 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
300 return tx_fifo_depth;
302 return tx_fifo_depth / tx_fifo_count;
306 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
307 * @hsotg: The device instance.
309 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
316 u32 *txfsz = hsotg->params.g_tx_fifo_size;
318 /* Reset fifo map if not correctly cleared during previous session */
319 WARN_ON(hsotg->fifo_map);
322 /* set RX/NPTX FIFO sizes */
323 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
324 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
325 FIFOSIZE_STARTADDR_SHIFT) |
326 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
330 * arange all the rest of the TX FIFOs, as some versions of this
331 * block have overlapping default addresses. This also ensures
332 * that if the settings have been changed, then they are set to
336 /* start at the end of the GNPTXFSIZ, rounded up */
337 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
340 * Configure fifos sizes from provided configuration and assign
341 * them to endpoints dynamically according to maxpacket size value of
344 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
348 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
349 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
350 "insufficient fifo memory");
353 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
354 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
357 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
358 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
361 * according to p428 of the design guide, we need to ensure that
362 * all fifos are flushed before continuing
365 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
366 GRSTCTL_RXFFLSH, GRSTCTL);
368 /* wait until the fifos are both flushed */
371 val = dwc2_readl(hsotg, GRSTCTL);
373 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
376 if (--timeout == 0) {
378 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
386 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
390 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
391 * @ep: USB endpoint to allocate request for.
392 * @flags: Allocation flags
394 * Allocate a new USB request structure appropriate for the specified endpoint
396 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
399 struct dwc2_hsotg_req *req;
401 req = kzalloc(sizeof(*req), flags);
405 INIT_LIST_HEAD(&req->queue);
411 * is_ep_periodic - return true if the endpoint is in periodic mode.
412 * @hs_ep: The endpoint to query.
414 * Returns true if the endpoint is in periodic mode, meaning it is being
415 * used for an Interrupt or ISO transfer.
417 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
419 return hs_ep->periodic;
423 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
424 * @hsotg: The device state.
425 * @hs_ep: The endpoint for the request
426 * @hs_req: The request being processed.
428 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
429 * of a request to ensure the buffer is ready for access by the caller.
431 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
432 struct dwc2_hsotg_ep *hs_ep,
433 struct dwc2_hsotg_req *hs_req)
435 struct usb_request *req = &hs_req->req;
437 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
441 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
442 * for Control endpoint
443 * @hsotg: The device state.
445 * This function will allocate 4 descriptor chains for EP 0: 2 for
446 * Setup stage, per one for IN and OUT data/status transactions.
448 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
450 hsotg->setup_desc[0] =
451 dmam_alloc_coherent(hsotg->dev,
452 sizeof(struct dwc2_dma_desc),
453 &hsotg->setup_desc_dma[0],
455 if (!hsotg->setup_desc[0])
458 hsotg->setup_desc[1] =
459 dmam_alloc_coherent(hsotg->dev,
460 sizeof(struct dwc2_dma_desc),
461 &hsotg->setup_desc_dma[1],
463 if (!hsotg->setup_desc[1])
466 hsotg->ctrl_in_desc =
467 dmam_alloc_coherent(hsotg->dev,
468 sizeof(struct dwc2_dma_desc),
469 &hsotg->ctrl_in_desc_dma,
471 if (!hsotg->ctrl_in_desc)
474 hsotg->ctrl_out_desc =
475 dmam_alloc_coherent(hsotg->dev,
476 sizeof(struct dwc2_dma_desc),
477 &hsotg->ctrl_out_desc_dma,
479 if (!hsotg->ctrl_out_desc)
489 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
490 * @hsotg: The controller state.
491 * @hs_ep: The endpoint we're going to write for.
492 * @hs_req: The request to write data for.
494 * This is called when the TxFIFO has some space in it to hold a new
495 * transmission and we have something to give it. The actual setup of
496 * the data size is done elsewhere, so all we have to do is to actually
499 * The return value is zero if there is more space (or nothing was done)
500 * otherwise -ENOSPC is returned if the FIFO space was used up.
502 * This routine is only needed for PIO
504 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
505 struct dwc2_hsotg_ep *hs_ep,
506 struct dwc2_hsotg_req *hs_req)
508 bool periodic = is_ep_periodic(hs_ep);
509 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
510 int buf_pos = hs_req->req.actual;
511 int to_write = hs_ep->size_loaded;
517 to_write -= (buf_pos - hs_ep->last_load);
519 /* if there's nothing to write, get out early */
523 if (periodic && !hsotg->dedicated_fifos) {
524 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
529 * work out how much data was loaded so we can calculate
530 * how much data is left in the fifo.
533 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
536 * if shared fifo, we cannot write anything until the
537 * previous data has been completely sent.
539 if (hs_ep->fifo_load != 0) {
540 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
544 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
546 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
548 /* how much of the data has moved */
549 size_done = hs_ep->size_loaded - size_left;
551 /* how much data is left in the fifo */
552 can_write = hs_ep->fifo_load - size_done;
553 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
554 __func__, can_write);
556 can_write = hs_ep->fifo_size - can_write;
557 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
558 __func__, can_write);
560 if (can_write <= 0) {
561 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
564 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
565 can_write = dwc2_readl(hsotg,
566 DTXFSTS(hs_ep->fifo_index));
571 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
573 "%s: no queue slots available (0x%08x)\n",
576 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
580 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
581 can_write *= 4; /* fifo size is in 32bit quantities. */
584 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
586 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
587 __func__, gnptxsts, can_write, to_write, max_transfer);
590 * limit to 512 bytes of data, it seems at least on the non-periodic
591 * FIFO, requests of >512 cause the endpoint to get stuck with a
592 * fragment of the end of the transfer in it.
594 if (can_write > 512 && !periodic)
598 * limit the write to one max-packet size worth of data, but allow
599 * the transfer to return that it did not run out of fifo space
602 if (to_write > max_transfer) {
603 to_write = max_transfer;
605 /* it's needed only when we do not use dedicated fifos */
606 if (!hsotg->dedicated_fifos)
607 dwc2_hsotg_en_gsint(hsotg,
608 periodic ? GINTSTS_PTXFEMP :
612 /* see if we can write data */
614 if (to_write > can_write) {
615 to_write = can_write;
616 pkt_round = to_write % max_transfer;
619 * Round the write down to an
620 * exact number of packets.
622 * Note, we do not currently check to see if we can ever
623 * write a full packet or not to the FIFO.
627 to_write -= pkt_round;
630 * enable correct FIFO interrupt to alert us when there
634 /* it's needed only when we do not use dedicated fifos */
635 if (!hsotg->dedicated_fifos)
636 dwc2_hsotg_en_gsint(hsotg,
637 periodic ? GINTSTS_PTXFEMP :
641 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
642 to_write, hs_req->req.length, can_write, buf_pos);
647 hs_req->req.actual = buf_pos + to_write;
648 hs_ep->total_data += to_write;
651 hs_ep->fifo_load += to_write;
653 to_write = DIV_ROUND_UP(to_write, 4);
654 data = hs_req->req.buf + buf_pos;
656 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
658 return (to_write >= can_write) ? -ENOSPC : 0;
662 * get_ep_limit - get the maximum data legnth for this endpoint
663 * @hs_ep: The endpoint
665 * Return the maximum data that can be queued in one go on a given endpoint
666 * so that transfers that are too long can be split.
668 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
670 int index = hs_ep->index;
671 unsigned int maxsize;
675 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
676 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
680 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
685 /* we made the constant loading easier above by using +1 */
690 * constrain by packet count if maxpkts*pktsize is greater
691 * than the length register size.
694 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
695 maxsize = maxpkt * hs_ep->ep.maxpacket;
701 * dwc2_hsotg_read_frameno - read current frame number
702 * @hsotg: The device instance
704 * Return the current frame number
706 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
710 dsts = dwc2_readl(hsotg, DSTS);
711 dsts &= DSTS_SOFFN_MASK;
712 dsts >>= DSTS_SOFFN_SHIFT;
718 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
719 * DMA descriptor chain prepared for specific endpoint
720 * @hs_ep: The endpoint
722 * Return the maximum data that can be queued in one go on a given endpoint
723 * depending on its descriptor chain capacity so that transfers that
724 * are too long can be split.
726 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
728 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
729 int is_isoc = hs_ep->isochronous;
730 unsigned int maxsize;
731 u32 mps = hs_ep->ep.maxpacket;
732 int dir_in = hs_ep->dir_in;
735 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
736 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
737 MAX_DMA_DESC_NUM_HS_ISOC;
739 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
741 /* Interrupt OUT EP with mps not multiple of 4 */
743 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
744 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
750 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
751 * @hs_ep: The endpoint
752 * @mask: RX/TX bytes mask to be defined
754 * Returns maximum data payload for one descriptor after analyzing endpoint
756 * DMA descriptor transfer bytes limit depends on EP type:
758 * Isochronous - descriptor rx/tx bytes bitfield limit,
759 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
760 * have concatenations from various descriptors within one packet.
761 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
762 * to a single descriptor.
764 * Selects corresponding mask for RX/TX bytes as well.
766 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
768 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
769 u32 mps = hs_ep->ep.maxpacket;
770 int dir_in = hs_ep->dir_in;
773 if (!hs_ep->index && !dir_in) {
775 *mask = DEV_DMA_NBYTES_MASK;
776 } else if (hs_ep->isochronous) {
778 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
779 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
781 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
782 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
785 desc_size = DEV_DMA_NBYTES_LIMIT;
786 *mask = DEV_DMA_NBYTES_MASK;
788 /* Round down desc_size to be mps multiple */
789 desc_size -= desc_size % mps;
792 /* Interrupt OUT EP with mps not multiple of 4 */
794 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
796 *mask = DEV_DMA_NBYTES_MASK;
802 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
803 struct dwc2_dma_desc **desc,
808 int dir_in = hs_ep->dir_in;
809 u32 mps = hs_ep->ep.maxpacket;
815 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
817 hs_ep->desc_count = (len / maxsize) +
818 ((len % maxsize) ? 1 : 0);
820 hs_ep->desc_count = 1;
822 for (i = 0; i < hs_ep->desc_count; ++i) {
824 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
825 << DEV_DMA_BUFF_STS_SHIFT);
828 if (!hs_ep->index && !dir_in)
829 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
832 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
833 (*desc)->buf = dma_buff + offset;
839 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
842 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
843 ((hs_ep->send_zlp && true_last) ?
847 len << DEV_DMA_NBYTES_SHIFT & mask;
848 (*desc)->buf = dma_buff + offset;
851 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
852 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
853 << DEV_DMA_BUFF_STS_SHIFT);
859 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
860 * @hs_ep: The endpoint
861 * @ureq: Request to transfer
862 * @offset: offset in bytes
863 * @len: Length of the transfer
865 * This function will iterate over descriptor chain and fill its entries
866 * with corresponding information based on transfer data.
868 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
872 struct usb_request *ureq = NULL;
873 struct dwc2_dma_desc *desc = hs_ep->desc_list;
874 struct scatterlist *sg;
879 ureq = &hs_ep->req->req;
881 /* non-DMA sg buffer */
882 if (!ureq || !ureq->num_sgs) {
883 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
884 dma_buff, len, true);
889 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
890 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
891 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
893 desc_count += hs_ep->desc_count;
896 hs_ep->desc_count = desc_count;
900 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
901 * @hs_ep: The isochronous endpoint.
902 * @dma_buff: usb requests dma buffer.
903 * @len: usb request transfer length.
905 * Fills next free descriptor with the data of the arrived usb request,
906 * frame info, sets Last and IOC bits increments next_desc. If filled
907 * descriptor is not the first one, removes L bit from the previous descriptor
910 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
911 dma_addr_t dma_buff, unsigned int len)
913 struct dwc2_dma_desc *desc;
914 struct dwc2_hsotg *hsotg = hs_ep->parent;
919 dwc2_gadget_get_desc_params(hs_ep, &mask);
921 index = hs_ep->next_desc;
922 desc = &hs_ep->desc_list[index];
924 /* Check if descriptor chain full */
925 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
926 DEV_DMA_BUFF_STS_HREADY) {
927 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
931 /* Clear L bit of previous desc if more than one entries in the chain */
932 if (hs_ep->next_desc)
933 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
935 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
936 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
939 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
941 desc->buf = dma_buff;
942 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
943 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
947 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
950 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
951 DEV_DMA_ISOC_PID_MASK) |
952 ((len % hs_ep->ep.maxpacket) ?
954 ((hs_ep->target_frame <<
955 DEV_DMA_ISOC_FRNUM_SHIFT) &
956 DEV_DMA_ISOC_FRNUM_MASK);
959 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
960 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
962 /* Increment frame number by interval for IN */
964 dwc2_gadget_incr_frame_num(hs_ep);
966 /* Update index of last configured entry in the chain */
968 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
969 hs_ep->next_desc = 0;
975 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
976 * @hs_ep: The isochronous endpoint.
978 * Prepare descriptor chain for isochronous endpoints. Afterwards
979 * write DMA address to HW and enable the endpoint.
981 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
983 struct dwc2_hsotg *hsotg = hs_ep->parent;
984 struct dwc2_hsotg_req *hs_req, *treq;
985 int index = hs_ep->index;
991 struct dwc2_dma_desc *desc;
993 if (list_empty(&hs_ep->queue)) {
994 hs_ep->target_frame = TARGET_FRAME_INITIAL;
995 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
999 /* Initialize descriptor chain by Host Busy status */
1000 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1001 desc = &hs_ep->desc_list[i];
1003 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1004 << DEV_DMA_BUFF_STS_SHIFT);
1007 hs_ep->next_desc = 0;
1008 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1009 dma_addr_t dma_addr = hs_req->req.dma;
1011 if (hs_req->req.num_sgs) {
1012 WARN_ON(hs_req->req.num_sgs > 1);
1013 dma_addr = sg_dma_address(hs_req->req.sg);
1015 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1016 hs_req->req.length);
1021 hs_ep->compl_desc = 0;
1022 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1023 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1025 /* write descriptor chain address to control register */
1026 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1028 ctrl = dwc2_readl(hsotg, depctl);
1029 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1030 dwc2_writel(hsotg, ctrl, depctl);
1033 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1034 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1035 struct dwc2_hsotg_ep *hs_ep,
1036 struct dwc2_hsotg_req *hs_req,
1040 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1041 * @hsotg: The controller state.
1042 * @hs_ep: The endpoint to process a request for
1043 * @hs_req: The request to start.
1044 * @continuing: True if we are doing more for the current request.
1046 * Start the given request running by setting the endpoint registers
1047 * appropriately, and writing any data to the FIFOs.
1049 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1050 struct dwc2_hsotg_ep *hs_ep,
1051 struct dwc2_hsotg_req *hs_req,
1054 struct usb_request *ureq = &hs_req->req;
1055 int index = hs_ep->index;
1056 int dir_in = hs_ep->dir_in;
1061 unsigned int length;
1062 unsigned int packets;
1063 unsigned int maxreq;
1064 unsigned int dma_reg;
1067 if (hs_ep->req && !continuing) {
1068 dev_err(hsotg->dev, "%s: active request\n", __func__);
1071 } else if (hs_ep->req != hs_req && continuing) {
1073 "%s: continue different req\n", __func__);
1079 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1080 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1081 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1083 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1084 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1085 hs_ep->dir_in ? "in" : "out");
1087 /* If endpoint is stalled, we will restart request later */
1088 ctrl = dwc2_readl(hsotg, epctrl_reg);
1090 if (index && ctrl & DXEPCTL_STALL) {
1091 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1095 length = ureq->length - ureq->actual;
1096 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1097 ureq->length, ureq->actual);
1099 if (!using_desc_dma(hsotg))
1100 maxreq = get_ep_limit(hs_ep);
1102 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1104 if (length > maxreq) {
1105 int round = maxreq % hs_ep->ep.maxpacket;
1107 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1108 __func__, length, maxreq, round);
1110 /* round down to multiple of packets */
1118 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1120 packets = 1; /* send one packet if length is zero. */
1122 if (dir_in && index != 0)
1123 if (hs_ep->isochronous)
1124 epsize = DXEPTSIZ_MC(packets);
1126 epsize = DXEPTSIZ_MC(1);
1131 * zero length packet should be programmed on its own and should not
1132 * be counted in DIEPTSIZ.PktCnt with other packets.
1134 if (dir_in && ureq->zero && !continuing) {
1135 /* Test if zlp is actually required. */
1136 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1137 !(ureq->length % hs_ep->ep.maxpacket))
1138 hs_ep->send_zlp = 1;
1141 epsize |= DXEPTSIZ_PKTCNT(packets);
1142 epsize |= DXEPTSIZ_XFERSIZE(length);
1144 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1145 __func__, packets, length, ureq->length, epsize, epsize_reg);
1147 /* store the request as the current one we're doing */
1148 hs_ep->req = hs_req;
1150 if (using_desc_dma(hsotg)) {
1152 u32 mps = hs_ep->ep.maxpacket;
1154 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1158 else if (length % mps)
1159 length += (mps - (length % mps));
1163 offset = ureq->actual;
1165 /* Fill DDMA chain entries */
1166 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1169 /* write descriptor chain address to control register */
1170 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1172 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1173 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1175 /* write size / packets */
1176 dwc2_writel(hsotg, epsize, epsize_reg);
1178 if (using_dma(hsotg) && !continuing && (length != 0)) {
1180 * write DMA address to control register, buffer
1181 * already synced by dwc2_hsotg_ep_queue().
1184 dwc2_writel(hsotg, ureq->dma, dma_reg);
1186 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1187 __func__, &ureq->dma, dma_reg);
1191 if (hs_ep->isochronous) {
1192 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1193 if (hs_ep->interval == 1) {
1194 if (hs_ep->target_frame & 0x1)
1195 ctrl |= DXEPCTL_SETODDFR;
1197 ctrl |= DXEPCTL_SETEVENFR;
1199 ctrl |= DXEPCTL_CNAK;
1201 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1206 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1208 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1210 /* For Setup request do not clear NAK */
1211 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1212 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1214 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1215 dwc2_writel(hsotg, ctrl, epctrl_reg);
1218 * set these, it seems that DMA support increments past the end
1219 * of the packet buffer so we need to calculate the length from
1222 hs_ep->size_loaded = length;
1223 hs_ep->last_load = ureq->actual;
1225 if (dir_in && !using_dma(hsotg)) {
1226 /* set these anyway, we may need them for non-periodic in */
1227 hs_ep->fifo_load = 0;
1229 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1233 * Note, trying to clear the NAK here causes problems with transmit
1234 * on the S3C6400 ending up with the TXFIFO becoming full.
1237 /* check ep is enabled */
1238 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1240 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1241 index, dwc2_readl(hsotg, epctrl_reg));
1243 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1244 __func__, dwc2_readl(hsotg, epctrl_reg));
1246 /* enable ep interrupts */
1247 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1251 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1252 * @hsotg: The device state.
1253 * @hs_ep: The endpoint the request is on.
1254 * @req: The request being processed.
1256 * We've been asked to queue a request, so ensure that the memory buffer
1257 * is correctly setup for DMA. If we've been passed an extant DMA address
1258 * then ensure the buffer has been synced to memory. If our buffer has no
1259 * DMA memory, then we map the memory and mark our request to allow us to
1260 * cleanup on completion.
1262 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1263 struct dwc2_hsotg_ep *hs_ep,
1264 struct usb_request *req)
1268 hs_ep->map_dir = hs_ep->dir_in;
1269 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1276 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1277 __func__, req->buf, req->length);
1282 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1283 struct dwc2_hsotg_ep *hs_ep,
1284 struct dwc2_hsotg_req *hs_req)
1286 void *req_buf = hs_req->req.buf;
1288 /* If dma is not being used or buffer is aligned */
1289 if (!using_dma(hsotg) || !((long)req_buf & 3))
1292 WARN_ON(hs_req->saved_req_buf);
1294 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1295 hs_ep->ep.name, req_buf, hs_req->req.length);
1297 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1298 if (!hs_req->req.buf) {
1299 hs_req->req.buf = req_buf;
1301 "%s: unable to allocate memory for bounce buffer\n",
1306 /* Save actual buffer */
1307 hs_req->saved_req_buf = req_buf;
1310 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1315 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1316 struct dwc2_hsotg_ep *hs_ep,
1317 struct dwc2_hsotg_req *hs_req)
1319 /* If dma is not being used or buffer was aligned */
1320 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1323 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1324 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1326 /* Copy data from bounce buffer on successful out transfer */
1327 if (!hs_ep->dir_in && !hs_req->req.status)
1328 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1329 hs_req->req.actual);
1331 /* Free bounce buffer */
1332 kfree(hs_req->req.buf);
1334 hs_req->req.buf = hs_req->saved_req_buf;
1335 hs_req->saved_req_buf = NULL;
1339 * dwc2_gadget_target_frame_elapsed - Checks target frame
1340 * @hs_ep: The driver endpoint to check
1342 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1343 * corresponding transfer.
1345 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1347 struct dwc2_hsotg *hsotg = hs_ep->parent;
1348 u32 target_frame = hs_ep->target_frame;
1349 u32 current_frame = hsotg->frame_number;
1350 bool frame_overrun = hs_ep->frame_overrun;
1351 u16 limit = DSTS_SOFFN_LIMIT;
1353 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1356 if (!frame_overrun && current_frame >= target_frame)
1359 if (frame_overrun && current_frame >= target_frame &&
1360 ((current_frame - target_frame) < limit / 2))
1367 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1368 * @hsotg: The driver state
1369 * @hs_ep: the ep descriptor chain is for
1371 * Called to update EP0 structure's pointers depend on stage of
1374 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1375 struct dwc2_hsotg_ep *hs_ep)
1377 switch (hsotg->ep0_state) {
1378 case DWC2_EP0_SETUP:
1379 case DWC2_EP0_STATUS_OUT:
1380 hs_ep->desc_list = hsotg->setup_desc[0];
1381 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1383 case DWC2_EP0_DATA_IN:
1384 case DWC2_EP0_STATUS_IN:
1385 hs_ep->desc_list = hsotg->ctrl_in_desc;
1386 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1388 case DWC2_EP0_DATA_OUT:
1389 hs_ep->desc_list = hsotg->ctrl_out_desc;
1390 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1393 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1401 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1404 struct dwc2_hsotg_req *hs_req = our_req(req);
1405 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1406 struct dwc2_hsotg *hs = hs_ep->parent;
1413 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1414 ep->name, req, req->length, req->buf, req->no_interrupt,
1415 req->zero, req->short_not_ok);
1417 /* Prevent new request submission when controller is suspended */
1418 if (hs->lx_state != DWC2_L0) {
1419 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1424 /* initialise status of the request */
1425 INIT_LIST_HEAD(&hs_req->queue);
1427 req->status = -EINPROGRESS;
1429 /* Don't queue ISOC request if length greater than mps*mc */
1430 if (hs_ep->isochronous &&
1431 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1432 dev_err(hs->dev, "req length > maxpacket*mc\n");
1436 /* In DDMA mode for ISOC's don't queue request if length greater
1437 * than descriptor limits.
1439 if (using_desc_dma(hs) && hs_ep->isochronous) {
1440 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1441 if (hs_ep->dir_in && req->length > maxsize) {
1442 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1443 req->length, maxsize);
1447 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1448 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1449 req->length, hs_ep->ep.maxpacket);
1454 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1458 /* if we're using DMA, sync the buffers as necessary */
1459 if (using_dma(hs)) {
1460 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1464 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1465 if (using_desc_dma(hs) && !hs_ep->index) {
1466 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1471 first = list_empty(&hs_ep->queue);
1472 list_add_tail(&hs_req->queue, &hs_ep->queue);
1475 * Handle DDMA isochronous transfers separately - just add new entry
1476 * to the descriptor chain.
1477 * Transfer will be started once SW gets either one of NAK or
1478 * OutTknEpDis interrupts.
1480 if (using_desc_dma(hs) && hs_ep->isochronous) {
1481 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1482 dma_addr_t dma_addr = hs_req->req.dma;
1484 if (hs_req->req.num_sgs) {
1485 WARN_ON(hs_req->req.num_sgs > 1);
1486 dma_addr = sg_dma_address(hs_req->req.sg);
1488 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1489 hs_req->req.length);
1494 /* Change EP direction if status phase request is after data out */
1495 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1496 hs->ep0_state == DWC2_EP0_DATA_OUT)
1500 if (!hs_ep->isochronous) {
1501 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1505 /* Update current frame number value. */
1506 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1507 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1508 dwc2_gadget_incr_frame_num(hs_ep);
1509 /* Update current frame number value once more as it
1512 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1515 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1516 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1521 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1524 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1525 struct dwc2_hsotg *hs = hs_ep->parent;
1526 unsigned long flags;
1529 spin_lock_irqsave(&hs->lock, flags);
1530 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1531 spin_unlock_irqrestore(&hs->lock, flags);
1536 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1537 struct usb_request *req)
1539 struct dwc2_hsotg_req *hs_req = our_req(req);
1545 * dwc2_hsotg_complete_oursetup - setup completion callback
1546 * @ep: The endpoint the request was on.
1547 * @req: The request completed.
1549 * Called on completion of any requests the driver itself
1550 * submitted that need cleaning up.
1552 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1553 struct usb_request *req)
1555 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1556 struct dwc2_hsotg *hsotg = hs_ep->parent;
1558 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1560 dwc2_hsotg_ep_free_request(ep, req);
1564 * ep_from_windex - convert control wIndex value to endpoint
1565 * @hsotg: The driver state.
1566 * @windex: The control request wIndex field (in host order).
1568 * Convert the given wIndex into a pointer to an driver endpoint
1569 * structure, or return NULL if it is not a valid endpoint.
1571 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1574 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1575 int idx = windex & 0x7F;
1577 if (windex >= 0x100)
1580 if (idx > hsotg->num_of_eps)
1583 return index_to_ep(hsotg, idx, dir);
1587 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1588 * @hsotg: The driver state.
1589 * @testmode: requested usb test mode
1590 * Enable usb Test Mode requested by the Host.
1592 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1594 int dctl = dwc2_readl(hsotg, DCTL);
1596 dctl &= ~DCTL_TSTCTL_MASK;
1600 case USB_TEST_SE0_NAK:
1601 case USB_TEST_PACKET:
1602 case USB_TEST_FORCE_ENABLE:
1603 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1608 dwc2_writel(hsotg, dctl, DCTL);
1613 * dwc2_hsotg_send_reply - send reply to control request
1614 * @hsotg: The device state
1616 * @buff: Buffer for request
1617 * @length: Length of reply.
1619 * Create a request and queue it on the given endpoint. This is useful as
1620 * an internal method of sending replies to certain control requests, etc.
1622 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1623 struct dwc2_hsotg_ep *ep,
1627 struct usb_request *req;
1630 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1632 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1633 hsotg->ep0_reply = req;
1635 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1639 req->buf = hsotg->ep0_buff;
1640 req->length = length;
1642 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1646 req->complete = dwc2_hsotg_complete_oursetup;
1649 memcpy(req->buf, buff, length);
1651 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1653 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1661 * dwc2_hsotg_process_req_status - process request GET_STATUS
1662 * @hsotg: The device state
1663 * @ctrl: USB control request
1665 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1666 struct usb_ctrlrequest *ctrl)
1668 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1669 struct dwc2_hsotg_ep *ep;
1674 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1677 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1681 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1682 case USB_RECIP_DEVICE:
1683 status = hsotg->gadget.is_selfpowered <<
1684 USB_DEVICE_SELF_POWERED;
1685 status |= hsotg->remote_wakeup_allowed <<
1686 USB_DEVICE_REMOTE_WAKEUP;
1687 reply = cpu_to_le16(status);
1690 case USB_RECIP_INTERFACE:
1691 /* currently, the data result should be zero */
1692 reply = cpu_to_le16(0);
1695 case USB_RECIP_ENDPOINT:
1696 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1700 reply = cpu_to_le16(ep->halted ? 1 : 0);
1707 if (le16_to_cpu(ctrl->wLength) != 2)
1710 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1712 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1719 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1722 * get_ep_head - return the first request on the endpoint
1723 * @hs_ep: The controller endpoint to get
1725 * Get the first request on the endpoint.
1727 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1729 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1734 * dwc2_gadget_start_next_request - Starts next request from ep queue
1735 * @hs_ep: Endpoint structure
1737 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1738 * in its handler. Hence we need to unmask it here to be able to do
1739 * resynchronization.
1741 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1743 struct dwc2_hsotg *hsotg = hs_ep->parent;
1744 int dir_in = hs_ep->dir_in;
1745 struct dwc2_hsotg_req *hs_req;
1747 if (!list_empty(&hs_ep->queue)) {
1748 hs_req = get_ep_head(hs_ep);
1749 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1752 if (!hs_ep->isochronous)
1756 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1759 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1765 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1766 * @hsotg: The device state
1767 * @ctrl: USB control request
1769 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1770 struct usb_ctrlrequest *ctrl)
1772 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1773 struct dwc2_hsotg_req *hs_req;
1774 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1775 struct dwc2_hsotg_ep *ep;
1782 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1783 __func__, set ? "SET" : "CLEAR");
1785 wValue = le16_to_cpu(ctrl->wValue);
1786 wIndex = le16_to_cpu(ctrl->wIndex);
1787 recip = ctrl->bRequestType & USB_RECIP_MASK;
1790 case USB_RECIP_DEVICE:
1792 case USB_DEVICE_REMOTE_WAKEUP:
1794 hsotg->remote_wakeup_allowed = 1;
1796 hsotg->remote_wakeup_allowed = 0;
1799 case USB_DEVICE_TEST_MODE:
1800 if ((wIndex & 0xff) != 0)
1805 hsotg->test_mode = wIndex >> 8;
1811 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1814 "%s: failed to send reply\n", __func__);
1819 case USB_RECIP_ENDPOINT:
1820 ep = ep_from_windex(hsotg, wIndex);
1822 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1828 case USB_ENDPOINT_HALT:
1829 halted = ep->halted;
1832 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1834 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1837 "%s: failed to send reply\n", __func__);
1842 * we have to complete all requests for ep if it was
1843 * halted, and the halt was cleared by CLEAR_FEATURE
1846 if (!set && halted) {
1848 * If we have request in progress,
1854 list_del_init(&hs_req->queue);
1855 if (hs_req->req.complete) {
1856 spin_unlock(&hsotg->lock);
1857 usb_gadget_giveback_request(
1858 &ep->ep, &hs_req->req);
1859 spin_lock(&hsotg->lock);
1863 /* If we have pending request, then start it */
1865 dwc2_gadget_start_next_request(ep);
1880 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1883 * dwc2_hsotg_stall_ep0 - stall ep0
1884 * @hsotg: The device state
1886 * Set stall for ep0 as response for setup request.
1888 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1890 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1894 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1895 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1898 * DxEPCTL_Stall will be cleared by EP once it has
1899 * taken effect, so no need to clear later.
1902 ctrl = dwc2_readl(hsotg, reg);
1903 ctrl |= DXEPCTL_STALL;
1904 ctrl |= DXEPCTL_CNAK;
1905 dwc2_writel(hsotg, ctrl, reg);
1908 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1909 ctrl, reg, dwc2_readl(hsotg, reg));
1912 * complete won't be called, so we enqueue
1913 * setup request here
1915 dwc2_hsotg_enqueue_setup(hsotg);
1919 * dwc2_hsotg_process_control - process a control request
1920 * @hsotg: The device state
1921 * @ctrl: The control request received
1923 * The controller has received the SETUP phase of a control request, and
1924 * needs to work out what to do next (and whether to pass it on to the
1927 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1928 struct usb_ctrlrequest *ctrl)
1930 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1935 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1936 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1937 ctrl->wIndex, ctrl->wLength);
1939 if (ctrl->wLength == 0) {
1941 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1942 } else if (ctrl->bRequestType & USB_DIR_IN) {
1944 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1947 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1950 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1951 switch (ctrl->bRequest) {
1952 case USB_REQ_SET_ADDRESS:
1953 hsotg->connected = 1;
1954 dcfg = dwc2_readl(hsotg, DCFG);
1955 dcfg &= ~DCFG_DEVADDR_MASK;
1956 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1957 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1958 dwc2_writel(hsotg, dcfg, DCFG);
1960 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1962 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1965 case USB_REQ_GET_STATUS:
1966 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1969 case USB_REQ_CLEAR_FEATURE:
1970 case USB_REQ_SET_FEATURE:
1971 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1976 /* as a fallback, try delivering it to the driver to deal with */
1978 if (ret == 0 && hsotg->driver) {
1979 spin_unlock(&hsotg->lock);
1980 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1981 spin_lock(&hsotg->lock);
1983 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1986 hsotg->delayed_status = false;
1987 if (ret == USB_GADGET_DELAYED_STATUS)
1988 hsotg->delayed_status = true;
1991 * the request is either unhandlable, or is not formatted correctly
1992 * so respond with a STALL for the status stage to indicate failure.
1996 dwc2_hsotg_stall_ep0(hsotg);
2000 * dwc2_hsotg_complete_setup - completion of a setup transfer
2001 * @ep: The endpoint the request was on.
2002 * @req: The request completed.
2004 * Called on completion of any requests the driver itself submitted for
2007 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2008 struct usb_request *req)
2010 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2011 struct dwc2_hsotg *hsotg = hs_ep->parent;
2013 if (req->status < 0) {
2014 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2018 spin_lock(&hsotg->lock);
2019 if (req->actual == 0)
2020 dwc2_hsotg_enqueue_setup(hsotg);
2022 dwc2_hsotg_process_control(hsotg, req->buf);
2023 spin_unlock(&hsotg->lock);
2027 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2028 * @hsotg: The device state.
2030 * Enqueue a request on EP0 if necessary to received any SETUP packets
2031 * received from the host.
2033 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2035 struct usb_request *req = hsotg->ctrl_req;
2036 struct dwc2_hsotg_req *hs_req = our_req(req);
2039 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2043 req->buf = hsotg->ctrl_buff;
2044 req->complete = dwc2_hsotg_complete_setup;
2046 if (!list_empty(&hs_req->queue)) {
2047 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2051 hsotg->eps_out[0]->dir_in = 0;
2052 hsotg->eps_out[0]->send_zlp = 0;
2053 hsotg->ep0_state = DWC2_EP0_SETUP;
2055 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2057 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2059 * Don't think there's much we can do other than watch the
2065 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2066 struct dwc2_hsotg_ep *hs_ep)
2069 u8 index = hs_ep->index;
2070 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2071 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2074 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2077 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2079 if (using_desc_dma(hsotg)) {
2080 /* Not specific buffer needed for ep0 ZLP */
2081 dma_addr_t dma = hs_ep->desc_list_dma;
2084 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2086 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2088 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2089 DXEPTSIZ_XFERSIZE(0),
2093 ctrl = dwc2_readl(hsotg, epctl_reg);
2094 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2095 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2096 ctrl |= DXEPCTL_USBACTEP;
2097 dwc2_writel(hsotg, ctrl, epctl_reg);
2101 * dwc2_hsotg_complete_request - complete a request given to us
2102 * @hsotg: The device state.
2103 * @hs_ep: The endpoint the request was on.
2104 * @hs_req: The request to complete.
2105 * @result: The result code (0 => Ok, otherwise errno)
2107 * The given request has finished, so call the necessary completion
2108 * if it has one and then look to see if we can start a new request
2111 * Note, expects the ep to already be locked as appropriate.
2113 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2114 struct dwc2_hsotg_ep *hs_ep,
2115 struct dwc2_hsotg_req *hs_req,
2119 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2123 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2124 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2127 * only replace the status if we've not already set an error
2128 * from a previous transaction
2131 if (hs_req->req.status == -EINPROGRESS)
2132 hs_req->req.status = result;
2134 if (using_dma(hsotg))
2135 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2137 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2140 list_del_init(&hs_req->queue);
2143 * call the complete request with the locks off, just in case the
2144 * request tries to queue more work for this endpoint.
2147 if (hs_req->req.complete) {
2148 spin_unlock(&hsotg->lock);
2149 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2150 spin_lock(&hsotg->lock);
2153 /* In DDMA don't need to proceed to starting of next ISOC request */
2154 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2158 * Look to see if there is anything else to do. Note, the completion
2159 * of the previous request may have caused a new request to be started
2160 * so be careful when doing this.
2163 if (!hs_ep->req && result >= 0)
2164 dwc2_gadget_start_next_request(hs_ep);
2168 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2169 * @hs_ep: The endpoint the request was on.
2171 * Get first request from the ep queue, determine descriptor on which complete
2172 * happened. SW discovers which descriptor currently in use by HW, adjusts
2173 * dma_address and calculates index of completed descriptor based on the value
2174 * of DEPDMA register. Update actual length of request, giveback to gadget.
2176 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2178 struct dwc2_hsotg *hsotg = hs_ep->parent;
2179 struct dwc2_hsotg_req *hs_req;
2180 struct usb_request *ureq;
2184 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2186 /* Process only descriptors with buffer status set to DMA done */
2187 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2188 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2190 hs_req = get_ep_head(hs_ep);
2192 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2195 ureq = &hs_req->req;
2197 /* Check completion status */
2198 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2200 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2201 DEV_DMA_ISOC_RX_NBYTES_MASK;
2202 ureq->actual = ureq->length - ((desc_sts & mask) >>
2203 DEV_DMA_ISOC_NBYTES_SHIFT);
2205 /* Adjust actual len for ISOC Out if len is
2208 if (!hs_ep->dir_in && ureq->length & 0x3)
2209 ureq->actual += 4 - (ureq->length & 0x3);
2211 /* Set actual frame number for completed transfers */
2212 ureq->frame_number =
2213 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2214 DEV_DMA_ISOC_FRNUM_SHIFT;
2217 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2219 hs_ep->compl_desc++;
2220 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2221 hs_ep->compl_desc = 0;
2222 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2227 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2228 * @hs_ep: The isochronous endpoint.
2230 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2231 * interrupt. Reset target frame and next_desc to allow to start
2232 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2233 * interrupt for OUT direction.
2235 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2237 struct dwc2_hsotg *hsotg = hs_ep->parent;
2240 dwc2_flush_rx_fifo(hsotg);
2241 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2243 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2244 hs_ep->next_desc = 0;
2245 hs_ep->compl_desc = 0;
2249 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2250 * @hsotg: The device state.
2251 * @ep_idx: The endpoint index for the data
2252 * @size: The size of data in the fifo, in bytes
2254 * The FIFO status shows there is data to read from the FIFO for a given
2255 * endpoint, so sort out whether we need to read the data into a request
2256 * that has been made for that endpoint.
2258 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2260 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2261 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2267 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2271 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2272 __func__, size, ep_idx, epctl);
2274 /* dump the data from the FIFO, we've nothing we can do */
2275 for (ptr = 0; ptr < size; ptr += 4)
2276 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2282 read_ptr = hs_req->req.actual;
2283 max_req = hs_req->req.length - read_ptr;
2285 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2286 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2288 if (to_read > max_req) {
2290 * more data appeared than we where willing
2291 * to deal with in this request.
2294 /* currently we don't deal this */
2298 hs_ep->total_data += to_read;
2299 hs_req->req.actual += to_read;
2300 to_read = DIV_ROUND_UP(to_read, 4);
2303 * note, we might over-write the buffer end by 3 bytes depending on
2304 * alignment of the data.
2306 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2307 hs_req->req.buf + read_ptr, to_read);
2311 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2312 * @hsotg: The device instance
2313 * @dir_in: If IN zlp
2315 * Generate a zero-length IN packet request for terminating a SETUP
2318 * Note, since we don't write any data to the TxFIFO, then it is
2319 * currently believed that we do not need to wait for any space in
2322 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2324 /* eps_out[0] is used in both directions */
2325 hsotg->eps_out[0]->dir_in = dir_in;
2326 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2328 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2332 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2333 * @hs_ep - The endpoint on which transfer went
2335 * Iterate over endpoints descriptor chain and get info on bytes remained
2336 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2338 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2340 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2341 struct dwc2_hsotg *hsotg = hs_ep->parent;
2342 unsigned int bytes_rem = 0;
2343 unsigned int bytes_rem_correction = 0;
2344 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2347 u32 mps = hs_ep->ep.maxpacket;
2348 int dir_in = hs_ep->dir_in;
2353 /* Interrupt OUT EP with mps not multiple of 4 */
2355 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2356 bytes_rem_correction = 4 - (mps % 4);
2358 for (i = 0; i < hs_ep->desc_count; ++i) {
2359 status = desc->status;
2360 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2361 bytes_rem -= bytes_rem_correction;
2363 if (status & DEV_DMA_STS_MASK)
2364 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2365 i, status & DEV_DMA_STS_MASK);
2367 if (status & DEV_DMA_L)
2377 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2378 * @hsotg: The device instance
2379 * @epnum: The endpoint received from
2381 * The RXFIFO has delivered an OutDone event, which means that the data
2382 * transfer for an OUT endpoint has been completed, either by a short
2383 * packet or by the finish of a transfer.
2385 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2387 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2388 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2389 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2390 struct usb_request *req = &hs_req->req;
2391 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2395 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2399 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2400 dev_dbg(hsotg->dev, "zlp packet received\n");
2401 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2402 dwc2_hsotg_enqueue_setup(hsotg);
2406 if (using_desc_dma(hsotg))
2407 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2409 if (using_dma(hsotg)) {
2410 unsigned int size_done;
2413 * Calculate the size of the transfer by checking how much
2414 * is left in the endpoint size register and then working it
2415 * out from the amount we loaded for the transfer.
2417 * We need to do this as DMA pointers are always 32bit aligned
2418 * so may overshoot/undershoot the transfer.
2421 size_done = hs_ep->size_loaded - size_left;
2422 size_done += hs_ep->last_load;
2424 req->actual = size_done;
2427 /* if there is more request to do, schedule new transfer */
2428 if (req->actual < req->length && size_left == 0) {
2429 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2433 if (req->actual < req->length && req->short_not_ok) {
2434 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2435 __func__, req->actual, req->length);
2438 * todo - what should we return here? there's no one else
2439 * even bothering to check the status.
2443 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2444 if (!using_desc_dma(hsotg) && epnum == 0 &&
2445 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2446 /* Move to STATUS IN */
2447 if (!hsotg->delayed_status)
2448 dwc2_hsotg_ep0_zlp(hsotg, true);
2451 /* Set actual frame number for completed transfers */
2452 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2453 req->frame_number = hs_ep->target_frame;
2454 dwc2_gadget_incr_frame_num(hs_ep);
2457 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2461 * dwc2_hsotg_handle_rx - RX FIFO has data
2462 * @hsotg: The device instance
2464 * The IRQ handler has detected that the RX FIFO has some data in it
2465 * that requires processing, so find out what is in there and do the
2468 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2469 * chunks, so if you have x packets received on an endpoint you'll get x
2470 * FIFO events delivered, each with a packet's worth of data in it.
2472 * When using DMA, we should not be processing events from the RXFIFO
2473 * as the actual data should be sent to the memory directly and we turn
2474 * on the completion interrupts to get notifications of transfer completion.
2476 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2478 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2479 u32 epnum, status, size;
2481 WARN_ON(using_dma(hsotg));
2483 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2484 status = grxstsr & GRXSTS_PKTSTS_MASK;
2486 size = grxstsr & GRXSTS_BYTECNT_MASK;
2487 size >>= GRXSTS_BYTECNT_SHIFT;
2489 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2490 __func__, grxstsr, size, epnum);
2492 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2493 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2494 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2497 case GRXSTS_PKTSTS_OUTDONE:
2498 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2499 dwc2_hsotg_read_frameno(hsotg));
2501 if (!using_dma(hsotg))
2502 dwc2_hsotg_handle_outdone(hsotg, epnum);
2505 case GRXSTS_PKTSTS_SETUPDONE:
2507 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2508 dwc2_hsotg_read_frameno(hsotg),
2509 dwc2_readl(hsotg, DOEPCTL(0)));
2511 * Call dwc2_hsotg_handle_outdone here if it was not called from
2512 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2513 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2515 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2516 dwc2_hsotg_handle_outdone(hsotg, epnum);
2519 case GRXSTS_PKTSTS_OUTRX:
2520 dwc2_hsotg_rx_data(hsotg, epnum, size);
2523 case GRXSTS_PKTSTS_SETUPRX:
2525 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2526 dwc2_hsotg_read_frameno(hsotg),
2527 dwc2_readl(hsotg, DOEPCTL(0)));
2529 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2531 dwc2_hsotg_rx_data(hsotg, epnum, size);
2535 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2538 dwc2_hsotg_dump(hsotg);
2544 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2545 * @mps: The maximum packet size in bytes.
2547 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2551 return D0EPCTL_MPS_64;
2553 return D0EPCTL_MPS_32;
2555 return D0EPCTL_MPS_16;
2557 return D0EPCTL_MPS_8;
2560 /* bad max packet size, warn and return invalid result */
2566 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2567 * @hsotg: The driver state.
2568 * @ep: The index number of the endpoint
2569 * @mps: The maximum packet size in bytes
2570 * @mc: The multicount value
2571 * @dir_in: True if direction is in.
2573 * Configure the maximum packet size for the given endpoint, updating
2574 * the hardware control registers to reflect this.
2576 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2577 unsigned int ep, unsigned int mps,
2578 unsigned int mc, unsigned int dir_in)
2580 struct dwc2_hsotg_ep *hs_ep;
2583 hs_ep = index_to_ep(hsotg, ep, dir_in);
2588 u32 mps_bytes = mps;
2590 /* EP0 is a special case */
2591 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2594 hs_ep->ep.maxpacket = mps_bytes;
2602 hs_ep->ep.maxpacket = mps;
2606 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2607 reg &= ~DXEPCTL_MPS_MASK;
2609 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2611 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2612 reg &= ~DXEPCTL_MPS_MASK;
2614 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2620 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2624 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2625 * @hsotg: The driver state
2626 * @idx: The index for the endpoint (0..15)
2628 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2630 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2633 /* wait until the fifo is flushed */
2634 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2635 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2640 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2641 * @hsotg: The driver state
2642 * @hs_ep: The driver endpoint to check.
2644 * Check to see if there is a request that has data to send, and if so
2645 * make an attempt to write data into the FIFO.
2647 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2648 struct dwc2_hsotg_ep *hs_ep)
2650 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2652 if (!hs_ep->dir_in || !hs_req) {
2654 * if request is not enqueued, we disable interrupts
2655 * for endpoints, excepting ep0
2657 if (hs_ep->index != 0)
2658 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2663 if (hs_req->req.actual < hs_req->req.length) {
2664 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2666 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2673 * dwc2_hsotg_complete_in - complete IN transfer
2674 * @hsotg: The device state.
2675 * @hs_ep: The endpoint that has just completed.
2677 * An IN transfer has been completed, update the transfer's state and then
2678 * call the relevant completion routines.
2680 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2681 struct dwc2_hsotg_ep *hs_ep)
2683 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2684 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2685 int size_left, size_done;
2688 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2692 /* Finish ZLP handling for IN EP0 transactions */
2693 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2694 dev_dbg(hsotg->dev, "zlp packet sent\n");
2697 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2698 * changed to IN. Change back to complete OUT transfer request
2702 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2703 if (hsotg->test_mode) {
2706 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2708 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2710 dwc2_hsotg_stall_ep0(hsotg);
2714 dwc2_hsotg_enqueue_setup(hsotg);
2719 * Calculate the size of the transfer by checking how much is left
2720 * in the endpoint size register and then working it out from
2721 * the amount we loaded for the transfer.
2723 * We do this even for DMA, as the transfer may have incremented
2724 * past the end of the buffer (DMA transfers are always 32bit
2727 if (using_desc_dma(hsotg)) {
2728 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2730 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2733 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2736 size_done = hs_ep->size_loaded - size_left;
2737 size_done += hs_ep->last_load;
2739 if (hs_req->req.actual != size_done)
2740 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2741 __func__, hs_req->req.actual, size_done);
2743 hs_req->req.actual = size_done;
2744 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2745 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2747 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2748 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2749 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2753 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2754 if (hs_ep->send_zlp) {
2755 hs_ep->send_zlp = 0;
2756 if (!using_desc_dma(hsotg)) {
2757 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2758 /* transfer will be completed on next complete interrupt */
2763 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2764 /* Move to STATUS OUT */
2765 dwc2_hsotg_ep0_zlp(hsotg, false);
2769 /* Set actual frame number for completed transfers */
2770 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2771 hs_req->req.frame_number = hs_ep->target_frame;
2772 dwc2_gadget_incr_frame_num(hs_ep);
2775 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2779 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2780 * @hsotg: The device state.
2781 * @idx: Index of ep.
2782 * @dir_in: Endpoint direction 1-in 0-out.
2784 * Reads for endpoint with given index and direction, by masking
2785 * epint_reg with coresponding mask.
2787 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2788 unsigned int idx, int dir_in)
2790 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2791 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2796 mask = dwc2_readl(hsotg, epmsk_reg);
2797 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2798 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2799 mask |= DXEPINT_SETUP_RCVD;
2801 ints = dwc2_readl(hsotg, epint_reg);
2807 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2808 * @hs_ep: The endpoint on which interrupt is asserted.
2810 * This interrupt indicates that the endpoint has been disabled per the
2811 * application's request.
2813 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2814 * in case of ISOC completes current request.
2816 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2817 * request starts it.
2819 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2821 struct dwc2_hsotg *hsotg = hs_ep->parent;
2822 struct dwc2_hsotg_req *hs_req;
2823 unsigned char idx = hs_ep->index;
2824 int dir_in = hs_ep->dir_in;
2825 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2826 int dctl = dwc2_readl(hsotg, DCTL);
2828 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2831 int epctl = dwc2_readl(hsotg, epctl_reg);
2833 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2835 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2836 int dctl = dwc2_readl(hsotg, DCTL);
2838 dctl |= DCTL_CGNPINNAK;
2839 dwc2_writel(hsotg, dctl, DCTL);
2843 if (dctl & DCTL_GOUTNAKSTS) {
2844 dctl |= DCTL_CGOUTNAK;
2845 dwc2_writel(hsotg, dctl, DCTL);
2849 if (!hs_ep->isochronous)
2852 if (list_empty(&hs_ep->queue)) {
2853 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2859 hs_req = get_ep_head(hs_ep);
2861 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2863 dwc2_gadget_incr_frame_num(hs_ep);
2864 /* Update current frame number value. */
2865 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2866 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2870 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2871 * @ep: The endpoint on which interrupt is asserted.
2873 * This is starting point for ISOC-OUT transfer, synchronization done with
2874 * first out token received from host while corresponding EP is disabled.
2876 * Device does not know initial frame in which out token will come. For this
2877 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2878 * getting this interrupt SW starts calculation for next transfer frame.
2880 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2882 struct dwc2_hsotg *hsotg = ep->parent;
2883 struct dwc2_hsotg_req *hs_req;
2884 int dir_in = ep->dir_in;
2886 if (dir_in || !ep->isochronous)
2889 if (using_desc_dma(hsotg)) {
2890 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2891 /* Start first ISO Out */
2892 ep->target_frame = hsotg->frame_number;
2893 dwc2_gadget_start_isoc_ddma(ep);
2898 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2901 ep->target_frame = hsotg->frame_number;
2902 if (ep->interval > 1) {
2903 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2904 if (ep->target_frame & 0x1)
2905 ctrl |= DXEPCTL_SETODDFR;
2907 ctrl |= DXEPCTL_SETEVENFR;
2909 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2913 while (dwc2_gadget_target_frame_elapsed(ep)) {
2914 hs_req = get_ep_head(ep);
2916 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2918 dwc2_gadget_incr_frame_num(ep);
2919 /* Update current frame number value. */
2920 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2924 dwc2_gadget_start_next_request(ep);
2928 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2929 struct dwc2_hsotg_ep *hs_ep);
2932 * dwc2_gadget_handle_nak - handle NAK interrupt
2933 * @hs_ep: The endpoint on which interrupt is asserted.
2935 * This is starting point for ISOC-IN transfer, synchronization done with
2936 * first IN token received from host while corresponding EP is disabled.
2938 * Device does not know when first one token will arrive from host. On first
2939 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2940 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2941 * sent in response to that as there was no data in FIFO. SW is basing on this
2942 * interrupt to obtain frame in which token has come and then based on the
2943 * interval calculates next frame for transfer.
2945 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2947 struct dwc2_hsotg *hsotg = hs_ep->parent;
2948 struct dwc2_hsotg_req *hs_req;
2949 int dir_in = hs_ep->dir_in;
2952 if (!dir_in || !hs_ep->isochronous)
2955 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2957 if (using_desc_dma(hsotg)) {
2958 hs_ep->target_frame = hsotg->frame_number;
2959 dwc2_gadget_incr_frame_num(hs_ep);
2961 /* In service interval mode target_frame must
2962 * be set to last (u)frame of the service interval.
2964 if (hsotg->params.service_interval) {
2965 /* Set target_frame to the first (u)frame of
2966 * the service interval
2968 hs_ep->target_frame &= ~hs_ep->interval + 1;
2970 /* Set target_frame to the last (u)frame of
2971 * the service interval
2973 dwc2_gadget_incr_frame_num(hs_ep);
2974 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2977 dwc2_gadget_start_isoc_ddma(hs_ep);
2981 hs_ep->target_frame = hsotg->frame_number;
2982 if (hs_ep->interval > 1) {
2983 u32 ctrl = dwc2_readl(hsotg,
2984 DIEPCTL(hs_ep->index));
2985 if (hs_ep->target_frame & 0x1)
2986 ctrl |= DXEPCTL_SETODDFR;
2988 ctrl |= DXEPCTL_SETEVENFR;
2990 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
2994 if (using_desc_dma(hsotg))
2997 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
2998 if (ctrl & DXEPCTL_EPENA)
2999 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3001 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3003 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3004 hs_req = get_ep_head(hs_ep);
3006 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3008 dwc2_gadget_incr_frame_num(hs_ep);
3009 /* Update current frame number value. */
3010 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3014 dwc2_gadget_start_next_request(hs_ep);
3018 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3019 * @hsotg: The driver state
3020 * @idx: The index for the endpoint (0..15)
3021 * @dir_in: Set if this is an IN endpoint
3023 * Process and clear any interrupt pending for an individual endpoint
3025 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3028 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3029 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3030 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3031 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3034 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3036 /* Clear endpoint interrupts */
3037 dwc2_writel(hsotg, ints, epint_reg);
3040 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3041 __func__, idx, dir_in ? "in" : "out");
3045 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3046 __func__, idx, dir_in ? "in" : "out", ints);
3048 /* Don't process XferCompl interrupt if it is a setup packet */
3049 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3050 ints &= ~DXEPINT_XFERCOMPL;
3053 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3054 * stage and xfercomplete was generated without SETUP phase done
3055 * interrupt. SW should parse received setup packet only after host's
3056 * exit from setup phase of control transfer.
3058 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3059 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3060 ints &= ~DXEPINT_XFERCOMPL;
3062 if (ints & DXEPINT_XFERCOMPL) {
3064 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3065 __func__, dwc2_readl(hsotg, epctl_reg),
3066 dwc2_readl(hsotg, epsiz_reg));
3068 /* In DDMA handle isochronous requests separately */
3069 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3070 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3071 } else if (dir_in) {
3073 * We get OutDone from the FIFO, so we only
3074 * need to look at completing IN requests here
3075 * if operating slave mode
3077 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3078 dwc2_hsotg_complete_in(hsotg, hs_ep);
3080 if (idx == 0 && !hs_ep->req)
3081 dwc2_hsotg_enqueue_setup(hsotg);
3082 } else if (using_dma(hsotg)) {
3084 * We're using DMA, we need to fire an OutDone here
3085 * as we ignore the RXFIFO.
3087 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3088 dwc2_hsotg_handle_outdone(hsotg, idx);
3092 if (ints & DXEPINT_EPDISBLD)
3093 dwc2_gadget_handle_ep_disabled(hs_ep);
3095 if (ints & DXEPINT_OUTTKNEPDIS)
3096 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3098 if (ints & DXEPINT_NAKINTRPT)
3099 dwc2_gadget_handle_nak(hs_ep);
3101 if (ints & DXEPINT_AHBERR)
3102 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3104 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3105 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3107 if (using_dma(hsotg) && idx == 0) {
3109 * this is the notification we've received a
3110 * setup packet. In non-DMA mode we'd get this
3111 * from the RXFIFO, instead we need to process
3118 dwc2_hsotg_handle_outdone(hsotg, 0);
3122 if (ints & DXEPINT_STSPHSERCVD) {
3123 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3125 /* Safety check EP0 state when STSPHSERCVD asserted */
3126 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3127 /* Move to STATUS IN for DDMA */
3128 if (using_desc_dma(hsotg)) {
3129 if (!hsotg->delayed_status)
3130 dwc2_hsotg_ep0_zlp(hsotg, true);
3132 /* In case of 3 stage Control Write with delayed
3133 * status, when Status IN transfer started
3134 * before STSPHSERCVD asserted, NAKSTS bit not
3135 * cleared by CNAK in dwc2_hsotg_start_req()
3136 * function. Clear now NAKSTS to allow complete
3139 dwc2_set_bit(hsotg, DIEPCTL(0),
3146 if (ints & DXEPINT_BACK2BACKSETUP)
3147 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3149 if (ints & DXEPINT_BNAINTR) {
3150 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3151 if (hs_ep->isochronous)
3152 dwc2_gadget_handle_isoc_bna(hs_ep);
3155 if (dir_in && !hs_ep->isochronous) {
3156 /* not sure if this is important, but we'll clear it anyway */
3157 if (ints & DXEPINT_INTKNTXFEMP) {
3158 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3162 /* this probably means something bad is happening */
3163 if (ints & DXEPINT_INTKNEPMIS) {
3164 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3168 /* FIFO has space or is empty (see GAHBCFG) */
3169 if (hsotg->dedicated_fifos &&
3170 ints & DXEPINT_TXFEMP) {
3171 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3173 if (!using_dma(hsotg))
3174 dwc2_hsotg_trytx(hsotg, hs_ep);
3180 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3181 * @hsotg: The device state.
3183 * Handle updating the device settings after the enumeration phase has
3186 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3188 u32 dsts = dwc2_readl(hsotg, DSTS);
3189 int ep0_mps = 0, ep_mps = 8;
3192 * This should signal the finish of the enumeration phase
3193 * of the USB handshaking, so we should now know what rate
3197 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3200 * note, since we're limited by the size of transfer on EP0, and
3201 * it seems IN transfers must be a even number of packets we do
3202 * not advertise a 64byte MPS on EP0.
3205 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3206 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3207 case DSTS_ENUMSPD_FS:
3208 case DSTS_ENUMSPD_FS48:
3209 hsotg->gadget.speed = USB_SPEED_FULL;
3210 ep0_mps = EP0_MPS_LIMIT;
3214 case DSTS_ENUMSPD_HS:
3215 hsotg->gadget.speed = USB_SPEED_HIGH;
3216 ep0_mps = EP0_MPS_LIMIT;
3220 case DSTS_ENUMSPD_LS:
3221 hsotg->gadget.speed = USB_SPEED_LOW;
3225 * note, we don't actually support LS in this driver at the
3226 * moment, and the documentation seems to imply that it isn't
3227 * supported by the PHYs on some of the devices.
3231 dev_info(hsotg->dev, "new device is %s\n",
3232 usb_speed_string(hsotg->gadget.speed));
3235 * we should now know the maximum packet size for an
3236 * endpoint, so set the endpoints to a default value.
3241 /* Initialize ep0 for both in and out directions */
3242 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3243 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3244 for (i = 1; i < hsotg->num_of_eps; i++) {
3245 if (hsotg->eps_in[i])
3246 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3248 if (hsotg->eps_out[i])
3249 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3254 /* ensure after enumeration our EP0 is active */
3256 dwc2_hsotg_enqueue_setup(hsotg);
3258 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3259 dwc2_readl(hsotg, DIEPCTL0),
3260 dwc2_readl(hsotg, DOEPCTL0));
3264 * kill_all_requests - remove all requests from the endpoint's queue
3265 * @hsotg: The device state.
3266 * @ep: The endpoint the requests may be on.
3267 * @result: The result code to use.
3269 * Go through the requests on the given endpoint and mark them
3270 * completed with the given result code.
3272 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3273 struct dwc2_hsotg_ep *ep,
3280 while (!list_empty(&ep->queue)) {
3281 struct dwc2_hsotg_req *req = get_ep_head(ep);
3283 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3286 if (!hsotg->dedicated_fifos)
3288 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3289 if (size < ep->fifo_size)
3290 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3294 * dwc2_hsotg_disconnect - disconnect service
3295 * @hsotg: The device state.
3297 * The device has been disconnected. Remove all current
3298 * transactions and signal the gadget driver that this
3301 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3305 if (!hsotg->connected)
3308 hsotg->connected = 0;
3309 hsotg->test_mode = 0;
3311 /* all endpoints should be shutdown */
3312 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3313 if (hsotg->eps_in[ep])
3314 kill_all_requests(hsotg, hsotg->eps_in[ep],
3316 if (hsotg->eps_out[ep])
3317 kill_all_requests(hsotg, hsotg->eps_out[ep],
3321 call_gadget(hsotg, disconnect);
3322 hsotg->lx_state = DWC2_L3;
3324 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3328 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3329 * @hsotg: The device state:
3330 * @periodic: True if this is a periodic FIFO interrupt
3332 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3334 struct dwc2_hsotg_ep *ep;
3337 /* look through for any more data to transmit */
3338 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3339 ep = index_to_ep(hsotg, epno, 1);
3347 if ((periodic && !ep->periodic) ||
3348 (!periodic && ep->periodic))
3351 ret = dwc2_hsotg_trytx(hsotg, ep);
3357 /* IRQ flags which will trigger a retry around the IRQ loop */
3358 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3362 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3364 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3365 * @hsotg: The device state
3366 * @is_usb_reset: Usb resetting flag
3368 * Issue a soft reset to the core, and await the core finishing it.
3370 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3379 /* Kill any ep0 requests as controller will be reinitialized */
3380 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3382 if (!is_usb_reset) {
3383 if (dwc2_core_reset(hsotg, true))
3386 /* all endpoints should be shutdown */
3387 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3388 if (hsotg->eps_in[ep])
3389 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3390 if (hsotg->eps_out[ep])
3391 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3396 * we must now enable ep0 ready for host detection and then
3397 * set configuration.
3400 /* keep other bits untouched (so e.g. forced modes are not lost) */
3401 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3402 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3403 usbcfg |= GUSBCFG_TOUTCAL(7);
3405 /* remove the HNP/SRP and set the PHY */
3406 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3407 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3409 dwc2_phy_init(hsotg, true);
3411 dwc2_hsotg_init_fifo(hsotg);
3414 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3416 dcfg |= DCFG_EPMISCNT(1);
3418 switch (hsotg->params.speed) {
3419 case DWC2_SPEED_PARAM_LOW:
3420 dcfg |= DCFG_DEVSPD_LS;
3422 case DWC2_SPEED_PARAM_FULL:
3423 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3424 dcfg |= DCFG_DEVSPD_FS48;
3426 dcfg |= DCFG_DEVSPD_FS;
3429 dcfg |= DCFG_DEVSPD_HS;
3432 if (hsotg->params.ipg_isoc_en)
3433 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3435 dwc2_writel(hsotg, dcfg, DCFG);
3437 /* Clear any pending OTG interrupts */
3438 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3440 /* Clear any pending interrupts */
3441 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3442 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3443 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3444 GINTSTS_USBRST | GINTSTS_RESETDET |
3445 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3446 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3447 GINTSTS_LPMTRANRCVD;
3449 if (!using_desc_dma(hsotg))
3450 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3452 if (!hsotg->params.external_id_pin_ctl)
3453 intmsk |= GINTSTS_CONIDSTSCHNG;
3455 dwc2_writel(hsotg, intmsk, GINTMSK);
3457 if (using_dma(hsotg)) {
3458 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3459 hsotg->params.ahbcfg,
3462 /* Set DDMA mode support in the core if needed */
3463 if (using_desc_dma(hsotg))
3464 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3467 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3468 (GAHBCFG_NP_TXF_EMP_LVL |
3469 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3470 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3474 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3475 * when we have no data to transfer. Otherwise we get being flooded by
3479 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3480 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3481 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3482 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3486 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3487 * DMA mode we may need this and StsPhseRcvd.
3489 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3490 DOEPMSK_STSPHSERCVDMSK) : 0) |
3491 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3495 /* Enable BNA interrupt for DDMA */
3496 if (using_desc_dma(hsotg)) {
3497 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3498 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3501 /* Enable Service Interval mode if supported */
3502 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3503 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3505 dwc2_writel(hsotg, 0, DAINTMSK);
3507 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3508 dwc2_readl(hsotg, DIEPCTL0),
3509 dwc2_readl(hsotg, DOEPCTL0));
3511 /* enable in and out endpoint interrupts */
3512 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3515 * Enable the RXFIFO when in slave mode, as this is how we collect
3516 * the data. In DMA mode, we get events from the FIFO but also
3517 * things we cannot process, so do not use it.
3519 if (!using_dma(hsotg))
3520 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3522 /* Enable interrupts for EP0 in and out */
3523 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3524 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3526 if (!is_usb_reset) {
3527 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3528 udelay(10); /* see openiboot */
3529 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3532 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3535 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3536 * writing to the EPCTL register..
3539 /* set to read 1 8byte packet */
3540 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3541 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3543 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3544 DXEPCTL_CNAK | DXEPCTL_EPENA |
3548 /* enable, but don't activate EP0in */
3549 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3550 DXEPCTL_USBACTEP, DIEPCTL0);
3552 /* clear global NAKs */
3553 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3555 val |= DCTL_SFTDISCON;
3556 dwc2_set_bit(hsotg, DCTL, val);
3558 /* configure the core to support LPM */
3559 dwc2_gadget_init_lpm(hsotg);
3561 /* program GREFCLK register if needed */
3562 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3563 dwc2_gadget_program_ref_clk(hsotg);
3565 /* must be at-least 3ms to allow bus to see disconnect */
3568 hsotg->lx_state = DWC2_L0;
3570 dwc2_hsotg_enqueue_setup(hsotg);
3572 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3573 dwc2_readl(hsotg, DIEPCTL0),
3574 dwc2_readl(hsotg, DOEPCTL0));
3577 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3579 /* set the soft-disconnect bit */
3580 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3583 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3585 /* remove the soft-disconnect and let's go */
3586 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3590 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3591 * @hsotg: The device state:
3593 * This interrupt indicates one of the following conditions occurred while
3594 * transmitting an ISOC transaction.
3595 * - Corrupted IN Token for ISOC EP.
3596 * - Packet not complete in FIFO.
3598 * The following actions will be taken:
3599 * - Determine the EP
3600 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3602 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3604 struct dwc2_hsotg_ep *hs_ep;
3609 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3611 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3613 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3614 hs_ep = hsotg->eps_in[idx];
3615 /* Proceed only unmasked ISOC EPs */
3616 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3619 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3620 if ((epctrl & DXEPCTL_EPENA) &&
3621 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3622 epctrl |= DXEPCTL_SNAK;
3623 epctrl |= DXEPCTL_EPDIS;
3624 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3628 /* Clear interrupt */
3629 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3633 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3634 * @hsotg: The device state:
3636 * This interrupt indicates one of the following conditions occurred while
3637 * transmitting an ISOC transaction.
3638 * - Corrupted OUT Token for ISOC EP.
3639 * - Packet not complete in FIFO.
3641 * The following actions will be taken:
3642 * - Determine the EP
3643 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3645 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3651 struct dwc2_hsotg_ep *hs_ep;
3654 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3656 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3657 daintmsk >>= DAINT_OUTEP_SHIFT;
3659 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3660 hs_ep = hsotg->eps_out[idx];
3661 /* Proceed only unmasked ISOC EPs */
3662 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3665 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3666 if ((epctrl & DXEPCTL_EPENA) &&
3667 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3668 /* Unmask GOUTNAKEFF interrupt */
3669 gintmsk = dwc2_readl(hsotg, GINTMSK);
3670 gintmsk |= GINTSTS_GOUTNAKEFF;
3671 dwc2_writel(hsotg, gintmsk, GINTMSK);
3673 gintsts = dwc2_readl(hsotg, GINTSTS);
3674 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3675 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3681 /* Clear interrupt */
3682 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3686 * dwc2_hsotg_irq - handle device interrupt
3687 * @irq: The IRQ number triggered
3688 * @pw: The pw value when registered the handler.
3690 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3692 struct dwc2_hsotg *hsotg = pw;
3693 int retry_count = 8;
3697 if (!dwc2_is_device_mode(hsotg))
3700 spin_lock(&hsotg->lock);
3702 gintsts = dwc2_readl(hsotg, GINTSTS);
3703 gintmsk = dwc2_readl(hsotg, GINTMSK);
3705 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3706 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3710 if (gintsts & GINTSTS_RESETDET) {
3711 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3713 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3715 /* This event must be used only if controller is suspended */
3716 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3717 dwc2_exit_partial_power_down(hsotg, 0, true);
3719 hsotg->lx_state = DWC2_L0;
3722 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3723 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3724 u32 connected = hsotg->connected;
3726 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3727 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3728 dwc2_readl(hsotg, GNPTXSTS));
3730 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3732 /* Report disconnection if it is not already done. */
3733 dwc2_hsotg_disconnect(hsotg);
3735 /* Reset device address to zero */
3736 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3738 if (usb_status & GOTGCTL_BSESVLD && connected)
3739 dwc2_hsotg_core_init_disconnected(hsotg, true);
3742 if (gintsts & GINTSTS_ENUMDONE) {
3743 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3745 dwc2_hsotg_irq_enumdone(hsotg);
3748 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3749 u32 daint = dwc2_readl(hsotg, DAINT);
3750 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3751 u32 daint_out, daint_in;
3755 daint_out = daint >> DAINT_OUTEP_SHIFT;
3756 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3758 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3760 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3761 ep++, daint_out >>= 1) {
3763 dwc2_hsotg_epint(hsotg, ep, 0);
3766 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3767 ep++, daint_in >>= 1) {
3769 dwc2_hsotg_epint(hsotg, ep, 1);
3773 /* check both FIFOs */
3775 if (gintsts & GINTSTS_NPTXFEMP) {
3776 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3779 * Disable the interrupt to stop it happening again
3780 * unless one of these endpoint routines decides that
3781 * it needs re-enabling
3784 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3785 dwc2_hsotg_irq_fifoempty(hsotg, false);
3788 if (gintsts & GINTSTS_PTXFEMP) {
3789 dev_dbg(hsotg->dev, "PTxFEmp\n");
3791 /* See note in GINTSTS_NPTxFEmp */
3793 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3794 dwc2_hsotg_irq_fifoempty(hsotg, true);
3797 if (gintsts & GINTSTS_RXFLVL) {
3799 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3800 * we need to retry dwc2_hsotg_handle_rx if this is still
3804 dwc2_hsotg_handle_rx(hsotg);
3807 if (gintsts & GINTSTS_ERLYSUSP) {
3808 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3809 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3813 * these next two seem to crop-up occasionally causing the core
3814 * to shutdown the USB transfer, so try clearing them and logging
3818 if (gintsts & GINTSTS_GOUTNAKEFF) {
3823 struct dwc2_hsotg_ep *hs_ep;
3825 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3826 daintmsk >>= DAINT_OUTEP_SHIFT;
3827 /* Mask this interrupt */
3828 gintmsk = dwc2_readl(hsotg, GINTMSK);
3829 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3830 dwc2_writel(hsotg, gintmsk, GINTMSK);
3832 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3833 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3834 hs_ep = hsotg->eps_out[idx];
3835 /* Proceed only unmasked ISOC EPs */
3836 if (BIT(idx) & ~daintmsk)
3839 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3842 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3843 epctrl |= DXEPCTL_SNAK;
3844 epctrl |= DXEPCTL_EPDIS;
3845 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3850 if (hs_ep->halted) {
3851 if (!(epctrl & DXEPCTL_EPENA))
3852 epctrl |= DXEPCTL_EPENA;
3853 epctrl |= DXEPCTL_EPDIS;
3854 epctrl |= DXEPCTL_STALL;
3855 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3859 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3862 if (gintsts & GINTSTS_GINNAKEFF) {
3863 dev_info(hsotg->dev, "GINNakEff triggered\n");
3865 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3867 dwc2_hsotg_dump(hsotg);
3870 if (gintsts & GINTSTS_INCOMPL_SOIN)
3871 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3873 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3874 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3877 * if we've had fifo events, we should try and go around the
3878 * loop again to see if there's any point in returning yet.
3881 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3884 /* Check WKUP_ALERT interrupt*/
3885 if (hsotg->params.service_interval)
3886 dwc2_gadget_wkup_alert_handler(hsotg);
3888 spin_unlock(&hsotg->lock);
3893 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3894 struct dwc2_hsotg_ep *hs_ep)
3899 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3900 DOEPCTL(hs_ep->index);
3901 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3902 DOEPINT(hs_ep->index);
3904 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3907 if (hs_ep->dir_in) {
3908 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3909 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3910 /* Wait for Nak effect */
3911 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3912 DXEPINT_INEPNAKEFF, 100))
3913 dev_warn(hsotg->dev,
3914 "%s: timeout DIEPINT.NAKEFF\n",
3917 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3918 /* Wait for Nak effect */
3919 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3920 GINTSTS_GINNAKEFF, 100))
3921 dev_warn(hsotg->dev,
3922 "%s: timeout GINTSTS.GINNAKEFF\n",
3926 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3927 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3929 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3930 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3932 if (!using_dma(hsotg)) {
3933 /* Wait for GINTSTS_RXFLVL interrupt */
3934 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3935 GINTSTS_RXFLVL, 100)) {
3936 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3940 * Pop GLOBAL OUT NAK status packet from RxFIFO
3941 * to assert GOUTNAKEFF interrupt
3943 dwc2_readl(hsotg, GRXSTSP);
3947 /* Wait for global nak to take effect */
3948 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3949 GINTSTS_GOUTNAKEFF, 100))
3950 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3955 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3957 /* Wait for ep to be disabled */
3958 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3959 dev_warn(hsotg->dev,
3960 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3962 /* Clear EPDISBLD interrupt */
3963 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3965 if (hs_ep->dir_in) {
3966 unsigned short fifo_index;
3968 if (hsotg->dedicated_fifos || hs_ep->periodic)
3969 fifo_index = hs_ep->fifo_index;
3974 dwc2_flush_tx_fifo(hsotg, fifo_index);
3976 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3977 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3978 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3981 /* Remove global NAKs */
3982 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3987 * dwc2_hsotg_ep_enable - enable the given endpoint
3988 * @ep: The USB endpint to configure
3989 * @desc: The USB endpoint descriptor to configure with.
3991 * This is called from the USB gadget code's usb_ep_enable().
3993 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3994 const struct usb_endpoint_descriptor *desc)
3996 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3997 struct dwc2_hsotg *hsotg = hs_ep->parent;
3998 unsigned long flags;
3999 unsigned int index = hs_ep->index;
4005 unsigned int dir_in;
4006 unsigned int i, val, size;
4008 unsigned char ep_type;
4012 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4013 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4014 desc->wMaxPacketSize, desc->bInterval);
4016 /* not to be called for EP0 */
4018 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4022 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4023 if (dir_in != hs_ep->dir_in) {
4024 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4028 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4029 mps = usb_endpoint_maxp(desc);
4030 mc = usb_endpoint_maxp_mult(desc);
4032 /* ISOC IN in DDMA supported bInterval up to 10 */
4033 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4034 dir_in && desc->bInterval > 10) {
4036 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4040 /* High bandwidth ISOC OUT in DDMA not supported */
4041 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4042 !dir_in && mc > 1) {
4044 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4048 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4050 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4051 epctrl = dwc2_readl(hsotg, epctrl_reg);
4053 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4054 __func__, epctrl, epctrl_reg);
4056 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4057 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4059 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4061 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4062 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4063 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4064 desc_num * sizeof(struct dwc2_dma_desc),
4065 &hs_ep->desc_list_dma, GFP_ATOMIC);
4066 if (!hs_ep->desc_list) {
4072 spin_lock_irqsave(&hsotg->lock, flags);
4074 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4075 epctrl |= DXEPCTL_MPS(mps);
4078 * mark the endpoint as active, otherwise the core may ignore
4079 * transactions entirely for this endpoint
4081 epctrl |= DXEPCTL_USBACTEP;
4083 /* update the endpoint state */
4084 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4086 /* default, set to non-periodic */
4087 hs_ep->isochronous = 0;
4088 hs_ep->periodic = 0;
4091 hs_ep->interval = desc->bInterval;
4094 case USB_ENDPOINT_XFER_ISOC:
4095 epctrl |= DXEPCTL_EPTYPE_ISO;
4096 epctrl |= DXEPCTL_SETEVENFR;
4097 hs_ep->isochronous = 1;
4098 hs_ep->interval = 1 << (desc->bInterval - 1);
4099 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4100 hs_ep->next_desc = 0;
4101 hs_ep->compl_desc = 0;
4103 hs_ep->periodic = 1;
4104 mask = dwc2_readl(hsotg, DIEPMSK);
4105 mask |= DIEPMSK_NAKMSK;
4106 dwc2_writel(hsotg, mask, DIEPMSK);
4108 epctrl |= DXEPCTL_SNAK;
4109 mask = dwc2_readl(hsotg, DOEPMSK);
4110 mask |= DOEPMSK_OUTTKNEPDISMSK;
4111 dwc2_writel(hsotg, mask, DOEPMSK);
4115 case USB_ENDPOINT_XFER_BULK:
4116 epctrl |= DXEPCTL_EPTYPE_BULK;
4119 case USB_ENDPOINT_XFER_INT:
4121 hs_ep->periodic = 1;
4123 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4124 hs_ep->interval = 1 << (desc->bInterval - 1);
4126 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4129 case USB_ENDPOINT_XFER_CONTROL:
4130 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4135 * if the hardware has dedicated fifos, we must give each IN EP
4136 * a unique tx-fifo even if it is non-periodic.
4138 if (dir_in && hsotg->dedicated_fifos) {
4139 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4141 u32 fifo_size = UINT_MAX;
4143 size = hs_ep->ep.maxpacket * hs_ep->mc;
4144 for (i = 1; i <= fifo_count; ++i) {
4145 if (hsotg->fifo_map & (1 << i))
4147 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4148 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4151 /* Search for smallest acceptable fifo */
4152 if (val < fifo_size) {
4159 "%s: No suitable fifo found\n", __func__);
4163 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4164 hsotg->fifo_map |= 1 << fifo_index;
4165 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4166 hs_ep->fifo_index = fifo_index;
4167 hs_ep->fifo_size = fifo_size;
4170 /* for non control endpoints, set PID to D0 */
4171 if (index && !hs_ep->isochronous)
4172 epctrl |= DXEPCTL_SETD0PID;
4174 /* WA for Full speed ISOC IN in DDMA mode.
4175 * By Clear NAK status of EP, core will send ZLP
4176 * to IN token and assert NAK interrupt relying
4177 * on TxFIFO status only
4180 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4181 hs_ep->isochronous && dir_in) {
4182 /* The WA applies only to core versions from 2.72a
4183 * to 4.00a (including both). Also for FS_IOT_1.00a
4186 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4188 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4189 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4190 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4191 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4192 epctrl |= DXEPCTL_CNAK;
4195 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4198 dwc2_writel(hsotg, epctrl, epctrl_reg);
4199 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4200 __func__, dwc2_readl(hsotg, epctrl_reg));
4202 /* enable the endpoint interrupt */
4203 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4206 spin_unlock_irqrestore(&hsotg->lock, flags);
4209 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4210 dmam_free_coherent(hsotg->dev, desc_num *
4211 sizeof(struct dwc2_dma_desc),
4212 hs_ep->desc_list, hs_ep->desc_list_dma);
4213 hs_ep->desc_list = NULL;
4220 * dwc2_hsotg_ep_disable - disable given endpoint
4221 * @ep: The endpoint to disable.
4223 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4225 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4226 struct dwc2_hsotg *hsotg = hs_ep->parent;
4227 int dir_in = hs_ep->dir_in;
4228 int index = hs_ep->index;
4232 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4234 if (ep == &hsotg->eps_out[0]->ep) {
4235 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4239 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4240 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4244 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4246 ctrl = dwc2_readl(hsotg, epctrl_reg);
4248 if (ctrl & DXEPCTL_EPENA)
4249 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4251 ctrl &= ~DXEPCTL_EPENA;
4252 ctrl &= ~DXEPCTL_USBACTEP;
4253 ctrl |= DXEPCTL_SNAK;
4255 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4256 dwc2_writel(hsotg, ctrl, epctrl_reg);
4258 /* disable endpoint interrupts */
4259 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4261 /* terminate all requests with shutdown */
4262 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4264 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4265 hs_ep->fifo_index = 0;
4266 hs_ep->fifo_size = 0;
4271 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4273 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4274 struct dwc2_hsotg *hsotg = hs_ep->parent;
4275 unsigned long flags;
4278 spin_lock_irqsave(&hsotg->lock, flags);
4279 ret = dwc2_hsotg_ep_disable(ep);
4280 spin_unlock_irqrestore(&hsotg->lock, flags);
4285 * on_list - check request is on the given endpoint
4286 * @ep: The endpoint to check.
4287 * @test: The request to test if it is on the endpoint.
4289 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4291 struct dwc2_hsotg_req *req, *treq;
4293 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4302 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4303 * @ep: The endpoint to dequeue.
4304 * @req: The request to be removed from a queue.
4306 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4308 struct dwc2_hsotg_req *hs_req = our_req(req);
4309 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4310 struct dwc2_hsotg *hs = hs_ep->parent;
4311 unsigned long flags;
4313 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4315 spin_lock_irqsave(&hs->lock, flags);
4317 if (!on_list(hs_ep, hs_req)) {
4318 spin_unlock_irqrestore(&hs->lock, flags);
4322 /* Dequeue already started request */
4323 if (req == &hs_ep->req->req)
4324 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4326 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4327 spin_unlock_irqrestore(&hs->lock, flags);
4333 * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
4334 * @ep: The endpoint to be wedged.
4337 static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
4339 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4340 struct dwc2_hsotg *hs = hs_ep->parent;
4342 unsigned long flags;
4345 spin_lock_irqsave(&hs->lock, flags);
4347 ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
4348 spin_unlock_irqrestore(&hs->lock, flags);
4354 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4355 * @ep: The endpoint to set halt.
4356 * @value: Set or unset the halt.
4357 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4358 * the endpoint is busy processing requests.
4360 * We need to stall the endpoint immediately if request comes from set_feature
4361 * protocol command handler.
4363 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4365 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4366 struct dwc2_hsotg *hs = hs_ep->parent;
4367 int index = hs_ep->index;
4372 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4376 dwc2_hsotg_stall_ep0(hs);
4379 "%s: can't clear halt on ep0\n", __func__);
4383 if (hs_ep->isochronous) {
4384 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4388 if (!now && value && !list_empty(&hs_ep->queue)) {
4389 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4394 if (hs_ep->dir_in) {
4395 epreg = DIEPCTL(index);
4396 epctl = dwc2_readl(hs, epreg);
4399 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4400 if (epctl & DXEPCTL_EPENA)
4401 epctl |= DXEPCTL_EPDIS;
4403 epctl &= ~DXEPCTL_STALL;
4405 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4406 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4407 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4408 epctl |= DXEPCTL_SETD0PID;
4410 dwc2_writel(hs, epctl, epreg);
4412 epreg = DOEPCTL(index);
4413 epctl = dwc2_readl(hs, epreg);
4416 /* Unmask GOUTNAKEFF interrupt */
4417 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4419 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4420 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4421 // STALL bit will be set in GOUTNAKEFF interrupt handler
4423 epctl &= ~DXEPCTL_STALL;
4425 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4426 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4427 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4428 epctl |= DXEPCTL_SETD0PID;
4429 dwc2_writel(hs, epctl, epreg);
4433 hs_ep->halted = value;
4438 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4439 * @ep: The endpoint to set halt.
4440 * @value: Set or unset the halt.
4442 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4444 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4445 struct dwc2_hsotg *hs = hs_ep->parent;
4446 unsigned long flags;
4449 spin_lock_irqsave(&hs->lock, flags);
4450 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4451 spin_unlock_irqrestore(&hs->lock, flags);
4456 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4457 .enable = dwc2_hsotg_ep_enable,
4458 .disable = dwc2_hsotg_ep_disable_lock,
4459 .alloc_request = dwc2_hsotg_ep_alloc_request,
4460 .free_request = dwc2_hsotg_ep_free_request,
4461 .queue = dwc2_hsotg_ep_queue_lock,
4462 .dequeue = dwc2_hsotg_ep_dequeue,
4463 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4464 .set_wedge = dwc2_gadget_ep_set_wedge,
4465 /* note, don't believe we have any call for the fifo routines */
4469 * dwc2_hsotg_init - initialize the usb core
4470 * @hsotg: The driver state
4472 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4474 /* unmask subset of endpoint interrupts */
4476 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4477 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4480 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4481 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4484 dwc2_writel(hsotg, 0, DAINTMSK);
4486 /* Be in disconnected state until gadget is registered */
4487 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4491 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4492 dwc2_readl(hsotg, GRXFSIZ),
4493 dwc2_readl(hsotg, GNPTXFSIZ));
4495 dwc2_hsotg_init_fifo(hsotg);
4497 if (using_dma(hsotg))
4498 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4502 * dwc2_hsotg_udc_start - prepare the udc for work
4503 * @gadget: The usb gadget state
4504 * @driver: The usb gadget driver
4506 * Perform initialization to prepare udc device and driver
4509 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4510 struct usb_gadget_driver *driver)
4512 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4513 unsigned long flags;
4517 pr_err("%s: called with no device\n", __func__);
4522 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4526 if (driver->max_speed < USB_SPEED_FULL)
4527 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4529 if (!driver->setup) {
4530 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4534 WARN_ON(hsotg->driver);
4536 driver->driver.bus = NULL;
4537 hsotg->driver = driver;
4538 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4539 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4541 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4542 ret = dwc2_lowlevel_hw_enable(hsotg);
4547 if (!IS_ERR_OR_NULL(hsotg->uphy))
4548 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4550 spin_lock_irqsave(&hsotg->lock, flags);
4551 if (dwc2_hw_is_device(hsotg)) {
4552 dwc2_hsotg_init(hsotg);
4553 dwc2_hsotg_core_init_disconnected(hsotg, false);
4557 spin_unlock_irqrestore(&hsotg->lock, flags);
4559 gadget->sg_supported = using_desc_dma(hsotg);
4560 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4565 hsotg->driver = NULL;
4570 * dwc2_hsotg_udc_stop - stop the udc
4571 * @gadget: The usb gadget state
4573 * Stop udc hw block and stay tunned for future transmissions
4575 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4577 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4578 unsigned long flags;
4584 /* all endpoints should be shutdown */
4585 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4586 if (hsotg->eps_in[ep])
4587 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4588 if (hsotg->eps_out[ep])
4589 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4592 spin_lock_irqsave(&hsotg->lock, flags);
4594 hsotg->driver = NULL;
4595 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4598 spin_unlock_irqrestore(&hsotg->lock, flags);
4600 if (!IS_ERR_OR_NULL(hsotg->uphy))
4601 otg_set_peripheral(hsotg->uphy->otg, NULL);
4603 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4604 dwc2_lowlevel_hw_disable(hsotg);
4610 * dwc2_hsotg_gadget_getframe - read the frame number
4611 * @gadget: The usb gadget state
4613 * Read the {micro} frame number
4615 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4617 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4621 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4622 * @gadget: The usb gadget state
4623 * @is_selfpowered: Whether the device is self-powered
4625 * Set if the device is self or bus powered.
4627 static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4630 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4631 unsigned long flags;
4633 spin_lock_irqsave(&hsotg->lock, flags);
4634 gadget->is_selfpowered = !!is_selfpowered;
4635 spin_unlock_irqrestore(&hsotg->lock, flags);
4641 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4642 * @gadget: The usb gadget state
4643 * @is_on: Current state of the USB PHY
4645 * Connect/Disconnect the USB PHY pullup
4647 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4649 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4650 unsigned long flags;
4652 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4655 /* Don't modify pullup state while in host mode */
4656 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4657 hsotg->enabled = is_on;
4661 spin_lock_irqsave(&hsotg->lock, flags);
4664 dwc2_hsotg_core_init_disconnected(hsotg, false);
4665 /* Enable ACG feature in device mode,if supported */
4666 dwc2_enable_acg(hsotg);
4667 dwc2_hsotg_core_connect(hsotg);
4669 dwc2_hsotg_core_disconnect(hsotg);
4670 dwc2_hsotg_disconnect(hsotg);
4674 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4675 spin_unlock_irqrestore(&hsotg->lock, flags);
4680 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4682 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4683 unsigned long flags;
4685 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4686 spin_lock_irqsave(&hsotg->lock, flags);
4689 * If controller is in partial power down state, it must exit from
4690 * that state before being initialized / de-initialized
4692 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4694 * No need to check the return value as
4695 * registers are not being restored.
4697 dwc2_exit_partial_power_down(hsotg, 0, false);
4700 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4702 dwc2_hsotg_core_init_disconnected(hsotg, false);
4703 if (hsotg->enabled) {
4704 /* Enable ACG feature in device mode,if supported */
4705 dwc2_enable_acg(hsotg);
4706 dwc2_hsotg_core_connect(hsotg);
4709 dwc2_hsotg_core_disconnect(hsotg);
4710 dwc2_hsotg_disconnect(hsotg);
4713 spin_unlock_irqrestore(&hsotg->lock, flags);
4718 * dwc2_hsotg_vbus_draw - report bMaxPower field
4719 * @gadget: The usb gadget state
4720 * @mA: Amount of current
4722 * Report how much power the device may consume to the phy.
4724 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4726 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4728 if (IS_ERR_OR_NULL(hsotg->uphy))
4730 return usb_phy_set_power(hsotg->uphy, mA);
4733 static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
4735 struct dwc2_hsotg *hsotg = to_hsotg(g);
4736 unsigned long flags;
4738 spin_lock_irqsave(&hsotg->lock, flags);
4740 case USB_SPEED_HIGH:
4741 hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
4743 case USB_SPEED_FULL:
4744 hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
4747 hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
4750 dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
4752 spin_unlock_irqrestore(&hsotg->lock, flags);
4755 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4756 .get_frame = dwc2_hsotg_gadget_getframe,
4757 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4758 .udc_start = dwc2_hsotg_udc_start,
4759 .udc_stop = dwc2_hsotg_udc_stop,
4760 .pullup = dwc2_hsotg_pullup,
4761 .udc_set_speed = dwc2_gadget_set_speed,
4762 .vbus_session = dwc2_hsotg_vbus_session,
4763 .vbus_draw = dwc2_hsotg_vbus_draw,
4767 * dwc2_hsotg_initep - initialise a single endpoint
4768 * @hsotg: The device state.
4769 * @hs_ep: The endpoint to be initialised.
4770 * @epnum: The endpoint number
4771 * @dir_in: True if direction is in.
4773 * Initialise the given endpoint (as part of the probe and device state
4774 * creation) to give to the gadget driver. Setup the endpoint name, any
4775 * direction information and other state that may be required.
4777 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4778 struct dwc2_hsotg_ep *hs_ep,
4791 hs_ep->dir_in = dir_in;
4792 hs_ep->index = epnum;
4794 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4796 INIT_LIST_HEAD(&hs_ep->queue);
4797 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4799 /* add to the list of endpoints known by the gadget driver */
4801 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4803 hs_ep->parent = hsotg;
4804 hs_ep->ep.name = hs_ep->name;
4806 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4807 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4809 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4810 epnum ? 1024 : EP0_MPS_LIMIT);
4811 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4814 hs_ep->ep.caps.type_control = true;
4816 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4817 hs_ep->ep.caps.type_iso = true;
4818 hs_ep->ep.caps.type_bulk = true;
4820 hs_ep->ep.caps.type_int = true;
4824 hs_ep->ep.caps.dir_in = true;
4826 hs_ep->ep.caps.dir_out = true;
4829 * if we're using dma, we need to set the next-endpoint pointer
4830 * to be something valid.
4833 if (using_dma(hsotg)) {
4834 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4837 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4839 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4844 * dwc2_hsotg_hw_cfg - read HW configuration registers
4845 * @hsotg: Programming view of the DWC_otg controller
4847 * Read the USB core HW configuration registers
4849 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4855 /* check hardware configuration */
4857 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4860 hsotg->num_of_eps++;
4862 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4863 sizeof(struct dwc2_hsotg_ep),
4865 if (!hsotg->eps_in[0])
4867 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4868 hsotg->eps_out[0] = hsotg->eps_in[0];
4870 cfg = hsotg->hw_params.dev_ep_dirs;
4871 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4873 /* Direction in or both */
4874 if (!(ep_type & 2)) {
4875 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4876 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4877 if (!hsotg->eps_in[i])
4880 /* Direction out or both */
4881 if (!(ep_type & 1)) {
4882 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4883 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4884 if (!hsotg->eps_out[i])
4889 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4890 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4892 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4894 hsotg->dedicated_fifos ? "dedicated" : "shared",
4900 * dwc2_hsotg_dump - dump state of the udc
4901 * @hsotg: Programming view of the DWC_otg controller
4904 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4907 struct device *dev = hsotg->dev;
4911 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4912 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4913 dwc2_readl(hsotg, DIEPMSK));
4915 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4916 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4918 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4919 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4921 /* show periodic fifo settings */
4923 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4924 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4925 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4926 val >> FIFOSIZE_DEPTH_SHIFT,
4927 val & FIFOSIZE_STARTADDR_MASK);
4930 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4932 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4933 dwc2_readl(hsotg, DIEPCTL(idx)),
4934 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4935 dwc2_readl(hsotg, DIEPDMA(idx)));
4937 val = dwc2_readl(hsotg, DOEPCTL(idx));
4939 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4940 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4941 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4942 dwc2_readl(hsotg, DOEPDMA(idx)));
4945 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4946 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4951 * dwc2_gadget_init - init function for gadget
4952 * @hsotg: Programming view of the DWC_otg controller
4955 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4957 struct device *dev = hsotg->dev;
4961 /* Dump fifo information */
4962 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4963 hsotg->params.g_np_tx_fifo_size);
4964 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4966 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4967 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4968 hsotg->gadget.name = dev_name(dev);
4969 hsotg->remote_wakeup_allowed = 0;
4971 if (hsotg->params.lpm)
4972 hsotg->gadget.lpm_capable = true;
4974 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4975 hsotg->gadget.is_otg = 1;
4976 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4977 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4979 ret = dwc2_hsotg_hw_cfg(hsotg);
4981 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4985 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4986 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4987 if (!hsotg->ctrl_buff)
4990 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4991 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4992 if (!hsotg->ep0_buff)
4995 if (using_desc_dma(hsotg)) {
4996 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
5001 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
5002 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
5004 dev_err(dev, "cannot claim IRQ for gadget\n");
5008 /* hsotg->num_of_eps holds number of EPs other than ep0 */
5010 if (hsotg->num_of_eps == 0) {
5011 dev_err(dev, "wrong number of EPs (zero)\n");
5015 /* setup endpoint information */
5017 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
5018 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
5020 /* allocate EP0 request */
5022 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
5024 if (!hsotg->ctrl_req) {
5025 dev_err(dev, "failed to allocate ctrl req\n");
5029 /* initialise the endpoints now the core has been initialised */
5030 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
5031 if (hsotg->eps_in[epnum])
5032 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
5034 if (hsotg->eps_out[epnum])
5035 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5039 dwc2_hsotg_dump(hsotg);
5045 * dwc2_hsotg_remove - remove function for hsotg driver
5046 * @hsotg: Programming view of the DWC_otg controller
5049 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5051 usb_del_gadget_udc(&hsotg->gadget);
5052 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5057 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5059 unsigned long flags;
5061 if (hsotg->lx_state != DWC2_L0)
5064 if (hsotg->driver) {
5067 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5068 hsotg->driver->driver.name);
5070 spin_lock_irqsave(&hsotg->lock, flags);
5072 dwc2_hsotg_core_disconnect(hsotg);
5073 dwc2_hsotg_disconnect(hsotg);
5074 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5075 spin_unlock_irqrestore(&hsotg->lock, flags);
5077 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
5078 if (hsotg->eps_in[ep])
5079 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5080 if (hsotg->eps_out[ep])
5081 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5088 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5090 unsigned long flags;
5092 if (hsotg->lx_state == DWC2_L2)
5095 if (hsotg->driver) {
5096 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5097 hsotg->driver->driver.name);
5099 spin_lock_irqsave(&hsotg->lock, flags);
5100 dwc2_hsotg_core_init_disconnected(hsotg, false);
5101 if (hsotg->enabled) {
5102 /* Enable ACG feature in device mode,if supported */
5103 dwc2_enable_acg(hsotg);
5104 dwc2_hsotg_core_connect(hsotg);
5106 spin_unlock_irqrestore(&hsotg->lock, flags);
5113 * dwc2_backup_device_registers() - Backup controller device registers.
5114 * When suspending usb bus, registers needs to be backuped
5115 * if controller power is disabled once suspended.
5117 * @hsotg: Programming view of the DWC_otg controller
5119 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5121 struct dwc2_dregs_backup *dr;
5124 dev_dbg(hsotg->dev, "%s\n", __func__);
5126 /* Backup dev regs */
5127 dr = &hsotg->dr_backup;
5129 dr->dcfg = dwc2_readl(hsotg, DCFG);
5130 dr->dctl = dwc2_readl(hsotg, DCTL);
5131 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5132 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5133 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5135 for (i = 0; i < hsotg->num_of_eps; i++) {
5137 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5139 /* Ensure DATA PID is correctly configured */
5140 if (dr->diepctl[i] & DXEPCTL_DPID)
5141 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5143 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5145 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5146 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5148 /* Backup OUT EPs */
5149 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5151 /* Ensure DATA PID is correctly configured */
5152 if (dr->doepctl[i] & DXEPCTL_DPID)
5153 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5155 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5157 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5158 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5159 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5166 * dwc2_restore_device_registers() - Restore controller device registers.
5167 * When resuming usb bus, device registers needs to be restored
5168 * if controller power were disabled.
5170 * @hsotg: Programming view of the DWC_otg controller
5171 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5173 * Return: 0 if successful, negative error code otherwise
5175 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5177 struct dwc2_dregs_backup *dr;
5180 dev_dbg(hsotg->dev, "%s\n", __func__);
5182 /* Restore dev regs */
5183 dr = &hsotg->dr_backup;
5185 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5192 dwc2_writel(hsotg, dr->dctl, DCTL);
5194 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5195 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5196 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5198 for (i = 0; i < hsotg->num_of_eps; i++) {
5199 /* Restore IN EPs */
5200 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5201 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5202 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5203 /** WA for enabled EPx's IN in DDMA mode. On entering to
5204 * hibernation wrong value read and saved from DIEPDMAx,
5205 * as result BNA interrupt asserted on hibernation exit
5206 * by restoring from saved area.
5208 if (hsotg->params.g_dma_desc &&
5209 (dr->diepctl[i] & DXEPCTL_EPENA))
5210 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5211 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5212 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5213 /* Restore OUT EPs */
5214 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5215 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5216 * hibernation wrong value read and saved from DOEPDMAx,
5217 * as result BNA interrupt asserted on hibernation exit
5218 * by restoring from saved area.
5220 if (hsotg->params.g_dma_desc &&
5221 (dr->doepctl[i] & DXEPCTL_EPENA))
5222 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5223 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5224 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5231 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5233 * @hsotg: Programming view of DWC_otg controller
5236 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5240 if (!hsotg->params.lpm)
5243 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5244 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5245 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5246 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5247 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5248 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5249 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5250 dwc2_writel(hsotg, val, GLPMCFG);
5251 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5253 /* Unmask WKUP_ALERT Interrupt */
5254 if (hsotg->params.service_interval)
5255 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5259 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5261 * @hsotg: Programming view of DWC_otg controller
5264 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5268 val |= GREFCLK_REF_CLK_MODE;
5269 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5270 val |= hsotg->params.sof_cnt_wkup_alert <<
5271 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5273 dwc2_writel(hsotg, val, GREFCLK);
5274 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5278 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5280 * @hsotg: Programming view of the DWC_otg controller
5282 * Return non-zero if failed to enter to hibernation.
5284 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5289 /* Change to L2(suspend) state */
5290 hsotg->lx_state = DWC2_L2;
5291 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5292 ret = dwc2_backup_global_registers(hsotg);
5294 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5298 ret = dwc2_backup_device_registers(hsotg);
5300 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5305 gpwrdn = GPWRDN_PWRDNRSTN;
5306 gpwrdn |= GPWRDN_PMUACTV;
5307 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5310 /* Set flag to indicate that we are in hibernation */
5311 hsotg->hibernated = 1;
5313 /* Enable interrupts from wake up logic */
5314 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5315 gpwrdn |= GPWRDN_PMUINTSEL;
5316 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5319 /* Unmask device mode interrupts in GPWRDN */
5320 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5321 gpwrdn |= GPWRDN_RST_DET_MSK;
5322 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5323 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5324 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5327 /* Enable Power Down Clamp */
5328 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5329 gpwrdn |= GPWRDN_PWRDNCLMP;
5330 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5333 /* Switch off VDD */
5334 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5335 gpwrdn |= GPWRDN_PWRDNSWTCH;
5336 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5339 /* Save gpwrdn register for further usage if stschng interrupt */
5340 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5341 dev_dbg(hsotg->dev, "Hibernation completed\n");
5347 * dwc2_gadget_exit_hibernation()
5348 * This function is for exiting from Device mode hibernation by host initiated
5349 * resume/reset and device initiated remote-wakeup.
5351 * @hsotg: Programming view of the DWC_otg controller
5352 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5353 * @reset: indicates whether resume is initiated by Reset.
5355 * Return non-zero if failed to exit from hibernation.
5357 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5358 int rem_wakeup, int reset)
5364 struct dwc2_gregs_backup *gr;
5365 struct dwc2_dregs_backup *dr;
5367 gr = &hsotg->gr_backup;
5368 dr = &hsotg->dr_backup;
5370 if (!hsotg->hibernated) {
5371 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5375 "%s: called with rem_wakeup = %d reset = %d\n",
5376 __func__, rem_wakeup, reset);
5378 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5381 /* Clear all pending interupts */
5382 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5385 /* De-assert Restore */
5386 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5387 gpwrdn &= ~GPWRDN_RESTORE;
5388 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5392 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5393 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5394 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5397 /* Restore GUSBCFG, DCFG and DCTL */
5398 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5399 dwc2_writel(hsotg, dr->dcfg, DCFG);
5400 dwc2_writel(hsotg, dr->dctl, DCTL);
5402 /* On USB Reset, reset device address to zero */
5404 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5406 /* De-assert Wakeup Logic */
5407 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5408 gpwrdn &= ~GPWRDN_PMUACTV;
5409 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5413 /* Start Remote Wakeup Signaling */
5414 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5417 /* Set Device programming done bit */
5418 dctl = dwc2_readl(hsotg, DCTL);
5419 dctl |= DCTL_PWRONPRGDONE;
5420 dwc2_writel(hsotg, dctl, DCTL);
5422 /* Wait for interrupts which must be cleared */
5424 /* Clear all pending interupts */
5425 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5427 /* Restore global registers */
5428 ret = dwc2_restore_global_registers(hsotg);
5430 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5435 /* Restore device registers */
5436 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5438 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5445 dctl = dwc2_readl(hsotg, DCTL);
5446 dctl &= ~DCTL_RMTWKUPSIG;
5447 dwc2_writel(hsotg, dctl, DCTL);
5450 hsotg->hibernated = 0;
5451 hsotg->lx_state = DWC2_L0;
5452 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5458 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5461 * @hsotg: Programming view of the DWC_otg controller
5463 * Return: non-zero if failed to enter device partial power down.
5465 * This function is for entering device mode partial power down.
5467 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5472 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5474 /* Backup all registers */
5475 ret = dwc2_backup_global_registers(hsotg);
5477 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5482 ret = dwc2_backup_device_registers(hsotg);
5484 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5490 * Clear any pending interrupts since dwc2 will not be able to
5491 * clear them after entering partial_power_down.
5493 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5495 /* Put the controller in low power state */
5496 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5498 pcgcctl |= PCGCTL_PWRCLMP;
5499 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5502 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5503 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5506 pcgcctl |= PCGCTL_STOPPCLK;
5507 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5509 /* Set in_ppd flag to 1 as here core enters suspend. */
5511 hsotg->lx_state = DWC2_L2;
5513 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5519 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5522 * @hsotg: Programming view of the DWC_otg controller
5523 * @restore: indicates whether need to restore the registers or not.
5525 * Return: non-zero if failed to exit device partial power down.
5527 * This function is for exiting from device mode partial power down.
5529 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5534 struct dwc2_dregs_backup *dr;
5537 dr = &hsotg->dr_backup;
5539 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5541 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5542 pcgcctl &= ~PCGCTL_STOPPCLK;
5543 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5545 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5546 pcgcctl &= ~PCGCTL_PWRCLMP;
5547 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5549 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5550 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5551 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5555 ret = dwc2_restore_global_registers(hsotg);
5557 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5562 dwc2_writel(hsotg, dr->dcfg, DCFG);
5564 ret = dwc2_restore_device_registers(hsotg, 0);
5566 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5572 /* Set the Power-On Programming done bit */
5573 dctl = dwc2_readl(hsotg, DCTL);
5574 dctl |= DCTL_PWRONPRGDONE;
5575 dwc2_writel(hsotg, dctl, DCTL);
5577 /* Set in_ppd flag to 0 as here core exits from suspend. */
5579 hsotg->lx_state = DWC2_L0;
5581 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5586 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5588 * @hsotg: Programming view of the DWC_otg controller
5590 * Return: non-zero if failed to enter device partial power down.
5592 * This function is for entering device mode clock gating.
5594 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5598 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5600 /* Set the Phy Clock bit as suspend is received. */
5601 pcgctl = dwc2_readl(hsotg, PCGCTL);
5602 pcgctl |= PCGCTL_STOPPCLK;
5603 dwc2_writel(hsotg, pcgctl, PCGCTL);
5606 /* Set the Gate hclk as suspend is received. */
5607 pcgctl = dwc2_readl(hsotg, PCGCTL);
5608 pcgctl |= PCGCTL_GATEHCLK;
5609 dwc2_writel(hsotg, pcgctl, PCGCTL);
5612 hsotg->lx_state = DWC2_L2;
5613 hsotg->bus_suspended = true;
5617 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5619 * @hsotg: Programming view of the DWC_otg controller
5620 * @rem_wakeup: indicates whether remote wake up is enabled.
5622 * This function is for exiting from device mode clock gating.
5624 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5629 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5631 /* Clear the Gate hclk. */
5632 pcgctl = dwc2_readl(hsotg, PCGCTL);
5633 pcgctl &= ~PCGCTL_GATEHCLK;
5634 dwc2_writel(hsotg, pcgctl, PCGCTL);
5637 /* Phy Clock bit. */
5638 pcgctl = dwc2_readl(hsotg, PCGCTL);
5639 pcgctl &= ~PCGCTL_STOPPCLK;
5640 dwc2_writel(hsotg, pcgctl, PCGCTL);
5644 /* Set Remote Wakeup Signaling */
5645 dctl = dwc2_readl(hsotg, DCTL);
5646 dctl |= DCTL_RMTWKUPSIG;
5647 dwc2_writel(hsotg, dctl, DCTL);
5650 /* Change to L0 state */
5651 call_gadget(hsotg, resume);
5652 hsotg->lx_state = DWC2_L0;
5653 hsotg->bus_suspended = false;