1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core_intr.c - DesignWare HS OTG Controller common interrupt handling
5 * Copyright (C) 2004-2013 Synopsys, Inc.
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20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * This file contains the common interrupt handlers
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/dma-mapping.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
57 static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
59 switch (hsotg->op_state) {
60 case OTG_STATE_A_HOST:
62 case OTG_STATE_A_SUSPEND:
64 case OTG_STATE_A_PERIPHERAL:
65 return "a_peripheral";
66 case OTG_STATE_B_PERIPHERAL:
67 return "b_peripheral";
68 case OTG_STATE_B_HOST:
76 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
77 * When the PRTINT interrupt fires, there are certain status bits in the Host
78 * Port that needs to get cleared.
80 * @hsotg: Programming view of DWC_otg controller
82 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
84 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
86 if (hprt0 & HPRT0_ENACHG) {
88 dwc2_writel(hsotg, hprt0, HPRT0);
93 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
95 * @hsotg: Programming view of DWC_otg controller
97 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
100 dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
102 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
103 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
107 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
108 * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
110 * @hsotg: Programming view of DWC_otg controller
112 static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
118 gotgint = dwc2_readl(hsotg, GOTGINT);
119 gotgctl = dwc2_readl(hsotg, GOTGCTL);
120 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
121 dwc2_op_state_str(hsotg));
123 if (gotgint & GOTGINT_SES_END_DET) {
125 " ++OTG Interrupt: Session End Detected++ (%s)\n",
126 dwc2_op_state_str(hsotg));
127 gotgctl = dwc2_readl(hsotg, GOTGCTL);
129 if (dwc2_is_device_mode(hsotg))
130 dwc2_hsotg_disconnect(hsotg);
132 if (hsotg->op_state == OTG_STATE_B_HOST) {
133 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
136 * If not B_HOST and Device HNP still set, HNP did
139 if (gotgctl & GOTGCTL_DEVHNPEN) {
140 dev_dbg(hsotg->dev, "Session End Detected\n");
142 "Device Not Connected/Responding!\n");
146 * If Session End Detected the B-Cable has been
149 /* Reset to a clean state */
150 hsotg->lx_state = DWC2_L0;
153 gotgctl = dwc2_readl(hsotg, GOTGCTL);
154 gotgctl &= ~GOTGCTL_DEVHNPEN;
155 dwc2_writel(hsotg, gotgctl, GOTGCTL);
158 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
160 " ++OTG Interrupt: Session Request Success Status Change++\n");
161 gotgctl = dwc2_readl(hsotg, GOTGCTL);
162 if (gotgctl & GOTGCTL_SESREQSCS) {
163 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
164 hsotg->params.i2c_enable) {
165 hsotg->srp_success = 1;
167 /* Clear Session Request */
168 gotgctl = dwc2_readl(hsotg, GOTGCTL);
169 gotgctl &= ~GOTGCTL_SESREQ;
170 dwc2_writel(hsotg, gotgctl, GOTGCTL);
175 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
177 * Print statements during the HNP interrupt handling
178 * can cause it to fail
180 gotgctl = dwc2_readl(hsotg, GOTGCTL);
182 * WA for 3.00a- HW is not setting cur_mode, even sometimes
185 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
187 if (gotgctl & GOTGCTL_HSTNEGSCS) {
188 if (dwc2_is_host_mode(hsotg)) {
189 hsotg->op_state = OTG_STATE_B_HOST;
191 * Need to disable SOF interrupt immediately.
192 * When switching from device to host, the PCD
193 * interrupt handler won't handle the interrupt
194 * if host mode is already set. The HCD
195 * interrupt handler won't get called if the
196 * HCD state is HALT. This means that the
197 * interrupt does not get handled and Linux
200 gintmsk = dwc2_readl(hsotg, GINTMSK);
201 gintmsk &= ~GINTSTS_SOF;
202 dwc2_writel(hsotg, gintmsk, GINTMSK);
205 * Call callback function with spin lock
208 spin_unlock(&hsotg->lock);
210 /* Initialize the Core for Host mode */
211 dwc2_hcd_start(hsotg);
212 spin_lock(&hsotg->lock);
213 hsotg->op_state = OTG_STATE_B_HOST;
216 gotgctl = dwc2_readl(hsotg, GOTGCTL);
217 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
218 dwc2_writel(hsotg, gotgctl, GOTGCTL);
219 dev_dbg(hsotg->dev, "HNP Failed\n");
221 "Device Not Connected/Responding\n");
225 if (gotgint & GOTGINT_HST_NEG_DET) {
227 * The disconnect interrupt is set at the same time as
228 * Host Negotiation Detected. During the mode switch all
229 * interrupts are cleared so the disconnect interrupt
230 * handler will not get executed.
233 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
234 (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
235 if (dwc2_is_device_mode(hsotg)) {
236 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
238 spin_unlock(&hsotg->lock);
239 dwc2_hcd_disconnect(hsotg, false);
240 spin_lock(&hsotg->lock);
241 hsotg->op_state = OTG_STATE_A_PERIPHERAL;
243 /* Need to disable SOF interrupt immediately */
244 gintmsk = dwc2_readl(hsotg, GINTMSK);
245 gintmsk &= ~GINTSTS_SOF;
246 dwc2_writel(hsotg, gintmsk, GINTMSK);
247 spin_unlock(&hsotg->lock);
248 dwc2_hcd_start(hsotg);
249 spin_lock(&hsotg->lock);
250 hsotg->op_state = OTG_STATE_A_HOST;
254 if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
256 " ++OTG Interrupt: A-Device Timeout Change++\n");
257 if (gotgint & GOTGINT_DBNCE_DONE)
258 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
261 dwc2_writel(hsotg, gotgint, GOTGINT);
265 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
268 * @hsotg: Programming view of DWC_otg controller
270 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
271 * Device to Host Mode transition or a Host to Device Mode transition. This only
272 * occurs when the cable is connected/removed from the PHY connector.
274 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
278 /* Clear interrupt */
279 dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
281 /* Need to disable SOF interrupt immediately */
282 gintmsk = dwc2_readl(hsotg, GINTMSK);
283 gintmsk &= ~GINTSTS_SOF;
284 dwc2_writel(hsotg, gintmsk, GINTMSK);
286 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
287 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
290 * Need to schedule a work, as there are possible DELAY function calls.
293 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
297 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
298 * initiating the Session Request Protocol to request the host to turn on bus
299 * power so a new session can begin
301 * @hsotg: Programming view of DWC_otg controller
303 * This handler responds by turning on bus power. If the DWC_otg controller is
304 * in low power mode, this handler brings the controller out of low power mode
305 * before turning on bus power.
307 static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
312 /* Clear interrupt */
313 dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
315 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
318 if (dwc2_is_device_mode(hsotg)) {
319 if (hsotg->lx_state == DWC2_L2) {
321 ret = dwc2_exit_partial_power_down(hsotg, 0,
325 "exit power_down failed\n");
328 /* Exit gadget mode clock gating. */
329 if (hsotg->params.power_down ==
330 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
331 dwc2_gadget_exit_clock_gating(hsotg, 0);
335 * Report disconnect if there is any previous session
338 dwc2_hsotg_disconnect(hsotg);
340 /* Turn on the port power bit. */
341 hprt0 = dwc2_read_hprt0(hsotg);
343 dwc2_writel(hsotg, hprt0, HPRT0);
344 /* Connect hcd after port power is set. */
345 dwc2_hcd_connect(hsotg);
350 * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state
352 * @hsotg: Programming view of DWC_otg controller
355 static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
360 if (hsotg->lx_state != DWC2_L1) {
361 dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n");
365 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
366 if (dwc2_is_device_mode(hsotg)) {
367 dev_dbg(hsotg->dev, "Exit from L1 state\n");
368 glpmcfg &= ~GLPMCFG_ENBLSLPM;
369 glpmcfg &= ~GLPMCFG_HIRD_THRES_EN;
370 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
373 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
375 if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK |
376 GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS)))
383 dev_err(hsotg->dev, "Failed to exit L1 sleep state in 200us.\n");
386 dwc2_gadget_init_lpm(hsotg);
389 dev_err(hsotg->dev, "Host side LPM is not supported.\n");
393 /* Change to L0 state */
394 hsotg->lx_state = DWC2_L0;
396 /* Inform gadget to exit from L1 */
397 call_gadget(hsotg, resume);
401 * This interrupt indicates that the DWC_otg controller has detected a
402 * resume or remote wakeup sequence. If the DWC_otg controller is in
403 * low power mode, the handler must brings the controller out of low
404 * power mode. The controller automatically begins resume signaling.
405 * The handler schedules a time to stop resume signaling.
407 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
411 /* Clear interrupt */
412 dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
414 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
415 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
417 if (hsotg->lx_state == DWC2_L1) {
418 dwc2_wakeup_from_lpm_l1(hsotg);
422 if (dwc2_is_device_mode(hsotg)) {
423 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
424 dwc2_readl(hsotg, DSTS));
425 if (hsotg->lx_state == DWC2_L2) {
427 u32 dctl = dwc2_readl(hsotg, DCTL);
428 /* Clear Remote Wakeup Signaling */
429 dctl &= ~DCTL_RMTWKUPSIG;
430 dwc2_writel(hsotg, dctl, DCTL);
431 ret = dwc2_exit_partial_power_down(hsotg, 1,
435 "exit partial_power_down failed\n");
436 call_gadget(hsotg, resume);
439 /* Exit gadget mode clock gating. */
440 if (hsotg->params.power_down ==
441 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
442 dwc2_gadget_exit_clock_gating(hsotg, 0);
444 /* Change to L0 state */
445 hsotg->lx_state = DWC2_L0;
448 if (hsotg->lx_state == DWC2_L2) {
450 ret = dwc2_exit_partial_power_down(hsotg, 1,
454 "exit partial_power_down failed\n");
457 if (hsotg->params.power_down ==
458 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
459 dwc2_host_exit_clock_gating(hsotg, 1);
462 * If we've got this quirk then the PHY is stuck upon
463 * wakeup. Assert reset. This will propagate out and
464 * eventually we'll re-enumerate the device. Not great
465 * but the best we can do. We can't call phy_reset()
466 * at interrupt time but there's no hurry, so we'll
467 * schedule it for later.
469 if (hsotg->reset_phy_on_wake)
470 dwc2_host_schedule_phy_reset(hsotg);
472 mod_timer(&hsotg->wkp_timer,
473 jiffies + msecs_to_jiffies(71));
475 /* Change to L0 state */
476 hsotg->lx_state = DWC2_L0;
482 * This interrupt indicates that a device has been disconnected from the
485 static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
487 dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
489 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
490 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
491 dwc2_op_state_str(hsotg));
493 if (hsotg->op_state == OTG_STATE_A_HOST)
494 dwc2_hcd_disconnect(hsotg, false);
498 * This interrupt indicates that SUSPEND state has been detected on the USB.
500 * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
503 * When power management is enabled the core will be put in low power mode.
505 static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
510 /* Clear interrupt */
511 dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
513 dev_dbg(hsotg->dev, "USB SUSPEND\n");
515 if (dwc2_is_device_mode(hsotg)) {
517 * Check the Device status register to determine if the Suspend
520 dsts = dwc2_readl(hsotg, DSTS);
521 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
523 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
524 !!(dsts & DSTS_SUSPSTS),
525 hsotg->hw_params.power_optimized,
526 hsotg->hw_params.hibernation);
528 /* Ignore suspend request before enumeration */
529 if (!dwc2_is_device_connected(hsotg)) {
531 "ignore suspend request before enumeration\n");
534 if (dsts & DSTS_SUSPSTS) {
535 switch (hsotg->params.power_down) {
536 case DWC2_POWER_DOWN_PARAM_PARTIAL:
537 ret = dwc2_enter_partial_power_down(hsotg);
540 "enter partial_power_down failed\n");
544 /* Ask phy to be suspended */
545 if (!IS_ERR_OR_NULL(hsotg->uphy))
546 usb_phy_set_suspend(hsotg->uphy, true);
548 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
549 ret = dwc2_enter_hibernation(hsotg, 0);
552 "enter hibernation failed\n");
554 case DWC2_POWER_DOWN_PARAM_NONE:
556 * If neither hibernation nor partial power down are supported,
557 * clock gating is used to save power.
559 dwc2_gadget_enter_clock_gating(hsotg);
563 * Change to L2 (suspend) state before releasing
566 hsotg->lx_state = DWC2_L2;
568 /* Call gadget suspend callback */
569 call_gadget(hsotg, suspend);
572 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
573 dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
575 /* Change to L2 (suspend) state */
576 hsotg->lx_state = DWC2_L2;
577 /* Clear the a_peripheral flag, back to a_host */
578 spin_unlock(&hsotg->lock);
579 dwc2_hcd_start(hsotg);
580 spin_lock(&hsotg->lock);
581 hsotg->op_state = OTG_STATE_A_HOST;
587 * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
589 * @hsotg: Programming view of DWC_otg controller
592 static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
601 /* Clear interrupt */
602 dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
604 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
606 if (!(glpmcfg & GLPMCFG_LPMCAP)) {
607 dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
611 hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT;
612 hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK &
613 ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT;
614 hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN;
615 enslpm = glpmcfg & GLPMCFG_ENBLSLPM;
617 if (dwc2_is_device_mode(hsotg)) {
618 dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en);
620 if (hird_thres_en && hird >= hird_thres) {
621 dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n");
623 dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
625 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
627 pcgcctl = dwc2_readl(hsotg, PCGCTL);
628 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
629 dwc2_writel(hsotg, pcgcctl, PCGCTL);
632 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
636 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
638 if (glpmcfg & GLPMCFG_SLPSTS) {
639 /* Save the current state */
640 hsotg->lx_state = DWC2_L1;
642 "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg);
644 /* Inform gadget that we are in L1 state */
645 call_gadget(hsotg, suspend);
650 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
651 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
652 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
653 GINTSTS_USBSUSP | GINTSTS_PRTINT | \
657 * This function returns the Core Interrupt register
659 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
664 u32 gintmsk_common = GINTMSK_COMMON;
666 gintsts = dwc2_readl(hsotg, GINTSTS);
667 gintmsk = dwc2_readl(hsotg, GINTMSK);
668 gahbcfg = dwc2_readl(hsotg, GAHBCFG);
670 /* If any common interrupts set */
671 if (gintsts & gintmsk_common)
672 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
675 if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
676 return gintsts & gintmsk & gintmsk_common;
682 * dwc_handle_gpwrdn_disc_det() - Handles the gpwrdn disconnect detect.
683 * Exits hibernation without restoring registers.
685 * @hsotg: Programming view of DWC_otg controller
686 * @gpwrdn: GPWRDN register
688 static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
693 /* Switch-on voltage to the core */
694 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
695 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
696 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
700 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
701 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
702 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
705 /* Disable Power Down Clamp */
706 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
707 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
708 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
711 /* Deassert reset core */
712 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
713 gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
714 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
717 /* Disable PMU interrupt */
718 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
719 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
720 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
722 /* De-assert Wakeup Logic */
723 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
724 gpwrdn_tmp &= ~GPWRDN_PMUACTV;
725 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
727 hsotg->hibernated = 0;
728 hsotg->bus_suspended = 0;
730 if (gpwrdn & GPWRDN_IDSTS) {
731 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
732 dwc2_core_init(hsotg, false);
733 dwc2_enable_global_interrupts(hsotg);
734 dwc2_hsotg_core_init_disconnected(hsotg, false);
735 dwc2_hsotg_core_connect(hsotg);
737 hsotg->op_state = OTG_STATE_A_HOST;
739 /* Initialize the Core for Host mode */
740 dwc2_core_init(hsotg, false);
741 dwc2_enable_global_interrupts(hsotg);
742 dwc2_hcd_start(hsotg);
747 * GPWRDN interrupt handler.
749 * The GPWRDN interrupts are those that occur in both Host and
750 * Device mode while core is in hibernated state.
752 static int dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
758 gpwrdn = dwc2_readl(hsotg, GPWRDN);
759 /* clear all interrupt */
760 dwc2_writel(hsotg, gpwrdn, GPWRDN);
761 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
763 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
766 if ((gpwrdn & GPWRDN_DISCONN_DET) &&
767 (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
768 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
770 * Call disconnect detect function to exit from
773 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
774 } else if ((gpwrdn & GPWRDN_LNSTSCHG) &&
775 (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
776 dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
777 if (hsotg->hw_params.hibernation &&
779 if (gpwrdn & GPWRDN_IDSTS) {
780 ret = dwc2_exit_hibernation(hsotg, 0, 0, 0);
783 "exit hibernation failed.\n");
784 call_gadget(hsotg, resume);
786 ret = dwc2_exit_hibernation(hsotg, 1, 0, 1);
789 "exit hibernation failed.\n");
792 } else if ((gpwrdn & GPWRDN_RST_DET) &&
793 (gpwrdn & GPWRDN_RST_DET_MSK)) {
794 dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
796 ret = dwc2_exit_hibernation(hsotg, 0, 1, 0);
799 "exit hibernation failed.\n");
801 } else if ((gpwrdn & GPWRDN_STS_CHGINT) &&
802 (gpwrdn & GPWRDN_STS_CHGINT_MSK)) {
803 dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
805 * As GPWRDN_STS_CHGINT exit from hibernation flow is
806 * the same as in GPWRDN_DISCONN_DET flow. Call
807 * disconnect detect helper function to exit from
810 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
817 * Common interrupt handler
819 * The common interrupts are those that occur in both Host and Device mode.
820 * This handler handles the following interrupts:
821 * - Mode Mismatch Interrupt
823 * - Connector ID Status Change Interrupt
824 * - Disconnect Interrupt
825 * - Session Request Interrupt
826 * - Resume / Remote Wakeup Detected Interrupt
827 * - Suspend Interrupt
829 irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
831 struct dwc2_hsotg *hsotg = dev;
833 irqreturn_t retval = IRQ_NONE;
835 spin_lock(&hsotg->lock);
837 if (!dwc2_is_controller_alive(hsotg)) {
838 dev_warn(hsotg->dev, "Controller is dead\n");
842 /* Reading current frame number value in device or host modes. */
843 if (dwc2_is_device_mode(hsotg))
844 hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
845 & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
847 hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
848 & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
850 gintsts = dwc2_read_common_intr(hsotg);
851 if (gintsts & ~GINTSTS_PRTINT)
852 retval = IRQ_HANDLED;
854 /* In case of hibernated state gintsts must not work */
855 if (hsotg->hibernated) {
856 dwc2_handle_gpwrdn_intr(hsotg);
857 retval = IRQ_HANDLED;
861 if (gintsts & GINTSTS_MODEMIS)
862 dwc2_handle_mode_mismatch_intr(hsotg);
863 if (gintsts & GINTSTS_OTGINT)
864 dwc2_handle_otg_intr(hsotg);
865 if (gintsts & GINTSTS_CONIDSTSCHNG)
866 dwc2_handle_conn_id_status_change_intr(hsotg);
867 if (gintsts & GINTSTS_DISCONNINT)
868 dwc2_handle_disconnect_intr(hsotg);
869 if (gintsts & GINTSTS_SESSREQINT)
870 dwc2_handle_session_req_intr(hsotg);
871 if (gintsts & GINTSTS_WKUPINT)
872 dwc2_handle_wakeup_detected_intr(hsotg);
873 if (gintsts & GINTSTS_USBSUSP)
874 dwc2_handle_usb_suspend_intr(hsotg);
875 if (gintsts & GINTSTS_LPMTRANRCVD)
876 dwc2_handle_lpm_intr(hsotg);
878 if (gintsts & GINTSTS_PRTINT) {
880 * The port interrupt occurs while in device mode with HPRT0
881 * Port Enable/Disable
883 if (dwc2_is_device_mode(hsotg)) {
885 " --Port interrupt received in Device mode--\n");
886 dwc2_handle_usb_port_intr(hsotg);
887 retval = IRQ_HANDLED;
892 spin_unlock(&hsotg->lock);