1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.c - DesignWare HS OTG Controller common routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
9 * The Core code provides basic services for accessing and managing the
10 * DWC_otg hardware. These services are used by both the Host Controller
11 * Driver and the Peripheral Controller Driver.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/usb.h>
24 #include <linux/usb/hcd.h>
25 #include <linux/usb/ch11.h>
31 * dwc2_backup_global_registers() - Backup global controller registers.
32 * When suspending usb bus, registers needs to be backuped
33 * if controller power is disabled once suspended.
35 * @hsotg: Programming view of the DWC_otg controller
37 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
39 struct dwc2_gregs_backup *gr;
41 dev_dbg(hsotg->dev, "%s\n", __func__);
43 /* Backup global regs */
44 gr = &hsotg->gr_backup;
46 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
47 gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
48 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
49 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
50 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
51 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
52 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
53 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
54 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
55 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
56 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
63 * dwc2_restore_global_registers() - Restore controller global registers.
64 * When resuming usb bus, device registers needs to be restored
65 * if controller power were disabled.
67 * @hsotg: Programming view of the DWC_otg controller
69 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
71 struct dwc2_gregs_backup *gr;
73 dev_dbg(hsotg->dev, "%s\n", __func__);
75 /* Restore global regs */
76 gr = &hsotg->gr_backup;
78 dev_err(hsotg->dev, "%s: no global registers to restore\n",
84 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
85 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
86 dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
87 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
88 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
89 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
90 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
91 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
92 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
93 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
94 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
95 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
101 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
103 * @hsotg: Programming view of the DWC_otg controller
104 * @rem_wakeup: indicates whether resume is initiated by Reset.
105 * @restore: Controller registers need to be restored
107 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
110 struct dwc2_gregs_backup *gr;
112 gr = &hsotg->gr_backup;
115 * Restore host or device regisers with the same mode core enterted
116 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup
117 * value of the "gotgctl" register.
119 if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
120 return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup,
123 return dwc2_gadget_exit_partial_power_down(hsotg, restore);
127 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
129 * @hsotg: Programming view of the DWC_otg controller
131 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
133 if (dwc2_is_host_mode(hsotg))
134 return dwc2_host_enter_partial_power_down(hsotg);
136 return dwc2_gadget_enter_partial_power_down(hsotg);
140 * dwc2_restore_essential_regs() - Restore essiential regs of core.
142 * @hsotg: Programming view of the DWC_otg controller
143 * @rmode: Restore mode, enabled in case of remote-wakeup.
144 * @is_host: Host or device mode.
146 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
150 struct dwc2_gregs_backup *gr;
151 struct dwc2_dregs_backup *dr;
152 struct dwc2_hregs_backup *hr;
154 gr = &hsotg->gr_backup;
155 dr = &hsotg->dr_backup;
156 hr = &hsotg->hr_backup;
158 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
160 /* Load restore values for [31:14] bits */
161 pcgcctl = (gr->pcgcctl & 0xffffc000);
164 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
167 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
170 dwc2_writel(hsotg, pcgcctl, PCGCTL);
172 /* Umnask global Interrupt in GAHBCFG and restore it */
173 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
175 /* Clear all pending interupts */
176 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
178 /* Unmask restore done interrupt */
179 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
181 /* Restore GUSBCFG and HCFG/DCFG */
182 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
185 dwc2_writel(hsotg, hr->hcfg, HCFG);
187 pcgcctl |= PCGCTL_RESTOREMODE;
188 dwc2_writel(hsotg, pcgcctl, PCGCTL);
191 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
192 dwc2_writel(hsotg, pcgcctl, PCGCTL);
195 dwc2_writel(hsotg, dr->dcfg, DCFG);
197 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
198 dwc2_writel(hsotg, pcgcctl, PCGCTL);
201 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
202 dwc2_writel(hsotg, pcgcctl, PCGCTL);
208 * dwc2_hib_restore_common() - Common part of restore routine.
210 * @hsotg: Programming view of the DWC_otg controller
211 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
212 * @is_host: Host or device mode.
214 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
219 /* Switch-on voltage to the core */
220 gpwrdn = dwc2_readl(hsotg, GPWRDN);
221 gpwrdn &= ~GPWRDN_PWRDNSWTCH;
222 dwc2_writel(hsotg, gpwrdn, GPWRDN);
226 gpwrdn = dwc2_readl(hsotg, GPWRDN);
227 gpwrdn &= ~GPWRDN_PWRDNRSTN;
228 dwc2_writel(hsotg, gpwrdn, GPWRDN);
231 /* Enable restore from PMU */
232 gpwrdn = dwc2_readl(hsotg, GPWRDN);
233 gpwrdn |= GPWRDN_RESTORE;
234 dwc2_writel(hsotg, gpwrdn, GPWRDN);
237 /* Disable Power Down Clamp */
238 gpwrdn = dwc2_readl(hsotg, GPWRDN);
239 gpwrdn &= ~GPWRDN_PWRDNCLMP;
240 dwc2_writel(hsotg, gpwrdn, GPWRDN);
243 if (!is_host && rem_wakeup)
246 /* Deassert reset core */
247 gpwrdn = dwc2_readl(hsotg, GPWRDN);
248 gpwrdn |= GPWRDN_PWRDNRSTN;
249 dwc2_writel(hsotg, gpwrdn, GPWRDN);
252 /* Disable PMU interrupt */
253 gpwrdn = dwc2_readl(hsotg, GPWRDN);
254 gpwrdn &= ~GPWRDN_PMUINTSEL;
255 dwc2_writel(hsotg, gpwrdn, GPWRDN);
258 /* Set Restore Essential Regs bit in PCGCCTL register */
259 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
262 * Wait For Restore_done Interrupt. This mechanism of polling the
263 * interrupt is introduced to avoid any possible race conditions
265 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
268 "%s: Restore Done wasn't generated here\n",
271 dev_dbg(hsotg->dev, "restore done generated here\n");
274 * To avoid restore done interrupt storm after restore is
275 * generated clear GINTSTS_RESTOREDONE bit.
277 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS);
282 * dwc2_wait_for_mode() - Waits for the controller mode.
283 * @hsotg: Programming view of the DWC_otg controller.
284 * @host_mode: If true, waits for host mode, otherwise device mode.
286 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
291 unsigned int timeout = 110;
293 dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
294 host_mode ? "host" : "device");
301 if (dwc2_is_host_mode(hsotg) == host_mode) {
302 dev_vdbg(hsotg->dev, "%s mode set\n",
303 host_mode ? "Host" : "Device");
308 ms = ktime_to_ms(ktime_sub(end, start));
310 if (ms >= (s64)timeout) {
311 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
312 __func__, host_mode ? "host" : "device");
316 usleep_range(1000, 2000);
321 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
324 * @hsotg: Programming view of DWC_otg controller
326 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
331 if (!dwc2_hw_is_otg(hsotg))
334 /* Check if core configuration includes the IDDIG filter. */
335 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
336 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
340 * Check if the IDDIG debounce filter is bypassed. Available
341 * in core version >= 3.10a.
343 gsnpsid = dwc2_readl(hsotg, GSNPSID);
344 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
345 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
347 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
355 * dwc2_enter_hibernation() - Common function to enter hibernation.
357 * @hsotg: Programming view of the DWC_otg controller
358 * @is_host: True if core is in host mode.
360 * Return: 0 if successful, negative error code otherwise
362 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
365 return dwc2_host_enter_hibernation(hsotg);
367 return dwc2_gadget_enter_hibernation(hsotg);
371 * dwc2_exit_hibernation() - Common function to exit from hibernation.
373 * @hsotg: Programming view of the DWC_otg controller
374 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
375 * @reset: Enabled in case of restore with reset.
376 * @is_host: True if core is in host mode.
378 * Return: 0 if successful, negative error code otherwise
380 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
381 int reset, int is_host)
384 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
386 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
390 * Do core a soft reset of the core. Be careful with this because it
391 * resets all the internal state machines of the core.
393 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
396 bool wait_for_host_mode = false;
398 dev_vdbg(hsotg->dev, "%s()\n", __func__);
401 * If the current mode is host, either due to the force mode
402 * bit being set (which persists after core reset) or the
403 * connector id pin, a core soft reset will temporarily reset
404 * the mode to device. A delay from the IDDIG debounce filter
405 * will occur before going back to host mode.
407 * Determine whether we will go back into host mode after a
408 * reset and account for this delay after the reset.
410 if (dwc2_iddig_filter_enabled(hsotg)) {
411 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
412 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
414 if (!(gotgctl & GOTGCTL_CONID_B) ||
415 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
416 wait_for_host_mode = true;
420 /* Core Soft Reset */
421 greset = dwc2_readl(hsotg, GRSTCTL);
422 greset |= GRSTCTL_CSFTRST;
423 dwc2_writel(hsotg, greset, GRSTCTL);
425 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
426 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
427 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
428 GRSTCTL_CSFTRST, 10000)) {
429 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
434 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
435 GRSTCTL_CSFTRST_DONE, 10000)) {
436 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
440 greset = dwc2_readl(hsotg, GRSTCTL);
441 greset &= ~GRSTCTL_CSFTRST;
442 greset |= GRSTCTL_CSFTRST_DONE;
443 dwc2_writel(hsotg, greset, GRSTCTL);
447 * Switching from device mode to host mode by disconnecting
448 * device cable core enters and exits form hibernation.
449 * However, the fifo map remains not cleared. It results
450 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/
451 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2])
452 * if in host mode we disconnect the micro a to b host
453 * cable. Because core reset occurs.
454 * To avoid the WARNING, fifo_map should be cleared
455 * in dwc2_core_reset() function by taking into account configs.
456 * fifo_map must be cleared only if driver is configured in
457 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE"
460 dwc2_clear_fifo_map(hsotg);
462 /* Wait for AHB master IDLE state */
463 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
464 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
469 if (wait_for_host_mode && !skip_wait)
470 dwc2_wait_for_mode(hsotg, true);
476 * dwc2_force_mode() - Force the mode of the controller.
478 * Forcing the mode is needed for two cases:
480 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
481 * controller to stay in a particular mode regardless of ID pin
482 * changes. We do this once during probe.
484 * 2) During probe we want to read reset values of the hw
485 * configuration registers that are only available in either host or
486 * device mode. We may need to force the mode if the current mode does
487 * not allow us to access the register in the mode that we want.
489 * In either case it only makes sense to force the mode if the
490 * controller hardware is OTG capable.
492 * Checks are done in this function to determine whether doing a force
493 * would be valid or not.
495 * If a force is done, it requires a IDDIG debounce filter delay if
496 * the filter is configured and enabled. We poll the current mode of
497 * the controller to account for this delay.
499 * @hsotg: Programming view of DWC_otg controller
500 * @host: Host mode flag
502 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
508 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
511 * Force mode has no effect if the hardware is not OTG.
513 if (!dwc2_hw_is_otg(hsotg))
517 * If dr_mode is either peripheral or host only, there is no
518 * need to ever force the mode to the opposite mode.
520 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
523 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
526 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
528 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
529 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
533 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
535 dwc2_wait_for_mode(hsotg, host);
540 * dwc2_clear_force_mode() - Clears the force mode bits.
542 * After clearing the bits, wait up to 100 ms to account for any
543 * potential IDDIG filter delay. We can't know if we expect this delay
544 * or not because the value of the connector ID status is affected by
545 * the force mode. We only need to call this once during probe if
548 * @hsotg: Programming view of DWC_otg controller
550 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
554 if (!dwc2_hw_is_otg(hsotg))
557 dev_dbg(hsotg->dev, "Clearing force mode bits\n");
559 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
560 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
561 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
562 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
564 if (dwc2_iddig_filter_enabled(hsotg))
569 * Sets or clears force mode based on the dr_mode parameter.
571 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
573 switch (hsotg->dr_mode) {
574 case USB_DR_MODE_HOST:
576 * NOTE: This is required for some rockchip soc based
577 * platforms on their host-only dwc2.
579 if (!dwc2_hw_is_otg(hsotg))
583 case USB_DR_MODE_PERIPHERAL:
585 * To prevent early notification to host without any
586 * preparation about device descriptor, forcing mode
587 * is defered until gadget driver is ready.
589 /* dwc2_force_mode(hsotg, false); */
591 case USB_DR_MODE_OTG:
592 dwc2_clear_force_mode(hsotg);
595 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
596 __func__, hsotg->dr_mode);
602 * dwc2_enable_acg - enable active clock gating feature
604 void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
606 if (hsotg->params.acg_enable) {
607 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
609 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
610 pcgcctl1 |= PCGCCTL1_GATEEN;
611 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
616 * dwc2_dump_host_registers() - Prints the host registers
618 * @hsotg: Programming view of DWC_otg controller
620 * NOTE: This function will be removed once the peripheral controller code
621 * is integrated and the driver is stable
623 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
629 dev_dbg(hsotg->dev, "Host Global Registers\n");
630 addr = hsotg->regs + HCFG;
631 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
632 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
633 addr = hsotg->regs + HFIR;
634 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
635 (unsigned long)addr, dwc2_readl(hsotg, HFIR));
636 addr = hsotg->regs + HFNUM;
637 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
638 (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
639 addr = hsotg->regs + HPTXSTS;
640 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
641 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
642 addr = hsotg->regs + HAINT;
643 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
644 (unsigned long)addr, dwc2_readl(hsotg, HAINT));
645 addr = hsotg->regs + HAINTMSK;
646 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
647 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
648 if (hsotg->params.dma_desc_enable) {
649 addr = hsotg->regs + HFLBADDR;
650 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
651 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
654 addr = hsotg->regs + HPRT0;
655 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
656 (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
658 for (i = 0; i < hsotg->params.host_channels; i++) {
659 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
660 addr = hsotg->regs + HCCHAR(i);
661 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
662 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
663 addr = hsotg->regs + HCSPLT(i);
664 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
665 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
666 addr = hsotg->regs + HCINT(i);
667 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
668 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
669 addr = hsotg->regs + HCINTMSK(i);
670 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
671 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
672 addr = hsotg->regs + HCTSIZ(i);
673 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
674 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
675 addr = hsotg->regs + HCDMA(i);
676 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
677 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
678 if (hsotg->params.dma_desc_enable) {
679 addr = hsotg->regs + HCDMAB(i);
680 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
681 (unsigned long)addr, dwc2_readl(hsotg,
689 * dwc2_dump_global_registers() - Prints the core global registers
691 * @hsotg: Programming view of DWC_otg controller
693 * NOTE: This function will be removed once the peripheral controller code
694 * is integrated and the driver is stable
696 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
701 dev_dbg(hsotg->dev, "Core Global Registers\n");
702 addr = hsotg->regs + GOTGCTL;
703 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
704 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
705 addr = hsotg->regs + GOTGINT;
706 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
707 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
708 addr = hsotg->regs + GAHBCFG;
709 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
710 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
711 addr = hsotg->regs + GUSBCFG;
712 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
713 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
714 addr = hsotg->regs + GRSTCTL;
715 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
716 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
717 addr = hsotg->regs + GINTSTS;
718 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
719 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
720 addr = hsotg->regs + GINTMSK;
721 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
722 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
723 addr = hsotg->regs + GRXSTSR;
724 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
725 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
726 addr = hsotg->regs + GRXFSIZ;
727 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
728 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
729 addr = hsotg->regs + GNPTXFSIZ;
730 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
731 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
732 addr = hsotg->regs + GNPTXSTS;
733 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
734 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
735 addr = hsotg->regs + GI2CCTL;
736 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
737 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
738 addr = hsotg->regs + GPVNDCTL;
739 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
740 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
741 addr = hsotg->regs + GGPIO;
742 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
743 (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
744 addr = hsotg->regs + GUID;
745 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
746 (unsigned long)addr, dwc2_readl(hsotg, GUID));
747 addr = hsotg->regs + GSNPSID;
748 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
749 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
750 addr = hsotg->regs + GHWCFG1;
751 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
752 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
753 addr = hsotg->regs + GHWCFG2;
754 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
755 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
756 addr = hsotg->regs + GHWCFG3;
757 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
758 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
759 addr = hsotg->regs + GHWCFG4;
760 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
761 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
762 addr = hsotg->regs + GLPMCFG;
763 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
764 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
765 addr = hsotg->regs + GPWRDN;
766 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
767 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
768 addr = hsotg->regs + GDFIFOCFG;
769 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
770 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
771 addr = hsotg->regs + HPTXFSIZ;
772 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
773 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
775 addr = hsotg->regs + PCGCTL;
776 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
777 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
782 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
784 * @hsotg: Programming view of DWC_otg controller
785 * @num: Tx FIFO to flush
787 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
791 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
793 /* Wait for AHB master IDLE state */
794 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
795 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
798 greset = GRSTCTL_TXFFLSH;
799 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
800 dwc2_writel(hsotg, greset, GRSTCTL);
802 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
803 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
806 /* Wait for at least 3 PHY Clocks */
811 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
813 * @hsotg: Programming view of DWC_otg controller
815 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
819 dev_vdbg(hsotg->dev, "%s()\n", __func__);
821 /* Wait for AHB master IDLE state */
822 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
823 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
826 greset = GRSTCTL_RXFFLSH;
827 dwc2_writel(hsotg, greset, GRSTCTL);
829 /* Wait for RxFIFO flush done */
830 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
831 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
834 /* Wait for at least 3 PHY Clocks */
838 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
840 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
847 * dwc2_enable_global_interrupts() - Enables the controller's Global
848 * Interrupt in the AHB Config register
850 * @hsotg: Programming view of DWC_otg controller
852 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
854 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
856 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
857 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
861 * dwc2_disable_global_interrupts() - Disables the controller's Global
862 * Interrupt in the AHB Config register
864 * @hsotg: Programming view of DWC_otg controller
866 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
868 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
870 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
871 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
874 /* Returns the controller's GHWCFG2.OTG_MODE. */
875 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
877 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
879 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
880 GHWCFG2_OP_MODE_SHIFT;
883 /* Returns true if the controller is capable of DRD. */
884 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
886 unsigned int op_mode = dwc2_op_mode(hsotg);
888 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
889 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
890 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
893 /* Returns true if the controller is host-only. */
894 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
896 unsigned int op_mode = dwc2_op_mode(hsotg);
898 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
899 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
902 /* Returns true if the controller is device-only. */
903 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
905 unsigned int op_mode = dwc2_op_mode(hsotg);
907 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
908 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
912 * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
913 * @hsotg: Programming view of DWC_otg controller.
914 * @offset: Register's offset where bit/bits must be set.
915 * @mask: Mask of the bit/bits which must be set.
916 * @timeout: Timeout to wait.
918 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
920 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
925 for (i = 0; i < timeout; i++) {
926 if (dwc2_readl(hsotg, offset) & mask)
935 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
936 * @hsotg: Programming view of DWC_otg controller.
937 * @offset: Register's offset where bit/bits must be set.
938 * @mask: Mask of the bit/bits which must be set.
939 * @timeout: Timeout to wait.
941 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
943 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
948 for (i = 0; i < timeout; i++) {
949 if (!(dwc2_readl(hsotg, offset) & mask))
958 * Initializes the FSLSPClkSel field of the HCFG register depending on the
961 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
965 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
966 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
967 hsotg->params.ulpi_fs_ls) ||
968 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
970 val = HCFG_FSLSPCLKSEL_48_MHZ;
972 /* High speed PHY running at full speed or high speed */
973 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
976 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
977 hcfg = dwc2_readl(hsotg, HCFG);
978 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
979 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
980 dwc2_writel(hsotg, hcfg, HCFG);
983 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
985 u32 usbcfg, ggpio, i2cctl;
989 * core_init() is now called on every switch so only call the
990 * following for the first time through
993 dev_dbg(hsotg->dev, "FS PHY selected\n");
995 usbcfg = dwc2_readl(hsotg, GUSBCFG);
996 if (!(usbcfg & GUSBCFG_PHYSEL)) {
997 usbcfg |= GUSBCFG_PHYSEL;
998 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1000 if (dwc2_is_host_mode(hsotg)) {
1001 /* Reset after a PHY select */
1002 retval = dwc2_core_reset(hsotg, false);
1006 "%s: Reset failed, aborting",
1013 if (hsotg->params.activate_stm_fs_transceiver) {
1014 ggpio = dwc2_readl(hsotg, GGPIO);
1015 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1016 dev_dbg(hsotg->dev, "Activating transceiver\n");
1018 * STM32F4x9 uses the GGPIO register as general
1019 * core configuration register.
1021 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1022 dwc2_writel(hsotg, ggpio, GGPIO);
1028 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1029 * do this on HNP Dev/Host mode switches (done in dev_init and
1032 if (dwc2_is_host_mode(hsotg))
1033 dwc2_init_fs_ls_pclk_sel(hsotg);
1035 if (hsotg->params.i2c_enable) {
1036 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1038 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
1039 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1040 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1041 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1043 /* Program GI2CCTL.I2CEn */
1044 i2cctl = dwc2_readl(hsotg, GI2CCTL);
1045 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1046 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1047 i2cctl &= ~GI2CCTL_I2CEN;
1048 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1049 i2cctl |= GI2CCTL_I2CEN;
1050 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1056 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1058 u32 usbcfg, usbcfg_old;
1064 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1065 usbcfg_old = usbcfg;
1068 * HS PHY parameters. These parameters are preserved during soft reset
1069 * so only program the first time. Do a soft reset immediately after
1072 switch (hsotg->params.phy_type) {
1073 case DWC2_PHY_TYPE_PARAM_ULPI:
1074 /* ULPI interface */
1075 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1076 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1077 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1078 if (hsotg->params.phy_ulpi_ddr)
1079 usbcfg |= GUSBCFG_DDRSEL;
1081 /* Set external VBUS indicator as needed. */
1082 if (hsotg->params.oc_disable)
1083 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1084 GUSBCFG_INDICATORPASSTHROUGH);
1086 case DWC2_PHY_TYPE_PARAM_UTMI:
1087 /* UTMI+ interface */
1088 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1089 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1090 if (hsotg->params.phy_utmi_width == 16)
1091 usbcfg |= GUSBCFG_PHYIF16;
1094 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1098 if (usbcfg != usbcfg_old) {
1099 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1101 if (dwc2_is_host_mode(hsotg)) {
1102 /* Reset after setting the PHY parameters */
1103 retval = dwc2_core_reset(hsotg, false);
1106 "%s: Reset failed, aborting", __func__);
1115 static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1119 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1122 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1124 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1125 if (hsotg->params.phy_utmi_width == 16)
1126 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1128 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1130 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1133 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1139 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1140 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1141 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1142 /* If FS/LS mode with FS/LS PHY */
1143 retval = dwc2_fs_phy_init(hsotg, select_phy);
1147 /* High speed PHY */
1148 retval = dwc2_hs_phy_init(hsotg, select_phy);
1152 if (dwc2_is_device_mode(hsotg))
1153 dwc2_set_turnaround_time(hsotg);
1156 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1157 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1158 hsotg->params.ulpi_fs_ls) {
1159 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1160 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1161 usbcfg |= GUSBCFG_ULPI_FS_LS;
1162 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1163 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1165 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1166 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1167 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1168 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1171 if (!hsotg->params.activate_ingenic_overcurrent_detection) {
1172 if (dwc2_is_host_mode(hsotg)) {
1173 otgctl = readl(hsotg->regs + GOTGCTL);
1174 otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL;
1175 writel(otgctl, hsotg->regs + GOTGCTL);
1182 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1183 MODULE_AUTHOR("Synopsys, Inc.");
1184 MODULE_LICENSE("Dual BSD/GPL");