1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - ChipIdea USB IP core family device controller
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 * Copyright (C) 2020 NXP
9 * Peter Chen <peter.chen@nxp.com>
12 * - Four transfers are supported, usbtest is passed
13 * - USB Certification for gadget: CH9 and Mass Storage are passed
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/extcon.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/module.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/otg.h>
34 #include <linux/usb/chipidea.h>
35 #include <linux/usb/of.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/usb/ehci_def.h>
47 /* Controller register map */
48 static const u8 ci_regs_nolpm[] = {
49 [CAP_CAPLENGTH] = 0x00U,
50 [CAP_HCCPARAMS] = 0x08U,
51 [CAP_DCCPARAMS] = 0x24U,
52 [CAP_TESTMODE] = 0x38U,
57 [OP_DEVICEADDR] = 0x14U,
58 [OP_ENDPTLISTADDR] = 0x18U,
60 [OP_BURSTSIZE] = 0x20U,
61 [OP_ULPI_VIEWPORT] = 0x30U,
66 [OP_ENDPTSETUPSTAT] = 0x6CU,
67 [OP_ENDPTPRIME] = 0x70U,
68 [OP_ENDPTFLUSH] = 0x74U,
69 [OP_ENDPTSTAT] = 0x78U,
70 [OP_ENDPTCOMPLETE] = 0x7CU,
71 [OP_ENDPTCTRL] = 0x80U,
74 static const u8 ci_regs_lpm[] = {
75 [CAP_CAPLENGTH] = 0x00U,
76 [CAP_HCCPARAMS] = 0x08U,
77 [CAP_DCCPARAMS] = 0x24U,
78 [CAP_TESTMODE] = 0xFCU,
83 [OP_DEVICEADDR] = 0x14U,
84 [OP_ENDPTLISTADDR] = 0x18U,
86 [OP_BURSTSIZE] = 0x20U,
87 [OP_ULPI_VIEWPORT] = 0x30U,
92 [OP_ENDPTSETUPSTAT] = 0xD8U,
93 [OP_ENDPTPRIME] = 0xDCU,
94 [OP_ENDPTFLUSH] = 0xE0U,
95 [OP_ENDPTSTAT] = 0xE4U,
96 [OP_ENDPTCOMPLETE] = 0xE8U,
97 [OP_ENDPTCTRL] = 0xECU,
100 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
104 for (i = 0; i < OP_ENDPTCTRL; i++)
105 ci->hw_bank.regmap[i] =
106 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
107 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
109 for (; i <= OP_LAST; i++)
110 ci->hw_bank.regmap[i] = ci->hw_bank.op +
111 4 * (i - OP_ENDPTCTRL) +
113 ? ci_regs_lpm[OP_ENDPTCTRL]
114 : ci_regs_nolpm[OP_ENDPTCTRL]);
118 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
120 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
121 enum ci_revision rev = CI_REVISION_UNKNOWN;
124 rev = hw_read_id_reg(ci, ID_ID, REVISION)
126 rev += CI_REVISION_20;
127 } else if (ver == 0x0) {
128 rev = CI_REVISION_1X;
135 * hw_read_intr_enable: returns interrupt enable register
137 * @ci: the controller
139 * This function returns register data
141 u32 hw_read_intr_enable(struct ci_hdrc *ci)
143 return hw_read(ci, OP_USBINTR, ~0);
147 * hw_read_intr_status: returns interrupt status register
149 * @ci: the controller
151 * This function returns register data
153 u32 hw_read_intr_status(struct ci_hdrc *ci)
155 return hw_read(ci, OP_USBSTS, ~0);
159 * hw_port_test_set: writes port test mode (execute without interruption)
160 * @ci: the controller
163 * This function returns an error code
165 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
167 const u8 TEST_MODE_MAX = 7;
169 if (mode > TEST_MODE_MAX)
172 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
177 * hw_port_test_get: reads port test mode value
179 * @ci: the controller
181 * This function returns port test mode value
183 u8 hw_port_test_get(struct ci_hdrc *ci)
185 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
188 static void hw_wait_phy_stable(void)
191 * The phy needs some delay to output the stable status from low
192 * power mode. And for OTGSC, the status inputs are debounced
193 * using a 1 ms time constant, so, delay 2ms for controller to get
194 * the stable status, like vbus and id when the phy leaves low power.
196 usleep_range(2000, 2500);
199 /* The PHY enters/leaves low power mode */
200 static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
202 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
203 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
206 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
207 PORTSC_PHCD(ci->hw_bank.lpm));
208 else if (!enable && lpm)
209 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
213 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
215 return ci->platdata->enter_lpm(ci, enable);
218 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
222 /* bank is a module variable */
223 ci->hw_bank.abs = base;
225 ci->hw_bank.cap = ci->hw_bank.abs;
226 ci->hw_bank.cap += ci->platdata->capoffset;
227 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
229 hw_alloc_regmap(ci, false);
230 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
231 __ffs(HCCPARAMS_LEN);
232 ci->hw_bank.lpm = reg;
234 hw_alloc_regmap(ci, !!reg);
235 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
236 ci->hw_bank.size += OP_LAST;
237 ci->hw_bank.size /= sizeof(u32);
239 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
240 __ffs(DCCPARAMS_DEN);
241 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
243 if (ci->hw_ep_max > ENDPT_MAX)
246 ci_hdrc_enter_lpm(ci, false);
248 /* Disable all interrupts bits */
249 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
251 /* Clear all interrupts status bits*/
252 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
254 ci->rev = ci_get_revision(ci);
257 "revision: %d, lpm: %d; cap: %px op: %px\n",
258 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
260 /* setup lock mode ? */
262 /* ENDPTSETUPSTAT is '0' by default */
264 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
269 void hw_phymode_configure(struct ci_hdrc *ci)
271 u32 portsc, lpm, sts = 0;
273 switch (ci->platdata->phy_mode) {
274 case USBPHY_INTERFACE_MODE_UTMI:
275 portsc = PORTSC_PTS(PTS_UTMI);
276 lpm = DEVLC_PTS(PTS_UTMI);
278 case USBPHY_INTERFACE_MODE_UTMIW:
279 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
280 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
282 case USBPHY_INTERFACE_MODE_ULPI:
283 portsc = PORTSC_PTS(PTS_ULPI);
284 lpm = DEVLC_PTS(PTS_ULPI);
286 case USBPHY_INTERFACE_MODE_SERIAL:
287 portsc = PORTSC_PTS(PTS_SERIAL);
288 lpm = DEVLC_PTS(PTS_SERIAL);
291 case USBPHY_INTERFACE_MODE_HSIC:
292 portsc = PORTSC_PTS(PTS_HSIC);
293 lpm = DEVLC_PTS(PTS_HSIC);
299 if (ci->hw_bank.lpm) {
300 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
302 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
304 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
306 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
309 EXPORT_SYMBOL_GPL(hw_phymode_configure);
312 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
314 * @ci: the controller
316 * This function returns an error code if the phy failed to init
318 static int _ci_usb_phy_init(struct ci_hdrc *ci)
323 ret = phy_init(ci->phy);
327 ret = phy_power_on(ci->phy);
333 ret = usb_phy_init(ci->usb_phy);
340 * ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
342 * @ci: the controller
344 static void ci_usb_phy_exit(struct ci_hdrc *ci)
346 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
350 phy_power_off(ci->phy);
353 usb_phy_shutdown(ci->usb_phy);
358 * ci_usb_phy_init: initialize phy according to different phy type
359 * @ci: the controller
361 * This function returns an error code if usb_phy_init has failed
363 static int ci_usb_phy_init(struct ci_hdrc *ci)
367 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
370 switch (ci->platdata->phy_mode) {
371 case USBPHY_INTERFACE_MODE_UTMI:
372 case USBPHY_INTERFACE_MODE_UTMIW:
373 case USBPHY_INTERFACE_MODE_HSIC:
374 ret = _ci_usb_phy_init(ci);
376 hw_wait_phy_stable();
379 hw_phymode_configure(ci);
381 case USBPHY_INTERFACE_MODE_ULPI:
382 case USBPHY_INTERFACE_MODE_SERIAL:
383 hw_phymode_configure(ci);
384 ret = _ci_usb_phy_init(ci);
389 ret = _ci_usb_phy_init(ci);
391 hw_wait_phy_stable();
399 * ci_platform_configure: do controller configure
400 * @ci: the controller
403 void ci_platform_configure(struct ci_hdrc *ci)
405 bool is_device_mode, is_host_mode;
407 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
408 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
410 if (is_device_mode) {
411 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
413 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
414 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
419 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
421 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
422 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
426 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
428 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
430 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
433 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
434 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
436 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
438 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
439 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
440 ci->platdata->ahb_burst_config);
442 /* override burst size, take effect only when ahb_burst_config is 0 */
443 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
444 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
445 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
446 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
448 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
449 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
450 ci->platdata->rx_burst_size);
455 * hw_controller_reset: do controller reset
456 * @ci: the controller
458 * This function returns an error code
460 static int hw_controller_reset(struct ci_hdrc *ci)
464 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
465 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
475 * hw_device_reset: resets chip (execute without interruption)
476 * @ci: the controller
478 * This function returns an error code
480 int hw_device_reset(struct ci_hdrc *ci)
484 /* should flush & stop before reset */
485 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
486 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
488 ret = hw_controller_reset(ci);
490 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
494 if (ci->platdata->notify_event) {
495 ret = ci->platdata->notify_event(ci,
496 CI_HDRC_CONTROLLER_RESET_EVENT);
501 /* USBMODE should be configured step by step */
502 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
503 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
505 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
507 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
508 dev_err(ci->dev, "cannot enter in %s device mode\n",
510 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
514 ci_platform_configure(ci);
519 static irqreturn_t ci_irq_handler(int irq, void *data)
521 struct ci_hdrc *ci = data;
522 irqreturn_t ret = IRQ_NONE;
526 disable_irq_nosync(irq);
527 ci->wakeup_int = true;
528 pm_runtime_get(ci->dev);
533 otgsc = hw_read_otgsc(ci, ~0);
534 if (ci_otg_is_fsm_mode(ci)) {
535 ret = ci_otg_fsm_irq(ci);
536 if (ret == IRQ_HANDLED)
542 * Handle id change interrupt, it indicates device/host function
545 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
547 /* Clear ID change irq status */
548 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
549 ci_otg_queue_work(ci);
554 * Handle vbus change interrupt, it indicates device connection
555 * and disconnection events.
557 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
558 ci->b_sess_valid_event = true;
560 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
561 ci_otg_queue_work(ci);
565 /* Handle device/host interrupt */
566 if (ci->role != CI_ROLE_END)
567 ret = ci_role(ci)->irq(ci);
572 static void ci_irq(struct ci_hdrc *ci)
576 local_irq_save(flags);
577 ci_irq_handler(ci->irq, ci);
578 local_irq_restore(flags);
581 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
584 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
585 struct ci_hdrc *ci = cbl->ci;
587 cbl->connected = event;
594 static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
596 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
600 spin_lock_irqsave(&ci->lock, flags);
601 role = ci_role_to_usb_role(ci);
602 spin_unlock_irqrestore(&ci->lock, flags);
607 static int ci_usb_role_switch_set(struct usb_role_switch *sw,
610 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
611 struct ci_hdrc_cable *cable;
613 if (role == USB_ROLE_HOST) {
614 cable = &ci->platdata->id_extcon;
615 cable->changed = true;
616 cable->connected = true;
617 cable = &ci->platdata->vbus_extcon;
618 cable->changed = true;
619 cable->connected = false;
620 } else if (role == USB_ROLE_DEVICE) {
621 cable = &ci->platdata->id_extcon;
622 cable->changed = true;
623 cable->connected = false;
624 cable = &ci->platdata->vbus_extcon;
625 cable->changed = true;
626 cable->connected = true;
628 cable = &ci->platdata->id_extcon;
629 cable->changed = true;
630 cable->connected = false;
631 cable = &ci->platdata->vbus_extcon;
632 cable->changed = true;
633 cable->connected = false;
640 static enum ci_role ci_get_role(struct ci_hdrc *ci)
644 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
646 role = ci_otg_role(ci);
647 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
650 * If the controller is not OTG capable, but support
651 * role switch, the defalt role is gadget, and the
652 * user can switch it through debugfs.
654 role = CI_ROLE_GADGET;
657 role = ci->roles[CI_ROLE_HOST] ? CI_ROLE_HOST
664 static struct usb_role_switch_desc ci_role_switch = {
665 .set = ci_usb_role_switch_set,
666 .get = ci_usb_role_switch_get,
667 .allow_userspace_control = true,
670 static int ci_get_platdata(struct device *dev,
671 struct ci_hdrc_platform_data *platdata)
673 struct extcon_dev *ext_vbus, *ext_id;
674 struct ci_hdrc_cable *cable;
677 if (!platdata->phy_mode)
678 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
680 if (!platdata->dr_mode)
681 platdata->dr_mode = usb_get_dr_mode(dev);
683 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
684 platdata->dr_mode = USB_DR_MODE_OTG;
686 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
687 /* Get the vbus regulator */
688 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
689 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
690 return -EPROBE_DEFER;
691 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
692 /* no vbus regulator is needed */
693 platdata->reg_vbus = NULL;
694 } else if (IS_ERR(platdata->reg_vbus)) {
695 dev_err(dev, "Getting regulator error: %ld\n",
696 PTR_ERR(platdata->reg_vbus));
697 return PTR_ERR(platdata->reg_vbus);
699 /* Get TPL support */
700 if (!platdata->tpl_support)
701 platdata->tpl_support =
702 of_usb_host_tpl_support(dev->of_node);
705 if (platdata->dr_mode == USB_DR_MODE_OTG) {
706 /* We can support HNP and SRP of OTG 2.0 */
707 platdata->ci_otg_caps.otg_rev = 0x0200;
708 platdata->ci_otg_caps.hnp_support = true;
709 platdata->ci_otg_caps.srp_support = true;
711 /* Update otg capabilities by DT properties */
712 ret = of_usb_update_otg_caps(dev->of_node,
713 &platdata->ci_otg_caps);
718 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
719 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
721 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
722 &platdata->phy_clkgate_delay_us);
724 platdata->itc_setting = 1;
726 of_property_read_u32(dev->of_node, "itc-setting",
727 &platdata->itc_setting);
729 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
730 &platdata->ahb_burst_config);
732 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
733 } else if (ret != -EINVAL) {
734 dev_err(dev, "failed to get ahb-burst-config\n");
738 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
739 &platdata->tx_burst_size);
741 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
742 } else if (ret != -EINVAL) {
743 dev_err(dev, "failed to get tx-burst-size-dword\n");
747 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
748 &platdata->rx_burst_size);
750 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
751 } else if (ret != -EINVAL) {
752 dev_err(dev, "failed to get rx-burst-size-dword\n");
756 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
757 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
759 ext_id = ERR_PTR(-ENODEV);
760 ext_vbus = ERR_PTR(-ENODEV);
761 if (of_property_read_bool(dev->of_node, "extcon")) {
762 /* Each one of them is not mandatory */
763 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
764 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
765 return PTR_ERR(ext_vbus);
767 ext_id = extcon_get_edev_by_phandle(dev, 1);
768 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
769 return PTR_ERR(ext_id);
772 cable = &platdata->vbus_extcon;
773 cable->nb.notifier_call = ci_cable_notifier;
774 cable->edev = ext_vbus;
776 if (!IS_ERR(ext_vbus)) {
777 ret = extcon_get_state(cable->edev, EXTCON_USB);
779 cable->connected = true;
781 cable->connected = false;
784 cable = &platdata->id_extcon;
785 cable->nb.notifier_call = ci_cable_notifier;
786 cable->edev = ext_id;
788 if (!IS_ERR(ext_id)) {
789 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
791 cable->connected = true;
793 cable->connected = false;
796 if (device_property_read_bool(dev, "usb-role-switch"))
797 ci_role_switch.fwnode = dev->fwnode;
799 platdata->pctl = devm_pinctrl_get(dev);
800 if (!IS_ERR(platdata->pctl)) {
801 struct pinctrl_state *p;
803 p = pinctrl_lookup_state(platdata->pctl, "default");
805 platdata->pins_default = p;
807 p = pinctrl_lookup_state(platdata->pctl, "host");
809 platdata->pins_host = p;
811 p = pinctrl_lookup_state(platdata->pctl, "device");
813 platdata->pins_device = p;
816 if (!platdata->enter_lpm)
817 platdata->enter_lpm = ci_hdrc_enter_lpm_common;
822 static int ci_extcon_register(struct ci_hdrc *ci)
824 struct ci_hdrc_cable *id, *vbus;
827 id = &ci->platdata->id_extcon;
829 if (!IS_ERR_OR_NULL(id->edev)) {
830 ret = devm_extcon_register_notifier(ci->dev, id->edev,
831 EXTCON_USB_HOST, &id->nb);
833 dev_err(ci->dev, "register ID failed\n");
838 vbus = &ci->platdata->vbus_extcon;
840 if (!IS_ERR_OR_NULL(vbus->edev)) {
841 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
842 EXTCON_USB, &vbus->nb);
844 dev_err(ci->dev, "register VBUS failed\n");
852 static DEFINE_IDA(ci_ida);
854 struct platform_device *ci_hdrc_add_device(struct device *dev,
855 struct resource *res, int nres,
856 struct ci_hdrc_platform_data *platdata)
858 struct platform_device *pdev;
861 ret = ci_get_platdata(dev, platdata);
865 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
869 pdev = platform_device_alloc("ci_hdrc", id);
875 pdev->dev.parent = dev;
876 device_set_of_node_from_dev(&pdev->dev, dev);
878 ret = platform_device_add_resources(pdev, res, nres);
882 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
886 ret = platform_device_add(pdev);
893 platform_device_put(pdev);
895 ida_simple_remove(&ci_ida, id);
898 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
900 void ci_hdrc_remove_device(struct platform_device *pdev)
903 platform_device_unregister(pdev);
904 ida_simple_remove(&ci_ida, id);
906 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
909 * ci_hdrc_query_available_role: get runtime available operation mode
911 * The glue layer can get current operation mode (host/peripheral/otg)
912 * This function should be called after ci core device has created.
914 * @pdev: the platform device of ci core.
916 * Return runtime usb_dr_mode.
918 enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
920 struct ci_hdrc *ci = platform_get_drvdata(pdev);
923 return USB_DR_MODE_UNKNOWN;
924 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
925 return USB_DR_MODE_OTG;
926 else if (ci->roles[CI_ROLE_HOST])
927 return USB_DR_MODE_HOST;
928 else if (ci->roles[CI_ROLE_GADGET])
929 return USB_DR_MODE_PERIPHERAL;
931 return USB_DR_MODE_UNKNOWN;
933 EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
935 static inline void ci_role_destroy(struct ci_hdrc *ci)
937 ci_hdrc_gadget_destroy(ci);
938 ci_hdrc_host_destroy(ci);
939 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
940 ci_hdrc_otg_destroy(ci);
943 static void ci_get_otg_capable(struct ci_hdrc *ci)
945 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
948 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
949 DCCPARAMS_DC | DCCPARAMS_HC)
950 == (DCCPARAMS_DC | DCCPARAMS_HC));
952 dev_dbg(ci->dev, "It is OTG capable controller\n");
953 /* Disable and clear all OTG irq */
954 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
955 OTGSC_INT_STATUS_BITS);
959 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
962 struct ci_hdrc *ci = dev_get_drvdata(dev);
964 if (ci->role != CI_ROLE_END)
965 return sprintf(buf, "%s\n", ci_role(ci)->name);
970 static ssize_t role_store(struct device *dev,
971 struct device_attribute *attr, const char *buf, size_t n)
973 struct ci_hdrc *ci = dev_get_drvdata(dev);
977 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
978 dev_warn(dev, "Current configuration is not dual-role, quit\n");
982 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
983 if (!strncmp(buf, ci->roles[role]->name,
984 strlen(ci->roles[role]->name)))
987 if (role == CI_ROLE_END)
990 if (role == ci->role)
993 pm_runtime_get_sync(dev);
994 disable_irq(ci->irq);
996 ret = ci_role_start(ci, role);
997 if (!ret && ci->role == CI_ROLE_GADGET)
998 ci_handle_vbus_change(ci);
1000 pm_runtime_put_sync(dev);
1002 return (ret == 0) ? n : ret;
1004 static DEVICE_ATTR_RW(role);
1006 static struct attribute *ci_attrs[] = {
1007 &dev_attr_role.attr,
1010 ATTRIBUTE_GROUPS(ci);
1012 static int ci_hdrc_probe(struct platform_device *pdev)
1014 struct device *dev = &pdev->dev;
1016 struct resource *res;
1019 enum usb_dr_mode dr_mode;
1021 if (!dev_get_platdata(dev)) {
1022 dev_err(dev, "platform data missing\n");
1026 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1027 base = devm_ioremap_resource(dev, res);
1029 return PTR_ERR(base);
1031 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
1035 spin_lock_init(&ci->lock);
1037 ci->platdata = dev_get_platdata(dev);
1038 ci->imx28_write_fix = !!(ci->platdata->flags &
1039 CI_HDRC_IMX28_WRITE_FIX);
1040 ci->supports_runtime_pm = !!(ci->platdata->flags &
1041 CI_HDRC_SUPPORTS_RUNTIME_PM);
1042 platform_set_drvdata(pdev, ci);
1044 ret = hw_device_init(ci, base);
1046 dev_err(dev, "can't initialize hardware\n");
1050 ret = ci_ulpi_init(ci);
1054 if (ci->platdata->phy) {
1055 ci->phy = ci->platdata->phy;
1056 } else if (ci->platdata->usb_phy) {
1057 ci->usb_phy = ci->platdata->usb_phy;
1059 /* Look for a generic PHY first */
1060 ci->phy = devm_phy_get(dev->parent, "usb-phy");
1062 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1063 ret = -EPROBE_DEFER;
1065 } else if (IS_ERR(ci->phy)) {
1069 /* Look for a legacy USB PHY from device-tree next */
1071 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1074 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1075 ret = -EPROBE_DEFER;
1077 } else if (IS_ERR(ci->usb_phy)) {
1082 /* Look for any registered legacy USB PHY as last resort */
1083 if (!ci->phy && !ci->usb_phy) {
1084 ci->usb_phy = devm_usb_get_phy(dev->parent,
1087 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1088 ret = -EPROBE_DEFER;
1090 } else if (IS_ERR(ci->usb_phy)) {
1095 /* No USB PHY was found in the end */
1096 if (!ci->phy && !ci->usb_phy) {
1102 ret = ci_usb_phy_init(ci);
1104 dev_err(dev, "unable to init phy: %d\n", ret);
1108 ci->hw_bank.phys = res->start;
1110 ci->irq = platform_get_irq(pdev, 0);
1116 ci_get_otg_capable(ci);
1118 dr_mode = ci->platdata->dr_mode;
1119 /* initialize role(s) before the interrupt is requested */
1120 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1121 ret = ci_hdrc_host_init(ci);
1124 dev_info(dev, "doesn't support host\n");
1130 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1131 ret = ci_hdrc_gadget_init(ci);
1134 dev_info(dev, "doesn't support gadget\n");
1140 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1141 dev_err(dev, "no supported roles\n");
1146 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1147 ret = ci_hdrc_otg_init(ci);
1149 dev_err(dev, "init otg fails, ret = %d\n", ret);
1154 if (ci_role_switch.fwnode) {
1155 ci_role_switch.driver_data = ci;
1156 ci->role_switch = usb_role_switch_register(dev,
1158 if (IS_ERR(ci->role_switch)) {
1159 ret = PTR_ERR(ci->role_switch);
1164 ci->role = ci_get_role(ci);
1165 if (!ci_otg_is_fsm_mode(ci)) {
1166 /* only update vbus status for peripheral */
1167 if (ci->role == CI_ROLE_GADGET) {
1168 /* Pull down DP for possible charger detection */
1169 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
1170 ci_handle_vbus_change(ci);
1173 ret = ci_role_start(ci, ci->role);
1175 dev_err(dev, "can't start %s role\n",
1181 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
1182 ci->platdata->name, ci);
1186 ret = ci_extcon_register(ci);
1190 if (ci->supports_runtime_pm) {
1191 pm_runtime_set_active(&pdev->dev);
1192 pm_runtime_enable(&pdev->dev);
1193 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1194 pm_runtime_mark_last_busy(ci->dev);
1195 pm_runtime_use_autosuspend(&pdev->dev);
1198 if (ci_otg_is_fsm_mode(ci))
1199 ci_hdrc_otg_fsm_start(ci);
1201 device_set_wakeup_capable(&pdev->dev, true);
1202 dbg_create_files(ci);
1207 if (ci->role_switch)
1208 usb_role_switch_unregister(ci->role_switch);
1210 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1211 ci_hdrc_otg_destroy(ci);
1213 ci_hdrc_gadget_destroy(ci);
1215 ci_hdrc_host_destroy(ci);
1217 ci_usb_phy_exit(ci);
1224 static int ci_hdrc_remove(struct platform_device *pdev)
1226 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1228 if (ci->role_switch)
1229 usb_role_switch_unregister(ci->role_switch);
1231 if (ci->supports_runtime_pm) {
1232 pm_runtime_get_sync(&pdev->dev);
1233 pm_runtime_disable(&pdev->dev);
1234 pm_runtime_put_noidle(&pdev->dev);
1237 dbg_remove_files(ci);
1238 ci_role_destroy(ci);
1239 ci_hdrc_enter_lpm(ci, true);
1240 ci_usb_phy_exit(ci);
1247 /* Prepare wakeup by SRP before suspend */
1248 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1250 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1251 !hw_read_otgsc(ci, OTGSC_ID)) {
1252 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1254 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1259 /* Handle SRP when wakeup by data pulse */
1260 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1262 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1263 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1264 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1265 ci->fsm.a_srp_det = 1;
1266 ci->fsm.a_bus_drop = 0;
1270 ci_otg_queue_work(ci);
1274 static void ci_controller_suspend(struct ci_hdrc *ci)
1276 disable_irq(ci->irq);
1277 ci_hdrc_enter_lpm(ci, true);
1278 if (ci->platdata->phy_clkgate_delay_us)
1279 usleep_range(ci->platdata->phy_clkgate_delay_us,
1280 ci->platdata->phy_clkgate_delay_us + 50);
1281 usb_phy_set_suspend(ci->usb_phy, 1);
1283 enable_irq(ci->irq);
1287 * Handle the wakeup interrupt triggered by extcon connector
1288 * We need to call ci_irq again for extcon since the first
1289 * interrupt (wakeup int) only let the controller be out of
1290 * low power mode, but not handle any interrupts.
1292 static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1294 struct ci_hdrc_cable *cable_id, *cable_vbus;
1295 u32 otgsc = hw_read_otgsc(ci, ~0);
1297 cable_id = &ci->platdata->id_extcon;
1298 cable_vbus = &ci->platdata->vbus_extcon;
1300 if ((!IS_ERR(cable_id->edev) || ci->role_switch)
1302 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1305 if ((!IS_ERR(cable_vbus->edev) || ci->role_switch)
1307 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1311 static int ci_controller_resume(struct device *dev)
1313 struct ci_hdrc *ci = dev_get_drvdata(dev);
1316 dev_dbg(dev, "at %s\n", __func__);
1323 ci_hdrc_enter_lpm(ci, false);
1325 ret = ci_ulpi_resume(ci);
1330 usb_phy_set_suspend(ci->usb_phy, 0);
1331 usb_phy_set_wakeup(ci->usb_phy, false);
1332 hw_wait_phy_stable();
1336 if (ci->wakeup_int) {
1337 ci->wakeup_int = false;
1338 pm_runtime_mark_last_busy(ci->dev);
1339 pm_runtime_put_autosuspend(ci->dev);
1340 enable_irq(ci->irq);
1341 if (ci_otg_is_fsm_mode(ci))
1342 ci_otg_fsm_wakeup_by_srp(ci);
1343 ci_extcon_wakeup_int(ci);
1349 #ifdef CONFIG_PM_SLEEP
1350 static int ci_suspend(struct device *dev)
1352 struct ci_hdrc *ci = dev_get_drvdata(dev);
1355 flush_workqueue(ci->wq);
1357 * Controller needs to be active during suspend, otherwise the core
1358 * may run resume when the parent is at suspend if other driver's
1359 * suspend fails, it occurs before parent's suspend has not started,
1360 * but the core suspend has finished.
1363 pm_runtime_resume(dev);
1370 /* Extra routine per role before system suspend */
1371 if (ci->role != CI_ROLE_END && ci_role(ci)->suspend)
1372 ci_role(ci)->suspend(ci);
1374 if (device_may_wakeup(dev)) {
1375 if (ci_otg_is_fsm_mode(ci))
1376 ci_otg_fsm_suspend_for_srp(ci);
1378 usb_phy_set_wakeup(ci->usb_phy, true);
1379 enable_irq_wake(ci->irq);
1382 ci_controller_suspend(ci);
1387 static void ci_handle_power_lost(struct ci_hdrc *ci)
1391 disable_irq_nosync(ci->irq);
1392 if (!ci_otg_is_fsm_mode(ci)) {
1393 role = ci_get_role(ci);
1395 if (ci->role != role) {
1396 ci_handle_id_switch(ci);
1397 } else if (role == CI_ROLE_GADGET) {
1398 if (ci->is_otg && hw_read_otgsc(ci, OTGSC_BSV))
1399 usb_gadget_vbus_connect(&ci->gadget);
1403 enable_irq(ci->irq);
1406 static int ci_resume(struct device *dev)
1408 struct ci_hdrc *ci = dev_get_drvdata(dev);
1412 /* Since ASYNCLISTADDR (host mode) and ENDPTLISTADDR (device
1413 * mode) share the same register address. We can check if
1414 * controller resume from power lost based on this address
1415 * due to this register will be reset after power lost.
1417 power_lost = !hw_read(ci, OP_ENDPTLISTADDR, ~0);
1419 if (device_may_wakeup(dev))
1420 disable_irq_wake(ci->irq);
1422 ret = ci_controller_resume(dev);
1427 /* shutdown and re-init for phy */
1428 ci_usb_phy_exit(ci);
1429 ci_usb_phy_init(ci);
1432 /* Extra routine per role after system resume */
1433 if (ci->role != CI_ROLE_END && ci_role(ci)->resume)
1434 ci_role(ci)->resume(ci, power_lost);
1437 ci_handle_power_lost(ci);
1439 if (ci->supports_runtime_pm) {
1440 pm_runtime_disable(dev);
1441 pm_runtime_set_active(dev);
1442 pm_runtime_enable(dev);
1447 #endif /* CONFIG_PM_SLEEP */
1449 static int ci_runtime_suspend(struct device *dev)
1451 struct ci_hdrc *ci = dev_get_drvdata(dev);
1453 dev_dbg(dev, "at %s\n", __func__);
1460 if (ci_otg_is_fsm_mode(ci))
1461 ci_otg_fsm_suspend_for_srp(ci);
1463 usb_phy_set_wakeup(ci->usb_phy, true);
1464 ci_controller_suspend(ci);
1469 static int ci_runtime_resume(struct device *dev)
1471 return ci_controller_resume(dev);
1474 #endif /* CONFIG_PM */
1475 static const struct dev_pm_ops ci_pm_ops = {
1476 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1477 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1480 static struct platform_driver ci_hdrc_driver = {
1481 .probe = ci_hdrc_probe,
1482 .remove = ci_hdrc_remove,
1486 .dev_groups = ci_groups,
1490 static int __init ci_hdrc_platform_register(void)
1492 ci_hdrc_host_driver_init();
1493 return platform_driver_register(&ci_hdrc_driver);
1495 module_init(ci_hdrc_platform_register);
1497 static void __exit ci_hdrc_platform_unregister(void)
1499 platform_driver_unregister(&ci_hdrc_driver);
1501 module_exit(ci_hdrc_platform_unregister);
1503 MODULE_ALIAS("platform:ci_hdrc");
1504 MODULE_LICENSE("GPL v2");
1505 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1506 MODULE_DESCRIPTION("ChipIdea HDRC Driver");