1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 MediaTek Inc.
5 * Stanley Chu <stanley.chu@mediatek.com>
6 * Peter Wang <peter.wang@mediatek.com>
9 #include <linux/arm-smccc.h>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_qos.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/reset.h>
22 #include <linux/sched/clock.h>
23 #include <linux/soc/mediatek/mtk_sip_svc.h>
25 #include <ufs/ufshcd.h>
26 #include "ufshcd-pltfrm.h"
27 #include <ufs/ufs_quirks.h>
28 #include <ufs/unipro.h>
29 #include "ufs-mediatek.h"
31 #define CREATE_TRACE_POINTS
32 #include "ufs-mediatek-trace.h"
34 static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
35 { .wmanufacturerid = UFS_ANY_VENDOR,
36 .model = UFS_ANY_MODEL,
37 .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM |
38 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
39 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
40 .model = "H9HQ21AFAMZDAR",
41 .quirk = UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES },
45 static const struct of_device_id ufs_mtk_of_match[] = {
46 { .compatible = "mediatek,mt8183-ufshci" },
50 static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
52 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
54 return !!(host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE);
57 static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba)
59 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
61 return !!(host->caps & UFS_MTK_CAP_VA09_PWR_CTRL);
64 static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba)
66 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
68 return !!(host->caps & UFS_MTK_CAP_BROKEN_VCC);
71 static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba)
73 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
75 return (host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);
78 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
84 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
86 (1 << RX_SYMBOL_CLK_GATE_EN) |
87 (1 << SYS_CLK_GATE_EN) |
88 (1 << TX_CLK_GATE_EN);
90 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
93 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
94 tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
96 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
99 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
100 tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
101 (1 << SYS_CLK_GATE_EN) |
102 (1 << TX_CLK_GATE_EN));
104 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
107 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
108 tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
110 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
114 static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
116 struct arm_smccc_res res;
118 ufs_mtk_crypto_ctrl(res, 1);
120 dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
122 hba->caps &= ~UFSHCD_CAP_CRYPTO;
126 static void ufs_mtk_host_reset(struct ufs_hba *hba)
128 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
130 reset_control_assert(host->hci_reset);
131 reset_control_assert(host->crypto_reset);
132 reset_control_assert(host->unipro_reset);
134 usleep_range(100, 110);
136 reset_control_deassert(host->unipro_reset);
137 reset_control_deassert(host->crypto_reset);
138 reset_control_deassert(host->hci_reset);
141 static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
142 struct reset_control **rc,
145 *rc = devm_reset_control_get(hba->dev, str);
147 dev_info(hba->dev, "Failed to get reset control %s: %ld\n",
153 static void ufs_mtk_init_reset(struct ufs_hba *hba)
155 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
157 ufs_mtk_init_reset_control(hba, &host->hci_reset,
159 ufs_mtk_init_reset_control(hba, &host->unipro_reset,
161 ufs_mtk_init_reset_control(hba, &host->crypto_reset,
165 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
166 enum ufs_notify_change_status status)
168 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
170 if (status == PRE_CHANGE) {
171 if (host->unipro_lpm) {
172 hba->vps->hba_enable_delay_us = 0;
174 hba->vps->hba_enable_delay_us = 600;
175 ufs_mtk_host_reset(hba);
178 if (hba->caps & UFSHCD_CAP_CRYPTO)
179 ufs_mtk_crypto_enable(hba);
181 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) {
182 ufshcd_writel(hba, 0,
183 REG_AUTO_HIBERNATE_IDLE_TIMER);
184 hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT;
189 * Turn on CLK_CG early to bypass abnormal ERR_CHK signal
190 * to prevent host hang issue
193 ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80,
200 static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
202 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
203 struct device *dev = hba->dev;
204 struct device_node *np = dev->of_node;
207 host->mphy = devm_of_phy_get_by_index(dev, np, 0);
209 if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
211 * UFS driver might be probed before the phy driver does.
212 * In that case we would like to return EPROBE_DEFER code.
216 "%s: required phy hasn't probed yet. err = %d\n",
218 } else if (IS_ERR(host->mphy)) {
219 err = PTR_ERR(host->mphy);
220 if (err != -ENODEV) {
221 dev_info(dev, "%s: PHY get failed %d\n", __func__,
229 * Allow unbound mphy because not every platform needs specific
238 static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
240 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
241 struct arm_smccc_res res;
242 ktime_t timeout, time_checked;
245 if (host->ref_clk_enabled == on)
248 ufs_mtk_ref_clk_notify(on, PRE_CHANGE, res);
251 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
253 ufshcd_delay_us(host->ref_clk_gating_wait_us, 10);
254 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
258 timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US);
260 time_checked = ktime_get();
261 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
263 /* Wait until ack bit equals to req bit */
264 if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
267 usleep_range(100, 200);
268 } while (ktime_before(time_checked, timeout));
270 dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
272 ufs_mtk_ref_clk_notify(host->ref_clk_enabled, POST_CHANGE, res);
277 host->ref_clk_enabled = on;
279 ufshcd_delay_us(host->ref_clk_ungating_wait_us, 10);
281 ufs_mtk_ref_clk_notify(on, POST_CHANGE, res);
286 static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
289 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
291 if (hba->dev_info.clk_gating_wait_us) {
292 host->ref_clk_gating_wait_us =
293 hba->dev_info.clk_gating_wait_us;
295 host->ref_clk_gating_wait_us = gating_us;
298 host->ref_clk_ungating_wait_us = REFCLK_DEFAULT_WAIT_US;
301 static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
303 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
305 if (((host->ip_ver >> 16) & 0xFF) >= 0x36) {
306 ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
307 ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
308 ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
309 ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2);
310 ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3);
312 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
316 static void ufs_mtk_wait_idle_state(struct ufs_hba *hba,
317 unsigned long retry_ms)
319 u64 timeout, time_checked;
323 /* cannot use plain ktime_get() in suspend */
324 timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL;
326 /* wait a specific time after check base */
331 time_checked = ktime_get_mono_fast_ns();
332 ufs_mtk_dbg_sel(hba);
333 val = ufshcd_readl(hba, REG_UFS_PROBE);
338 * if state is in H8 enter and H8 enter confirm
339 * wait until return to idle state.
341 if ((sm >= VS_HIB_ENTER) && (sm <= VS_HIB_EXIT)) {
345 } else if (!wait_idle)
348 if (wait_idle && (sm == VS_HCE_BASE))
350 } while (time_checked < timeout);
352 if (wait_idle && sm != VS_HCE_BASE)
353 dev_info(hba->dev, "wait idle tmo: 0x%x\n", val);
356 static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
357 unsigned long max_wait_ms)
359 ktime_t timeout, time_checked;
362 timeout = ktime_add_ms(ktime_get(), max_wait_ms);
364 time_checked = ktime_get();
365 ufs_mtk_dbg_sel(hba);
366 val = ufshcd_readl(hba, REG_UFS_PROBE);
372 /* Sleep for max. 200us */
373 usleep_range(100, 200);
374 } while (ktime_before(time_checked, timeout));
382 static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
384 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
385 struct phy *mphy = host->mphy;
386 struct arm_smccc_res res;
389 if (!mphy || !(on ^ host->mphy_powered_on))
393 if (ufs_mtk_is_va09_supported(hba)) {
394 ret = regulator_enable(host->reg_va09);
397 /* wait 200 us to stablize VA09 */
398 usleep_range(200, 210);
399 ufs_mtk_va09_pwr_ctrl(res, 1);
404 if (ufs_mtk_is_va09_supported(hba)) {
405 ufs_mtk_va09_pwr_ctrl(res, 0);
406 ret = regulator_disable(host->reg_va09);
414 "failed to %s va09: %d\n",
415 on ? "enable" : "disable",
418 host->mphy_powered_on = on;
424 static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
425 struct clk **clk_out)
430 clk = devm_clk_get(dev, name);
439 static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
441 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
442 struct ufs_mtk_crypt_cfg *cfg;
443 struct regulator *reg;
446 if (!ufs_mtk_is_boost_crypt_enabled(hba))
450 volt = cfg->vcore_volt;
451 reg = cfg->reg_vcore;
453 ret = clk_prepare_enable(cfg->clk_crypt_mux);
455 dev_info(hba->dev, "clk_prepare_enable(): %d\n",
461 ret = regulator_set_voltage(reg, volt, INT_MAX);
464 "failed to set vcore to %d\n", volt);
468 ret = clk_set_parent(cfg->clk_crypt_mux,
469 cfg->clk_crypt_perf);
472 "failed to set clk_crypt_perf\n");
473 regulator_set_voltage(reg, 0, INT_MAX);
477 ret = clk_set_parent(cfg->clk_crypt_mux,
481 "failed to set clk_crypt_lp\n");
485 ret = regulator_set_voltage(reg, 0, INT_MAX);
488 "failed to set vcore to MIN\n");
492 clk_disable_unprepare(cfg->clk_crypt_mux);
495 static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
500 ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
502 dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
509 static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
511 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
512 struct ufs_mtk_crypt_cfg *cfg;
513 struct device *dev = hba->dev;
514 struct regulator *reg;
517 host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
522 reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
524 dev_info(dev, "failed to get dvfsrc-vcore: %ld",
529 if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min",
531 dev_info(dev, "failed to get boost-crypt-vcore-min");
536 if (ufs_mtk_init_host_clk(hba, "crypt_mux",
537 &cfg->clk_crypt_mux))
540 if (ufs_mtk_init_host_clk(hba, "crypt_lp",
544 if (ufs_mtk_init_host_clk(hba, "crypt_perf",
545 &cfg->clk_crypt_perf))
548 cfg->reg_vcore = reg;
549 cfg->vcore_volt = volt;
550 host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
556 static void ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba *hba)
558 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
560 host->reg_va09 = regulator_get(hba->dev, "va09");
561 if (IS_ERR(host->reg_va09))
562 dev_info(hba->dev, "failed to get va09");
564 host->caps |= UFS_MTK_CAP_VA09_PWR_CTRL;
567 static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
569 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
570 struct device_node *np = hba->dev->of_node;
572 if (of_property_read_bool(np, "mediatek,ufs-boost-crypt"))
573 ufs_mtk_init_boost_crypt(hba);
575 if (of_property_read_bool(np, "mediatek,ufs-support-va09"))
576 ufs_mtk_init_va09_pwr_ctrl(hba);
578 if (of_property_read_bool(np, "mediatek,ufs-disable-ah8"))
579 host->caps |= UFS_MTK_CAP_DISABLE_AH8;
581 if (of_property_read_bool(np, "mediatek,ufs-broken-vcc"))
582 host->caps |= UFS_MTK_CAP_BROKEN_VCC;
584 if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto"))
585 host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO;
587 dev_info(hba->dev, "caps: 0x%x", host->caps);
590 static void ufs_mtk_boost_pm_qos(struct ufs_hba *hba, bool boost)
592 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
594 if (!host || !host->pm_qos_init)
597 cpu_latency_qos_update_request(&host->pm_qos_req,
598 boost ? 0 : PM_QOS_DEFAULT_VALUE);
601 static void ufs_mtk_pwr_ctrl(struct ufs_hba *hba, bool on)
603 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
606 phy_power_on(host->mphy);
607 ufs_mtk_setup_ref_clk(hba, on);
608 ufs_mtk_boost_crypt(hba, on);
609 ufs_mtk_boost_pm_qos(hba, on);
611 ufs_mtk_boost_pm_qos(hba, on);
612 ufs_mtk_boost_crypt(hba, on);
613 ufs_mtk_setup_ref_clk(hba, on);
614 phy_power_off(host->mphy);
619 * ufs_mtk_setup_clocks - enables/disable clocks
620 * @hba: host controller instance
621 * @on: If true, enable clocks else disable them.
622 * @status: PRE_CHANGE or POST_CHANGE notify
624 * Returns 0 on success, non-zero on failure.
626 static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
627 enum ufs_notify_change_status status)
629 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
630 bool clk_pwr_off = false;
634 * In case ufs_mtk_init() is not yet done, simply ignore.
635 * This ufs_mtk_setup_clocks() shall be called from
636 * ufs_mtk_init() after init is done.
641 if (!on && status == PRE_CHANGE) {
642 if (ufshcd_is_link_off(hba)) {
644 } else if (ufshcd_is_link_hibern8(hba) ||
645 (!ufshcd_can_hibern8_during_gating(hba) &&
646 ufshcd_is_auto_hibern8_enabled(hba))) {
648 * Gate ref-clk and poweroff mphy if link state is in
649 * OFF or Hibern8 by either Auto-Hibern8 or
650 * ufshcd_link_state_transition().
652 ret = ufs_mtk_wait_link_state(hba,
660 ufs_mtk_pwr_ctrl(hba, false);
661 } else if (on && status == POST_CHANGE) {
662 ufs_mtk_pwr_ctrl(hba, true);
668 static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
670 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
673 if (host->hw_ver.major)
676 /* Set default (minimum) version anyway */
677 host->hw_ver.major = 2;
679 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &ver);
681 if (ver >= UFS_UNIPRO_VER_1_8) {
682 host->hw_ver.major = 3;
684 * Fix HCI version for some platforms with
687 if (hba->ufs_version < ufshci_version(3, 0))
688 hba->ufs_version = ufshci_version(3, 0);
693 static u32 ufs_mtk_get_ufs_hci_version(struct ufs_hba *hba)
695 return hba->ufs_version;
698 #define MAX_VCC_NAME 30
699 static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba)
701 struct ufs_vreg_info *info = &hba->vreg_info;
702 struct device_node *np = hba->dev->of_node;
703 struct device *dev = hba->dev;
704 char vcc_name[MAX_VCC_NAME];
705 struct arm_smccc_res res;
708 if (hba->vreg_info.vcc)
711 if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) {
712 ufs_mtk_get_vcc_num(res);
713 if (res.a1 > UFS_VCC_NONE && res.a1 < UFS_VCC_MAX)
714 snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%lu", res.a1);
717 } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) {
718 ver = (hba->dev_info.wspecversion & 0xF00) >> 8;
719 snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver);
724 err = ufshcd_populate_vreg(dev, vcc_name, &info->vcc);
728 err = ufshcd_get_vreg(dev, info->vcc);
732 err = regulator_enable(info->vcc->reg);
734 info->vcc->enabled = true;
735 dev_info(dev, "%s: %s enabled\n", __func__, vcc_name);
741 static void ufs_mtk_vreg_fix_vccqx(struct ufs_hba *hba)
743 struct ufs_vreg_info *info = &hba->vreg_info;
744 struct ufs_vreg **vreg_on, **vreg_off;
746 if (hba->dev_info.wspecversion >= 0x0300) {
747 vreg_on = &info->vccq;
748 vreg_off = &info->vccq2;
750 vreg_on = &info->vccq2;
751 vreg_off = &info->vccq;
755 (*vreg_on)->always_on = true;
758 regulator_disable((*vreg_off)->reg);
759 devm_kfree(hba->dev, (*vreg_off)->name);
760 devm_kfree(hba->dev, *vreg_off);
766 * ufs_mtk_init - find other essential mmio bases
767 * @hba: host controller instance
769 * Binds PHY with controller and powers up PHY enabling clocks
772 * Returns -EPROBE_DEFER if binding fails, returns negative error
773 * on phy power up failure and returns zero on success.
775 static int ufs_mtk_init(struct ufs_hba *hba)
777 const struct of_device_id *id;
778 struct device *dev = hba->dev;
779 struct ufs_mtk_host *host;
782 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
785 dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
790 ufshcd_set_variant(hba, host);
792 id = of_match_device(ufs_mtk_of_match, dev);
798 /* Initialize host capability */
799 ufs_mtk_init_host_caps(hba);
801 err = ufs_mtk_bind_mphy(hba);
803 goto out_variant_clear;
805 ufs_mtk_init_reset(hba);
807 /* Enable runtime autosuspend */
808 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
810 /* Enable clock-gating */
811 hba->caps |= UFSHCD_CAP_CLK_GATING;
813 /* Enable inline encryption */
814 hba->caps |= UFSHCD_CAP_CRYPTO;
816 /* Enable WriteBooster */
817 hba->caps |= UFSHCD_CAP_WB_EN;
818 hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
819 hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
821 if (host->caps & UFS_MTK_CAP_DISABLE_AH8)
822 hba->caps |= UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
825 * ufshcd_vops_init() is invoked after
826 * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
827 * phy clock setup is skipped.
829 * Enable phy clocks specifically here.
831 ufs_mtk_mphy_power_on(hba, true);
832 ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
834 host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
839 ufshcd_set_variant(hba, NULL);
844 static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba,
845 struct ufs_pa_layer_attr *dev_req_params)
847 if (!ufs_mtk_is_pmc_via_fastauto(hba))
850 if (dev_req_params->hs_rate == hba->pwr_info.hs_rate)
853 if (dev_req_params->pwr_tx != FAST_MODE &&
854 dev_req_params->gear_tx < UFS_HS_G4)
857 if (dev_req_params->pwr_rx != FAST_MODE &&
858 dev_req_params->gear_rx < UFS_HS_G4)
864 static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
865 struct ufs_pa_layer_attr *dev_max_params,
866 struct ufs_pa_layer_attr *dev_req_params)
868 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
869 struct ufs_dev_params host_cap;
872 ufshcd_init_pwr_dev_param(&host_cap);
873 host_cap.hs_rx_gear = UFS_HS_G5;
874 host_cap.hs_tx_gear = UFS_HS_G5;
876 ret = ufshcd_get_pwr_dev_param(&host_cap,
880 pr_info("%s: failed to determine capabilities\n",
884 if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) {
885 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
886 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), UFS_HS_G1);
888 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
889 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), UFS_HS_G1);
891 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
892 dev_req_params->lane_tx);
893 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
894 dev_req_params->lane_rx);
895 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
896 dev_req_params->hs_rate);
898 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE),
901 ret = ufshcd_uic_change_pwr_mode(hba,
902 FASTAUTO_MODE << 4 | FASTAUTO_MODE);
905 dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=%d\n",
910 if (host->hw_ver.major >= 3) {
911 ret = ufshcd_dme_configure_adapt(hba,
912 dev_req_params->gear_tx,
919 static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
920 enum ufs_notify_change_status stage,
921 struct ufs_pa_layer_attr *dev_max_params,
922 struct ufs_pa_layer_attr *dev_req_params)
928 ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
941 static int ufs_mtk_unipro_set_lpm(struct ufs_hba *hba, bool lpm)
944 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
946 ret = ufshcd_dme_set(hba,
947 UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
951 * Forcibly set as non-LPM mode if UIC commands is failed
952 * to use default hba_enable_delay_us value for re-enabling
955 host->unipro_lpm = lpm;
961 static int ufs_mtk_pre_link(struct ufs_hba *hba)
966 ufs_mtk_get_controller_version(hba);
968 ret = ufs_mtk_unipro_set_lpm(hba, false);
973 * Setting PA_Local_TX_LCC_Enable to 0 before link startup
974 * to make sure that both host and device TX LCC are disabled
975 * once link startup is completed.
977 ret = ufshcd_disable_host_tx_lcc(hba);
981 /* disable deep stall */
982 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
988 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
993 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
997 if (ufshcd_is_clkgating_allowed(hba)) {
998 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
999 ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
1003 ufshcd_clkgate_delay_set(hba->dev, ah_ms + 5);
1007 static int ufs_mtk_post_link(struct ufs_hba *hba)
1009 /* enable unipro clock gating feature */
1010 ufs_mtk_cfg_unipro_cg(hba, true);
1012 /* will be configured during probe hba */
1013 if (ufshcd_is_auto_hibern8_supported(hba))
1014 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
1015 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
1017 ufs_mtk_setup_clk_gating(hba);
1022 static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
1023 enum ufs_notify_change_status stage)
1029 ret = ufs_mtk_pre_link(hba);
1032 ret = ufs_mtk_post_link(hba);
1042 static int ufs_mtk_device_reset(struct ufs_hba *hba)
1044 struct arm_smccc_res res;
1046 /* disable hba before device reset */
1047 ufshcd_hba_stop(hba);
1049 ufs_mtk_device_reset_ctrl(0, res);
1052 * The reset signal is active low. UFS devices shall detect
1053 * more than or equal to 1us of positive or negative RST_n
1056 * To be on safe side, keep the reset low for at least 10us.
1058 usleep_range(10, 15);
1060 ufs_mtk_device_reset_ctrl(1, res);
1062 /* Some devices may need time to respond to rst_n */
1063 usleep_range(10000, 15000);
1065 dev_info(hba->dev, "device reset done\n");
1070 static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
1074 err = ufshcd_hba_enable(hba);
1078 err = ufs_mtk_unipro_set_lpm(hba, false);
1082 err = ufshcd_uic_hibern8_exit(hba);
1084 ufshcd_set_link_active(hba);
1088 err = ufshcd_make_hba_operational(hba);
1095 static int ufs_mtk_link_set_lpm(struct ufs_hba *hba)
1099 /* Disable reset confirm feature by UniPro */
1101 (ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) & ~0x100),
1102 REG_UFS_XOUFS_CTRL);
1104 err = ufs_mtk_unipro_set_lpm(hba, true);
1106 /* Resume UniPro state for following error recovery */
1107 ufs_mtk_unipro_set_lpm(hba, false);
1114 static void ufs_mtk_vccqx_set_lpm(struct ufs_hba *hba, bool lpm)
1116 struct ufs_vreg *vccqx = NULL;
1118 if (hba->vreg_info.vccq)
1119 vccqx = hba->vreg_info.vccq;
1121 vccqx = hba->vreg_info.vccq2;
1123 regulator_set_mode(vccqx->reg,
1124 lpm ? REGULATOR_MODE_IDLE : REGULATOR_MODE_NORMAL);
1127 static void ufs_mtk_vsx_set_lpm(struct ufs_hba *hba, bool lpm)
1129 struct arm_smccc_res res;
1131 ufs_mtk_device_pwr_ctrl(!lpm,
1132 (unsigned long)hba->dev_info.wspecversion,
1136 static void ufs_mtk_dev_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
1138 if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
1141 /* Skip if VCC is assumed always-on */
1142 if (!hba->vreg_info.vcc)
1145 /* Bypass LPM when device is still active */
1146 if (lpm && ufshcd_is_ufs_dev_active(hba))
1149 /* Bypass LPM if VCC is enabled */
1150 if (lpm && hba->vreg_info.vcc->enabled)
1154 ufs_mtk_vccqx_set_lpm(hba, lpm);
1155 ufs_mtk_vsx_set_lpm(hba, lpm);
1157 ufs_mtk_vsx_set_lpm(hba, lpm);
1158 ufs_mtk_vccqx_set_lpm(hba, lpm);
1162 static void ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
1166 /* disable auto-hibern8 */
1167 ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
1169 /* wait host return to idle state when auto-hibern8 off */
1170 ufs_mtk_wait_idle_state(hba, 5);
1172 ret = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
1174 dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret);
1177 static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
1178 enum ufs_notify_change_status status)
1181 struct arm_smccc_res res;
1183 if (status == PRE_CHANGE) {
1184 if (!ufshcd_is_auto_hibern8_supported(hba))
1186 ufs_mtk_auto_hibern8_disable(hba);
1190 if (ufshcd_is_link_hibern8(hba)) {
1191 err = ufs_mtk_link_set_lpm(hba);
1196 if (!ufshcd_is_link_active(hba)) {
1198 * Make sure no error will be returned to prevent
1199 * ufshcd_suspend() re-enabling regulators while vreg is still
1200 * in low-power mode.
1202 err = ufs_mtk_mphy_power_on(hba, false);
1207 if (ufshcd_is_link_off(hba))
1208 ufs_mtk_device_reset_ctrl(0, res);
1210 ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, false, res);
1215 * Set link as off state enforcedly to trigger
1216 * ufshcd_host_reset_and_restore() in ufshcd_suspend()
1217 * for completed host reset.
1219 ufshcd_set_link_off(hba);
1223 static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1226 struct arm_smccc_res res;
1228 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
1229 ufs_mtk_dev_vreg_set_lpm(hba, false);
1231 ufs_mtk_host_pwr_ctrl(HOST_PWR_HCI, true, res);
1233 err = ufs_mtk_mphy_power_on(hba, true);
1237 if (ufshcd_is_link_hibern8(hba)) {
1238 err = ufs_mtk_link_set_hpm(hba);
1245 return ufshcd_link_recovery(hba);
1248 static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
1250 ufshcd_dump_regs(hba, REG_UFS_REFCLK_CTRL, 0x4, "Ref-Clk Ctrl ");
1252 ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg ");
1254 ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL,
1255 REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4,
1258 /* Direct debugging information to REG_MTK_PROBE */
1259 ufs_mtk_dbg_sel(hba);
1260 ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
1263 static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
1265 struct ufs_dev_info *dev_info = &hba->dev_info;
1266 u16 mid = dev_info->wmanufacturerid;
1268 if (mid == UFS_VENDOR_SAMSUNG) {
1269 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
1270 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10);
1274 * Decide waiting time before gating reference clock and
1275 * after ungating reference clock according to vendors'
1278 if (mid == UFS_VENDOR_SAMSUNG)
1279 ufs_mtk_setup_ref_clk_wait_us(hba, 1);
1280 else if (mid == UFS_VENDOR_SKHYNIX)
1281 ufs_mtk_setup_ref_clk_wait_us(hba, 30);
1282 else if (mid == UFS_VENDOR_TOSHIBA)
1283 ufs_mtk_setup_ref_clk_wait_us(hba, 100);
1285 ufs_mtk_setup_ref_clk_wait_us(hba,
1286 REFCLK_DEFAULT_WAIT_US);
1290 static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
1292 ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
1294 if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc &&
1295 (hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)) {
1296 hba->vreg_info.vcc->always_on = true;
1298 * VCC will be kept always-on thus we don't
1299 * need any delay during regulator operations
1301 hba->dev_quirks &= ~(UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
1302 UFS_DEVICE_QUIRK_DELAY_AFTER_LPM);
1305 ufs_mtk_vreg_fix_vcc(hba);
1306 ufs_mtk_vreg_fix_vccqx(hba);
1309 static void ufs_mtk_event_notify(struct ufs_hba *hba,
1310 enum ufs_event_type evt, void *data)
1312 unsigned int val = *(u32 *)data;
1314 trace_ufs_mtk_event(evt, val);
1318 * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
1320 * The variant operations configure the necessary controller and PHY
1321 * handshake during initialization.
1323 static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
1324 .name = "mediatek.ufshci",
1325 .init = ufs_mtk_init,
1326 .get_ufs_hci_version = ufs_mtk_get_ufs_hci_version,
1327 .setup_clocks = ufs_mtk_setup_clocks,
1328 .hce_enable_notify = ufs_mtk_hce_enable_notify,
1329 .link_startup_notify = ufs_mtk_link_startup_notify,
1330 .pwr_change_notify = ufs_mtk_pwr_change_notify,
1331 .apply_dev_quirks = ufs_mtk_apply_dev_quirks,
1332 .fixup_dev_quirks = ufs_mtk_fixup_dev_quirks,
1333 .suspend = ufs_mtk_suspend,
1334 .resume = ufs_mtk_resume,
1335 .dbg_register_dump = ufs_mtk_dbg_register_dump,
1336 .device_reset = ufs_mtk_device_reset,
1337 .event_notify = ufs_mtk_event_notify,
1341 * ufs_mtk_probe - probe routine of the driver
1342 * @pdev: pointer to Platform device handle
1344 * Return zero for success and non-zero for failure
1346 static int ufs_mtk_probe(struct platform_device *pdev)
1349 struct device *dev = &pdev->dev;
1350 struct device_node *reset_node;
1351 struct platform_device *reset_pdev;
1352 struct device_link *link;
1354 reset_node = of_find_compatible_node(NULL, NULL,
1357 dev_notice(dev, "find ti,syscon-reset fail\n");
1360 reset_pdev = of_find_device_by_node(reset_node);
1362 dev_notice(dev, "find reset_pdev fail\n");
1365 link = device_link_add(dev, &reset_pdev->dev,
1366 DL_FLAG_AUTOPROBE_CONSUMER);
1367 put_device(&reset_pdev->dev);
1369 dev_notice(dev, "add reset device_link fail\n");
1372 /* supplier is not probed */
1373 if (link->status == DL_STATE_DORMANT) {
1374 err = -EPROBE_DEFER;
1379 /* perform generic probe */
1380 err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
1384 dev_info(dev, "probe failed %d\n", err);
1386 of_node_put(reset_node);
1391 * ufs_mtk_remove - set driver_data of the device to NULL
1392 * @pdev: pointer to platform device handle
1396 static int ufs_mtk_remove(struct platform_device *pdev)
1398 struct ufs_hba *hba = platform_get_drvdata(pdev);
1400 pm_runtime_get_sync(&(pdev)->dev);
1405 #ifdef CONFIG_PM_SLEEP
1406 static int ufs_mtk_system_suspend(struct device *dev)
1408 struct ufs_hba *hba = dev_get_drvdata(dev);
1411 ret = ufshcd_system_suspend(dev);
1415 ufs_mtk_dev_vreg_set_lpm(hba, true);
1420 static int ufs_mtk_system_resume(struct device *dev)
1422 struct ufs_hba *hba = dev_get_drvdata(dev);
1424 ufs_mtk_dev_vreg_set_lpm(hba, false);
1426 return ufshcd_system_resume(dev);
1430 static int ufs_mtk_runtime_suspend(struct device *dev)
1432 struct ufs_hba *hba = dev_get_drvdata(dev);
1435 ret = ufshcd_runtime_suspend(dev);
1439 ufs_mtk_dev_vreg_set_lpm(hba, true);
1444 static int ufs_mtk_runtime_resume(struct device *dev)
1446 struct ufs_hba *hba = dev_get_drvdata(dev);
1448 ufs_mtk_dev_vreg_set_lpm(hba, false);
1450 return ufshcd_runtime_resume(dev);
1453 static const struct dev_pm_ops ufs_mtk_pm_ops = {
1454 SET_SYSTEM_SLEEP_PM_OPS(ufs_mtk_system_suspend,
1455 ufs_mtk_system_resume)
1456 SET_RUNTIME_PM_OPS(ufs_mtk_runtime_suspend,
1457 ufs_mtk_runtime_resume, NULL)
1458 .prepare = ufshcd_suspend_prepare,
1459 .complete = ufshcd_resume_complete,
1462 static struct platform_driver ufs_mtk_pltform = {
1463 .probe = ufs_mtk_probe,
1464 .remove = ufs_mtk_remove,
1465 .shutdown = ufshcd_pltfrm_shutdown,
1467 .name = "ufshcd-mtk",
1468 .pm = &ufs_mtk_pm_ops,
1469 .of_match_table = ufs_mtk_of_match,
1473 MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
1474 MODULE_AUTHOR("Peter Wang <peter.wang@mediatek.com>");
1475 MODULE_DESCRIPTION("MediaTek UFS Host Driver");
1476 MODULE_LICENSE("GPL v2");
1478 module_platform_driver(ufs_mtk_pltform);