drivers/ufs/host/ufs-mediatek.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 MediaTek Inc.
   4  * Authors:
   5  *      Stanley Chu <stanley.chu@mediatek.com>
   6  *      Peter Wang <peter.wang@mediatek.com>
   7  */
   8
   9 #include <linux/arm-smccc.h>
  10 #include <linux/bitfield.h>
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_device.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/sched/clock.h>
  22 #include <linux/soc/mediatek/mtk_sip_svc.h>
  23
  24 #include <ufs/ufshcd.h>
  25 #include "ufshcd-pltfrm.h"
  26 #include <ufs/ufs_quirks.h>
  27 #include <ufs/unipro.h>
  28 #include "ufs-mediatek.h"
  29
  30 #define CREATE_TRACE_POINTS
  31 #include "ufs-mediatek-trace.h"
  32
  33 static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
  34         { .wmanufacturerid = UFS_ANY_VENDOR,
  35           .model = UFS_ANY_MODEL,
  36           .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM |
  37                 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
  38         { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
  39           .model = "H9HQ21AFAMZDAR",
  40           .quirk = UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES },
  41         {}
  42 };
  43
  44 static const struct of_device_id ufs_mtk_of_match[] = {
  45         { .compatible = "mediatek,mt8183-ufshci" },
  46         {},
  47 };
  48
  49 static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
  50 {
  51         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
  52
  53         return !!(host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE);
  54 }
  55
  56 static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba)
  57 {
  58         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
  59
  60         return !!(host->caps & UFS_MTK_CAP_VA09_PWR_CTRL);
  61 }
  62
  63 static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba)
  64 {
  65         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
  66
  67         return !!(host->caps & UFS_MTK_CAP_BROKEN_VCC);
  68 }
  69
  70 static bool ufs_mtk_is_pmc_via_fastauto(struct ufs_hba *hba)
  71 {
  72         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
  73
  74         return (host->caps & UFS_MTK_CAP_PMC_VIA_FASTAUTO);
  75 }
  76
  77 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
  78 {
  79         u32 tmp;
  80
  81         if (enable) {
  82                 ufshcd_dme_get(hba,
  83                                UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
  84                 tmp = tmp |
  85                       (1 << RX_SYMBOL_CLK_GATE_EN) |
  86                       (1 << SYS_CLK_GATE_EN) |
  87                       (1 << TX_CLK_GATE_EN);
  88                 ufshcd_dme_set(hba,
  89                                UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
  90
  91                 ufshcd_dme_get(hba,
  92                                UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
  93                 tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
  94                 ufshcd_dme_set(hba,
  95                                UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
  96         } else {
  97                 ufshcd_dme_get(hba,
  98                                UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
  99                 tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
 100                               (1 << SYS_CLK_GATE_EN) |
 101                               (1 << TX_CLK_GATE_EN));
 102                 ufshcd_dme_set(hba,
 103                                UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
 104
 105                 ufshcd_dme_get(hba,
 106                                UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
 107                 tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
 108                 ufshcd_dme_set(hba,
 109                                UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
 110         }
 111 }
 112
 113 static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
 114 {
 115         struct arm_smccc_res res;
 116
 117         ufs_mtk_crypto_ctrl(res, 1);
 118         if (res.a0) {
 119                 dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
 120                          __func__, res.a0);
 121                 hba->caps &= ~UFSHCD_CAP_CRYPTO;
 122         }
 123 }
 124
 125 static void ufs_mtk_host_reset(struct ufs_hba *hba)
 126 {
 127         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 128
 129         reset_control_assert(host->hci_reset);
 130         reset_control_assert(host->crypto_reset);
 131         reset_control_assert(host->unipro_reset);
 132
 133         usleep_range(100, 110);
 134
 135         reset_control_deassert(host->unipro_reset);
 136         reset_control_deassert(host->crypto_reset);
 137         reset_control_deassert(host->hci_reset);
 138 }
 139
 140 static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
 141                                        struct reset_control **rc,
 142                                        char *str)
 143 {
 144         *rc = devm_reset_control_get(hba->dev, str);
 145         if (IS_ERR(*rc)) {
 146                 dev_info(hba->dev, "Failed to get reset control %s: %ld\n",
 147                          str, PTR_ERR(*rc));
 148                 *rc = NULL;
 149         }
 150 }
 151
 152 static void ufs_mtk_init_reset(struct ufs_hba *hba)
 153 {
 154         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 155
 156         ufs_mtk_init_reset_control(hba, &host->hci_reset,
 157                                    "hci_rst");
 158         ufs_mtk_init_reset_control(hba, &host->unipro_reset,
 159                                    "unipro_rst");
 160         ufs_mtk_init_reset_control(hba, &host->crypto_reset,
 161                                    "crypto_rst");
 162 }
 163
 164 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
 165                                      enum ufs_notify_change_status status)
 166 {
 167         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 168
 169         if (status == PRE_CHANGE) {
 170                 if (host->unipro_lpm) {
 171                         hba->vps->hba_enable_delay_us = 0;
 172                 } else {
 173                         hba->vps->hba_enable_delay_us = 600;
 174                         ufs_mtk_host_reset(hba);
 175                 }
 176
 177                 if (hba->caps & UFSHCD_CAP_CRYPTO)
 178                         ufs_mtk_crypto_enable(hba);
 179
 180                 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) {
 181                         ufshcd_writel(hba, 0,
 182                                       REG_AUTO_HIBERNATE_IDLE_TIMER);
 183                         hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT;
 184                         hba->ahit = 0;
 185                 }
 186         }
 187
 188         return 0;
 189 }
 190
 191 static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
 192 {
 193         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 194         struct device *dev = hba->dev;
 195         struct device_node *np = dev->of_node;
 196         int err = 0;
 197
 198         host->mphy = devm_of_phy_get_by_index(dev, np, 0);
 199
 200         if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
 201                 /*
 202                  * UFS driver might be probed before the phy driver does.
 203                  * In that case we would like to return EPROBE_DEFER code.
 204                  */
 205                 err = -EPROBE_DEFER;
 206                 dev_info(dev,
 207                          "%s: required phy hasn't probed yet. err = %d\n",
 208                         __func__, err);
 209         } else if (IS_ERR(host->mphy)) {
 210                 err = PTR_ERR(host->mphy);
 211                 if (err != -ENODEV) {
 212                         dev_info(dev, "%s: PHY get failed %d\n", __func__,
 213                                  err);
 214                 }
 215         }
 216
 217         if (err)
 218                 host->mphy = NULL;
 219         /*
 220          * Allow unbound mphy because not every platform needs specific
 221          * mphy control.
 222          */
 223         if (err == -ENODEV)
 224                 err = 0;
 225
 226         return err;
 227 }
 228
 229 static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
 230 {
 231         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 232         struct arm_smccc_res res;
 233         ktime_t timeout, time_checked;
 234         u32 value;
 235
 236         if (host->ref_clk_enabled == on)
 237                 return 0;
 238
 239         if (on) {
 240                 ufs_mtk_ref_clk_notify(on, res);
 241                 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
 242         } else {
 243                 ufshcd_delay_us(host->ref_clk_gating_wait_us, 10);
 244                 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
 245         }
 246
 247         /* Wait for ack */
 248         timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US);
 249         do {
 250                 time_checked = ktime_get();
 251                 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
 252
 253                 /* Wait until ack bit equals to req bit */
 254                 if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
 255                         goto out;
 256
 257                 usleep_range(100, 200);
 258         } while (ktime_before(time_checked, timeout));
 259
 260         dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
 261
 262         ufs_mtk_ref_clk_notify(host->ref_clk_enabled, res);
 263
 264         return -ETIMEDOUT;
 265
 266 out:
 267         host->ref_clk_enabled = on;
 268         if (on)
 269                 ufshcd_delay_us(host->ref_clk_ungating_wait_us, 10);
 270         else
 271                 ufs_mtk_ref_clk_notify(on, res);
 272
 273         return 0;
 274 }
 275
 276 static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
 277                                           u16 gating_us)
 278 {
 279         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 280
 281         if (hba->dev_info.clk_gating_wait_us) {
 282                 host->ref_clk_gating_wait_us =
 283                         hba->dev_info.clk_gating_wait_us;
 284         } else {
 285                 host->ref_clk_gating_wait_us = gating_us;
 286         }
 287
 288         host->ref_clk_ungating_wait_us = REFCLK_DEFAULT_WAIT_US;
 289 }
 290
 291 static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
 292 {
 293         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 294
 295         if (((host->ip_ver >> 16) & 0xFF) >= 0x36) {
 296                 ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
 297                 ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
 298                 ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
 299                 ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2);
 300                 ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3);
 301         } else {
 302                 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
 303         }
 304 }
 305
 306 static void ufs_mtk_wait_idle_state(struct ufs_hba *hba,
 307                             unsigned long retry_ms)
 308 {
 309         u64 timeout, time_checked;
 310         u32 val, sm;
 311         bool wait_idle;
 312
 313         /* cannot use plain ktime_get() in suspend */
 314         timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL;
 315
 316         /* wait a specific time after check base */
 317         udelay(10);
 318         wait_idle = false;
 319
 320         do {
 321                 time_checked = ktime_get_mono_fast_ns();
 322                 ufs_mtk_dbg_sel(hba);
 323                 val = ufshcd_readl(hba, REG_UFS_PROBE);
 324
 325                 sm = val & 0x1f;
 326
 327                 /*
 328                  * if state is in H8 enter and H8 enter confirm
 329                  * wait until return to idle state.
 330                  */
 331                 if ((sm >= VS_HIB_ENTER) && (sm <= VS_HIB_EXIT)) {
 332                         wait_idle = true;
 333                         udelay(50);
 334                         continue;
 335                 } else if (!wait_idle)
 336                         break;
 337
 338                 if (wait_idle && (sm == VS_HCE_BASE))
 339                         break;
 340         } while (time_checked < timeout);
 341
 342         if (wait_idle && sm != VS_HCE_BASE)
 343                 dev_info(hba->dev, "wait idle tmo: 0x%x\n", val);
 344 }
 345
 346 static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
 347                                    unsigned long max_wait_ms)
 348 {
 349         ktime_t timeout, time_checked;
 350         u32 val;
 351
 352         timeout = ktime_add_ms(ktime_get(), max_wait_ms);
 353         do {
 354                 time_checked = ktime_get();
 355                 ufs_mtk_dbg_sel(hba);
 356                 val = ufshcd_readl(hba, REG_UFS_PROBE);
 357                 val = val >> 28;
 358
 359                 if (val == state)
 360                         return 0;
 361
 362                 /* Sleep for max. 200us */
 363                 usleep_range(100, 200);
 364         } while (ktime_before(time_checked, timeout));
 365
 366         if (val == state)
 367                 return 0;
 368
 369         return -ETIMEDOUT;
 370 }
 371
 372 static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
 373 {
 374         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 375         struct phy *mphy = host->mphy;
 376         struct arm_smccc_res res;
 377         int ret = 0;
 378
 379         if (!mphy || !(on ^ host->mphy_powered_on))
 380                 return 0;
 381
 382         if (on) {
 383                 if (ufs_mtk_is_va09_supported(hba)) {
 384                         ret = regulator_enable(host->reg_va09);
 385                         if (ret < 0)
 386                                 goto out;
 387                         /* wait 200 us to stablize VA09 */
 388                         usleep_range(200, 210);
 389                         ufs_mtk_va09_pwr_ctrl(res, 1);
 390                 }
 391                 phy_power_on(mphy);
 392         } else {
 393                 phy_power_off(mphy);
 394                 if (ufs_mtk_is_va09_supported(hba)) {
 395                         ufs_mtk_va09_pwr_ctrl(res, 0);
 396                         ret = regulator_disable(host->reg_va09);
 397                         if (ret < 0)
 398                                 goto out;
 399                 }
 400         }
 401 out:
 402         if (ret) {
 403                 dev_info(hba->dev,
 404                          "failed to %s va09: %d\n",
 405                          on ? "enable" : "disable",
 406                          ret);
 407         } else {
 408                 host->mphy_powered_on = on;
 409         }
 410
 411         return ret;
 412 }
 413
 414 static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
 415                                 struct clk **clk_out)
 416 {
 417         struct clk *clk;
 418         int err = 0;
 419
 420         clk = devm_clk_get(dev, name);
 421         if (IS_ERR(clk))
 422                 err = PTR_ERR(clk);
 423         else
 424                 *clk_out = clk;
 425
 426         return err;
 427 }
 428
 429 static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
 430 {
 431         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 432         struct ufs_mtk_crypt_cfg *cfg;
 433         struct regulator *reg;
 434         int volt, ret;
 435
 436         if (!ufs_mtk_is_boost_crypt_enabled(hba))
 437                 return;
 438
 439         cfg = host->crypt;
 440         volt = cfg->vcore_volt;
 441         reg = cfg->reg_vcore;
 442
 443         ret = clk_prepare_enable(cfg->clk_crypt_mux);
 444         if (ret) {
 445                 dev_info(hba->dev, "clk_prepare_enable(): %d\n",
 446                          ret);
 447                 return;
 448         }
 449
 450         if (boost) {
 451                 ret = regulator_set_voltage(reg, volt, INT_MAX);
 452                 if (ret) {
 453                         dev_info(hba->dev,
 454                                  "failed to set vcore to %d\n", volt);
 455                         goto out;
 456                 }
 457
 458                 ret = clk_set_parent(cfg->clk_crypt_mux,
 459                                      cfg->clk_crypt_perf);
 460                 if (ret) {
 461                         dev_info(hba->dev,
 462                                  "failed to set clk_crypt_perf\n");
 463                         regulator_set_voltage(reg, 0, INT_MAX);
 464                         goto out;
 465                 }
 466         } else {
 467                 ret = clk_set_parent(cfg->clk_crypt_mux,
 468                                      cfg->clk_crypt_lp);
 469                 if (ret) {
 470                         dev_info(hba->dev,
 471                                  "failed to set clk_crypt_lp\n");
 472                         goto out;
 473                 }
 474
 475                 ret = regulator_set_voltage(reg, 0, INT_MAX);
 476                 if (ret) {
 477                         dev_info(hba->dev,
 478                                  "failed to set vcore to MIN\n");
 479                 }
 480         }
 481 out:
 482         clk_disable_unprepare(cfg->clk_crypt_mux);
 483 }
 484
 485 static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
 486                                  struct clk **clk)
 487 {
 488         int ret;
 489
 490         ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
 491         if (ret) {
 492                 dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
 493                          name, ret);
 494         }
 495
 496         return ret;
 497 }
 498
 499 static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
 500 {
 501         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 502         struct ufs_mtk_crypt_cfg *cfg;
 503         struct device *dev = hba->dev;
 504         struct regulator *reg;
 505         u32 volt;
 506
 507         host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
 508                                    GFP_KERNEL);
 509         if (!host->crypt)
 510                 goto disable_caps;
 511
 512         reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
 513         if (IS_ERR(reg)) {
 514                 dev_info(dev, "failed to get dvfsrc-vcore: %ld",
 515                          PTR_ERR(reg));
 516                 goto disable_caps;
 517         }
 518
 519         if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min",
 520                                  &volt)) {
 521                 dev_info(dev, "failed to get boost-crypt-vcore-min");
 522                 goto disable_caps;
 523         }
 524
 525         cfg = host->crypt;
 526         if (ufs_mtk_init_host_clk(hba, "crypt_mux",
 527                                   &cfg->clk_crypt_mux))
 528                 goto disable_caps;
 529
 530         if (ufs_mtk_init_host_clk(hba, "crypt_lp",
 531                                   &cfg->clk_crypt_lp))
 532                 goto disable_caps;
 533
 534         if (ufs_mtk_init_host_clk(hba, "crypt_perf",
 535                                   &cfg->clk_crypt_perf))
 536                 goto disable_caps;
 537
 538         cfg->reg_vcore = reg;
 539         cfg->vcore_volt = volt;
 540         host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
 541
 542 disable_caps:
 543         return;
 544 }
 545
 546 static void ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba *hba)
 547 {
 548         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 549
 550         host->reg_va09 = regulator_get(hba->dev, "va09");
 551         if (IS_ERR(host->reg_va09))
 552                 dev_info(hba->dev, "failed to get va09");
 553         else
 554                 host->caps |= UFS_MTK_CAP_VA09_PWR_CTRL;
 555 }
 556
 557 static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
 558 {
 559         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 560         struct device_node *np = hba->dev->of_node;
 561
 562         if (of_property_read_bool(np, "mediatek,ufs-boost-crypt"))
 563                 ufs_mtk_init_boost_crypt(hba);
 564
 565         if (of_property_read_bool(np, "mediatek,ufs-support-va09"))
 566                 ufs_mtk_init_va09_pwr_ctrl(hba);
 567
 568         if (of_property_read_bool(np, "mediatek,ufs-disable-ah8"))
 569                 host->caps |= UFS_MTK_CAP_DISABLE_AH8;
 570
 571         if (of_property_read_bool(np, "mediatek,ufs-broken-vcc"))
 572                 host->caps |= UFS_MTK_CAP_BROKEN_VCC;
 573
 574         if (of_property_read_bool(np, "mediatek,ufs-pmc-via-fastauto"))
 575                 host->caps |= UFS_MTK_CAP_PMC_VIA_FASTAUTO;
 576
 577         dev_info(hba->dev, "caps: 0x%x", host->caps);
 578 }
 579
 580 static void ufs_mtk_scale_perf(struct ufs_hba *hba, bool up)
 581 {
 582         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 583
 584         ufs_mtk_boost_crypt(hba, up);
 585         ufs_mtk_setup_ref_clk(hba, up);
 586
 587         if (up)
 588                 phy_power_on(host->mphy);
 589         else
 590                 phy_power_off(host->mphy);
 591 }
 592
 593 /**
 594  * ufs_mtk_setup_clocks - enables/disable clocks
 595  * @hba: host controller instance
 596  * @on: If true, enable clocks else disable them.
 597  * @status: PRE_CHANGE or POST_CHANGE notify
 598  *
 599  * Returns 0 on success, non-zero on failure.
 600  */
 601 static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
 602                                 enum ufs_notify_change_status status)
 603 {
 604         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 605         bool clk_pwr_off = false;
 606         int ret = 0;
 607
 608         /*
 609          * In case ufs_mtk_init() is not yet done, simply ignore.
 610          * This ufs_mtk_setup_clocks() shall be called from
 611          * ufs_mtk_init() after init is done.
 612          */
 613         if (!host)
 614                 return 0;
 615
 616         if (!on && status == PRE_CHANGE) {
 617                 if (ufshcd_is_link_off(hba)) {
 618                         clk_pwr_off = true;
 619                 } else if (ufshcd_is_link_hibern8(hba) ||
 620                          (!ufshcd_can_hibern8_during_gating(hba) &&
 621                          ufshcd_is_auto_hibern8_enabled(hba))) {
 622                         /*
 623                          * Gate ref-clk and poweroff mphy if link state is in
 624                          * OFF or Hibern8 by either Auto-Hibern8 or
 625                          * ufshcd_link_state_transition().
 626                          */
 627                         ret = ufs_mtk_wait_link_state(hba,
 628                                                       VS_LINK_HIBERN8,
 629                                                       15);
 630                         if (!ret)
 631                                 clk_pwr_off = true;
 632                 }
 633
 634                 if (clk_pwr_off)
 635                         ufs_mtk_scale_perf(hba, false);
 636         } else if (on && status == POST_CHANGE) {
 637                 ufs_mtk_scale_perf(hba, true);
 638         }
 639
 640         return ret;
 641 }
 642
 643 static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
 644 {
 645         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 646         int ret, ver = 0;
 647
 648         if (host->hw_ver.major)
 649                 return;
 650
 651         /* Set default (minimum) version anyway */
 652         host->hw_ver.major = 2;
 653
 654         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &ver);
 655         if (!ret) {
 656                 if (ver >= UFS_UNIPRO_VER_1_8) {
 657                         host->hw_ver.major = 3;
 658                         /*
 659                          * Fix HCI version for some platforms with
 660                          * incorrect version
 661                          */
 662                         if (hba->ufs_version < ufshci_version(3, 0))
 663                                 hba->ufs_version = ufshci_version(3, 0);
 664                 }
 665         }
 666 }
 667
 668 static u32 ufs_mtk_get_ufs_hci_version(struct ufs_hba *hba)
 669 {
 670         return hba->ufs_version;
 671 }
 672
 673 #define MAX_VCC_NAME 30
 674 static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba)
 675 {
 676         struct ufs_vreg_info *info = &hba->vreg_info;
 677         struct device_node *np = hba->dev->of_node;
 678         struct device *dev = hba->dev;
 679         char vcc_name[MAX_VCC_NAME];
 680         struct arm_smccc_res res;
 681         int err, ver;
 682
 683         if (hba->vreg_info.vcc)
 684                 return 0;
 685
 686         if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) {
 687                 ufs_mtk_get_vcc_num(res);
 688                 if (res.a1 > UFS_VCC_NONE && res.a1 < UFS_VCC_MAX)
 689                         snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%lu", res.a1);
 690                 else
 691                         return -ENODEV;
 692         } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) {
 693                 ver = (hba->dev_info.wspecversion & 0xF00) >> 8;
 694                 snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver);
 695         } else {
 696                 return 0;
 697         }
 698
 699         err = ufshcd_populate_vreg(dev, vcc_name, &info->vcc);
 700         if (err)
 701                 return err;
 702
 703         err = ufshcd_get_vreg(dev, info->vcc);
 704         if (err)
 705                 return err;
 706
 707         err = regulator_enable(info->vcc->reg);
 708         if (!err) {
 709                 info->vcc->enabled = true;
 710                 dev_info(dev, "%s: %s enabled\n", __func__, vcc_name);
 711         }
 712
 713         return err;
 714 }
 715
 716 static void ufs_mtk_vreg_fix_vccqx(struct ufs_hba *hba)
 717 {
 718         struct ufs_vreg_info *info = &hba->vreg_info;
 719         struct ufs_vreg **vreg_on, **vreg_off;
 720
 721         if (hba->dev_info.wspecversion >= 0x0300) {
 722                 vreg_on = &info->vccq;
 723                 vreg_off = &info->vccq2;
 724         } else {
 725                 vreg_on = &info->vccq2;
 726                 vreg_off = &info->vccq;
 727         }
 728
 729         if (*vreg_on)
 730                 (*vreg_on)->always_on = true;
 731
 732         if (*vreg_off) {
 733                 regulator_disable((*vreg_off)->reg);
 734                 devm_kfree(hba->dev, (*vreg_off)->name);
 735                 devm_kfree(hba->dev, *vreg_off);
 736         }
 737 }
 738
 739 /**
 740  * ufs_mtk_init - find other essential mmio bases
 741  * @hba: host controller instance
 742  *
 743  * Binds PHY with controller and powers up PHY enabling clocks
 744  * and regulators.
 745  *
 746  * Returns -EPROBE_DEFER if binding fails, returns negative error
 747  * on phy power up failure and returns zero on success.
 748  */
 749 static int ufs_mtk_init(struct ufs_hba *hba)
 750 {
 751         const struct of_device_id *id;
 752         struct device *dev = hba->dev;
 753         struct ufs_mtk_host *host;
 754         int err = 0;
 755
 756         host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
 757         if (!host) {
 758                 err = -ENOMEM;
 759                 dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
 760                 goto out;
 761         }
 762
 763         host->hba = hba;
 764         ufshcd_set_variant(hba, host);
 765
 766         id = of_match_device(ufs_mtk_of_match, dev);
 767         if (!id) {
 768                 err = -EINVAL;
 769                 goto out;
 770         }
 771
 772         /* Initialize host capability */
 773         ufs_mtk_init_host_caps(hba);
 774
 775         err = ufs_mtk_bind_mphy(hba);
 776         if (err)
 777                 goto out_variant_clear;
 778
 779         ufs_mtk_init_reset(hba);
 780
 781         /* Enable runtime autosuspend */
 782         hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
 783
 784         /* Enable clock-gating */
 785         hba->caps |= UFSHCD_CAP_CLK_GATING;
 786
 787         /* Enable inline encryption */
 788         hba->caps |= UFSHCD_CAP_CRYPTO;
 789
 790         /* Enable WriteBooster */
 791         hba->caps |= UFSHCD_CAP_WB_EN;
 792         hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
 793         hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
 794
 795         if (host->caps & UFS_MTK_CAP_DISABLE_AH8)
 796                 hba->caps |= UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
 797
 798         /*
 799          * ufshcd_vops_init() is invoked after
 800          * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
 801          * phy clock setup is skipped.
 802          *
 803          * Enable phy clocks specifically here.
 804          */
 805         ufs_mtk_mphy_power_on(hba, true);
 806         ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
 807
 808         host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
 809
 810         goto out;
 811
 812 out_variant_clear:
 813         ufshcd_set_variant(hba, NULL);
 814 out:
 815         return err;
 816 }
 817
 818 static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba,
 819                                      struct ufs_pa_layer_attr *dev_req_params)
 820 {
 821         if (!ufs_mtk_is_pmc_via_fastauto(hba))
 822                 return false;
 823
 824         if (dev_req_params->hs_rate == hba->pwr_info.hs_rate)
 825                 return false;
 826
 827         if (dev_req_params->pwr_tx != FAST_MODE &&
 828             dev_req_params->gear_tx < UFS_HS_G4)
 829                 return false;
 830
 831         if (dev_req_params->pwr_rx != FAST_MODE &&
 832             dev_req_params->gear_rx < UFS_HS_G4)
 833                 return false;
 834
 835         return true;
 836 }
 837
 838 static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
 839                                   struct ufs_pa_layer_attr *dev_max_params,
 840                                   struct ufs_pa_layer_attr *dev_req_params)
 841 {
 842         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 843         struct ufs_dev_params host_cap;
 844         int ret;
 845
 846         ufshcd_init_pwr_dev_param(&host_cap);
 847         host_cap.hs_rx_gear = UFS_HS_G5;
 848         host_cap.hs_tx_gear = UFS_HS_G5;
 849
 850         ret = ufshcd_get_pwr_dev_param(&host_cap,
 851                                        dev_max_params,
 852                                        dev_req_params);
 853         if (ret) {
 854                 pr_info("%s: failed to determine capabilities\n",
 855                         __func__);
 856         }
 857
 858         if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) {
 859                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
 860                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), UFS_HS_G1);
 861
 862                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
 863                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), UFS_HS_G1);
 864
 865                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
 866                                dev_req_params->lane_tx);
 867                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
 868                                dev_req_params->lane_rx);
 869                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
 870                                dev_req_params->hs_rate);
 871
 872                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE),
 873                                PA_NO_ADAPT);
 874
 875                 ret = ufshcd_uic_change_pwr_mode(hba,
 876                                         FASTAUTO_MODE << 4 | FASTAUTO_MODE);
 877
 878                 if (ret) {
 879                         dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=%d\n",
 880                                 __func__, ret);
 881                 }
 882         }
 883
 884         if (host->hw_ver.major >= 3) {
 885                 ret = ufshcd_dme_configure_adapt(hba,
 886                                            dev_req_params->gear_tx,
 887                                            PA_INITIAL_ADAPT);
 888         }
 889
 890         return ret;
 891 }
 892
 893 static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
 894                                      enum ufs_notify_change_status stage,
 895                                      struct ufs_pa_layer_attr *dev_max_params,
 896                                      struct ufs_pa_layer_attr *dev_req_params)
 897 {
 898         int ret = 0;
 899
 900         switch (stage) {
 901         case PRE_CHANGE:
 902                 ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
 903                                              dev_req_params);
 904                 break;
 905         case POST_CHANGE:
 906                 break;
 907         default:
 908                 ret = -EINVAL;
 909                 break;
 910         }
 911
 912         return ret;
 913 }
 914
 915 static int ufs_mtk_unipro_set_lpm(struct ufs_hba *hba, bool lpm)
 916 {
 917         int ret;
 918         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 919
 920         ret = ufshcd_dme_set(hba,
 921                              UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
 922                              lpm ? 1 : 0);
 923         if (!ret || !lpm) {
 924                 /*
 925                  * Forcibly set as non-LPM mode if UIC commands is failed
 926                  * to use default hba_enable_delay_us value for re-enabling
 927                  * the host.
 928                  */
 929                 host->unipro_lpm = lpm;
 930         }
 931
 932         return ret;
 933 }
 934
 935 static int ufs_mtk_pre_link(struct ufs_hba *hba)
 936 {
 937         int ret;
 938         u32 tmp;
 939
 940         ufs_mtk_get_controller_version(hba);
 941
 942         ret = ufs_mtk_unipro_set_lpm(hba, false);
 943         if (ret)
 944                 return ret;
 945
 946         /*
 947          * Setting PA_Local_TX_LCC_Enable to 0 before link startup
 948          * to make sure that both host and device TX LCC are disabled
 949          * once link startup is completed.
 950          */
 951         ret = ufshcd_disable_host_tx_lcc(hba);
 952         if (ret)
 953                 return ret;
 954
 955         /* disable deep stall */
 956         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
 957         if (ret)
 958                 return ret;
 959
 960         tmp &= ~(1 << 6);
 961
 962         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
 963
 964         return ret;
 965 }
 966
 967 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
 968 {
 969         u32 ah_ms;
 970
 971         if (ufshcd_is_clkgating_allowed(hba)) {
 972                 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
 973                         ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
 974                                           hba->ahit);
 975                 else
 976                         ah_ms = 10;
 977                 ufshcd_clkgate_delay_set(hba->dev, ah_ms + 5);
 978         }
 979 }
 980
 981 static int ufs_mtk_post_link(struct ufs_hba *hba)
 982 {
 983         /* enable unipro clock gating feature */
 984         ufs_mtk_cfg_unipro_cg(hba, true);
 985
 986         /* will be configured during probe hba */
 987         if (ufshcd_is_auto_hibern8_supported(hba))
 988                 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
 989                         FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
 990
 991         ufs_mtk_setup_clk_gating(hba);
 992
 993         return 0;
 994 }
 995
 996 static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
 997                                        enum ufs_notify_change_status stage)
 998 {
 999         int ret = 0;
1000
1001         switch (stage) {
1002         case PRE_CHANGE:
1003                 ret = ufs_mtk_pre_link(hba);
1004                 break;
1005         case POST_CHANGE:
1006                 ret = ufs_mtk_post_link(hba);
1007                 break;
1008         default:
1009                 ret = -EINVAL;
1010                 break;
1011         }
1012
1013         return ret;
1014 }
1015
1016 static int ufs_mtk_device_reset(struct ufs_hba *hba)
1017 {
1018         struct arm_smccc_res res;
1019
1020         /* disable hba before device reset */
1021         ufshcd_hba_stop(hba);
1022
1023         ufs_mtk_device_reset_ctrl(0, res);
1024
1025         /*
1026          * The reset signal is active low. UFS devices shall detect
1027          * more than or equal to 1us of positive or negative RST_n
1028          * pulse width.
1029          *
1030          * To be on safe side, keep the reset low for at least 10us.
1031          */
1032         usleep_range(10, 15);
1033
1034         ufs_mtk_device_reset_ctrl(1, res);
1035
1036         /* Some devices may need time to respond to rst_n */
1037         usleep_range(10000, 15000);
1038
1039         dev_info(hba->dev, "device reset done\n");
1040
1041         return 0;
1042 }
1043
1044 static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
1045 {
1046         int err;
1047
1048         err = ufshcd_hba_enable(hba);
1049         if (err)
1050                 return err;
1051
1052         err = ufs_mtk_unipro_set_lpm(hba, false);
1053         if (err)
1054                 return err;
1055
1056         err = ufshcd_uic_hibern8_exit(hba);
1057         if (!err)
1058                 ufshcd_set_link_active(hba);
1059         else
1060                 return err;
1061
1062         err = ufshcd_make_hba_operational(hba);
1063         if (err)
1064                 return err;
1065
1066         return 0;
1067 }
1068
1069 static int ufs_mtk_link_set_lpm(struct ufs_hba *hba)
1070 {
1071         int err;
1072
1073         err = ufs_mtk_unipro_set_lpm(hba, true);
1074         if (err) {
1075                 /* Resume UniPro state for following error recovery */
1076                 ufs_mtk_unipro_set_lpm(hba, false);
1077                 return err;
1078         }
1079
1080         return 0;
1081 }
1082
1083 static void ufs_mtk_vccqx_set_lpm(struct ufs_hba *hba, bool lpm)
1084 {
1085         struct ufs_vreg *vccqx = NULL;
1086
1087         if (hba->vreg_info.vccq)
1088                 vccqx = hba->vreg_info.vccq;
1089         else
1090                 vccqx = hba->vreg_info.vccq2;
1091
1092         regulator_set_mode(vccqx->reg,
1093                            lpm ? REGULATOR_MODE_IDLE : REGULATOR_MODE_NORMAL);
1094 }
1095
1096 static void ufs_mtk_vsx_set_lpm(struct ufs_hba *hba, bool lpm)
1097 {
1098         struct arm_smccc_res res;
1099
1100         ufs_mtk_device_pwr_ctrl(!lpm,
1101                                 (unsigned long)hba->dev_info.wspecversion,
1102                                 res);
1103 }
1104
1105 static void ufs_mtk_dev_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
1106 {
1107         if (!hba->vreg_info.vccq && !hba->vreg_info.vccq2)
1108                 return;
1109
1110         /* Skip if VCC is assumed always-on */
1111         if (!hba->vreg_info.vcc)
1112                 return;
1113
1114         /* Bypass LPM when device is still active */
1115         if (lpm && ufshcd_is_ufs_dev_active(hba))
1116                 return;
1117
1118         /* Bypass LPM if VCC is enabled */
1119         if (lpm && hba->vreg_info.vcc->enabled)
1120                 return;
1121
1122         if (lpm) {
1123                 ufs_mtk_vccqx_set_lpm(hba, lpm);
1124                 ufs_mtk_vsx_set_lpm(hba, lpm);
1125         } else {
1126                 ufs_mtk_vsx_set_lpm(hba, lpm);
1127                 ufs_mtk_vccqx_set_lpm(hba, lpm);
1128         }
1129 }
1130
1131 static void ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
1132 {
1133         int ret;
1134
1135         /* disable auto-hibern8 */
1136         ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
1137
1138         /* wait host return to idle state when auto-hibern8 off */
1139         ufs_mtk_wait_idle_state(hba, 5);
1140
1141         ret = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
1142         if (ret)
1143                 dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret);
1144 }
1145
1146 static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
1147         enum ufs_notify_change_status status)
1148 {
1149         int err;
1150         struct arm_smccc_res res;
1151
1152         if (status == PRE_CHANGE) {
1153                 if (!ufshcd_is_auto_hibern8_supported(hba))
1154                         return 0;
1155                 ufs_mtk_auto_hibern8_disable(hba);
1156                 return 0;
1157         }
1158
1159         if (ufshcd_is_link_hibern8(hba)) {
1160                 err = ufs_mtk_link_set_lpm(hba);
1161                 if (err)
1162                         goto fail;
1163         }
1164
1165         if (!ufshcd_is_link_active(hba)) {
1166                 /*
1167                  * Make sure no error will be returned to prevent
1168                  * ufshcd_suspend() re-enabling regulators while vreg is still
1169                  * in low-power mode.
1170                  */
1171                 err = ufs_mtk_mphy_power_on(hba, false);
1172                 if (err)
1173                         goto fail;
1174         }
1175
1176         if (ufshcd_is_link_off(hba))
1177                 ufs_mtk_device_reset_ctrl(0, res);
1178
1179         return 0;
1180 fail:
1181         /*
1182          * Set link as off state enforcedly to trigger
1183          * ufshcd_host_reset_and_restore() in ufshcd_suspend()
1184          * for completed host reset.
1185          */
1186         ufshcd_set_link_off(hba);
1187         return -EAGAIN;
1188 }
1189
1190 static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1191 {
1192         int err;
1193
1194         if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
1195                 ufs_mtk_dev_vreg_set_lpm(hba, false);
1196
1197         err = ufs_mtk_mphy_power_on(hba, true);
1198         if (err)
1199                 goto fail;
1200
1201         if (ufshcd_is_link_hibern8(hba)) {
1202                 err = ufs_mtk_link_set_hpm(hba);
1203                 if (err)
1204                         goto fail;
1205         }
1206
1207         return 0;
1208 fail:
1209         return ufshcd_link_recovery(hba);
1210 }
1211
1212 static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
1213 {
1214         ufshcd_dump_regs(hba, REG_UFS_REFCLK_CTRL, 0x4, "Ref-Clk Ctrl ");
1215
1216         ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg ");
1217
1218         ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL,
1219                          REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4,
1220                          "MPHY Ctrl ");
1221
1222         /* Direct debugging information to REG_MTK_PROBE */
1223         ufs_mtk_dbg_sel(hba);
1224         ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
1225 }
1226
1227 static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
1228 {
1229         struct ufs_dev_info *dev_info = &hba->dev_info;
1230         u16 mid = dev_info->wmanufacturerid;
1231
1232         if (mid == UFS_VENDOR_SAMSUNG)
1233                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
1234
1235         /*
1236          * Decide waiting time before gating reference clock and
1237          * after ungating reference clock according to vendors'
1238          * requirements.
1239          */
1240         if (mid == UFS_VENDOR_SAMSUNG)
1241                 ufs_mtk_setup_ref_clk_wait_us(hba, 1);
1242         else if (mid == UFS_VENDOR_SKHYNIX)
1243                 ufs_mtk_setup_ref_clk_wait_us(hba, 30);
1244         else if (mid == UFS_VENDOR_TOSHIBA)
1245                 ufs_mtk_setup_ref_clk_wait_us(hba, 100);
1246         else
1247                 ufs_mtk_setup_ref_clk_wait_us(hba,
1248                                               REFCLK_DEFAULT_WAIT_US);
1249         return 0;
1250 }
1251
1252 static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
1253 {
1254         ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
1255
1256         if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc &&
1257             (hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)) {
1258                 hba->vreg_info.vcc->always_on = true;
1259                 /*
1260                  * VCC will be kept always-on thus we don't
1261                  * need any delay during regulator operations
1262                  */
1263                 hba->dev_quirks &= ~(UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
1264                         UFS_DEVICE_QUIRK_DELAY_AFTER_LPM);
1265         }
1266
1267         ufs_mtk_vreg_fix_vcc(hba);
1268         ufs_mtk_vreg_fix_vccqx(hba);
1269 }
1270
1271 static void ufs_mtk_event_notify(struct ufs_hba *hba,
1272                                  enum ufs_event_type evt, void *data)
1273 {
1274         unsigned int val = *(u32 *)data;
1275
1276         trace_ufs_mtk_event(evt, val);
1277 }
1278
1279 /*
1280  * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
1281  *
1282  * The variant operations configure the necessary controller and PHY
1283  * handshake during initialization.
1284  */
1285 static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
1286         .name                = "mediatek.ufshci",
1287         .init                = ufs_mtk_init,
1288         .get_ufs_hci_version = ufs_mtk_get_ufs_hci_version,
1289         .setup_clocks        = ufs_mtk_setup_clocks,
1290         .hce_enable_notify   = ufs_mtk_hce_enable_notify,
1291         .link_startup_notify = ufs_mtk_link_startup_notify,
1292         .pwr_change_notify   = ufs_mtk_pwr_change_notify,
1293         .apply_dev_quirks    = ufs_mtk_apply_dev_quirks,
1294         .fixup_dev_quirks    = ufs_mtk_fixup_dev_quirks,
1295         .suspend             = ufs_mtk_suspend,
1296         .resume              = ufs_mtk_resume,
1297         .dbg_register_dump   = ufs_mtk_dbg_register_dump,
1298         .device_reset        = ufs_mtk_device_reset,
1299         .event_notify        = ufs_mtk_event_notify,
1300 };
1301
1302 /**
1303  * ufs_mtk_probe - probe routine of the driver
1304  * @pdev: pointer to Platform device handle
1305  *
1306  * Return zero for success and non-zero for failure
1307  */
1308 static int ufs_mtk_probe(struct platform_device *pdev)
1309 {
1310         int err;
1311         struct device *dev = &pdev->dev;
1312         struct device_node *reset_node;
1313         struct platform_device *reset_pdev;
1314         struct device_link *link;
1315
1316         reset_node = of_find_compatible_node(NULL, NULL,
1317                                              "ti,syscon-reset");
1318         if (!reset_node) {
1319                 dev_notice(dev, "find ti,syscon-reset fail\n");
1320                 goto skip_reset;
1321         }
1322         reset_pdev = of_find_device_by_node(reset_node);
1323         if (!reset_pdev) {
1324                 dev_notice(dev, "find reset_pdev fail\n");
1325                 goto skip_reset;
1326         }
1327         link = device_link_add(dev, &reset_pdev->dev,
1328                 DL_FLAG_AUTOPROBE_CONSUMER);
1329         put_device(&reset_pdev->dev);
1330         if (!link) {
1331                 dev_notice(dev, "add reset device_link fail\n");
1332                 goto skip_reset;
1333         }
1334         /* supplier is not probed */
1335         if (link->status == DL_STATE_DORMANT) {
1336                 err = -EPROBE_DEFER;
1337                 goto out;
1338         }
1339
1340 skip_reset:
1341         /* perform generic probe */
1342         err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
1343
1344 out:
1345         if (err)
1346                 dev_info(dev, "probe failed %d\n", err);
1347
1348         of_node_put(reset_node);
1349         return err;
1350 }
1351
1352 /**
1353  * ufs_mtk_remove - set driver_data of the device to NULL
1354  * @pdev: pointer to platform device handle
1355  *
1356  * Always return 0
1357  */
1358 static int ufs_mtk_remove(struct platform_device *pdev)
1359 {
1360         struct ufs_hba *hba =  platform_get_drvdata(pdev);
1361
1362         pm_runtime_get_sync(&(pdev)->dev);
1363         ufshcd_remove(hba);
1364         return 0;
1365 }
1366
1367 #ifdef CONFIG_PM_SLEEP
1368 static int ufs_mtk_system_suspend(struct device *dev)
1369 {
1370         struct ufs_hba *hba = dev_get_drvdata(dev);
1371         int ret;
1372
1373         ret = ufshcd_system_suspend(dev);
1374         if (ret)
1375                 return ret;
1376
1377         ufs_mtk_dev_vreg_set_lpm(hba, true);
1378
1379         return 0;
1380 }
1381
1382 static int ufs_mtk_system_resume(struct device *dev)
1383 {
1384         struct ufs_hba *hba = dev_get_drvdata(dev);
1385
1386         ufs_mtk_dev_vreg_set_lpm(hba, false);
1387
1388         return ufshcd_system_resume(dev);
1389 }
1390 #endif
1391
1392 static int ufs_mtk_runtime_suspend(struct device *dev)
1393 {
1394         struct ufs_hba *hba = dev_get_drvdata(dev);
1395         int ret = 0;
1396
1397         ret = ufshcd_runtime_suspend(dev);
1398         if (ret)
1399                 return ret;
1400
1401         ufs_mtk_dev_vreg_set_lpm(hba, true);
1402
1403         return 0;
1404 }
1405
1406 static int ufs_mtk_runtime_resume(struct device *dev)
1407 {
1408         struct ufs_hba *hba = dev_get_drvdata(dev);
1409
1410         ufs_mtk_dev_vreg_set_lpm(hba, false);
1411
1412         return ufshcd_runtime_resume(dev);
1413 }
1414
1415 static const struct dev_pm_ops ufs_mtk_pm_ops = {
1416         SET_SYSTEM_SLEEP_PM_OPS(ufs_mtk_system_suspend,
1417                                 ufs_mtk_system_resume)
1418         SET_RUNTIME_PM_OPS(ufs_mtk_runtime_suspend,
1419                            ufs_mtk_runtime_resume, NULL)
1420         .prepare         = ufshcd_suspend_prepare,
1421         .complete        = ufshcd_resume_complete,
1422 };
1423
1424 static struct platform_driver ufs_mtk_pltform = {
1425         .probe      = ufs_mtk_probe,
1426         .remove     = ufs_mtk_remove,
1427         .shutdown   = ufshcd_pltfrm_shutdown,
1428         .driver = {
1429                 .name   = "ufshcd-mtk",
1430                 .pm     = &ufs_mtk_pm_ops,
1431                 .of_match_table = ufs_mtk_of_match,
1432         },
1433 };
1434
1435 MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
1436 MODULE_AUTHOR("Peter Wang <peter.wang@mediatek.com>");
1437 MODULE_DESCRIPTION("MediaTek UFS Host Driver");
1438 MODULE_LICENSE("GPL v2");
1439
1440 module_platform_driver(ufs_mtk_pltform);