1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 MediaTek Inc.
5 * Stanley Chu <stanley.chu@mediatek.com>
6 * Peter Wang <peter.wang@mediatek.com>
9 #include <linux/arm-smccc.h>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/reset.h>
21 #include <linux/sched/clock.h>
22 #include <linux/soc/mediatek/mtk_sip_svc.h>
24 #include <ufs/ufshcd.h>
25 #include "ufshcd-pltfrm.h"
26 #include <ufs/ufs_quirks.h>
27 #include <ufs/unipro.h>
28 #include "ufs-mediatek.h"
30 #define CREATE_TRACE_POINTS
31 #include "ufs-mediatek-trace.h"
33 #define ufs_mtk_smc(cmd, val, res) \
34 arm_smccc_smc(MTK_SIP_UFS_CONTROL, \
35 cmd, val, 0, 0, 0, 0, 0, &(res))
37 #define ufs_mtk_va09_pwr_ctrl(res, on) \
38 ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, on, res)
40 #define ufs_mtk_crypto_ctrl(res, enable) \
41 ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, enable, res)
43 #define ufs_mtk_ref_clk_notify(on, res) \
44 ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, on, res)
46 #define ufs_mtk_device_reset_ctrl(high, res) \
47 ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, high, res)
49 static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
50 { .wmanufacturerid = UFS_VENDOR_MICRON,
51 .model = UFS_ANY_MODEL,
52 .quirk = UFS_DEVICE_QUIRK_DELAY_AFTER_LPM },
53 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
54 .model = "H9HQ21AFAMZDAR",
55 .quirk = UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES },
59 static const struct of_device_id ufs_mtk_of_match[] = {
60 { .compatible = "mediatek,mt8183-ufshci" },
64 static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
66 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
68 return !!(host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE);
71 static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba)
73 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
75 return !!(host->caps & UFS_MTK_CAP_VA09_PWR_CTRL);
78 static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba)
80 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
82 return !!(host->caps & UFS_MTK_CAP_BROKEN_VCC);
85 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
91 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
93 (1 << RX_SYMBOL_CLK_GATE_EN) |
94 (1 << SYS_CLK_GATE_EN) |
95 (1 << TX_CLK_GATE_EN);
97 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
100 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
101 tmp = tmp & ~(1 << TX_SYMBOL_CLK_REQ_FORCE);
103 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
106 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
107 tmp = tmp & ~((1 << RX_SYMBOL_CLK_GATE_EN) |
108 (1 << SYS_CLK_GATE_EN) |
109 (1 << TX_CLK_GATE_EN));
111 UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
114 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), &tmp);
115 tmp = tmp | (1 << TX_SYMBOL_CLK_REQ_FORCE);
117 UIC_ARG_MIB(VS_DEBUGCLOCKENABLE), tmp);
121 static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
123 struct arm_smccc_res res;
125 ufs_mtk_crypto_ctrl(res, 1);
127 dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
129 hba->caps &= ~UFSHCD_CAP_CRYPTO;
133 static void ufs_mtk_host_reset(struct ufs_hba *hba)
135 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
137 reset_control_assert(host->hci_reset);
138 reset_control_assert(host->crypto_reset);
139 reset_control_assert(host->unipro_reset);
141 usleep_range(100, 110);
143 reset_control_deassert(host->unipro_reset);
144 reset_control_deassert(host->crypto_reset);
145 reset_control_deassert(host->hci_reset);
148 static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
149 struct reset_control **rc,
152 *rc = devm_reset_control_get(hba->dev, str);
154 dev_info(hba->dev, "Failed to get reset control %s: %ld\n",
160 static void ufs_mtk_init_reset(struct ufs_hba *hba)
162 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
164 ufs_mtk_init_reset_control(hba, &host->hci_reset,
166 ufs_mtk_init_reset_control(hba, &host->unipro_reset,
168 ufs_mtk_init_reset_control(hba, &host->crypto_reset,
172 static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
173 enum ufs_notify_change_status status)
175 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
177 if (status == PRE_CHANGE) {
178 if (host->unipro_lpm) {
179 hba->vps->hba_enable_delay_us = 0;
181 hba->vps->hba_enable_delay_us = 600;
182 ufs_mtk_host_reset(hba);
185 if (hba->caps & UFSHCD_CAP_CRYPTO)
186 ufs_mtk_crypto_enable(hba);
188 if (host->caps & UFS_MTK_CAP_DISABLE_AH8) {
189 ufshcd_writel(hba, 0,
190 REG_AUTO_HIBERNATE_IDLE_TIMER);
191 hba->capabilities &= ~MASK_AUTO_HIBERN8_SUPPORT;
199 static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
201 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
202 struct device *dev = hba->dev;
203 struct device_node *np = dev->of_node;
206 host->mphy = devm_of_phy_get_by_index(dev, np, 0);
208 if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
210 * UFS driver might be probed before the phy driver does.
211 * In that case we would like to return EPROBE_DEFER code.
215 "%s: required phy hasn't probed yet. err = %d\n",
217 } else if (IS_ERR(host->mphy)) {
218 err = PTR_ERR(host->mphy);
219 if (err != -ENODEV) {
220 dev_info(dev, "%s: PHY get failed %d\n", __func__,
228 * Allow unbound mphy because not every platform needs specific
237 static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
239 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
240 struct arm_smccc_res res;
241 ktime_t timeout, time_checked;
244 if (host->ref_clk_enabled == on)
248 ufs_mtk_ref_clk_notify(on, res);
249 ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
251 ufshcd_delay_us(host->ref_clk_gating_wait_us, 10);
252 ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
256 timeout = ktime_add_us(ktime_get(), REFCLK_REQ_TIMEOUT_US);
258 time_checked = ktime_get();
259 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
261 /* Wait until ack bit equals to req bit */
262 if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
265 usleep_range(100, 200);
266 } while (ktime_before(time_checked, timeout));
268 dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
270 ufs_mtk_ref_clk_notify(host->ref_clk_enabled, res);
275 host->ref_clk_enabled = on;
277 ufshcd_delay_us(host->ref_clk_ungating_wait_us, 10);
279 ufs_mtk_ref_clk_notify(on, res);
284 static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
287 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
289 if (hba->dev_info.clk_gating_wait_us) {
290 host->ref_clk_gating_wait_us =
291 hba->dev_info.clk_gating_wait_us;
293 host->ref_clk_gating_wait_us = gating_us;
296 host->ref_clk_ungating_wait_us = REFCLK_DEFAULT_WAIT_US;
299 static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
301 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
303 if (((host->ip_ver >> 16) & 0xFF) >= 0x36) {
304 ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
305 ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
306 ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
307 ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2);
308 ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3);
310 ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
314 static void ufs_mtk_wait_idle_state(struct ufs_hba *hba,
315 unsigned long retry_ms)
317 u64 timeout, time_checked;
321 /* cannot use plain ktime_get() in suspend */
322 timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL;
324 /* wait a specific time after check base */
329 time_checked = ktime_get_mono_fast_ns();
330 ufs_mtk_dbg_sel(hba);
331 val = ufshcd_readl(hba, REG_UFS_PROBE);
336 * if state is in H8 enter and H8 enter confirm
337 * wait until return to idle state.
339 if ((sm >= VS_HIB_ENTER) && (sm <= VS_HIB_EXIT)) {
343 } else if (!wait_idle)
346 if (wait_idle && (sm == VS_HCE_BASE))
348 } while (time_checked < timeout);
350 if (wait_idle && sm != VS_HCE_BASE)
351 dev_info(hba->dev, "wait idle tmo: 0x%x\n", val);
354 static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
355 unsigned long max_wait_ms)
357 ktime_t timeout, time_checked;
360 timeout = ktime_add_ms(ktime_get(), max_wait_ms);
362 time_checked = ktime_get();
363 ufs_mtk_dbg_sel(hba);
364 val = ufshcd_readl(hba, REG_UFS_PROBE);
370 /* Sleep for max. 200us */
371 usleep_range(100, 200);
372 } while (ktime_before(time_checked, timeout));
380 static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
382 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
383 struct phy *mphy = host->mphy;
384 struct arm_smccc_res res;
387 if (!mphy || !(on ^ host->mphy_powered_on))
391 if (ufs_mtk_is_va09_supported(hba)) {
392 ret = regulator_enable(host->reg_va09);
395 /* wait 200 us to stablize VA09 */
396 usleep_range(200, 210);
397 ufs_mtk_va09_pwr_ctrl(res, 1);
402 if (ufs_mtk_is_va09_supported(hba)) {
403 ufs_mtk_va09_pwr_ctrl(res, 0);
404 ret = regulator_disable(host->reg_va09);
412 "failed to %s va09: %d\n",
413 on ? "enable" : "disable",
416 host->mphy_powered_on = on;
422 static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
423 struct clk **clk_out)
428 clk = devm_clk_get(dev, name);
437 static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
439 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
440 struct ufs_mtk_crypt_cfg *cfg;
441 struct regulator *reg;
444 if (!ufs_mtk_is_boost_crypt_enabled(hba))
448 volt = cfg->vcore_volt;
449 reg = cfg->reg_vcore;
451 ret = clk_prepare_enable(cfg->clk_crypt_mux);
453 dev_info(hba->dev, "clk_prepare_enable(): %d\n",
459 ret = regulator_set_voltage(reg, volt, INT_MAX);
462 "failed to set vcore to %d\n", volt);
466 ret = clk_set_parent(cfg->clk_crypt_mux,
467 cfg->clk_crypt_perf);
470 "failed to set clk_crypt_perf\n");
471 regulator_set_voltage(reg, 0, INT_MAX);
475 ret = clk_set_parent(cfg->clk_crypt_mux,
479 "failed to set clk_crypt_lp\n");
483 ret = regulator_set_voltage(reg, 0, INT_MAX);
486 "failed to set vcore to MIN\n");
490 clk_disable_unprepare(cfg->clk_crypt_mux);
493 static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
498 ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
500 dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
507 static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
509 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
510 struct ufs_mtk_crypt_cfg *cfg;
511 struct device *dev = hba->dev;
512 struct regulator *reg;
515 host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
520 reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
522 dev_info(dev, "failed to get dvfsrc-vcore: %ld",
527 if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min",
529 dev_info(dev, "failed to get boost-crypt-vcore-min");
534 if (ufs_mtk_init_host_clk(hba, "crypt_mux",
535 &cfg->clk_crypt_mux))
538 if (ufs_mtk_init_host_clk(hba, "crypt_lp",
542 if (ufs_mtk_init_host_clk(hba, "crypt_perf",
543 &cfg->clk_crypt_perf))
546 cfg->reg_vcore = reg;
547 cfg->vcore_volt = volt;
548 host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
554 static void ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba *hba)
556 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
558 host->reg_va09 = regulator_get(hba->dev, "va09");
559 if (IS_ERR(host->reg_va09))
560 dev_info(hba->dev, "failed to get va09");
562 host->caps |= UFS_MTK_CAP_VA09_PWR_CTRL;
565 static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
567 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
568 struct device_node *np = hba->dev->of_node;
570 if (of_property_read_bool(np, "mediatek,ufs-boost-crypt"))
571 ufs_mtk_init_boost_crypt(hba);
573 if (of_property_read_bool(np, "mediatek,ufs-support-va09"))
574 ufs_mtk_init_va09_pwr_ctrl(hba);
576 if (of_property_read_bool(np, "mediatek,ufs-disable-ah8"))
577 host->caps |= UFS_MTK_CAP_DISABLE_AH8;
579 if (of_property_read_bool(np, "mediatek,ufs-broken-vcc"))
580 host->caps |= UFS_MTK_CAP_BROKEN_VCC;
582 dev_info(hba->dev, "caps: 0x%x", host->caps);
585 static void ufs_mtk_scale_perf(struct ufs_hba *hba, bool up)
587 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
589 ufs_mtk_boost_crypt(hba, up);
590 ufs_mtk_setup_ref_clk(hba, up);
593 phy_power_on(host->mphy);
595 phy_power_off(host->mphy);
599 * ufs_mtk_setup_clocks - enables/disable clocks
600 * @hba: host controller instance
601 * @on: If true, enable clocks else disable them.
602 * @status: PRE_CHANGE or POST_CHANGE notify
604 * Returns 0 on success, non-zero on failure.
606 static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
607 enum ufs_notify_change_status status)
609 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
610 bool clk_pwr_off = false;
614 * In case ufs_mtk_init() is not yet done, simply ignore.
615 * This ufs_mtk_setup_clocks() shall be called from
616 * ufs_mtk_init() after init is done.
621 if (!on && status == PRE_CHANGE) {
622 if (ufshcd_is_link_off(hba)) {
624 } else if (ufshcd_is_link_hibern8(hba) ||
625 (!ufshcd_can_hibern8_during_gating(hba) &&
626 ufshcd_is_auto_hibern8_enabled(hba))) {
628 * Gate ref-clk and poweroff mphy if link state is in
629 * OFF or Hibern8 by either Auto-Hibern8 or
630 * ufshcd_link_state_transition().
632 ret = ufs_mtk_wait_link_state(hba,
640 ufs_mtk_scale_perf(hba, false);
641 } else if (on && status == POST_CHANGE) {
642 ufs_mtk_scale_perf(hba, true);
648 static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
650 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
653 if (host->hw_ver.major)
656 /* Set default (minimum) version anyway */
657 host->hw_ver.major = 2;
659 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_LOCALVERINFO), &ver);
661 if (ver >= UFS_UNIPRO_VER_1_8) {
662 host->hw_ver.major = 3;
664 * Fix HCI version for some platforms with
667 if (hba->ufs_version < ufshci_version(3, 0))
668 hba->ufs_version = ufshci_version(3, 0);
673 static u32 ufs_mtk_get_ufs_hci_version(struct ufs_hba *hba)
675 return hba->ufs_version;
679 * ufs_mtk_init - find other essential mmio bases
680 * @hba: host controller instance
682 * Binds PHY with controller and powers up PHY enabling clocks
685 * Returns -EPROBE_DEFER if binding fails, returns negative error
686 * on phy power up failure and returns zero on success.
688 static int ufs_mtk_init(struct ufs_hba *hba)
690 const struct of_device_id *id;
691 struct device *dev = hba->dev;
692 struct ufs_mtk_host *host;
695 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
698 dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
703 ufshcd_set_variant(hba, host);
705 id = of_match_device(ufs_mtk_of_match, dev);
711 /* Initialize host capability */
712 ufs_mtk_init_host_caps(hba);
714 err = ufs_mtk_bind_mphy(hba);
716 goto out_variant_clear;
718 ufs_mtk_init_reset(hba);
720 /* Enable runtime autosuspend */
721 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
723 /* Enable clock-gating */
724 hba->caps |= UFSHCD_CAP_CLK_GATING;
726 /* Enable inline encryption */
727 hba->caps |= UFSHCD_CAP_CRYPTO;
729 /* Enable WriteBooster */
730 hba->caps |= UFSHCD_CAP_WB_EN;
731 hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
732 hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
734 if (host->caps & UFS_MTK_CAP_DISABLE_AH8)
735 hba->caps |= UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
738 * ufshcd_vops_init() is invoked after
739 * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
740 * phy clock setup is skipped.
742 * Enable phy clocks specifically here.
744 ufs_mtk_mphy_power_on(hba, true);
745 ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
747 host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
752 ufshcd_set_variant(hba, NULL);
757 static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
758 struct ufs_pa_layer_attr *dev_max_params,
759 struct ufs_pa_layer_attr *dev_req_params)
761 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
762 struct ufs_dev_params host_cap;
765 ufshcd_init_pwr_dev_param(&host_cap);
766 host_cap.hs_rx_gear = UFS_HS_G4;
767 host_cap.hs_tx_gear = UFS_HS_G4;
769 ret = ufshcd_get_pwr_dev_param(&host_cap,
773 pr_info("%s: failed to determine capabilities\n",
777 if (host->hw_ver.major >= 3) {
778 ret = ufshcd_dme_configure_adapt(hba,
779 dev_req_params->gear_tx,
786 static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
787 enum ufs_notify_change_status stage,
788 struct ufs_pa_layer_attr *dev_max_params,
789 struct ufs_pa_layer_attr *dev_req_params)
795 ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
808 static int ufs_mtk_unipro_set_lpm(struct ufs_hba *hba, bool lpm)
811 struct ufs_mtk_host *host = ufshcd_get_variant(hba);
813 ret = ufshcd_dme_set(hba,
814 UIC_ARG_MIB_SEL(VS_UNIPROPOWERDOWNCONTROL, 0),
818 * Forcibly set as non-LPM mode if UIC commands is failed
819 * to use default hba_enable_delay_us value for re-enabling
822 host->unipro_lpm = lpm;
828 static int ufs_mtk_pre_link(struct ufs_hba *hba)
833 ufs_mtk_get_controller_version(hba);
835 ret = ufs_mtk_unipro_set_lpm(hba, false);
840 * Setting PA_Local_TX_LCC_Enable to 0 before link startup
841 * to make sure that both host and device TX LCC are disabled
842 * once link startup is completed.
844 ret = ufshcd_disable_host_tx_lcc(hba);
848 /* disable deep stall */
849 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), &tmp);
855 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_SAVEPOWERCONTROL), tmp);
860 static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
864 if (ufshcd_is_clkgating_allowed(hba)) {
865 if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
866 ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
870 ufshcd_clkgate_delay_set(hba->dev, ah_ms + 5);
874 static int ufs_mtk_post_link(struct ufs_hba *hba)
876 /* enable unipro clock gating feature */
877 ufs_mtk_cfg_unipro_cg(hba, true);
879 /* will be configured during probe hba */
880 if (ufshcd_is_auto_hibern8_supported(hba))
881 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
882 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
884 ufs_mtk_setup_clk_gating(hba);
889 static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
890 enum ufs_notify_change_status stage)
896 ret = ufs_mtk_pre_link(hba);
899 ret = ufs_mtk_post_link(hba);
909 static int ufs_mtk_device_reset(struct ufs_hba *hba)
911 struct arm_smccc_res res;
913 /* disable hba before device reset */
914 ufshcd_hba_stop(hba);
916 ufs_mtk_device_reset_ctrl(0, res);
919 * The reset signal is active low. UFS devices shall detect
920 * more than or equal to 1us of positive or negative RST_n
923 * To be on safe side, keep the reset low for at least 10us.
925 usleep_range(10, 15);
927 ufs_mtk_device_reset_ctrl(1, res);
929 /* Some devices may need time to respond to rst_n */
930 usleep_range(10000, 15000);
932 dev_info(hba->dev, "device reset done\n");
937 static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
941 err = ufshcd_hba_enable(hba);
945 err = ufs_mtk_unipro_set_lpm(hba, false);
949 err = ufshcd_uic_hibern8_exit(hba);
951 ufshcd_set_link_active(hba);
955 err = ufshcd_make_hba_operational(hba);
962 static int ufs_mtk_link_set_lpm(struct ufs_hba *hba)
966 err = ufs_mtk_unipro_set_lpm(hba, true);
968 /* Resume UniPro state for following error recovery */
969 ufs_mtk_unipro_set_lpm(hba, false);
976 static void ufs_mtk_vreg_set_lpm(struct ufs_hba *hba, bool lpm)
978 if (!hba->vreg_info.vccq2 || !hba->vreg_info.vcc)
981 if (lpm && !hba->vreg_info.vcc->enabled)
982 regulator_set_mode(hba->vreg_info.vccq2->reg,
983 REGULATOR_MODE_IDLE);
985 regulator_set_mode(hba->vreg_info.vccq2->reg,
986 REGULATOR_MODE_NORMAL);
989 static void ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
993 /* disable auto-hibern8 */
994 ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
996 /* wait host return to idle state when auto-hibern8 off */
997 ufs_mtk_wait_idle_state(hba, 5);
999 ret = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
1001 dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret);
1004 static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
1005 enum ufs_notify_change_status status)
1008 struct arm_smccc_res res;
1010 if (status == PRE_CHANGE) {
1011 if (!ufshcd_is_auto_hibern8_supported(hba))
1013 ufs_mtk_auto_hibern8_disable(hba);
1017 if (ufshcd_is_link_hibern8(hba)) {
1018 err = ufs_mtk_link_set_lpm(hba);
1023 if (!ufshcd_is_link_active(hba)) {
1025 * Make sure no error will be returned to prevent
1026 * ufshcd_suspend() re-enabling regulators while vreg is still
1027 * in low-power mode.
1029 ufs_mtk_vreg_set_lpm(hba, true);
1030 err = ufs_mtk_mphy_power_on(hba, false);
1035 if (ufshcd_is_link_off(hba))
1036 ufs_mtk_device_reset_ctrl(0, res);
1041 * Set link as off state enforcedly to trigger
1042 * ufshcd_host_reset_and_restore() in ufshcd_suspend()
1043 * for completed host reset.
1045 ufshcd_set_link_off(hba);
1049 static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1053 err = ufs_mtk_mphy_power_on(hba, true);
1057 ufs_mtk_vreg_set_lpm(hba, false);
1059 if (ufshcd_is_link_hibern8(hba)) {
1060 err = ufs_mtk_link_set_hpm(hba);
1067 return ufshcd_link_recovery(hba);
1070 static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
1072 ufshcd_dump_regs(hba, REG_UFS_REFCLK_CTRL, 0x4, "Ref-Clk Ctrl ");
1074 ufshcd_dump_regs(hba, REG_UFS_EXTREG, 0x4, "Ext Reg ");
1076 ufshcd_dump_regs(hba, REG_UFS_MPHYCTRL,
1077 REG_UFS_REJECT_MON - REG_UFS_MPHYCTRL + 4,
1080 /* Direct debugging information to REG_MTK_PROBE */
1081 ufs_mtk_dbg_sel(hba);
1082 ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
1085 static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba)
1087 struct ufs_dev_info *dev_info = &hba->dev_info;
1088 u16 mid = dev_info->wmanufacturerid;
1090 if (mid == UFS_VENDOR_SAMSUNG)
1091 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6);
1094 * Decide waiting time before gating reference clock and
1095 * after ungating reference clock according to vendors'
1098 if (mid == UFS_VENDOR_SAMSUNG)
1099 ufs_mtk_setup_ref_clk_wait_us(hba, 1);
1100 else if (mid == UFS_VENDOR_SKHYNIX)
1101 ufs_mtk_setup_ref_clk_wait_us(hba, 30);
1102 else if (mid == UFS_VENDOR_TOSHIBA)
1103 ufs_mtk_setup_ref_clk_wait_us(hba, 100);
1105 ufs_mtk_setup_ref_clk_wait_us(hba,
1106 REFCLK_DEFAULT_WAIT_US);
1111 static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
1113 ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
1115 if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc &&
1116 (hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)) {
1117 hba->vreg_info.vcc->always_on = true;
1119 * VCC will be kept always-on thus we don't
1120 * need any delay during regulator operations
1122 hba->dev_quirks &= ~(UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
1123 UFS_DEVICE_QUIRK_DELAY_AFTER_LPM);
1127 static void ufs_mtk_event_notify(struct ufs_hba *hba,
1128 enum ufs_event_type evt, void *data)
1130 unsigned int val = *(u32 *)data;
1132 trace_ufs_mtk_event(evt, val);
1136 * struct ufs_hba_mtk_vops - UFS MTK specific variant operations
1138 * The variant operations configure the necessary controller and PHY
1139 * handshake during initialization.
1141 static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
1142 .name = "mediatek.ufshci",
1143 .init = ufs_mtk_init,
1144 .get_ufs_hci_version = ufs_mtk_get_ufs_hci_version,
1145 .setup_clocks = ufs_mtk_setup_clocks,
1146 .hce_enable_notify = ufs_mtk_hce_enable_notify,
1147 .link_startup_notify = ufs_mtk_link_startup_notify,
1148 .pwr_change_notify = ufs_mtk_pwr_change_notify,
1149 .apply_dev_quirks = ufs_mtk_apply_dev_quirks,
1150 .fixup_dev_quirks = ufs_mtk_fixup_dev_quirks,
1151 .suspend = ufs_mtk_suspend,
1152 .resume = ufs_mtk_resume,
1153 .dbg_register_dump = ufs_mtk_dbg_register_dump,
1154 .device_reset = ufs_mtk_device_reset,
1155 .event_notify = ufs_mtk_event_notify,
1159 * ufs_mtk_probe - probe routine of the driver
1160 * @pdev: pointer to Platform device handle
1162 * Return zero for success and non-zero for failure
1164 static int ufs_mtk_probe(struct platform_device *pdev)
1167 struct device *dev = &pdev->dev;
1168 struct device_node *reset_node;
1169 struct platform_device *reset_pdev;
1170 struct device_link *link;
1172 reset_node = of_find_compatible_node(NULL, NULL,
1175 dev_notice(dev, "find ti,syscon-reset fail\n");
1178 reset_pdev = of_find_device_by_node(reset_node);
1180 dev_notice(dev, "find reset_pdev fail\n");
1183 link = device_link_add(dev, &reset_pdev->dev,
1184 DL_FLAG_AUTOPROBE_CONSUMER);
1185 put_device(&reset_pdev->dev);
1187 dev_notice(dev, "add reset device_link fail\n");
1190 /* supplier is not probed */
1191 if (link->status == DL_STATE_DORMANT) {
1192 err = -EPROBE_DEFER;
1197 /* perform generic probe */
1198 err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
1202 dev_info(dev, "probe failed %d\n", err);
1204 of_node_put(reset_node);
1209 * ufs_mtk_remove - set driver_data of the device to NULL
1210 * @pdev: pointer to platform device handle
1214 static int ufs_mtk_remove(struct platform_device *pdev)
1216 struct ufs_hba *hba = platform_get_drvdata(pdev);
1218 pm_runtime_get_sync(&(pdev)->dev);
1223 static const struct dev_pm_ops ufs_mtk_pm_ops = {
1224 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
1225 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1226 .prepare = ufshcd_suspend_prepare,
1227 .complete = ufshcd_resume_complete,
1230 static struct platform_driver ufs_mtk_pltform = {
1231 .probe = ufs_mtk_probe,
1232 .remove = ufs_mtk_remove,
1233 .shutdown = ufshcd_pltfrm_shutdown,
1235 .name = "ufshcd-mtk",
1236 .pm = &ufs_mtk_pm_ops,
1237 .of_match_table = ufs_mtk_of_match,
1241 MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
1242 MODULE_AUTHOR("Peter Wang <peter.wang@mediatek.com>");
1243 MODULE_DESCRIPTION("MediaTek UFS Host Driver");
1244 MODULE_LICENSE("GPL v2");
1246 module_platform_driver(ufs_mtk_pltform);