1 // SPDX-License-Identifier: GPL-1.0+
3 * Device driver for Microgate SyncLink GT serial adapters.
5 * written by Paul Fulghum for Microgate Corporation
8 * Microgate and SyncLink are trademarks of Microgate Corporation
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 * DEBUG OUTPUT DEFINITIONS
26 * uncomment lines below to enable specific types of debug output
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42 /*#define DBGTBUF(info) dump_tbufs(info)*/
43 /*#define DBGRBUF(info) dump_rbufs(info)*/
46 #include <linux/module.h>
47 #include <linux/errno.h>
48 #include <linux/signal.h>
49 #include <linux/sched.h>
50 #include <linux/timer.h>
51 #include <linux/interrupt.h>
52 #include <linux/pci.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55 #include <linux/serial.h>
56 #include <linux/major.h>
57 #include <linux/string.h>
58 #include <linux/fcntl.h>
59 #include <linux/ptrace.h>
60 #include <linux/ioport.h>
62 #include <linux/seq_file.h>
63 #include <linux/slab.h>
64 #include <linux/netdevice.h>
65 #include <linux/vmalloc.h>
66 #include <linux/init.h>
67 #include <linux/delay.h>
68 #include <linux/ioctl.h>
69 #include <linux/termios.h>
70 #include <linux/bitops.h>
71 #include <linux/workqueue.h>
72 #include <linux/hdlc.h>
73 #include <linux/synclink.h>
78 #include <asm/types.h>
79 #include <linux/uaccess.h>
81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82 #define SYNCLINK_GENERIC_HDLC 1
84 #define SYNCLINK_GENERIC_HDLC 0
88 * module identification
90 static char *driver_name = "SyncLink GT";
91 static char *slgt_driver_name = "synclink_gt";
92 static char *tty_dev_prefix = "ttySLG";
93 MODULE_LICENSE("GPL");
94 #define MGSL_MAGIC 0x5401
95 #define MAX_DEVICES 32
97 static const struct pci_device_id pci_table[] = {
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {0,}, /* terminate list */
104 MODULE_DEVICE_TABLE(pci, pci_table);
106 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
107 static void remove_one(struct pci_dev *dev);
108 static struct pci_driver pci_driver = {
109 .name = "synclink_gt",
110 .id_table = pci_table,
112 .remove = remove_one,
115 static bool pci_registered;
118 * module configuration and status
120 static struct slgt_info *slgt_device_list;
121 static int slgt_device_count;
124 static int debug_level;
125 static int maxframe[MAX_DEVICES];
127 module_param(ttymajor, int, 0);
128 module_param(debug_level, int, 0);
129 module_param_array(maxframe, int, NULL, 0);
131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
136 * tty support and callbacks
138 static struct tty_driver *serial_driver;
140 static void wait_until_sent(struct tty_struct *tty, int timeout);
141 static void flush_buffer(struct tty_struct *tty);
142 static void tx_release(struct tty_struct *tty);
145 * generic HDLC support
147 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
151 * device specific structures, macros and functions
154 #define SLGT_MAX_PORTS 4
155 #define SLGT_REG_SIZE 256
158 * conditional wait facility
161 struct cond_wait *next;
163 wait_queue_entry_t wait;
166 static void flush_cond_wait(struct cond_wait **head);
169 * DMA buffer descriptor and access macros
175 __le32 pbuf; /* physical address of data buffer */
176 __le32 next; /* physical address of next descriptor */
178 /* driver book keeping */
179 char *buf; /* virtual address of data buffer */
180 unsigned int pdesc; /* physical address of this descriptor */
181 dma_addr_t buf_dma_addr;
182 unsigned short buf_count;
185 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
186 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
187 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
188 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
189 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
190 #define desc_count(a) (le16_to_cpu((a).count))
191 #define desc_status(a) (le16_to_cpu((a).status))
192 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
193 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
194 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
195 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
196 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
198 struct _input_signal_events {
210 * device instance data structure
213 void *if_ptr; /* General purpose pointer (used by SPPP) */
214 struct tty_port port;
216 struct slgt_info *next_device; /* device list link */
220 char device_name[25];
221 struct pci_dev *pdev;
223 int port_count; /* count of ports on adapter */
224 int adapter_num; /* adapter instance number */
225 int port_num; /* port instance number */
227 /* array of pointers to port contexts on this adapter */
228 struct slgt_info *port_array[SLGT_MAX_PORTS];
230 int line; /* tty line instance number */
232 struct mgsl_icount icount;
235 int x_char; /* xon/xoff character */
236 unsigned int read_status_mask;
237 unsigned int ignore_status_mask;
239 wait_queue_head_t status_event_wait_q;
240 wait_queue_head_t event_wait_q;
241 struct timer_list tx_timer;
242 struct timer_list rx_timer;
244 unsigned int gpio_present;
245 struct cond_wait *gpio_wait_q;
247 spinlock_t lock; /* spinlock for synchronizing with ISR */
249 struct work_struct task;
255 bool irq_requested; /* true if IRQ requested */
256 bool irq_occurred; /* for diagnostics use */
258 /* device configuration */
260 unsigned int bus_type;
261 unsigned int irq_level;
262 unsigned long irq_flags;
264 unsigned char __iomem * reg_addr; /* memory mapped registers address */
266 bool reg_addr_requested;
268 MGSL_PARAMS params; /* communications parameters */
270 u32 max_frame_size; /* as set by device config */
272 unsigned int rbuf_fill_level;
274 unsigned int if_mode;
275 unsigned int base_clock;
287 unsigned char signals; /* serial signal states */
288 int init_error; /* initialization error */
290 unsigned char *tx_buf;
294 bool drop_rts_on_tx_done;
295 struct _input_signal_events input_signal_events;
297 int dcd_chkcount; /* check counts to prevent */
298 int cts_chkcount; /* too many IRQs if a signal */
299 int dsr_chkcount; /* is floating */
302 char *bufs; /* virtual address of DMA buffer lists */
303 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
305 unsigned int rbuf_count;
306 struct slgt_desc *rbufs;
307 unsigned int rbuf_current;
308 unsigned int rbuf_index;
309 unsigned int rbuf_fill_index;
310 unsigned short rbuf_fill_count;
312 unsigned int tbuf_count;
313 struct slgt_desc *tbufs;
314 unsigned int tbuf_current;
315 unsigned int tbuf_start;
317 unsigned char *tmp_rbuf;
318 unsigned int tmp_rbuf_count;
320 /* SPPP/Cisco HDLC device parts */
324 #if SYNCLINK_GENERIC_HDLC
325 struct net_device *netdev;
330 static MGSL_PARAMS default_params = {
331 .mode = MGSL_MODE_HDLC,
333 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
334 .encoding = HDLC_ENCODING_NRZI_SPACE,
337 .crc_type = HDLC_CRC_16_CCITT,
338 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
339 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
343 .parity = ASYNC_PARITY_NONE
348 #define BH_TRANSMIT 2
350 #define IO_PIN_SHUTDOWN_LIMIT 100
352 #define DMABUFSIZE 256
353 #define DESC_LIST_SIZE 4096
355 #define MASK_PARITY BIT1
356 #define MASK_FRAMING BIT0
357 #define MASK_BREAK BIT14
358 #define MASK_OVERRUN BIT4
360 #define GSR 0x00 /* global status */
361 #define JCR 0x04 /* JTAG control */
362 #define IODR 0x08 /* GPIO direction */
363 #define IOER 0x0c /* GPIO interrupt enable */
364 #define IOVR 0x10 /* GPIO value */
365 #define IOSR 0x14 /* GPIO interrupt status */
366 #define TDR 0x80 /* tx data */
367 #define RDR 0x80 /* rx data */
368 #define TCR 0x82 /* tx control */
369 #define TIR 0x84 /* tx idle */
370 #define TPR 0x85 /* tx preamble */
371 #define RCR 0x86 /* rx control */
372 #define VCR 0x88 /* V.24 control */
373 #define CCR 0x89 /* clock control */
374 #define BDR 0x8a /* baud divisor */
375 #define SCR 0x8c /* serial control */
376 #define SSR 0x8e /* serial status */
377 #define RDCSR 0x90 /* rx DMA control/status */
378 #define TDCSR 0x94 /* tx DMA control/status */
379 #define RDDAR 0x98 /* rx DMA descriptor address */
380 #define TDDAR 0x9c /* tx DMA descriptor address */
381 #define XSR 0x40 /* extended sync pattern */
382 #define XCR 0x44 /* extended control */
385 #define RXBREAK BIT14
386 #define IRQ_TXDATA BIT13
387 #define IRQ_TXIDLE BIT12
388 #define IRQ_TXUNDER BIT11 /* HDLC */
389 #define IRQ_RXDATA BIT10
390 #define IRQ_RXIDLE BIT9 /* HDLC */
391 #define IRQ_RXBREAK BIT9 /* async */
392 #define IRQ_RXOVER BIT8
397 #define IRQ_ALL 0x3ff0
398 #define IRQ_MASTER BIT0
400 #define slgt_irq_on(info, mask) \
401 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
402 #define slgt_irq_off(info, mask) \
403 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
405 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
406 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
407 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
408 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
409 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
410 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
412 static void msc_set_vcr(struct slgt_info *info);
414 static int startup(struct slgt_info *info);
415 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
416 static void shutdown(struct slgt_info *info);
417 static void program_hw(struct slgt_info *info);
418 static void change_params(struct slgt_info *info);
420 static int adapter_test(struct slgt_info *info);
422 static void reset_port(struct slgt_info *info);
423 static void async_mode(struct slgt_info *info);
424 static void sync_mode(struct slgt_info *info);
426 static void rx_stop(struct slgt_info *info);
427 static void rx_start(struct slgt_info *info);
428 static void reset_rbufs(struct slgt_info *info);
429 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
430 static bool rx_get_frame(struct slgt_info *info);
431 static bool rx_get_buf(struct slgt_info *info);
433 static void tx_start(struct slgt_info *info);
434 static void tx_stop(struct slgt_info *info);
435 static void tx_set_idle(struct slgt_info *info);
436 static unsigned int tbuf_bytes(struct slgt_info *info);
437 static void reset_tbufs(struct slgt_info *info);
438 static void tdma_reset(struct slgt_info *info);
439 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
441 static void get_gtsignals(struct slgt_info *info);
442 static void set_gtsignals(struct slgt_info *info);
443 static void set_rate(struct slgt_info *info, u32 data_rate);
445 static void bh_transmit(struct slgt_info *info);
446 static void isr_txeom(struct slgt_info *info, unsigned short status);
448 static void tx_timeout(struct timer_list *t);
449 static void rx_timeout(struct timer_list *t);
454 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
455 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
456 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
457 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
458 static int set_txidle(struct slgt_info *info, int idle_mode);
459 static int tx_enable(struct slgt_info *info, int enable);
460 static int tx_abort(struct slgt_info *info);
461 static int rx_enable(struct slgt_info *info, int enable);
462 static int modem_input_wait(struct slgt_info *info,int arg);
463 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
464 static int get_interface(struct slgt_info *info, int __user *if_mode);
465 static int set_interface(struct slgt_info *info, int if_mode);
466 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
467 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
468 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
469 static int get_xsync(struct slgt_info *info, int __user *if_mode);
470 static int set_xsync(struct slgt_info *info, int if_mode);
471 static int get_xctrl(struct slgt_info *info, int __user *if_mode);
472 static int set_xctrl(struct slgt_info *info, int if_mode);
477 static void release_resources(struct slgt_info *info);
496 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
500 printk("%s %s data:\n",info->device_name, label);
502 linecount = (count > 16) ? 16 : count;
503 for(i=0; i < linecount; i++)
504 printk("%02X ",(unsigned char)data[i]);
507 for(i=0;i<linecount;i++) {
508 if (data[i]>=040 && data[i]<=0176)
509 printk("%c",data[i]);
519 #define DBGDATA(info, buf, size, label)
523 static void dump_tbufs(struct slgt_info *info)
526 printk("tbuf_current=%d\n", info->tbuf_current);
527 for (i=0 ; i < info->tbuf_count ; i++) {
528 printk("%d: count=%04X status=%04X\n",
529 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
533 #define DBGTBUF(info)
537 static void dump_rbufs(struct slgt_info *info)
540 printk("rbuf_current=%d\n", info->rbuf_current);
541 for (i=0 ; i < info->rbuf_count ; i++) {
542 printk("%d: count=%04X status=%04X\n",
543 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
547 #define DBGRBUF(info)
550 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
554 printk("null struct slgt_info for (%s) in %s\n", devname, name);
557 if (info->magic != MGSL_MAGIC) {
558 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
569 * line discipline callback wrappers
571 * The wrappers maintain line discipline references
572 * while calling into the line discipline.
574 * ldisc_receive_buf - pass receive data to line discipline
576 static void ldisc_receive_buf(struct tty_struct *tty,
577 const __u8 *data, char *flags, int count)
579 struct tty_ldisc *ld;
582 ld = tty_ldisc_ref(tty);
584 if (ld->ops->receive_buf)
585 ld->ops->receive_buf(tty, data, flags, count);
592 static int open(struct tty_struct *tty, struct file *filp)
594 struct slgt_info *info;
599 if (line >= slgt_device_count) {
600 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
604 info = slgt_device_list;
605 while(info && info->line != line)
606 info = info->next_device;
607 if (sanity_check(info, tty->name, "open"))
609 if (info->init_error) {
610 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
614 tty->driver_data = info;
615 info->port.tty = tty;
617 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
619 mutex_lock(&info->port.mutex);
621 spin_lock_irqsave(&info->netlock, flags);
622 if (info->netcount) {
624 spin_unlock_irqrestore(&info->netlock, flags);
625 mutex_unlock(&info->port.mutex);
629 spin_unlock_irqrestore(&info->netlock, flags);
631 if (info->port.count == 1) {
632 /* 1st open on this device, init hardware */
633 retval = startup(info);
635 mutex_unlock(&info->port.mutex);
639 mutex_unlock(&info->port.mutex);
640 retval = block_til_ready(tty, filp, info);
642 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
651 info->port.tty = NULL; /* tty layer will release tty struct */
656 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
660 static void close(struct tty_struct *tty, struct file *filp)
662 struct slgt_info *info = tty->driver_data;
664 if (sanity_check(info, tty->name, "close"))
666 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
668 if (tty_port_close_start(&info->port, tty, filp) == 0)
671 mutex_lock(&info->port.mutex);
672 if (tty_port_initialized(&info->port))
673 wait_until_sent(tty, info->timeout);
675 tty_ldisc_flush(tty);
678 mutex_unlock(&info->port.mutex);
680 tty_port_close_end(&info->port, tty);
681 info->port.tty = NULL;
683 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
686 static void hangup(struct tty_struct *tty)
688 struct slgt_info *info = tty->driver_data;
691 if (sanity_check(info, tty->name, "hangup"))
693 DBGINFO(("%s hangup\n", info->device_name));
697 mutex_lock(&info->port.mutex);
700 spin_lock_irqsave(&info->port.lock, flags);
701 info->port.count = 0;
702 info->port.tty = NULL;
703 spin_unlock_irqrestore(&info->port.lock, flags);
704 tty_port_set_active(&info->port, 0);
705 mutex_unlock(&info->port.mutex);
707 wake_up_interruptible(&info->port.open_wait);
710 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
712 struct slgt_info *info = tty->driver_data;
715 DBGINFO(("%s set_termios\n", tty->driver->name));
719 /* Handle transition to B0 status */
720 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
721 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
722 spin_lock_irqsave(&info->lock,flags);
724 spin_unlock_irqrestore(&info->lock,flags);
727 /* Handle transition away from B0 status */
728 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
729 info->signals |= SerialSignal_DTR;
730 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
731 info->signals |= SerialSignal_RTS;
732 spin_lock_irqsave(&info->lock,flags);
734 spin_unlock_irqrestore(&info->lock,flags);
737 /* Handle turning off CRTSCTS */
738 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
744 static void update_tx_timer(struct slgt_info *info)
747 * use worst case speed of 1200bps to calculate transmit timeout
748 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
750 if (info->params.mode == MGSL_MODE_HDLC) {
751 int timeout = (tbuf_bytes(info) * 7) + 1000;
752 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
756 static int write(struct tty_struct *tty,
757 const unsigned char *buf, int count)
760 struct slgt_info *info = tty->driver_data;
763 if (sanity_check(info, tty->name, "write"))
766 DBGINFO(("%s write count=%d\n", info->device_name, count));
768 if (!info->tx_buf || (count > info->max_frame_size))
771 if (!count || tty->flow.stopped || tty->hw_stopped)
774 spin_lock_irqsave(&info->lock, flags);
776 if (info->tx_count) {
777 /* send accumulated data from send_char() */
778 if (!tx_load(info, info->tx_buf, info->tx_count))
783 if (tx_load(info, buf, count))
787 spin_unlock_irqrestore(&info->lock, flags);
788 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
792 static int put_char(struct tty_struct *tty, unsigned char ch)
794 struct slgt_info *info = tty->driver_data;
798 if (sanity_check(info, tty->name, "put_char"))
800 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
803 spin_lock_irqsave(&info->lock,flags);
804 if (info->tx_count < info->max_frame_size) {
805 info->tx_buf[info->tx_count++] = ch;
808 spin_unlock_irqrestore(&info->lock,flags);
812 static void send_xchar(struct tty_struct *tty, char ch)
814 struct slgt_info *info = tty->driver_data;
817 if (sanity_check(info, tty->name, "send_xchar"))
819 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
822 spin_lock_irqsave(&info->lock,flags);
823 if (!info->tx_enabled)
825 spin_unlock_irqrestore(&info->lock,flags);
829 static void wait_until_sent(struct tty_struct *tty, int timeout)
831 struct slgt_info *info = tty->driver_data;
832 unsigned long orig_jiffies, char_time;
836 if (sanity_check(info, tty->name, "wait_until_sent"))
838 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
839 if (!tty_port_initialized(&info->port))
842 orig_jiffies = jiffies;
844 /* Set check interval to 1/5 of estimated time to
845 * send a character, and make it at least 1. The check
846 * interval should also be less than the timeout.
847 * Note: use tight timings here to satisfy the NIST-PCTS.
850 if (info->params.data_rate) {
851 char_time = info->timeout/(32 * 5);
858 char_time = min_t(unsigned long, char_time, timeout);
860 while (info->tx_active) {
861 msleep_interruptible(jiffies_to_msecs(char_time));
862 if (signal_pending(current))
864 if (timeout && time_after(jiffies, orig_jiffies + timeout))
868 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
871 static unsigned int write_room(struct tty_struct *tty)
873 struct slgt_info *info = tty->driver_data;
876 if (sanity_check(info, tty->name, "write_room"))
878 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
879 DBGINFO(("%s write_room=%u\n", info->device_name, ret));
883 static void flush_chars(struct tty_struct *tty)
885 struct slgt_info *info = tty->driver_data;
888 if (sanity_check(info, tty->name, "flush_chars"))
890 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
892 if (info->tx_count <= 0 || tty->flow.stopped ||
893 tty->hw_stopped || !info->tx_buf)
896 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
898 spin_lock_irqsave(&info->lock,flags);
899 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
901 spin_unlock_irqrestore(&info->lock,flags);
904 static void flush_buffer(struct tty_struct *tty)
906 struct slgt_info *info = tty->driver_data;
909 if (sanity_check(info, tty->name, "flush_buffer"))
911 DBGINFO(("%s flush_buffer\n", info->device_name));
913 spin_lock_irqsave(&info->lock, flags);
915 spin_unlock_irqrestore(&info->lock, flags);
921 * throttle (stop) transmitter
923 static void tx_hold(struct tty_struct *tty)
925 struct slgt_info *info = tty->driver_data;
928 if (sanity_check(info, tty->name, "tx_hold"))
930 DBGINFO(("%s tx_hold\n", info->device_name));
931 spin_lock_irqsave(&info->lock,flags);
932 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
934 spin_unlock_irqrestore(&info->lock,flags);
938 * release (start) transmitter
940 static void tx_release(struct tty_struct *tty)
942 struct slgt_info *info = tty->driver_data;
945 if (sanity_check(info, tty->name, "tx_release"))
947 DBGINFO(("%s tx_release\n", info->device_name));
948 spin_lock_irqsave(&info->lock, flags);
949 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
951 spin_unlock_irqrestore(&info->lock, flags);
955 * Service an IOCTL request
959 * tty pointer to tty instance data
960 * cmd IOCTL command code
961 * arg command argument/context
963 * Return 0 if success, otherwise error code
965 static int ioctl(struct tty_struct *tty,
966 unsigned int cmd, unsigned long arg)
968 struct slgt_info *info = tty->driver_data;
969 void __user *argp = (void __user *)arg;
972 if (sanity_check(info, tty->name, "ioctl"))
974 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
976 if (cmd != TIOCMIWAIT) {
977 if (tty_io_error(tty))
982 case MGSL_IOCWAITEVENT:
983 return wait_mgsl_event(info, argp);
985 return modem_input_wait(info,(int)arg);
987 return set_gpio(info, argp);
989 return get_gpio(info, argp);
990 case MGSL_IOCWAITGPIO:
991 return wait_gpio(info, argp);
993 return get_xsync(info, argp);
995 return set_xsync(info, (int)arg);
997 return get_xctrl(info, argp);
999 return set_xctrl(info, (int)arg);
1001 mutex_lock(&info->port.mutex);
1003 case MGSL_IOCGPARAMS:
1004 ret = get_params(info, argp);
1006 case MGSL_IOCSPARAMS:
1007 ret = set_params(info, argp);
1009 case MGSL_IOCGTXIDLE:
1010 ret = get_txidle(info, argp);
1012 case MGSL_IOCSTXIDLE:
1013 ret = set_txidle(info, (int)arg);
1015 case MGSL_IOCTXENABLE:
1016 ret = tx_enable(info, (int)arg);
1018 case MGSL_IOCRXENABLE:
1019 ret = rx_enable(info, (int)arg);
1021 case MGSL_IOCTXABORT:
1022 ret = tx_abort(info);
1024 case MGSL_IOCGSTATS:
1025 ret = get_stats(info, argp);
1028 ret = get_interface(info, argp);
1031 ret = set_interface(info,(int)arg);
1036 mutex_unlock(&info->port.mutex);
1040 static int get_icount(struct tty_struct *tty,
1041 struct serial_icounter_struct *icount)
1044 struct slgt_info *info = tty->driver_data;
1045 struct mgsl_icount cnow; /* kernel counter temps */
1046 unsigned long flags;
1048 spin_lock_irqsave(&info->lock,flags);
1049 cnow = info->icount;
1050 spin_unlock_irqrestore(&info->lock,flags);
1052 icount->cts = cnow.cts;
1053 icount->dsr = cnow.dsr;
1054 icount->rng = cnow.rng;
1055 icount->dcd = cnow.dcd;
1056 icount->rx = cnow.rx;
1057 icount->tx = cnow.tx;
1058 icount->frame = cnow.frame;
1059 icount->overrun = cnow.overrun;
1060 icount->parity = cnow.parity;
1061 icount->brk = cnow.brk;
1062 icount->buf_overrun = cnow.buf_overrun;
1068 * support for 32 bit ioctl calls on 64 bit systems
1070 #ifdef CONFIG_COMPAT
1071 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1073 struct MGSL_PARAMS32 tmp_params;
1075 DBGINFO(("%s get_params32\n", info->device_name));
1076 memset(&tmp_params, 0, sizeof(tmp_params));
1077 tmp_params.mode = (compat_ulong_t)info->params.mode;
1078 tmp_params.loopback = info->params.loopback;
1079 tmp_params.flags = info->params.flags;
1080 tmp_params.encoding = info->params.encoding;
1081 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1082 tmp_params.addr_filter = info->params.addr_filter;
1083 tmp_params.crc_type = info->params.crc_type;
1084 tmp_params.preamble_length = info->params.preamble_length;
1085 tmp_params.preamble = info->params.preamble;
1086 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1087 tmp_params.data_bits = info->params.data_bits;
1088 tmp_params.stop_bits = info->params.stop_bits;
1089 tmp_params.parity = info->params.parity;
1090 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1095 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1097 struct MGSL_PARAMS32 tmp_params;
1099 DBGINFO(("%s set_params32\n", info->device_name));
1100 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1103 spin_lock(&info->lock);
1104 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1105 info->base_clock = tmp_params.clock_speed;
1107 info->params.mode = tmp_params.mode;
1108 info->params.loopback = tmp_params.loopback;
1109 info->params.flags = tmp_params.flags;
1110 info->params.encoding = tmp_params.encoding;
1111 info->params.clock_speed = tmp_params.clock_speed;
1112 info->params.addr_filter = tmp_params.addr_filter;
1113 info->params.crc_type = tmp_params.crc_type;
1114 info->params.preamble_length = tmp_params.preamble_length;
1115 info->params.preamble = tmp_params.preamble;
1116 info->params.data_rate = tmp_params.data_rate;
1117 info->params.data_bits = tmp_params.data_bits;
1118 info->params.stop_bits = tmp_params.stop_bits;
1119 info->params.parity = tmp_params.parity;
1121 spin_unlock(&info->lock);
1128 static long slgt_compat_ioctl(struct tty_struct *tty,
1129 unsigned int cmd, unsigned long arg)
1131 struct slgt_info *info = tty->driver_data;
1134 if (sanity_check(info, tty->name, "compat_ioctl"))
1136 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1139 case MGSL_IOCSPARAMS32:
1140 rc = set_params32(info, compat_ptr(arg));
1143 case MGSL_IOCGPARAMS32:
1144 rc = get_params32(info, compat_ptr(arg));
1147 case MGSL_IOCGPARAMS:
1148 case MGSL_IOCSPARAMS:
1149 case MGSL_IOCGTXIDLE:
1150 case MGSL_IOCGSTATS:
1151 case MGSL_IOCWAITEVENT:
1155 case MGSL_IOCWAITGPIO:
1156 case MGSL_IOCGXSYNC:
1157 case MGSL_IOCGXCTRL:
1158 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1161 rc = ioctl(tty, cmd, arg);
1163 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1167 #define slgt_compat_ioctl NULL
1168 #endif /* ifdef CONFIG_COMPAT */
1173 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1176 unsigned long flags;
1178 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1179 info->device_name, info->phys_reg_addr,
1180 info->irq_level, info->max_frame_size);
1182 /* output current serial signal states */
1183 spin_lock_irqsave(&info->lock,flags);
1184 get_gtsignals(info);
1185 spin_unlock_irqrestore(&info->lock,flags);
1189 if (info->signals & SerialSignal_RTS)
1190 strcat(stat_buf, "|RTS");
1191 if (info->signals & SerialSignal_CTS)
1192 strcat(stat_buf, "|CTS");
1193 if (info->signals & SerialSignal_DTR)
1194 strcat(stat_buf, "|DTR");
1195 if (info->signals & SerialSignal_DSR)
1196 strcat(stat_buf, "|DSR");
1197 if (info->signals & SerialSignal_DCD)
1198 strcat(stat_buf, "|CD");
1199 if (info->signals & SerialSignal_RI)
1200 strcat(stat_buf, "|RI");
1202 if (info->params.mode != MGSL_MODE_ASYNC) {
1203 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1204 info->icount.txok, info->icount.rxok);
1205 if (info->icount.txunder)
1206 seq_printf(m, " txunder:%d", info->icount.txunder);
1207 if (info->icount.txabort)
1208 seq_printf(m, " txabort:%d", info->icount.txabort);
1209 if (info->icount.rxshort)
1210 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1211 if (info->icount.rxlong)
1212 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1213 if (info->icount.rxover)
1214 seq_printf(m, " rxover:%d", info->icount.rxover);
1215 if (info->icount.rxcrc)
1216 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1218 seq_printf(m, "\tASYNC tx:%d rx:%d",
1219 info->icount.tx, info->icount.rx);
1220 if (info->icount.frame)
1221 seq_printf(m, " fe:%d", info->icount.frame);
1222 if (info->icount.parity)
1223 seq_printf(m, " pe:%d", info->icount.parity);
1224 if (info->icount.brk)
1225 seq_printf(m, " brk:%d", info->icount.brk);
1226 if (info->icount.overrun)
1227 seq_printf(m, " oe:%d", info->icount.overrun);
1230 /* Append serial signal status to end */
1231 seq_printf(m, " %s\n", stat_buf+1);
1233 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1234 info->tx_active,info->bh_requested,info->bh_running,
1238 /* Called to print information about devices
1240 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1242 struct slgt_info *info;
1244 seq_puts(m, "synclink_gt driver\n");
1246 info = slgt_device_list;
1249 info = info->next_device;
1255 * return count of bytes in transmit buffer
1257 static unsigned int chars_in_buffer(struct tty_struct *tty)
1259 struct slgt_info *info = tty->driver_data;
1261 if (sanity_check(info, tty->name, "chars_in_buffer"))
1263 count = tbuf_bytes(info);
1264 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1269 * signal remote device to throttle send data (our receive data)
1271 static void throttle(struct tty_struct * tty)
1273 struct slgt_info *info = tty->driver_data;
1274 unsigned long flags;
1276 if (sanity_check(info, tty->name, "throttle"))
1278 DBGINFO(("%s throttle\n", info->device_name));
1280 send_xchar(tty, STOP_CHAR(tty));
1281 if (C_CRTSCTS(tty)) {
1282 spin_lock_irqsave(&info->lock,flags);
1283 info->signals &= ~SerialSignal_RTS;
1284 set_gtsignals(info);
1285 spin_unlock_irqrestore(&info->lock,flags);
1290 * signal remote device to stop throttling send data (our receive data)
1292 static void unthrottle(struct tty_struct * tty)
1294 struct slgt_info *info = tty->driver_data;
1295 unsigned long flags;
1297 if (sanity_check(info, tty->name, "unthrottle"))
1299 DBGINFO(("%s unthrottle\n", info->device_name));
1304 send_xchar(tty, START_CHAR(tty));
1306 if (C_CRTSCTS(tty)) {
1307 spin_lock_irqsave(&info->lock,flags);
1308 info->signals |= SerialSignal_RTS;
1309 set_gtsignals(info);
1310 spin_unlock_irqrestore(&info->lock,flags);
1315 * set or clear transmit break condition
1316 * break_state -1=set break condition, 0=clear
1318 static int set_break(struct tty_struct *tty, int break_state)
1320 struct slgt_info *info = tty->driver_data;
1321 unsigned short value;
1322 unsigned long flags;
1324 if (sanity_check(info, tty->name, "set_break"))
1326 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1328 spin_lock_irqsave(&info->lock,flags);
1329 value = rd_reg16(info, TCR);
1330 if (break_state == -1)
1334 wr_reg16(info, TCR, value);
1335 spin_unlock_irqrestore(&info->lock,flags);
1339 #if SYNCLINK_GENERIC_HDLC
1342 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1343 * @dev: pointer to network device structure
1344 * @encoding: serial encoding setting
1345 * @parity: FCS setting
1347 * Set encoding and frame check sequence (FCS) options.
1349 * Return: 0 if success, otherwise error code
1351 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1352 unsigned short parity)
1354 struct slgt_info *info = dev_to_port(dev);
1355 unsigned char new_encoding;
1356 unsigned short new_crctype;
1358 /* return error if TTY interface open */
1359 if (info->port.count)
1362 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1366 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1367 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1368 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1369 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1370 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1371 default: return -EINVAL;
1376 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1377 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1378 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1379 default: return -EINVAL;
1382 info->params.encoding = new_encoding;
1383 info->params.crc_type = new_crctype;
1385 /* if network interface up, reprogram hardware */
1393 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1394 * @skb: socket buffer containing HDLC frame
1395 * @dev: pointer to network device structure
1397 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1398 struct net_device *dev)
1400 struct slgt_info *info = dev_to_port(dev);
1401 unsigned long flags;
1403 DBGINFO(("%s hdlc_xmit\n", dev->name));
1406 return NETDEV_TX_OK;
1408 /* stop sending until this frame completes */
1409 netif_stop_queue(dev);
1411 /* update network statistics */
1412 dev->stats.tx_packets++;
1413 dev->stats.tx_bytes += skb->len;
1415 /* save start time for transmit timeout detection */
1416 netif_trans_update(dev);
1418 spin_lock_irqsave(&info->lock, flags);
1419 tx_load(info, skb->data, skb->len);
1420 spin_unlock_irqrestore(&info->lock, flags);
1422 /* done with socket buffer, so free it */
1425 return NETDEV_TX_OK;
1429 * hdlcdev_open - called by network layer when interface enabled
1430 * @dev: pointer to network device structure
1432 * Claim resources and initialize hardware.
1434 * Return: 0 if success, otherwise error code
1436 static int hdlcdev_open(struct net_device *dev)
1438 struct slgt_info *info = dev_to_port(dev);
1440 unsigned long flags;
1442 if (!try_module_get(THIS_MODULE))
1445 DBGINFO(("%s hdlcdev_open\n", dev->name));
1447 /* generic HDLC layer open processing */
1448 rc = hdlc_open(dev);
1452 /* arbitrate between network and tty opens */
1453 spin_lock_irqsave(&info->netlock, flags);
1454 if (info->port.count != 0 || info->netcount != 0) {
1455 DBGINFO(("%s hdlc_open busy\n", dev->name));
1456 spin_unlock_irqrestore(&info->netlock, flags);
1460 spin_unlock_irqrestore(&info->netlock, flags);
1462 /* claim resources and init adapter */
1463 if ((rc = startup(info)) != 0) {
1464 spin_lock_irqsave(&info->netlock, flags);
1466 spin_unlock_irqrestore(&info->netlock, flags);
1470 /* assert RTS and DTR, apply hardware settings */
1471 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1474 /* enable network layer transmit */
1475 netif_trans_update(dev);
1476 netif_start_queue(dev);
1478 /* inform generic HDLC layer of current DCD status */
1479 spin_lock_irqsave(&info->lock, flags);
1480 get_gtsignals(info);
1481 spin_unlock_irqrestore(&info->lock, flags);
1482 if (info->signals & SerialSignal_DCD)
1483 netif_carrier_on(dev);
1485 netif_carrier_off(dev);
1490 * hdlcdev_close - called by network layer when interface is disabled
1491 * @dev: pointer to network device structure
1493 * Shutdown hardware and release resources.
1495 * Return: 0 if success, otherwise error code
1497 static int hdlcdev_close(struct net_device *dev)
1499 struct slgt_info *info = dev_to_port(dev);
1500 unsigned long flags;
1502 DBGINFO(("%s hdlcdev_close\n", dev->name));
1504 netif_stop_queue(dev);
1506 /* shutdown adapter and release resources */
1511 spin_lock_irqsave(&info->netlock, flags);
1513 spin_unlock_irqrestore(&info->netlock, flags);
1515 module_put(THIS_MODULE);
1520 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1521 * @dev: pointer to network device structure
1522 * @ifr: pointer to network interface request structure
1523 * @cmd: IOCTL command code
1525 * Return: 0 if success, otherwise error code
1527 static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
1529 const size_t size = sizeof(sync_serial_settings);
1530 sync_serial_settings new_line;
1531 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1532 struct slgt_info *info = dev_to_port(dev);
1535 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1537 /* return error if TTY interface open */
1538 if (info->port.count)
1541 memset(&new_line, 0, sizeof(new_line));
1543 switch (ifs->type) {
1544 case IF_GET_IFACE: /* return current sync_serial_settings */
1546 ifs->type = IF_IFACE_SYNC_SERIAL;
1547 if (ifs->size < size) {
1548 ifs->size = size; /* data size wanted */
1552 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1553 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1554 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1555 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1558 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1559 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1560 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1561 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1562 default: new_line.clock_type = CLOCK_DEFAULT;
1565 new_line.clock_rate = info->params.clock_speed;
1566 new_line.loopback = info->params.loopback ? 1:0;
1568 if (copy_to_user(line, &new_line, size))
1572 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1574 if(!capable(CAP_NET_ADMIN))
1576 if (copy_from_user(&new_line, line, size))
1579 switch (new_line.clock_type)
1581 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1582 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1583 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1584 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1585 case CLOCK_DEFAULT: flags = info->params.flags &
1586 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1587 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1588 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1589 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1590 default: return -EINVAL;
1593 if (new_line.loopback != 0 && new_line.loopback != 1)
1596 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1597 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1598 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1599 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1600 info->params.flags |= flags;
1602 info->params.loopback = new_line.loopback;
1604 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1605 info->params.clock_speed = new_line.clock_rate;
1607 info->params.clock_speed = 0;
1609 /* if network interface up, reprogram hardware */
1615 return hdlc_ioctl(dev, ifs);
1620 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1621 * @dev: pointer to network device structure
1624 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1626 struct slgt_info *info = dev_to_port(dev);
1627 unsigned long flags;
1629 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1631 dev->stats.tx_errors++;
1632 dev->stats.tx_aborted_errors++;
1634 spin_lock_irqsave(&info->lock,flags);
1636 spin_unlock_irqrestore(&info->lock,flags);
1638 netif_wake_queue(dev);
1642 * hdlcdev_tx_done - called by device driver when transmit completes
1643 * @info: pointer to device instance information
1645 * Reenable network layer transmit if stopped.
1647 static void hdlcdev_tx_done(struct slgt_info *info)
1649 if (netif_queue_stopped(info->netdev))
1650 netif_wake_queue(info->netdev);
1654 * hdlcdev_rx - called by device driver when frame received
1655 * @info: pointer to device instance information
1656 * @buf: pointer to buffer contianing frame data
1657 * @size: count of data bytes in buf
1659 * Pass frame to network layer.
1661 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1663 struct sk_buff *skb = dev_alloc_skb(size);
1664 struct net_device *dev = info->netdev;
1666 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1669 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1670 dev->stats.rx_dropped++;
1674 skb_put_data(skb, buf, size);
1676 skb->protocol = hdlc_type_trans(skb, dev);
1678 dev->stats.rx_packets++;
1679 dev->stats.rx_bytes += size;
1684 static const struct net_device_ops hdlcdev_ops = {
1685 .ndo_open = hdlcdev_open,
1686 .ndo_stop = hdlcdev_close,
1687 .ndo_start_xmit = hdlc_start_xmit,
1688 .ndo_siocwandev = hdlcdev_ioctl,
1689 .ndo_tx_timeout = hdlcdev_tx_timeout,
1693 * hdlcdev_init - called by device driver when adding device instance
1694 * @info: pointer to device instance information
1696 * Do generic HDLC initialization.
1698 * Return: 0 if success, otherwise error code
1700 static int hdlcdev_init(struct slgt_info *info)
1703 struct net_device *dev;
1706 /* allocate and initialize network and HDLC layer objects */
1708 dev = alloc_hdlcdev(info);
1710 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1714 /* for network layer reporting purposes only */
1715 dev->mem_start = info->phys_reg_addr;
1716 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1717 dev->irq = info->irq_level;
1719 /* network layer callbacks and settings */
1720 dev->netdev_ops = &hdlcdev_ops;
1721 dev->watchdog_timeo = 10 * HZ;
1722 dev->tx_queue_len = 50;
1724 /* generic HDLC layer callbacks and settings */
1725 hdlc = dev_to_hdlc(dev);
1726 hdlc->attach = hdlcdev_attach;
1727 hdlc->xmit = hdlcdev_xmit;
1729 /* register objects with HDLC layer */
1730 rc = register_hdlc_device(dev);
1732 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1742 * hdlcdev_exit - called by device driver when removing device instance
1743 * @info: pointer to device instance information
1745 * Do generic HDLC cleanup.
1747 static void hdlcdev_exit(struct slgt_info *info)
1751 unregister_hdlc_device(info->netdev);
1752 free_netdev(info->netdev);
1753 info->netdev = NULL;
1756 #endif /* ifdef CONFIG_HDLC */
1759 * get async data from rx DMA buffers
1761 static void rx_async(struct slgt_info *info)
1763 struct mgsl_icount *icount = &info->icount;
1764 unsigned int start, end;
1766 unsigned char status;
1767 struct slgt_desc *bufs = info->rbufs;
1773 start = end = info->rbuf_current;
1775 while(desc_complete(bufs[end])) {
1776 count = desc_count(bufs[end]) - info->rbuf_index;
1777 p = bufs[end].buf + info->rbuf_index;
1779 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1780 DBGDATA(info, p, count, "rx");
1782 for(i=0 ; i < count; i+=2, p+=2) {
1788 status = *(p + 1) & (BIT1 + BIT0);
1792 else if (status & BIT0)
1794 /* discard char if tty control flags say so */
1795 if (status & info->ignore_status_mask)
1799 else if (status & BIT0)
1802 tty_insert_flip_char(&info->port, ch, stat);
1807 /* receive buffer not completed */
1808 info->rbuf_index += i;
1809 mod_timer(&info->rx_timer, jiffies + 1);
1813 info->rbuf_index = 0;
1814 free_rbufs(info, end, end);
1816 if (++end == info->rbuf_count)
1819 /* if entire list searched then no frame available */
1825 tty_flip_buffer_push(&info->port);
1829 * return next bottom half action to perform
1831 static int bh_action(struct slgt_info *info)
1833 unsigned long flags;
1836 spin_lock_irqsave(&info->lock,flags);
1838 if (info->pending_bh & BH_RECEIVE) {
1839 info->pending_bh &= ~BH_RECEIVE;
1841 } else if (info->pending_bh & BH_TRANSMIT) {
1842 info->pending_bh &= ~BH_TRANSMIT;
1844 } else if (info->pending_bh & BH_STATUS) {
1845 info->pending_bh &= ~BH_STATUS;
1848 /* Mark BH routine as complete */
1849 info->bh_running = false;
1850 info->bh_requested = false;
1854 spin_unlock_irqrestore(&info->lock,flags);
1860 * perform bottom half processing
1862 static void bh_handler(struct work_struct *work)
1864 struct slgt_info *info = container_of(work, struct slgt_info, task);
1867 info->bh_running = true;
1869 while((action = bh_action(info))) {
1872 DBGBH(("%s bh receive\n", info->device_name));
1873 switch(info->params.mode) {
1874 case MGSL_MODE_ASYNC:
1877 case MGSL_MODE_HDLC:
1878 while(rx_get_frame(info));
1881 case MGSL_MODE_MONOSYNC:
1882 case MGSL_MODE_BISYNC:
1883 case MGSL_MODE_XSYNC:
1884 while(rx_get_buf(info));
1887 /* restart receiver if rx DMA buffers exhausted */
1888 if (info->rx_restart)
1895 DBGBH(("%s bh status\n", info->device_name));
1896 info->ri_chkcount = 0;
1897 info->dsr_chkcount = 0;
1898 info->dcd_chkcount = 0;
1899 info->cts_chkcount = 0;
1902 DBGBH(("%s unknown action\n", info->device_name));
1906 DBGBH(("%s bh_handler exit\n", info->device_name));
1909 static void bh_transmit(struct slgt_info *info)
1911 struct tty_struct *tty = info->port.tty;
1913 DBGBH(("%s bh_transmit\n", info->device_name));
1918 static void dsr_change(struct slgt_info *info, unsigned short status)
1920 if (status & BIT3) {
1921 info->signals |= SerialSignal_DSR;
1922 info->input_signal_events.dsr_up++;
1924 info->signals &= ~SerialSignal_DSR;
1925 info->input_signal_events.dsr_down++;
1927 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1928 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1929 slgt_irq_off(info, IRQ_DSR);
1933 wake_up_interruptible(&info->status_event_wait_q);
1934 wake_up_interruptible(&info->event_wait_q);
1935 info->pending_bh |= BH_STATUS;
1938 static void cts_change(struct slgt_info *info, unsigned short status)
1940 if (status & BIT2) {
1941 info->signals |= SerialSignal_CTS;
1942 info->input_signal_events.cts_up++;
1944 info->signals &= ~SerialSignal_CTS;
1945 info->input_signal_events.cts_down++;
1947 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1948 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1949 slgt_irq_off(info, IRQ_CTS);
1953 wake_up_interruptible(&info->status_event_wait_q);
1954 wake_up_interruptible(&info->event_wait_q);
1955 info->pending_bh |= BH_STATUS;
1957 if (tty_port_cts_enabled(&info->port)) {
1958 if (info->port.tty) {
1959 if (info->port.tty->hw_stopped) {
1960 if (info->signals & SerialSignal_CTS) {
1961 info->port.tty->hw_stopped = 0;
1962 info->pending_bh |= BH_TRANSMIT;
1966 if (!(info->signals & SerialSignal_CTS))
1967 info->port.tty->hw_stopped = 1;
1973 static void dcd_change(struct slgt_info *info, unsigned short status)
1975 if (status & BIT1) {
1976 info->signals |= SerialSignal_DCD;
1977 info->input_signal_events.dcd_up++;
1979 info->signals &= ~SerialSignal_DCD;
1980 info->input_signal_events.dcd_down++;
1982 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1983 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1984 slgt_irq_off(info, IRQ_DCD);
1988 #if SYNCLINK_GENERIC_HDLC
1989 if (info->netcount) {
1990 if (info->signals & SerialSignal_DCD)
1991 netif_carrier_on(info->netdev);
1993 netif_carrier_off(info->netdev);
1996 wake_up_interruptible(&info->status_event_wait_q);
1997 wake_up_interruptible(&info->event_wait_q);
1998 info->pending_bh |= BH_STATUS;
2000 if (tty_port_check_carrier(&info->port)) {
2001 if (info->signals & SerialSignal_DCD)
2002 wake_up_interruptible(&info->port.open_wait);
2005 tty_hangup(info->port.tty);
2010 static void ri_change(struct slgt_info *info, unsigned short status)
2012 if (status & BIT0) {
2013 info->signals |= SerialSignal_RI;
2014 info->input_signal_events.ri_up++;
2016 info->signals &= ~SerialSignal_RI;
2017 info->input_signal_events.ri_down++;
2019 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2020 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2021 slgt_irq_off(info, IRQ_RI);
2025 wake_up_interruptible(&info->status_event_wait_q);
2026 wake_up_interruptible(&info->event_wait_q);
2027 info->pending_bh |= BH_STATUS;
2030 static void isr_rxdata(struct slgt_info *info)
2032 unsigned int count = info->rbuf_fill_count;
2033 unsigned int i = info->rbuf_fill_index;
2036 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2037 reg = rd_reg16(info, RDR);
2038 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2039 if (desc_complete(info->rbufs[i])) {
2040 /* all buffers full */
2042 info->rx_restart = true;
2045 info->rbufs[i].buf[count++] = (unsigned char)reg;
2046 /* async mode saves status byte to buffer for each data byte */
2047 if (info->params.mode == MGSL_MODE_ASYNC)
2048 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2049 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2050 /* buffer full or end of frame */
2051 set_desc_count(info->rbufs[i], count);
2052 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2053 info->rbuf_fill_count = count = 0;
2054 if (++i == info->rbuf_count)
2056 info->pending_bh |= BH_RECEIVE;
2060 info->rbuf_fill_index = i;
2061 info->rbuf_fill_count = count;
2064 static void isr_serial(struct slgt_info *info)
2066 unsigned short status = rd_reg16(info, SSR);
2068 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2070 wr_reg16(info, SSR, status); /* clear pending */
2072 info->irq_occurred = true;
2074 if (info->params.mode == MGSL_MODE_ASYNC) {
2075 if (status & IRQ_TXIDLE) {
2076 if (info->tx_active)
2077 isr_txeom(info, status);
2079 if (info->rx_pio && (status & IRQ_RXDATA))
2081 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2083 /* process break detection if tty control allows */
2084 if (info->port.tty) {
2085 if (!(status & info->ignore_status_mask)) {
2086 if (info->read_status_mask & MASK_BREAK) {
2087 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2088 if (info->port.flags & ASYNC_SAK)
2089 do_SAK(info->port.tty);
2095 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2096 isr_txeom(info, status);
2097 if (info->rx_pio && (status & IRQ_RXDATA))
2099 if (status & IRQ_RXIDLE) {
2100 if (status & RXIDLE)
2101 info->icount.rxidle++;
2103 info->icount.exithunt++;
2104 wake_up_interruptible(&info->event_wait_q);
2107 if (status & IRQ_RXOVER)
2111 if (status & IRQ_DSR)
2112 dsr_change(info, status);
2113 if (status & IRQ_CTS)
2114 cts_change(info, status);
2115 if (status & IRQ_DCD)
2116 dcd_change(info, status);
2117 if (status & IRQ_RI)
2118 ri_change(info, status);
2121 static void isr_rdma(struct slgt_info *info)
2123 unsigned int status = rd_reg32(info, RDCSR);
2125 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2127 /* RDCSR (rx DMA control/status)
2130 * 06 save status byte to DMA buffer
2132 * 04 eol (end of list)
2133 * 03 eob (end of buffer)
2138 wr_reg32(info, RDCSR, status); /* clear pending */
2140 if (status & (BIT5 + BIT4)) {
2141 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2142 info->rx_restart = true;
2144 info->pending_bh |= BH_RECEIVE;
2147 static void isr_tdma(struct slgt_info *info)
2149 unsigned int status = rd_reg32(info, TDCSR);
2151 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2153 /* TDCSR (tx DMA control/status)
2157 * 04 eol (end of list)
2158 * 03 eob (end of buffer)
2163 wr_reg32(info, TDCSR, status); /* clear pending */
2165 if (status & (BIT5 + BIT4 + BIT3)) {
2166 // another transmit buffer has completed
2167 // run bottom half to get more send data from user
2168 info->pending_bh |= BH_TRANSMIT;
2173 * return true if there are unsent tx DMA buffers, otherwise false
2175 * if there are unsent buffers then info->tbuf_start
2176 * is set to index of first unsent buffer
2178 static bool unsent_tbufs(struct slgt_info *info)
2180 unsigned int i = info->tbuf_current;
2184 * search backwards from last loaded buffer (precedes tbuf_current)
2185 * for first unsent buffer (desc_count > 0)
2192 i = info->tbuf_count - 1;
2193 if (!desc_count(info->tbufs[i]))
2195 info->tbuf_start = i;
2197 } while (i != info->tbuf_current);
2202 static void isr_txeom(struct slgt_info *info, unsigned short status)
2204 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2206 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2208 if (status & IRQ_TXUNDER) {
2209 unsigned short val = rd_reg16(info, TCR);
2210 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2211 wr_reg16(info, TCR, val); /* clear reset bit */
2214 if (info->tx_active) {
2215 if (info->params.mode != MGSL_MODE_ASYNC) {
2216 if (status & IRQ_TXUNDER)
2217 info->icount.txunder++;
2218 else if (status & IRQ_TXIDLE)
2219 info->icount.txok++;
2222 if (unsent_tbufs(info)) {
2224 update_tx_timer(info);
2227 info->tx_active = false;
2229 del_timer(&info->tx_timer);
2231 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2232 info->signals &= ~SerialSignal_RTS;
2233 info->drop_rts_on_tx_done = false;
2234 set_gtsignals(info);
2237 #if SYNCLINK_GENERIC_HDLC
2239 hdlcdev_tx_done(info);
2243 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2247 info->pending_bh |= BH_TRANSMIT;
2252 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2254 struct cond_wait *w, *prev;
2256 /* wake processes waiting for specific transitions */
2257 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2258 if (w->data & changed) {
2260 wake_up_interruptible(&w->q);
2262 prev->next = w->next;
2264 info->gpio_wait_q = w->next;
2270 /* interrupt service routine
2272 * irq interrupt number
2273 * dev_id device ID supplied during interrupt registration
2275 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2277 struct slgt_info *info = dev_id;
2281 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2283 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2284 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2285 info->irq_occurred = true;
2286 for(i=0; i < info->port_count ; i++) {
2287 if (info->port_array[i] == NULL)
2289 spin_lock(&info->port_array[i]->lock);
2290 if (gsr & (BIT8 << i))
2291 isr_serial(info->port_array[i]);
2292 if (gsr & (BIT16 << (i*2)))
2293 isr_rdma(info->port_array[i]);
2294 if (gsr & (BIT17 << (i*2)))
2295 isr_tdma(info->port_array[i]);
2296 spin_unlock(&info->port_array[i]->lock);
2300 if (info->gpio_present) {
2302 unsigned int changed;
2303 spin_lock(&info->lock);
2304 while ((changed = rd_reg32(info, IOSR)) != 0) {
2305 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2306 /* read latched state of GPIO signals */
2307 state = rd_reg32(info, IOVR);
2308 /* clear pending GPIO interrupt bits */
2309 wr_reg32(info, IOSR, changed);
2310 for (i=0 ; i < info->port_count ; i++) {
2311 if (info->port_array[i] != NULL)
2312 isr_gpio(info->port_array[i], changed, state);
2315 spin_unlock(&info->lock);
2318 for(i=0; i < info->port_count ; i++) {
2319 struct slgt_info *port = info->port_array[i];
2322 spin_lock(&port->lock);
2323 if ((port->port.count || port->netcount) &&
2324 port->pending_bh && !port->bh_running &&
2325 !port->bh_requested) {
2326 DBGISR(("%s bh queued\n", port->device_name));
2327 schedule_work(&port->task);
2328 port->bh_requested = true;
2330 spin_unlock(&port->lock);
2333 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2337 static int startup(struct slgt_info *info)
2339 DBGINFO(("%s startup\n", info->device_name));
2341 if (tty_port_initialized(&info->port))
2344 if (!info->tx_buf) {
2345 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2346 if (!info->tx_buf) {
2347 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2352 info->pending_bh = 0;
2354 memset(&info->icount, 0, sizeof(info->icount));
2356 /* program hardware for current parameters */
2357 change_params(info);
2360 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2362 tty_port_set_initialized(&info->port, 1);
2368 * called by close() and hangup() to shutdown hardware
2370 static void shutdown(struct slgt_info *info)
2372 unsigned long flags;
2374 if (!tty_port_initialized(&info->port))
2377 DBGINFO(("%s shutdown\n", info->device_name));
2379 /* clear status wait queue because status changes */
2380 /* can't happen after shutting down the hardware */
2381 wake_up_interruptible(&info->status_event_wait_q);
2382 wake_up_interruptible(&info->event_wait_q);
2384 del_timer_sync(&info->tx_timer);
2385 del_timer_sync(&info->rx_timer);
2387 kfree(info->tx_buf);
2388 info->tx_buf = NULL;
2390 spin_lock_irqsave(&info->lock,flags);
2395 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2397 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2398 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2399 set_gtsignals(info);
2402 flush_cond_wait(&info->gpio_wait_q);
2404 spin_unlock_irqrestore(&info->lock,flags);
2407 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2409 tty_port_set_initialized(&info->port, 0);
2412 static void program_hw(struct slgt_info *info)
2414 unsigned long flags;
2416 spin_lock_irqsave(&info->lock,flags);
2421 if (info->params.mode != MGSL_MODE_ASYNC ||
2427 set_gtsignals(info);
2429 info->dcd_chkcount = 0;
2430 info->cts_chkcount = 0;
2431 info->ri_chkcount = 0;
2432 info->dsr_chkcount = 0;
2434 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2435 get_gtsignals(info);
2437 if (info->netcount ||
2438 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2441 spin_unlock_irqrestore(&info->lock,flags);
2445 * reconfigure adapter based on new parameters
2447 static void change_params(struct slgt_info *info)
2452 if (!info->port.tty)
2454 DBGINFO(("%s change_params\n", info->device_name));
2456 cflag = info->port.tty->termios.c_cflag;
2458 /* if B0 rate (hangup) specified then negate RTS and DTR */
2459 /* otherwise assert RTS and DTR */
2461 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2463 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2465 /* byte size and parity */
2467 info->params.data_bits = tty_get_char_size(cflag);
2468 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2471 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2473 info->params.parity = ASYNC_PARITY_NONE;
2475 /* calculate number of jiffies to transmit a full
2476 * FIFO (32 bytes) at specified data rate
2478 bits_per_char = info->params.data_bits +
2479 info->params.stop_bits + 1;
2481 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2483 if (info->params.data_rate) {
2484 info->timeout = (32*HZ*bits_per_char) /
2485 info->params.data_rate;
2487 info->timeout += HZ/50; /* Add .02 seconds of slop */
2489 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2490 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2492 /* process tty input control flags */
2494 info->read_status_mask = IRQ_RXOVER;
2495 if (I_INPCK(info->port.tty))
2496 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2497 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2498 info->read_status_mask |= MASK_BREAK;
2499 if (I_IGNPAR(info->port.tty))
2500 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2501 if (I_IGNBRK(info->port.tty)) {
2502 info->ignore_status_mask |= MASK_BREAK;
2503 /* If ignoring parity and break indicators, ignore
2504 * overruns too. (For real raw support).
2506 if (I_IGNPAR(info->port.tty))
2507 info->ignore_status_mask |= MASK_OVERRUN;
2513 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2515 DBGINFO(("%s get_stats\n", info->device_name));
2517 memset(&info->icount, 0, sizeof(info->icount));
2519 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2525 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2527 DBGINFO(("%s get_params\n", info->device_name));
2528 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2533 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2535 unsigned long flags;
2536 MGSL_PARAMS tmp_params;
2538 DBGINFO(("%s set_params\n", info->device_name));
2539 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2542 spin_lock_irqsave(&info->lock, flags);
2543 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2544 info->base_clock = tmp_params.clock_speed;
2546 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2547 spin_unlock_irqrestore(&info->lock, flags);
2554 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2556 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2557 if (put_user(info->idle_mode, idle_mode))
2562 static int set_txidle(struct slgt_info *info, int idle_mode)
2564 unsigned long flags;
2565 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2566 spin_lock_irqsave(&info->lock,flags);
2567 info->idle_mode = idle_mode;
2568 if (info->params.mode != MGSL_MODE_ASYNC)
2570 spin_unlock_irqrestore(&info->lock,flags);
2574 static int tx_enable(struct slgt_info *info, int enable)
2576 unsigned long flags;
2577 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2578 spin_lock_irqsave(&info->lock,flags);
2580 if (!info->tx_enabled)
2583 if (info->tx_enabled)
2586 spin_unlock_irqrestore(&info->lock,flags);
2591 * abort transmit HDLC frame
2593 static int tx_abort(struct slgt_info *info)
2595 unsigned long flags;
2596 DBGINFO(("%s tx_abort\n", info->device_name));
2597 spin_lock_irqsave(&info->lock,flags);
2599 spin_unlock_irqrestore(&info->lock,flags);
2603 static int rx_enable(struct slgt_info *info, int enable)
2605 unsigned long flags;
2606 unsigned int rbuf_fill_level;
2607 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2608 spin_lock_irqsave(&info->lock,flags);
2610 * enable[31..16] = receive DMA buffer fill level
2611 * 0 = noop (leave fill level unchanged)
2612 * fill level must be multiple of 4 and <= buffer size
2614 rbuf_fill_level = ((unsigned int)enable) >> 16;
2615 if (rbuf_fill_level) {
2616 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2617 spin_unlock_irqrestore(&info->lock, flags);
2620 info->rbuf_fill_level = rbuf_fill_level;
2621 if (rbuf_fill_level < 128)
2622 info->rx_pio = 1; /* PIO mode */
2624 info->rx_pio = 0; /* DMA mode */
2625 rx_stop(info); /* restart receiver to use new fill level */
2629 * enable[1..0] = receiver enable command
2632 * 2 = enable or force hunt mode if already enabled
2636 if (!info->rx_enabled)
2638 else if (enable == 2) {
2639 /* force hunt mode (write 1 to RCR[3]) */
2640 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2643 if (info->rx_enabled)
2646 spin_unlock_irqrestore(&info->lock,flags);
2651 * wait for specified event to occur
2653 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2655 unsigned long flags;
2658 struct mgsl_icount cprev, cnow;
2661 struct _input_signal_events oldsigs, newsigs;
2662 DECLARE_WAITQUEUE(wait, current);
2664 if (get_user(mask, mask_ptr))
2667 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2669 spin_lock_irqsave(&info->lock,flags);
2671 /* return immediately if state matches requested events */
2672 get_gtsignals(info);
2676 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2677 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2678 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2679 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2681 spin_unlock_irqrestore(&info->lock,flags);
2685 /* save current irq counts */
2686 cprev = info->icount;
2687 oldsigs = info->input_signal_events;
2689 /* enable hunt and idle irqs if needed */
2690 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2691 unsigned short val = rd_reg16(info, SCR);
2692 if (!(val & IRQ_RXIDLE))
2693 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2696 set_current_state(TASK_INTERRUPTIBLE);
2697 add_wait_queue(&info->event_wait_q, &wait);
2699 spin_unlock_irqrestore(&info->lock,flags);
2703 if (signal_pending(current)) {
2708 /* get current irq counts */
2709 spin_lock_irqsave(&info->lock,flags);
2710 cnow = info->icount;
2711 newsigs = info->input_signal_events;
2712 set_current_state(TASK_INTERRUPTIBLE);
2713 spin_unlock_irqrestore(&info->lock,flags);
2715 /* if no change, wait aborted for some reason */
2716 if (newsigs.dsr_up == oldsigs.dsr_up &&
2717 newsigs.dsr_down == oldsigs.dsr_down &&
2718 newsigs.dcd_up == oldsigs.dcd_up &&
2719 newsigs.dcd_down == oldsigs.dcd_down &&
2720 newsigs.cts_up == oldsigs.cts_up &&
2721 newsigs.cts_down == oldsigs.cts_down &&
2722 newsigs.ri_up == oldsigs.ri_up &&
2723 newsigs.ri_down == oldsigs.ri_down &&
2724 cnow.exithunt == cprev.exithunt &&
2725 cnow.rxidle == cprev.rxidle) {
2731 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2732 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2733 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2734 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2735 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2736 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2737 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2738 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2739 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2740 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2748 remove_wait_queue(&info->event_wait_q, &wait);
2749 set_current_state(TASK_RUNNING);
2752 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2753 spin_lock_irqsave(&info->lock,flags);
2754 if (!waitqueue_active(&info->event_wait_q)) {
2755 /* disable enable exit hunt mode/idle rcvd IRQs */
2757 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2759 spin_unlock_irqrestore(&info->lock,flags);
2763 rc = put_user(events, mask_ptr);
2767 static int get_interface(struct slgt_info *info, int __user *if_mode)
2769 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2770 if (put_user(info->if_mode, if_mode))
2775 static int set_interface(struct slgt_info *info, int if_mode)
2777 unsigned long flags;
2780 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2781 spin_lock_irqsave(&info->lock,flags);
2782 info->if_mode = if_mode;
2786 /* TCR (tx control) 07 1=RTS driver control */
2787 val = rd_reg16(info, TCR);
2788 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2792 wr_reg16(info, TCR, val);
2794 spin_unlock_irqrestore(&info->lock,flags);
2798 static int get_xsync(struct slgt_info *info, int __user *xsync)
2800 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2801 if (put_user(info->xsync, xsync))
2807 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2809 * sync pattern is contained in least significant bytes of value
2810 * most significant byte of sync pattern is oldest (1st sent/detected)
2812 static int set_xsync(struct slgt_info *info, int xsync)
2814 unsigned long flags;
2816 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2817 spin_lock_irqsave(&info->lock, flags);
2818 info->xsync = xsync;
2819 wr_reg32(info, XSR, xsync);
2820 spin_unlock_irqrestore(&info->lock, flags);
2824 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2826 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2827 if (put_user(info->xctrl, xctrl))
2833 * set extended control options
2835 * xctrl[31:19] reserved, must be zero
2836 * xctrl[18:17] extended sync pattern length in bytes
2837 * 00 = 1 byte in xsr[7:0]
2838 * 01 = 2 bytes in xsr[15:0]
2839 * 10 = 3 bytes in xsr[23:0]
2840 * 11 = 4 bytes in xsr[31:0]
2841 * xctrl[16] 1 = enable terminal count, 0=disabled
2842 * xctrl[15:0] receive terminal count for fixed length packets
2843 * value is count minus one (0 = 1 byte packet)
2844 * when terminal count is reached, receiver
2845 * automatically returns to hunt mode and receive
2846 * FIFO contents are flushed to DMA buffers with
2847 * end of frame (EOF) status
2849 static int set_xctrl(struct slgt_info *info, int xctrl)
2851 unsigned long flags;
2853 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2854 spin_lock_irqsave(&info->lock, flags);
2855 info->xctrl = xctrl;
2856 wr_reg32(info, XCR, xctrl);
2857 spin_unlock_irqrestore(&info->lock, flags);
2862 * set general purpose IO pin state and direction
2865 * state each bit indicates a pin state
2866 * smask set bit indicates pin state to set
2867 * dir each bit indicates a pin direction (0=input, 1=output)
2868 * dmask set bit indicates pin direction to set
2870 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2872 unsigned long flags;
2873 struct gpio_desc gpio;
2876 if (!info->gpio_present)
2878 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2880 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2881 info->device_name, gpio.state, gpio.smask,
2882 gpio.dir, gpio.dmask));
2884 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2886 data = rd_reg32(info, IODR);
2887 data |= gpio.dmask & gpio.dir;
2888 data &= ~(gpio.dmask & ~gpio.dir);
2889 wr_reg32(info, IODR, data);
2892 data = rd_reg32(info, IOVR);
2893 data |= gpio.smask & gpio.state;
2894 data &= ~(gpio.smask & ~gpio.state);
2895 wr_reg32(info, IOVR, data);
2897 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2903 * get general purpose IO pin state and direction
2905 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2907 struct gpio_desc gpio;
2908 if (!info->gpio_present)
2910 gpio.state = rd_reg32(info, IOVR);
2911 gpio.smask = 0xffffffff;
2912 gpio.dir = rd_reg32(info, IODR);
2913 gpio.dmask = 0xffffffff;
2914 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2916 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2917 info->device_name, gpio.state, gpio.dir));
2922 * conditional wait facility
2924 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2926 init_waitqueue_head(&w->q);
2927 init_waitqueue_entry(&w->wait, current);
2931 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2933 set_current_state(TASK_INTERRUPTIBLE);
2934 add_wait_queue(&w->q, &w->wait);
2939 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2941 struct cond_wait *w, *prev;
2942 remove_wait_queue(&cw->q, &cw->wait);
2943 set_current_state(TASK_RUNNING);
2944 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2947 prev->next = w->next;
2955 static void flush_cond_wait(struct cond_wait **head)
2957 while (*head != NULL) {
2958 wake_up_interruptible(&(*head)->q);
2959 *head = (*head)->next;
2964 * wait for general purpose I/O pin(s) to enter specified state
2967 * state - bit indicates target pin state
2968 * smask - set bit indicates watched pin
2970 * The wait ends when at least one watched pin enters the specified
2971 * state. When 0 (no error) is returned, user_gpio->state is set to the
2972 * state of all GPIO pins when the wait ends.
2974 * Note: Each pin may be a dedicated input, dedicated output, or
2975 * configurable input/output. The number and configuration of pins
2976 * varies with the specific adapter model. Only input pins (dedicated
2977 * or configured) can be monitored with this function.
2979 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2981 unsigned long flags;
2983 struct gpio_desc gpio;
2984 struct cond_wait wait;
2987 if (!info->gpio_present)
2989 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2991 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2992 info->device_name, gpio.state, gpio.smask));
2993 /* ignore output pins identified by set IODR bit */
2994 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2996 init_cond_wait(&wait, gpio.smask);
2998 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2999 /* enable interrupts for watched pins */
3000 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3001 /* get current pin states */
3002 state = rd_reg32(info, IOVR);
3004 if (gpio.smask & ~(state ^ gpio.state)) {
3005 /* already in target state */
3008 /* wait for target state */
3009 add_cond_wait(&info->gpio_wait_q, &wait);
3010 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3012 if (signal_pending(current))
3015 gpio.state = wait.data;
3016 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3017 remove_cond_wait(&info->gpio_wait_q, &wait);
3020 /* disable all GPIO interrupts if no waiting processes */
3021 if (info->gpio_wait_q == NULL)
3022 wr_reg32(info, IOER, 0);
3023 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3025 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3030 static int modem_input_wait(struct slgt_info *info,int arg)
3032 unsigned long flags;
3034 struct mgsl_icount cprev, cnow;
3035 DECLARE_WAITQUEUE(wait, current);
3037 /* save current irq counts */
3038 spin_lock_irqsave(&info->lock,flags);
3039 cprev = info->icount;
3040 add_wait_queue(&info->status_event_wait_q, &wait);
3041 set_current_state(TASK_INTERRUPTIBLE);
3042 spin_unlock_irqrestore(&info->lock,flags);
3046 if (signal_pending(current)) {
3051 /* get new irq counts */
3052 spin_lock_irqsave(&info->lock,flags);
3053 cnow = info->icount;
3054 set_current_state(TASK_INTERRUPTIBLE);
3055 spin_unlock_irqrestore(&info->lock,flags);
3057 /* if no change, wait aborted for some reason */
3058 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3059 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3064 /* check for change in caller specified modem input */
3065 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3066 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3067 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3068 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3075 remove_wait_queue(&info->status_event_wait_q, &wait);
3076 set_current_state(TASK_RUNNING);
3081 * return state of serial control and status signals
3083 static int tiocmget(struct tty_struct *tty)
3085 struct slgt_info *info = tty->driver_data;
3086 unsigned int result;
3087 unsigned long flags;
3089 spin_lock_irqsave(&info->lock,flags);
3090 get_gtsignals(info);
3091 spin_unlock_irqrestore(&info->lock,flags);
3093 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3094 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3095 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3096 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3097 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3098 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3100 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3105 * set modem control signals (DTR/RTS)
3107 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3108 * TIOCMSET = set/clear signal values
3109 * value bit mask for command
3111 static int tiocmset(struct tty_struct *tty,
3112 unsigned int set, unsigned int clear)
3114 struct slgt_info *info = tty->driver_data;
3115 unsigned long flags;
3117 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3119 if (set & TIOCM_RTS)
3120 info->signals |= SerialSignal_RTS;
3121 if (set & TIOCM_DTR)
3122 info->signals |= SerialSignal_DTR;
3123 if (clear & TIOCM_RTS)
3124 info->signals &= ~SerialSignal_RTS;
3125 if (clear & TIOCM_DTR)
3126 info->signals &= ~SerialSignal_DTR;
3128 spin_lock_irqsave(&info->lock,flags);
3129 set_gtsignals(info);
3130 spin_unlock_irqrestore(&info->lock,flags);
3134 static int carrier_raised(struct tty_port *port)
3136 unsigned long flags;
3137 struct slgt_info *info = container_of(port, struct slgt_info, port);
3139 spin_lock_irqsave(&info->lock,flags);
3140 get_gtsignals(info);
3141 spin_unlock_irqrestore(&info->lock,flags);
3142 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3145 static void dtr_rts(struct tty_port *port, int on)
3147 unsigned long flags;
3148 struct slgt_info *info = container_of(port, struct slgt_info, port);
3150 spin_lock_irqsave(&info->lock,flags);
3152 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3154 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3155 set_gtsignals(info);
3156 spin_unlock_irqrestore(&info->lock,flags);
3161 * block current process until the device is ready to open
3163 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3164 struct slgt_info *info)
3166 DECLARE_WAITQUEUE(wait, current);
3168 bool do_clocal = false;
3169 unsigned long flags;
3171 struct tty_port *port = &info->port;
3173 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3175 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3176 /* nonblock mode is set or port is not enabled */
3177 tty_port_set_active(port, 1);
3184 /* Wait for carrier detect and the line to become
3185 * free (i.e., not in use by the callout). While we are in
3186 * this loop, port->count is dropped by one, so that
3187 * close() knows when to free things. We restore it upon
3188 * exit, either normal or abnormal.
3192 add_wait_queue(&port->open_wait, &wait);
3194 spin_lock_irqsave(&info->lock, flags);
3196 spin_unlock_irqrestore(&info->lock, flags);
3197 port->blocked_open++;
3200 if (C_BAUD(tty) && tty_port_initialized(port))
3201 tty_port_raise_dtr_rts(port);
3203 set_current_state(TASK_INTERRUPTIBLE);
3205 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3206 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3207 -EAGAIN : -ERESTARTSYS;
3211 cd = tty_port_carrier_raised(port);
3212 if (do_clocal || cd)
3215 if (signal_pending(current)) {
3216 retval = -ERESTARTSYS;
3220 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3226 set_current_state(TASK_RUNNING);
3227 remove_wait_queue(&port->open_wait, &wait);
3229 if (!tty_hung_up_p(filp))
3231 port->blocked_open--;
3234 tty_port_set_active(port, 1);
3236 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3241 * allocate buffers used for calling line discipline receive_buf
3242 * directly in synchronous mode
3243 * note: add 5 bytes to max frame size to allow appending
3244 * 32-bit CRC and status byte when configured to do so
3246 static int alloc_tmp_rbuf(struct slgt_info *info)
3248 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3249 if (info->tmp_rbuf == NULL)
3251 /* unused flag buffer to satisfy receive_buf calling interface */
3252 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3253 if (!info->flag_buf) {
3254 kfree(info->tmp_rbuf);
3255 info->tmp_rbuf = NULL;
3261 static void free_tmp_rbuf(struct slgt_info *info)
3263 kfree(info->tmp_rbuf);
3264 info->tmp_rbuf = NULL;
3265 kfree(info->flag_buf);
3266 info->flag_buf = NULL;
3270 * allocate DMA descriptor lists.
3272 static int alloc_desc(struct slgt_info *info)
3277 /* allocate memory to hold descriptor lists */
3278 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3279 &info->bufs_dma_addr, GFP_KERNEL);
3280 if (info->bufs == NULL)
3283 info->rbufs = (struct slgt_desc*)info->bufs;
3284 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3286 pbufs = (unsigned int)info->bufs_dma_addr;
3289 * Build circular lists of descriptors
3292 for (i=0; i < info->rbuf_count; i++) {
3293 /* physical address of this descriptor */
3294 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3296 /* physical address of next descriptor */
3297 if (i == info->rbuf_count - 1)
3298 info->rbufs[i].next = cpu_to_le32(pbufs);
3300 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3301 set_desc_count(info->rbufs[i], DMABUFSIZE);
3304 for (i=0; i < info->tbuf_count; i++) {
3305 /* physical address of this descriptor */
3306 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3308 /* physical address of next descriptor */
3309 if (i == info->tbuf_count - 1)
3310 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3312 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3318 static void free_desc(struct slgt_info *info)
3320 if (info->bufs != NULL) {
3321 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3322 info->bufs, info->bufs_dma_addr);
3329 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3332 for (i=0; i < count; i++) {
3333 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3334 &bufs[i].buf_dma_addr, GFP_KERNEL);
3337 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3342 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3345 for (i=0; i < count; i++) {
3346 if (bufs[i].buf == NULL)
3348 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3349 bufs[i].buf_dma_addr);
3354 static int alloc_dma_bufs(struct slgt_info *info)
3356 info->rbuf_count = 32;
3357 info->tbuf_count = 32;
3359 if (alloc_desc(info) < 0 ||
3360 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3361 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3362 alloc_tmp_rbuf(info) < 0) {
3363 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3370 static void free_dma_bufs(struct slgt_info *info)
3373 free_bufs(info, info->rbufs, info->rbuf_count);
3374 free_bufs(info, info->tbufs, info->tbuf_count);
3377 free_tmp_rbuf(info);
3380 static int claim_resources(struct slgt_info *info)
3382 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3383 DBGERR(("%s reg addr conflict, addr=%08X\n",
3384 info->device_name, info->phys_reg_addr));
3385 info->init_error = DiagStatus_AddressConflict;
3389 info->reg_addr_requested = true;
3391 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3392 if (!info->reg_addr) {
3393 DBGERR(("%s can't map device registers, addr=%08X\n",
3394 info->device_name, info->phys_reg_addr));
3395 info->init_error = DiagStatus_CantAssignPciResources;
3401 release_resources(info);
3405 static void release_resources(struct slgt_info *info)
3407 if (info->irq_requested) {
3408 free_irq(info->irq_level, info);
3409 info->irq_requested = false;
3412 if (info->reg_addr_requested) {
3413 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3414 info->reg_addr_requested = false;
3417 if (info->reg_addr) {
3418 iounmap(info->reg_addr);
3419 info->reg_addr = NULL;
3423 /* Add the specified device instance data structure to the
3424 * global linked list of devices and increment the device count.
3426 static void add_device(struct slgt_info *info)
3430 info->next_device = NULL;
3431 info->line = slgt_device_count;
3432 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3434 if (info->line < MAX_DEVICES) {
3435 if (maxframe[info->line])
3436 info->max_frame_size = maxframe[info->line];
3439 slgt_device_count++;
3441 if (!slgt_device_list)
3442 slgt_device_list = info;
3444 struct slgt_info *current_dev = slgt_device_list;
3445 while(current_dev->next_device)
3446 current_dev = current_dev->next_device;
3447 current_dev->next_device = info;
3450 if (info->max_frame_size < 4096)
3451 info->max_frame_size = 4096;
3452 else if (info->max_frame_size > 65535)
3453 info->max_frame_size = 65535;
3455 switch(info->pdev->device) {
3456 case SYNCLINK_GT_DEVICE_ID:
3459 case SYNCLINK_GT2_DEVICE_ID:
3462 case SYNCLINK_GT4_DEVICE_ID:
3465 case SYNCLINK_AC_DEVICE_ID:
3467 info->params.mode = MGSL_MODE_ASYNC;
3470 devstr = "(unknown model)";
3472 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3473 devstr, info->device_name, info->phys_reg_addr,
3474 info->irq_level, info->max_frame_size);
3476 #if SYNCLINK_GENERIC_HDLC
3481 static const struct tty_port_operations slgt_port_ops = {
3482 .carrier_raised = carrier_raised,
3487 * allocate device instance structure, return NULL on failure
3489 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3491 struct slgt_info *info;
3493 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3496 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3497 driver_name, adapter_num, port_num));
3499 tty_port_init(&info->port);
3500 info->port.ops = &slgt_port_ops;
3501 info->magic = MGSL_MAGIC;
3502 INIT_WORK(&info->task, bh_handler);
3503 info->max_frame_size = 4096;
3504 info->base_clock = 14745600;
3505 info->rbuf_fill_level = DMABUFSIZE;
3506 init_waitqueue_head(&info->status_event_wait_q);
3507 init_waitqueue_head(&info->event_wait_q);
3508 spin_lock_init(&info->netlock);
3509 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3510 info->idle_mode = HDLC_TXIDLE_FLAGS;
3511 info->adapter_num = adapter_num;
3512 info->port_num = port_num;
3514 timer_setup(&info->tx_timer, tx_timeout, 0);
3515 timer_setup(&info->rx_timer, rx_timeout, 0);
3517 /* Copy configuration info to device instance data */
3519 info->irq_level = pdev->irq;
3520 info->phys_reg_addr = pci_resource_start(pdev,0);
3522 info->bus_type = MGSL_BUS_TYPE_PCI;
3523 info->irq_flags = IRQF_SHARED;
3525 info->init_error = -1; /* assume error, set to 0 on successful init */
3531 static void device_init(int adapter_num, struct pci_dev *pdev)
3533 struct slgt_info *port_array[SLGT_MAX_PORTS];
3537 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3539 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3542 /* allocate device instances for all ports */
3543 for (i=0; i < port_count; ++i) {
3544 port_array[i] = alloc_dev(adapter_num, i, pdev);
3545 if (port_array[i] == NULL) {
3546 for (--i; i >= 0; --i) {
3547 tty_port_destroy(&port_array[i]->port);
3548 kfree(port_array[i]);
3554 /* give copy of port_array to all ports and add to device list */
3555 for (i=0; i < port_count; ++i) {
3556 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3557 add_device(port_array[i]);
3558 port_array[i]->port_count = port_count;
3559 spin_lock_init(&port_array[i]->lock);
3562 /* Allocate and claim adapter resources */
3563 if (!claim_resources(port_array[0])) {
3565 alloc_dma_bufs(port_array[0]);
3567 /* copy resource information from first port to others */
3568 for (i = 1; i < port_count; ++i) {
3569 port_array[i]->irq_level = port_array[0]->irq_level;
3570 port_array[i]->reg_addr = port_array[0]->reg_addr;
3571 alloc_dma_bufs(port_array[i]);
3574 if (request_irq(port_array[0]->irq_level,
3576 port_array[0]->irq_flags,
3577 port_array[0]->device_name,
3578 port_array[0]) < 0) {
3579 DBGERR(("%s request_irq failed IRQ=%d\n",
3580 port_array[0]->device_name,
3581 port_array[0]->irq_level));
3583 port_array[0]->irq_requested = true;
3584 adapter_test(port_array[0]);
3585 for (i=1 ; i < port_count ; i++) {
3586 port_array[i]->init_error = port_array[0]->init_error;
3587 port_array[i]->gpio_present = port_array[0]->gpio_present;
3592 for (i = 0; i < port_count; ++i) {
3593 struct slgt_info *info = port_array[i];
3594 tty_port_register_device(&info->port, serial_driver, info->line,
3599 static int init_one(struct pci_dev *dev,
3600 const struct pci_device_id *ent)
3602 if (pci_enable_device(dev)) {
3603 printk("error enabling pci device %p\n", dev);
3606 pci_set_master(dev);
3607 device_init(slgt_device_count, dev);
3611 static void remove_one(struct pci_dev *dev)
3615 static const struct tty_operations ops = {
3619 .put_char = put_char,
3620 .flush_chars = flush_chars,
3621 .write_room = write_room,
3622 .chars_in_buffer = chars_in_buffer,
3623 .flush_buffer = flush_buffer,
3625 .compat_ioctl = slgt_compat_ioctl,
3626 .throttle = throttle,
3627 .unthrottle = unthrottle,
3628 .send_xchar = send_xchar,
3629 .break_ctl = set_break,
3630 .wait_until_sent = wait_until_sent,
3631 .set_termios = set_termios,
3633 .start = tx_release,
3635 .tiocmget = tiocmget,
3636 .tiocmset = tiocmset,
3637 .get_icount = get_icount,
3638 .proc_show = synclink_gt_proc_show,
3641 static void slgt_cleanup(void)
3643 struct slgt_info *info;
3644 struct slgt_info *tmp;
3646 printk(KERN_INFO "unload %s\n", driver_name);
3648 if (serial_driver) {
3649 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3650 tty_unregister_device(serial_driver, info->line);
3651 tty_unregister_driver(serial_driver);
3652 tty_driver_kref_put(serial_driver);
3656 info = slgt_device_list;
3659 info = info->next_device;
3662 /* release devices */
3663 info = slgt_device_list;
3665 #if SYNCLINK_GENERIC_HDLC
3668 free_dma_bufs(info);
3669 free_tmp_rbuf(info);
3670 if (info->port_num == 0)
3671 release_resources(info);
3673 info = info->next_device;
3674 tty_port_destroy(&tmp->port);
3679 pci_unregister_driver(&pci_driver);
3683 * Driver initialization entry point.
3685 static int __init slgt_init(void)
3689 printk(KERN_INFO "%s\n", driver_name);
3691 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
3692 TTY_DRIVER_DYNAMIC_DEV);
3693 if (IS_ERR(serial_driver)) {
3694 printk("%s can't allocate tty driver\n", driver_name);
3695 return PTR_ERR(serial_driver);
3698 /* Initialize the tty_driver structure */
3700 serial_driver->driver_name = slgt_driver_name;
3701 serial_driver->name = tty_dev_prefix;
3702 serial_driver->major = ttymajor;
3703 serial_driver->minor_start = 64;
3704 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3705 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3706 serial_driver->init_termios = tty_std_termios;
3707 serial_driver->init_termios.c_cflag =
3708 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3709 serial_driver->init_termios.c_ispeed = 9600;
3710 serial_driver->init_termios.c_ospeed = 9600;
3711 tty_set_operations(serial_driver, &ops);
3712 if ((rc = tty_register_driver(serial_driver)) < 0) {
3713 DBGERR(("%s can't register serial driver\n", driver_name));
3714 tty_driver_kref_put(serial_driver);
3715 serial_driver = NULL;
3719 printk(KERN_INFO "%s, tty major#%d\n",
3720 driver_name, serial_driver->major);
3722 slgt_device_count = 0;
3723 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3724 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3727 pci_registered = true;
3729 if (!slgt_device_list)
3730 printk("%s no devices found\n",driver_name);
3739 static void __exit slgt_exit(void)
3744 module_init(slgt_init);
3745 module_exit(slgt_exit);
3748 * register access routines
3751 #define CALC_REGADDR() \
3752 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3754 reg_addr += (info->port_num) * 32; \
3755 else if (addr >= 0x40) \
3756 reg_addr += (info->port_num) * 16;
3758 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3761 return readb((void __iomem *)reg_addr);
3764 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3767 writeb(value, (void __iomem *)reg_addr);
3770 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3773 return readw((void __iomem *)reg_addr);
3776 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3779 writew(value, (void __iomem *)reg_addr);
3782 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3785 return readl((void __iomem *)reg_addr);
3788 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3791 writel(value, (void __iomem *)reg_addr);
3794 static void rdma_reset(struct slgt_info *info)
3799 wr_reg32(info, RDCSR, BIT1);
3801 /* wait for enable bit cleared */
3802 for(i=0 ; i < 1000 ; i++)
3803 if (!(rd_reg32(info, RDCSR) & BIT0))
3807 static void tdma_reset(struct slgt_info *info)
3812 wr_reg32(info, TDCSR, BIT1);
3814 /* wait for enable bit cleared */
3815 for(i=0 ; i < 1000 ; i++)
3816 if (!(rd_reg32(info, TDCSR) & BIT0))
3821 * enable internal loopback
3822 * TxCLK and RxCLK are generated from BRG
3823 * and TxD is looped back to RxD internally.
3825 static void enable_loopback(struct slgt_info *info)
3827 /* SCR (serial control) BIT2=loopback enable */
3828 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3830 if (info->params.mode != MGSL_MODE_ASYNC) {
3831 /* CCR (clock control)
3832 * 07..05 tx clock source (010 = BRG)
3833 * 04..02 rx clock source (010 = BRG)
3834 * 01 auxclk enable (0 = disable)
3835 * 00 BRG enable (1 = enable)
3839 wr_reg8(info, CCR, 0x49);
3841 /* set speed if available, otherwise use default */
3842 if (info->params.clock_speed)
3843 set_rate(info, info->params.clock_speed);
3845 set_rate(info, 3686400);
3850 * set baud rate generator to specified rate
3852 static void set_rate(struct slgt_info *info, u32 rate)
3855 unsigned int osc = info->base_clock;
3857 /* div = osc/rate - 1
3859 * Round div up if osc/rate is not integer to
3860 * force to next slowest rate.
3865 if (!(osc % rate) && div)
3867 wr_reg16(info, BDR, (unsigned short)div);
3871 static void rx_stop(struct slgt_info *info)
3875 /* disable and reset receiver */
3876 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3877 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3878 wr_reg16(info, RCR, val); /* clear reset bit */
3880 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3882 /* clear pending rx interrupts */
3883 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3887 info->rx_enabled = false;
3888 info->rx_restart = false;
3891 static void rx_start(struct slgt_info *info)
3895 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3897 /* clear pending rx overrun IRQ */
3898 wr_reg16(info, SSR, IRQ_RXOVER);
3900 /* reset and disable receiver */
3901 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3902 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3903 wr_reg16(info, RCR, val); /* clear reset bit */
3909 /* rx request when rx FIFO not empty */
3910 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3911 slgt_irq_on(info, IRQ_RXDATA);
3912 if (info->params.mode == MGSL_MODE_ASYNC) {
3913 /* enable saving of rx status */
3914 wr_reg32(info, RDCSR, BIT6);
3917 /* rx request when rx FIFO half full */
3918 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3919 /* set 1st descriptor address */
3920 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3922 if (info->params.mode != MGSL_MODE_ASYNC) {
3923 /* enable rx DMA and DMA interrupt */
3924 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3926 /* enable saving of rx status, rx DMA and DMA interrupt */
3927 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3931 slgt_irq_on(info, IRQ_RXOVER);
3933 /* enable receiver */
3934 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3936 info->rx_restart = false;
3937 info->rx_enabled = true;
3940 static void tx_start(struct slgt_info *info)
3942 if (!info->tx_enabled) {
3944 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3945 info->tx_enabled = true;
3948 if (desc_count(info->tbufs[info->tbuf_start])) {
3949 info->drop_rts_on_tx_done = false;
3951 if (info->params.mode != MGSL_MODE_ASYNC) {
3952 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3953 get_gtsignals(info);
3954 if (!(info->signals & SerialSignal_RTS)) {
3955 info->signals |= SerialSignal_RTS;
3956 set_gtsignals(info);
3957 info->drop_rts_on_tx_done = true;
3961 slgt_irq_off(info, IRQ_TXDATA);
3962 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3963 /* clear tx idle and underrun status bits */
3964 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3966 slgt_irq_off(info, IRQ_TXDATA);
3967 slgt_irq_on(info, IRQ_TXIDLE);
3968 /* clear tx idle status bit */
3969 wr_reg16(info, SSR, IRQ_TXIDLE);
3971 /* set 1st descriptor address and start DMA */
3972 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3973 wr_reg32(info, TDCSR, BIT2 + BIT0);
3974 info->tx_active = true;
3978 static void tx_stop(struct slgt_info *info)
3982 del_timer(&info->tx_timer);
3986 /* reset and disable transmitter */
3987 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3988 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3990 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3992 /* clear tx idle and underrun status bit */
3993 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3997 info->tx_enabled = false;
3998 info->tx_active = false;
4001 static void reset_port(struct slgt_info *info)
4003 if (!info->reg_addr)
4009 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4010 set_gtsignals(info);
4012 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4015 static void reset_adapter(struct slgt_info *info)
4018 for (i=0; i < info->port_count; ++i) {
4019 if (info->port_array[i])
4020 reset_port(info->port_array[i]);
4024 static void async_mode(struct slgt_info *info)
4028 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4034 * 15..13 mode, 010=async
4035 * 12..10 encoding, 000=NRZ
4037 * 08 1=odd parity, 0=even parity
4038 * 07 1=RTS driver control
4040 * 05..04 character length
4045 * 03 0=1 stop bit, 1=2 stop bits
4048 * 00 auto-CTS enable
4052 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4055 if (info->params.parity != ASYNC_PARITY_NONE) {
4057 if (info->params.parity == ASYNC_PARITY_ODD)
4061 switch (info->params.data_bits)
4063 case 6: val |= BIT4; break;
4064 case 7: val |= BIT5; break;
4065 case 8: val |= BIT5 + BIT4; break;
4068 if (info->params.stop_bits != 1)
4071 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4074 wr_reg16(info, TCR, val);
4078 * 15..13 mode, 010=async
4079 * 12..10 encoding, 000=NRZ
4081 * 08 1=odd parity, 0=even parity
4082 * 07..06 reserved, must be 0
4083 * 05..04 character length
4088 * 03 reserved, must be zero
4091 * 00 auto-DCD enable
4095 if (info->params.parity != ASYNC_PARITY_NONE) {
4097 if (info->params.parity == ASYNC_PARITY_ODD)
4101 switch (info->params.data_bits)
4103 case 6: val |= BIT4; break;
4104 case 7: val |= BIT5; break;
4105 case 8: val |= BIT5 + BIT4; break;
4108 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4111 wr_reg16(info, RCR, val);
4113 /* CCR (clock control)
4115 * 07..05 011 = tx clock source is BRG/16
4116 * 04..02 010 = rx clock source is BRG
4117 * 01 0 = auxclk disabled
4118 * 00 1 = BRG enabled
4122 wr_reg8(info, CCR, 0x69);
4126 /* SCR (serial control)
4128 * 15 1=tx req on FIFO half empty
4129 * 14 1=rx req on FIFO half full
4130 * 13 tx data IRQ enable
4131 * 12 tx idle IRQ enable
4132 * 11 rx break on IRQ enable
4133 * 10 rx data IRQ enable
4134 * 09 rx break off IRQ enable
4135 * 08 overrun IRQ enable
4140 * 03 0=16x sampling, 1=8x sampling
4141 * 02 1=txd->rxd internal loopback enable
4142 * 01 reserved, must be zero
4143 * 00 1=master IRQ enable
4145 val = BIT15 + BIT14 + BIT0;
4146 /* JCR[8] : 1 = x8 async mode feature available */
4147 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4148 ((info->base_clock < (info->params.data_rate * 16)) ||
4149 (info->base_clock % (info->params.data_rate * 16)))) {
4150 /* use 8x sampling */
4152 set_rate(info, info->params.data_rate * 8);
4154 /* use 16x sampling */
4155 set_rate(info, info->params.data_rate * 16);
4157 wr_reg16(info, SCR, val);
4159 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4161 if (info->params.loopback)
4162 enable_loopback(info);
4165 static void sync_mode(struct slgt_info *info)
4169 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4177 * 001=raw bit synchronous
4178 * 010=asynchronous/isochronous
4179 * 011=monosync byte synchronous
4180 * 100=bisync byte synchronous
4181 * 101=xsync byte synchronous
4185 * 07 1=RTS driver control
4186 * 06 preamble enable
4187 * 05..04 preamble length
4188 * 03 share open/close flag
4191 * 00 auto-CTS enable
4195 switch(info->params.mode) {
4196 case MGSL_MODE_XSYNC:
4197 val |= BIT15 + BIT13;
4199 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4200 case MGSL_MODE_BISYNC: val |= BIT15; break;
4201 case MGSL_MODE_RAW: val |= BIT13; break;
4203 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4206 switch(info->params.encoding)
4208 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4209 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4210 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4211 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4212 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4213 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4214 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4217 switch (info->params.crc_type & HDLC_CRC_MASK)
4219 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4220 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4223 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4226 switch (info->params.preamble_length)
4228 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4229 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4230 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4233 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4236 wr_reg16(info, TCR, val);
4238 /* TPR (transmit preamble) */
4240 switch (info->params.preamble)
4242 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4243 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4244 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4245 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4246 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4247 default: val = 0x7e; break;
4249 wr_reg8(info, TPR, (unsigned char)val);
4255 * 001=raw bit synchronous
4256 * 010=asynchronous/isochronous
4257 * 011=monosync byte synchronous
4258 * 100=bisync byte synchronous
4259 * 101=xsync byte synchronous
4263 * 07..03 reserved, must be 0
4266 * 00 auto-DCD enable
4270 switch(info->params.mode) {
4271 case MGSL_MODE_XSYNC:
4272 val |= BIT15 + BIT13;
4274 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4275 case MGSL_MODE_BISYNC: val |= BIT15; break;
4276 case MGSL_MODE_RAW: val |= BIT13; break;
4279 switch(info->params.encoding)
4281 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4282 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4283 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4284 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4285 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4286 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4287 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4290 switch (info->params.crc_type & HDLC_CRC_MASK)
4292 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4293 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4296 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4299 wr_reg16(info, RCR, val);
4301 /* CCR (clock control)
4303 * 07..05 tx clock source
4304 * 04..02 rx clock source
4310 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4312 // when RxC source is DPLL, BRG generates 16X DPLL
4313 // reference clock, so take TxC from BRG/16 to get
4314 // transmit clock at actual data rate
4315 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4316 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4318 val |= BIT6; /* 010, txclk = BRG */
4320 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4321 val |= BIT7; /* 100, txclk = DPLL Input */
4322 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4323 val |= BIT5; /* 001, txclk = RXC Input */
4325 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4326 val |= BIT3; /* 010, rxclk = BRG */
4327 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4328 val |= BIT4; /* 100, rxclk = DPLL */
4329 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4330 val |= BIT2; /* 001, rxclk = TXC Input */
4332 if (info->params.clock_speed)
4335 wr_reg8(info, CCR, (unsigned char)val);
4337 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4339 // program DPLL mode
4340 switch(info->params.encoding)
4342 case HDLC_ENCODING_BIPHASE_MARK:
4343 case HDLC_ENCODING_BIPHASE_SPACE:
4345 case HDLC_ENCODING_BIPHASE_LEVEL:
4346 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4347 val = BIT7 + BIT6; break;
4348 default: val = BIT6; // NRZ encodings
4350 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4352 // DPLL requires a 16X reference clock from BRG
4353 set_rate(info, info->params.clock_speed * 16);
4356 set_rate(info, info->params.clock_speed);
4362 /* SCR (serial control)
4364 * 15 1=tx req on FIFO half empty
4365 * 14 1=rx req on FIFO half full
4366 * 13 tx data IRQ enable
4367 * 12 tx idle IRQ enable
4368 * 11 underrun IRQ enable
4369 * 10 rx data IRQ enable
4370 * 09 rx idle IRQ enable
4371 * 08 overrun IRQ enable
4376 * 03 reserved, must be zero
4377 * 02 1=txd->rxd internal loopback enable
4378 * 01 reserved, must be zero
4379 * 00 1=master IRQ enable
4381 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4383 if (info->params.loopback)
4384 enable_loopback(info);
4388 * set transmit idle mode
4390 static void tx_set_idle(struct slgt_info *info)
4395 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4396 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4398 tcr = rd_reg16(info, TCR);
4399 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4400 /* disable preamble, set idle size to 16 bits */
4401 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4402 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4403 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4404 } else if (!(tcr & BIT6)) {
4405 /* preamble is disabled, set idle size to 8 bits */
4406 tcr &= ~(BIT5 + BIT4);
4408 wr_reg16(info, TCR, tcr);
4410 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4411 /* LSB of custom tx idle specified in tx idle register */
4412 val = (unsigned char)(info->idle_mode & 0xff);
4414 /* standard 8 bit idle patterns */
4415 switch(info->idle_mode)
4417 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4418 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4419 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4420 case HDLC_TXIDLE_ZEROS:
4421 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4422 default: val = 0xff;
4426 wr_reg8(info, TIR, val);
4430 * get state of V24 status (input) signals
4432 static void get_gtsignals(struct slgt_info *info)
4434 unsigned short status = rd_reg16(info, SSR);
4436 /* clear all serial signals except RTS and DTR */
4437 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4440 info->signals |= SerialSignal_DSR;
4442 info->signals |= SerialSignal_CTS;
4444 info->signals |= SerialSignal_DCD;
4446 info->signals |= SerialSignal_RI;
4450 * set V.24 Control Register based on current configuration
4452 static void msc_set_vcr(struct slgt_info *info)
4454 unsigned char val = 0;
4456 /* VCR (V.24 control)
4458 * 07..04 serial IF select
4465 switch(info->if_mode & MGSL_INTERFACE_MASK)
4467 case MGSL_INTERFACE_RS232:
4468 val |= BIT5; /* 0010 */
4470 case MGSL_INTERFACE_V35:
4471 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4473 case MGSL_INTERFACE_RS422:
4474 val |= BIT6; /* 0100 */
4478 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4480 if (info->signals & SerialSignal_DTR)
4482 if (info->signals & SerialSignal_RTS)
4484 if (info->if_mode & MGSL_INTERFACE_LL)
4486 if (info->if_mode & MGSL_INTERFACE_RL)
4488 wr_reg8(info, VCR, val);
4492 * set state of V24 control (output) signals
4494 static void set_gtsignals(struct slgt_info *info)
4496 unsigned char val = rd_reg8(info, VCR);
4497 if (info->signals & SerialSignal_DTR)
4501 if (info->signals & SerialSignal_RTS)
4505 wr_reg8(info, VCR, val);
4509 * free range of receive DMA buffers (i to last)
4511 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4516 /* reset current buffer for reuse */
4517 info->rbufs[i].status = 0;
4518 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4521 if (++i == info->rbuf_count)
4524 info->rbuf_current = i;
4528 * mark all receive DMA buffers as free
4530 static void reset_rbufs(struct slgt_info *info)
4532 free_rbufs(info, 0, info->rbuf_count - 1);
4533 info->rbuf_fill_index = 0;
4534 info->rbuf_fill_count = 0;
4538 * pass receive HDLC frame to upper layer
4540 * return true if frame available, otherwise false
4542 static bool rx_get_frame(struct slgt_info *info)
4544 unsigned int start, end;
4545 unsigned short status;
4546 unsigned int framesize = 0;
4547 unsigned long flags;
4548 struct tty_struct *tty = info->port.tty;
4549 unsigned char addr_field = 0xff;
4550 unsigned int crc_size = 0;
4552 switch (info->params.crc_type & HDLC_CRC_MASK) {
4553 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4554 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4561 start = end = info->rbuf_current;
4564 if (!desc_complete(info->rbufs[end]))
4567 if (framesize == 0 && info->params.addr_filter != 0xff)
4568 addr_field = info->rbufs[end].buf[0];
4570 framesize += desc_count(info->rbufs[end]);
4572 if (desc_eof(info->rbufs[end]))
4575 if (++end == info->rbuf_count)
4578 if (end == info->rbuf_current) {
4579 if (info->rx_enabled){
4580 spin_lock_irqsave(&info->lock,flags);
4582 spin_unlock_irqrestore(&info->lock,flags);
4590 * 15 buffer complete
4593 * 02 eof (end of frame)
4597 status = desc_status(info->rbufs[end]);
4599 /* ignore CRC bit if not using CRC (bit is undefined) */
4600 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4603 if (framesize == 0 ||
4604 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4605 free_rbufs(info, start, end);
4609 if (framesize < (2 + crc_size) || status & BIT0) {
4610 info->icount.rxshort++;
4612 } else if (status & BIT1) {
4613 info->icount.rxcrc++;
4614 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4618 #if SYNCLINK_GENERIC_HDLC
4619 if (framesize == 0) {
4620 info->netdev->stats.rx_errors++;
4621 info->netdev->stats.rx_frame_errors++;
4625 DBGBH(("%s rx frame status=%04X size=%d\n",
4626 info->device_name, status, framesize));
4627 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4630 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4631 framesize -= crc_size;
4635 if (framesize > info->max_frame_size + crc_size)
4636 info->icount.rxlong++;
4638 /* copy dma buffer(s) to contiguous temp buffer */
4639 int copy_count = framesize;
4641 unsigned char *p = info->tmp_rbuf;
4642 info->tmp_rbuf_count = framesize;
4644 info->icount.rxok++;
4647 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4648 memcpy(p, info->rbufs[i].buf, partial_count);
4650 copy_count -= partial_count;
4651 if (++i == info->rbuf_count)
4655 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4656 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4660 #if SYNCLINK_GENERIC_HDLC
4662 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4665 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4668 free_rbufs(info, start, end);
4676 * pass receive buffer (RAW synchronous mode) to tty layer
4677 * return true if buffer available, otherwise false
4679 static bool rx_get_buf(struct slgt_info *info)
4681 unsigned int i = info->rbuf_current;
4684 if (!desc_complete(info->rbufs[i]))
4686 count = desc_count(info->rbufs[i]);
4687 switch(info->params.mode) {
4688 case MGSL_MODE_MONOSYNC:
4689 case MGSL_MODE_BISYNC:
4690 case MGSL_MODE_XSYNC:
4691 /* ignore residue in byte synchronous modes */
4692 if (desc_residue(info->rbufs[i]))
4696 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4697 DBGINFO(("rx_get_buf size=%d\n", count));
4699 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4700 info->flag_buf, count);
4701 free_rbufs(info, i, i);
4705 static void reset_tbufs(struct slgt_info *info)
4708 info->tbuf_current = 0;
4709 for (i=0 ; i < info->tbuf_count ; i++) {
4710 info->tbufs[i].status = 0;
4711 info->tbufs[i].count = 0;
4716 * return number of free transmit DMA buffers
4718 static unsigned int free_tbuf_count(struct slgt_info *info)
4720 unsigned int count = 0;
4721 unsigned int i = info->tbuf_current;
4725 if (desc_count(info->tbufs[i]))
4726 break; /* buffer in use */
4728 if (++i == info->tbuf_count)
4730 } while (i != info->tbuf_current);
4732 /* if tx DMA active, last zero count buffer is in use */
4733 if (count && (rd_reg32(info, TDCSR) & BIT0))
4740 * return number of bytes in unsent transmit DMA buffers
4741 * and the serial controller tx FIFO
4743 static unsigned int tbuf_bytes(struct slgt_info *info)
4745 unsigned int total_count = 0;
4746 unsigned int i = info->tbuf_current;
4747 unsigned int reg_value;
4749 unsigned int active_buf_count = 0;
4752 * Add descriptor counts for all tx DMA buffers.
4753 * If count is zero (cleared by DMA controller after read),
4754 * the buffer is complete or is actively being read from.
4756 * Record buf_count of last buffer with zero count starting
4757 * from current ring position. buf_count is mirror
4758 * copy of count and is not cleared by serial controller.
4759 * If DMA controller is active, that buffer is actively
4760 * being read so add to total.
4763 count = desc_count(info->tbufs[i]);
4765 total_count += count;
4766 else if (!total_count)
4767 active_buf_count = info->tbufs[i].buf_count;
4768 if (++i == info->tbuf_count)
4770 } while (i != info->tbuf_current);
4772 /* read tx DMA status register */
4773 reg_value = rd_reg32(info, TDCSR);
4775 /* if tx DMA active, last zero count buffer is in use */
4776 if (reg_value & BIT0)
4777 total_count += active_buf_count;
4779 /* add tx FIFO count = reg_value[15..8] */
4780 total_count += (reg_value >> 8) & 0xff;
4782 /* if transmitter active add one byte for shift register */
4783 if (info->tx_active)
4790 * load data into transmit DMA buffer ring and start transmitter if needed
4791 * return true if data accepted, otherwise false (buffers full)
4793 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4795 unsigned short count;
4797 struct slgt_desc *d;
4799 /* check required buffer space */
4800 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4803 DBGDATA(info, buf, size, "tx");
4806 * copy data to one or more DMA buffers in circular ring
4807 * tbuf_start = first buffer for this data
4808 * tbuf_current = next free buffer
4810 * Copy all data before making data visible to DMA controller by
4811 * setting descriptor count of the first buffer.
4812 * This prevents an active DMA controller from reading the first DMA
4813 * buffers of a frame and stopping before the final buffers are filled.
4816 info->tbuf_start = i = info->tbuf_current;
4819 d = &info->tbufs[i];
4821 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4822 memcpy(d->buf, buf, count);
4828 * set EOF bit for last buffer of HDLC frame or
4829 * for every buffer in raw mode
4831 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4832 info->params.mode == MGSL_MODE_RAW)
4833 set_desc_eof(*d, 1);
4835 set_desc_eof(*d, 0);
4837 /* set descriptor count for all but first buffer */
4838 if (i != info->tbuf_start)
4839 set_desc_count(*d, count);
4840 d->buf_count = count;
4842 if (++i == info->tbuf_count)
4846 info->tbuf_current = i;
4848 /* set first buffer count to make new data visible to DMA controller */
4849 d = &info->tbufs[info->tbuf_start];
4850 set_desc_count(*d, d->buf_count);
4852 /* start transmitter if needed and update transmit timeout */
4853 if (!info->tx_active)
4855 update_tx_timer(info);
4860 static int register_test(struct slgt_info *info)
4862 static unsigned short patterns[] =
4863 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4864 static unsigned int count = ARRAY_SIZE(patterns);
4868 for (i=0 ; i < count ; i++) {
4869 wr_reg16(info, TIR, patterns[i]);
4870 wr_reg16(info, BDR, patterns[(i+1)%count]);
4871 if ((rd_reg16(info, TIR) != patterns[i]) ||
4872 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4877 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4878 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4882 static int irq_test(struct slgt_info *info)
4884 unsigned long timeout;
4885 unsigned long flags;
4886 struct tty_struct *oldtty = info->port.tty;
4887 u32 speed = info->params.data_rate;
4889 info->params.data_rate = 921600;
4890 info->port.tty = NULL;
4892 spin_lock_irqsave(&info->lock, flags);
4894 slgt_irq_on(info, IRQ_TXIDLE);
4896 /* enable transmitter */
4898 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4900 /* write one byte and wait for tx idle */
4901 wr_reg16(info, TDR, 0);
4903 /* assume failure */
4904 info->init_error = DiagStatus_IrqFailure;
4905 info->irq_occurred = false;
4907 spin_unlock_irqrestore(&info->lock, flags);
4910 while(timeout-- && !info->irq_occurred)
4911 msleep_interruptible(10);
4913 spin_lock_irqsave(&info->lock,flags);
4915 spin_unlock_irqrestore(&info->lock,flags);
4917 info->params.data_rate = speed;
4918 info->port.tty = oldtty;
4920 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4921 return info->irq_occurred ? 0 : -ENODEV;
4924 static int loopback_test_rx(struct slgt_info *info)
4926 unsigned char *src, *dest;
4929 if (desc_complete(info->rbufs[0])) {
4930 count = desc_count(info->rbufs[0]);
4931 src = info->rbufs[0].buf;
4932 dest = info->tmp_rbuf;
4934 for( ; count ; count-=2, src+=2) {
4935 /* src=data byte (src+1)=status byte */
4936 if (!(*(src+1) & (BIT9 + BIT8))) {
4939 info->tmp_rbuf_count++;
4942 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4948 static int loopback_test(struct slgt_info *info)
4950 #define TESTFRAMESIZE 20
4952 unsigned long timeout;
4954 unsigned char buf[TESTFRAMESIZE];
4956 unsigned long flags;
4958 struct tty_struct *oldtty = info->port.tty;
4961 memcpy(¶ms, &info->params, sizeof(params));
4963 info->params.mode = MGSL_MODE_ASYNC;
4964 info->params.data_rate = 921600;
4965 info->params.loopback = 1;
4966 info->port.tty = NULL;
4968 /* build and send transmit frame */
4969 for (count = 0; count < TESTFRAMESIZE; ++count)
4970 buf[count] = (unsigned char)count;
4972 info->tmp_rbuf_count = 0;
4973 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4975 /* program hardware for HDLC and enabled receiver */
4976 spin_lock_irqsave(&info->lock,flags);
4979 tx_load(info, buf, count);
4980 spin_unlock_irqrestore(&info->lock, flags);
4982 /* wait for receive complete */
4983 for (timeout = 100; timeout; --timeout) {
4984 msleep_interruptible(10);
4985 if (loopback_test_rx(info)) {
4991 /* verify received frame length and contents */
4992 if (!rc && (info->tmp_rbuf_count != count ||
4993 memcmp(buf, info->tmp_rbuf, count))) {
4997 spin_lock_irqsave(&info->lock,flags);
4998 reset_adapter(info);
4999 spin_unlock_irqrestore(&info->lock,flags);
5001 memcpy(&info->params, ¶ms, sizeof(info->params));
5002 info->port.tty = oldtty;
5004 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5008 static int adapter_test(struct slgt_info *info)
5010 DBGINFO(("testing %s\n", info->device_name));
5011 if (register_test(info) < 0) {
5012 printk("register test failure %s addr=%08X\n",
5013 info->device_name, info->phys_reg_addr);
5014 } else if (irq_test(info) < 0) {
5015 printk("IRQ test failure %s IRQ=%d\n",
5016 info->device_name, info->irq_level);
5017 } else if (loopback_test(info) < 0) {
5018 printk("loopback test failure %s\n", info->device_name);
5020 return info->init_error;
5024 * transmit timeout handler
5026 static void tx_timeout(struct timer_list *t)
5028 struct slgt_info *info = from_timer(info, t, tx_timer);
5029 unsigned long flags;
5031 DBGINFO(("%s tx_timeout\n", info->device_name));
5032 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5033 info->icount.txtimeout++;
5035 spin_lock_irqsave(&info->lock,flags);
5037 spin_unlock_irqrestore(&info->lock,flags);
5039 #if SYNCLINK_GENERIC_HDLC
5041 hdlcdev_tx_done(info);
5048 * receive buffer polling timer
5050 static void rx_timeout(struct timer_list *t)
5052 struct slgt_info *info = from_timer(info, t, rx_timer);
5053 unsigned long flags;
5055 DBGINFO(("%s rx_timeout\n", info->device_name));
5056 spin_lock_irqsave(&info->lock, flags);
5057 info->pending_bh |= BH_RECEIVE;
5058 spin_unlock_irqrestore(&info->lock, flags);
5059 bh_handler(&info->task);