1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/console.h>
15 #include <linux/serial_core.h>
16 #include <linux/slab.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/clk.h>
20 #include <linux/irq.h>
23 #include <linux/module.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/iopoll.h>
27 #define CDNS_UART_TTY_NAME "ttyPS"
28 #define CDNS_UART_NAME "xuartps"
29 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
30 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
31 #define CDNS_UART_NR_PORTS 16
32 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
33 #define CDNS_UART_REGISTER_SPACE 0x1000
34 #define TX_TIMEOUT 500000
36 /* Rx Trigger level */
37 static int rx_trigger_level = 56;
38 module_param(rx_trigger_level, uint, 0444);
39 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
42 static int rx_timeout = 10;
43 module_param(rx_timeout, uint, 0444);
44 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
46 /* Register offsets for the UART. */
47 #define CDNS_UART_CR 0x00 /* Control Register */
48 #define CDNS_UART_MR 0x04 /* Mode Register */
49 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
50 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
51 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
52 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
53 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
54 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
55 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
56 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
57 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
58 #define CDNS_UART_SR 0x2C /* Channel Status */
59 #define CDNS_UART_FIFO 0x30 /* FIFO */
60 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
61 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
62 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
63 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
64 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
65 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
67 /* Control Register Bit Definitions */
68 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
69 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
70 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
71 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
72 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
73 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
74 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
75 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
76 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
77 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
78 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
79 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
83 * The mode register (MR) defines the mode of transfer as well as the data
84 * format. If this register is modified during transmission or reception,
85 * data validity cannot be guaranteed.
87 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
88 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
89 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
90 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
92 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
93 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
95 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
96 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
97 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
98 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
99 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
101 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
102 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
103 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
106 * Interrupt Registers:
107 * Interrupt control logic uses the interrupt enable register (IER) and the
108 * interrupt disable register (IDR) to set the value of the bits in the
109 * interrupt mask register (IMR). The IMR determines whether to pass an
110 * interrupt to the interrupt status register (ISR).
111 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
112 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
113 * Reading either IER or IDR returns 0x00.
114 * All four registers have the same bit definitions.
116 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
117 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
118 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
119 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
120 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
121 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
122 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
123 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
124 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
125 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
126 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
129 * Do not enable parity error interrupt for the following
130 * reason: When parity error interrupt is enabled, each Rx
131 * parity error always results in 2 events. The first one
132 * being parity error interrupt and the second one with a
133 * proper Rx interrupt with the incoming data. Disabling
134 * parity error interrupt ensures better handling of parity
135 * error events. With this change, for a parity error case, we
136 * get a Rx interrupt with parity error set in ISR register
137 * and we still handle parity errors in the desired way.
140 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
141 CDNS_UART_IXR_OVERRUN | \
142 CDNS_UART_IXR_RXTRIG | \
145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
146 #define CDNS_UART_IXR_BRK 0x00002000
148 #define CDNS_UART_RXBS_SUPPORT BIT(1)
150 * Modem Control register:
151 * The read/write Modem Control register controls the interface with the modem
152 * or data set, or a peripheral device emulating a modem.
154 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
155 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
156 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
159 * Modem Status register:
160 * The read/write Modem Status register reports the interface with the modem
161 * or data set, or a peripheral device emulating a modem.
163 #define CDNS_UART_MODEMSR_DCD BIT(7) /* Data Carrier Detect */
164 #define CDNS_UART_MODEMSR_RI BIT(6) /* Ting Indicator */
165 #define CDNS_UART_MODEMSR_DSR BIT(5) /* Data Set Ready */
166 #define CDNS_UART_MODEMSR_CTS BIT(4) /* Clear To Send */
169 * Channel Status Register:
170 * The channel status register (CSR) is provided to enable the control logic
171 * to monitor the status of bits in the channel interrupt status register,
172 * even if these are masked out by the interrupt mask register.
174 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
175 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
176 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
177 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
178 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
180 /* baud dividers min/max values */
181 #define CDNS_UART_BDIV_MIN 4
182 #define CDNS_UART_BDIV_MAX 255
183 #define CDNS_UART_CD_MAX 65535
184 #define UART_AUTOSUSPEND_TIMEOUT 3000
187 * struct cdns_uart - device data
188 * @port: Pointer to the UART port
189 * @uartclk: Reference clock
191 * @cdns_uart_driver: Pointer to UART driver
192 * @baud: Current baud rate
193 * @clk_rate_change_nb: Notifier block for clock changes
194 * @quirks: Flags for RXBS support.
195 * @cts_override: Modem control state override
198 struct uart_port *port;
201 struct uart_driver *cdns_uart_driver;
203 struct notifier_block clk_rate_change_nb;
207 struct cdns_platform_data {
210 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
214 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
215 * @dev_id: Id of the UART port
216 * @isrstatus: The interrupt status register value as read
219 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
221 struct uart_port *port = (struct uart_port *)dev_id;
222 struct cdns_uart *cdns_uart = port->private_data;
224 unsigned int rxbs_status = 0;
225 unsigned int status_mask;
226 unsigned int framerrprocessed = 0;
227 char status = TTY_NORMAL;
228 bool is_rxbs_support;
230 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
232 while ((readl(port->membase + CDNS_UART_SR) &
233 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
235 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
236 data = readl(port->membase + CDNS_UART_FIFO);
239 * There is no hardware break detection in Zynq, so we interpret
240 * framing error with all-zeros data as a break sequence.
241 * Most of the time, there's another non-zero byte at the
242 * end of the sequence.
244 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
246 port->read_status_mask |= CDNS_UART_IXR_BRK;
247 framerrprocessed = 1;
251 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
254 if (uart_handle_break(port))
258 isrstatus &= port->read_status_mask;
259 isrstatus &= ~port->ignore_status_mask;
260 status_mask = port->read_status_mask;
261 status_mask &= ~port->ignore_status_mask;
264 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
265 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
267 if (uart_handle_break(port))
271 if (uart_handle_sysrq_char(port, data))
274 if (is_rxbs_support) {
275 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
276 && (status_mask & CDNS_UART_IXR_PARITY)) {
277 port->icount.parity++;
280 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
281 && (status_mask & CDNS_UART_IXR_PARITY)) {
282 port->icount.frame++;
286 if (isrstatus & CDNS_UART_IXR_PARITY) {
287 port->icount.parity++;
290 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
292 port->icount.frame++;
296 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
297 port->icount.overrun++;
298 tty_insert_flip_char(&port->state->port, 0,
301 tty_insert_flip_char(&port->state->port, data, status);
305 tty_flip_buffer_push(&port->state->port);
309 * cdns_uart_handle_tx - Handle the bytes to be Txed.
310 * @dev_id: Id of the UART port
313 static void cdns_uart_handle_tx(void *dev_id)
315 struct uart_port *port = (struct uart_port *)dev_id;
316 struct circ_buf *xmit = &port->state->xmit;
317 unsigned int numbytes;
319 if (uart_circ_empty(xmit)) {
320 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
324 numbytes = port->fifosize;
325 while (numbytes && !uart_circ_empty(xmit) &&
326 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
328 writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO);
329 uart_xmit_advance(port, 1);
333 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
334 uart_write_wakeup(port);
338 * cdns_uart_isr - Interrupt handler
340 * @dev_id: Id of the port
344 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
346 struct uart_port *port = (struct uart_port *)dev_id;
347 unsigned int isrstatus;
349 spin_lock(&port->lock);
351 /* Read the interrupt status register to determine which
352 * interrupt(s) is/are active and clear them.
354 isrstatus = readl(port->membase + CDNS_UART_ISR);
355 writel(isrstatus, port->membase + CDNS_UART_ISR);
357 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
358 cdns_uart_handle_tx(dev_id);
359 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
362 isrstatus &= port->read_status_mask;
363 isrstatus &= ~port->ignore_status_mask;
365 * Skip RX processing if RX is disabled as RXEMPTY will never be set
366 * as read bytes will not be removed from the FIFO.
368 if (isrstatus & CDNS_UART_IXR_RXMASK &&
369 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
370 cdns_uart_handle_rx(dev_id, isrstatus);
372 spin_unlock(&port->lock);
377 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
378 * @clk: UART module input clock
379 * @baud: Desired baud rate
380 * @rbdiv: BDIV value (return value)
381 * @rcd: CD value (return value)
382 * @div8: Value for clk_sel bit in mod (return value)
383 * Return: baud rate, requested baud when possible, or actual baud when there
384 * was too much error, zero if no valid divisors are found.
386 * Formula to obtain baud rate is
387 * baud_tx/rx rate = clk/CD * (BDIV + 1)
388 * input_clk = (Uart User Defined Clock or Apb Clock)
389 * depends on UCLKEN in MR Reg
390 * clk = input_clk or input_clk/8;
391 * depends on CLKS in MR reg
392 * CD and BDIV depends on values in
393 * baud rate generate register
394 * baud rate clock divisor register
396 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
397 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
400 unsigned int calc_baud;
401 unsigned int bestbaud = 0;
402 unsigned int bauderror;
403 unsigned int besterror = ~0;
405 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
412 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
413 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
414 if (cd < 1 || cd > CDNS_UART_CD_MAX)
417 calc_baud = clk / (cd * (bdiv + 1));
419 if (baud > calc_baud)
420 bauderror = baud - calc_baud;
422 bauderror = calc_baud - baud;
424 if (besterror > bauderror) {
427 bestbaud = calc_baud;
428 besterror = bauderror;
431 /* use the values when percent error is acceptable */
432 if (((besterror * 100) / baud) < 3)
439 * cdns_uart_set_baud_rate - Calculate and set the baud rate
440 * @port: Handle to the uart port structure
441 * @baud: Baud rate to set
442 * Return: baud rate, requested baud when possible, or actual baud when there
443 * was too much error, zero if no valid divisors are found.
445 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
448 unsigned int calc_baud;
449 u32 cd = 0, bdiv = 0;
452 struct cdns_uart *cdns_uart = port->private_data;
454 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
457 /* Write new divisors to hardware */
458 mreg = readl(port->membase + CDNS_UART_MR);
460 mreg |= CDNS_UART_MR_CLKSEL;
462 mreg &= ~CDNS_UART_MR_CLKSEL;
463 writel(mreg, port->membase + CDNS_UART_MR);
464 writel(cd, port->membase + CDNS_UART_BAUDGEN);
465 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
466 cdns_uart->baud = baud;
471 #ifdef CONFIG_COMMON_CLK
473 * cdns_uart_clk_notifier_cb - Clock notifier callback
474 * @nb: Notifier block
475 * @event: Notify event
476 * @data: Notifier data
477 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
479 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
480 unsigned long event, void *data)
483 struct uart_port *port;
485 struct clk_notifier_data *ndata = data;
486 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
489 port = cdns_uart->port;
494 case PRE_RATE_CHANGE:
500 * Find out if current baud-rate can be achieved with new clock
503 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
504 &bdiv, &cd, &div8)) {
505 dev_warn(port->dev, "clock rate change rejected\n");
509 spin_lock_irqsave(&cdns_uart->port->lock, flags);
511 /* Disable the TX and RX to set baud rate */
512 ctrl_reg = readl(port->membase + CDNS_UART_CR);
513 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
514 writel(ctrl_reg, port->membase + CDNS_UART_CR);
516 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
520 case POST_RATE_CHANGE:
522 * Set clk dividers to generate correct baud with new clock
526 spin_lock_irqsave(&cdns_uart->port->lock, flags);
529 port->uartclk = ndata->new_rate;
531 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
534 case ABORT_RATE_CHANGE:
536 spin_lock_irqsave(&cdns_uart->port->lock, flags);
538 /* Set TX/RX Reset */
539 ctrl_reg = readl(port->membase + CDNS_UART_CR);
540 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
541 writel(ctrl_reg, port->membase + CDNS_UART_CR);
543 while (readl(port->membase + CDNS_UART_CR) &
544 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
548 * Clear the RX disable and TX disable bits and then set the TX
549 * enable bit and RX enable bit to enable the transmitter and
552 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
553 ctrl_reg = readl(port->membase + CDNS_UART_CR);
554 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
555 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
556 writel(ctrl_reg, port->membase + CDNS_UART_CR);
558 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
568 * cdns_uart_start_tx - Start transmitting bytes
569 * @port: Handle to the uart port structure
571 static void cdns_uart_start_tx(struct uart_port *port)
575 if (uart_tx_stopped(port))
579 * Set the TX enable bit and clear the TX disable bit to enable the
582 status = readl(port->membase + CDNS_UART_CR);
583 status &= ~CDNS_UART_CR_TX_DIS;
584 status |= CDNS_UART_CR_TX_EN;
585 writel(status, port->membase + CDNS_UART_CR);
587 if (uart_circ_empty(&port->state->xmit))
590 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
592 cdns_uart_handle_tx(port);
594 /* Enable the TX Empty interrupt */
595 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
599 * cdns_uart_stop_tx - Stop TX
600 * @port: Handle to the uart port structure
602 static void cdns_uart_stop_tx(struct uart_port *port)
606 regval = readl(port->membase + CDNS_UART_CR);
607 regval |= CDNS_UART_CR_TX_DIS;
608 /* Disable the transmitter */
609 writel(regval, port->membase + CDNS_UART_CR);
613 * cdns_uart_stop_rx - Stop RX
614 * @port: Handle to the uart port structure
616 static void cdns_uart_stop_rx(struct uart_port *port)
620 /* Disable RX IRQs */
621 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
623 /* Disable the receiver */
624 regval = readl(port->membase + CDNS_UART_CR);
625 regval |= CDNS_UART_CR_RX_DIS;
626 writel(regval, port->membase + CDNS_UART_CR);
630 * cdns_uart_tx_empty - Check whether TX is empty
631 * @port: Handle to the uart port structure
633 * Return: TIOCSER_TEMT on success, 0 otherwise
635 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
639 status = readl(port->membase + CDNS_UART_SR) &
640 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE);
641 return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0;
645 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
646 * transmitting char breaks
647 * @port: Handle to the uart port structure
648 * @ctl: Value based on which start or stop decision is taken
650 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
655 spin_lock_irqsave(&port->lock, flags);
657 status = readl(port->membase + CDNS_UART_CR);
660 writel(CDNS_UART_CR_STARTBRK | status,
661 port->membase + CDNS_UART_CR);
663 if ((status & CDNS_UART_CR_STOPBRK) == 0)
664 writel(CDNS_UART_CR_STOPBRK | status,
665 port->membase + CDNS_UART_CR);
667 spin_unlock_irqrestore(&port->lock, flags);
671 * cdns_uart_set_termios - termios operations, handling data length, parity,
672 * stop bits, flow control, baud rate
673 * @port: Handle to the uart port structure
674 * @termios: Handle to the input termios structure
675 * @old: Values of the previously saved termios structure
677 static void cdns_uart_set_termios(struct uart_port *port,
678 struct ktermios *termios,
679 const struct ktermios *old)
682 unsigned int baud, minbaud, maxbaud;
684 unsigned int ctrl_reg, mode_reg;
686 spin_lock_irqsave(&port->lock, flags);
688 /* Disable the TX and RX to set baud rate */
689 ctrl_reg = readl(port->membase + CDNS_UART_CR);
690 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
691 writel(ctrl_reg, port->membase + CDNS_UART_CR);
694 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
695 * min and max baud should be calculated here based on port->uartclk.
696 * this way we get a valid baud and can safely call set_baud()
698 minbaud = port->uartclk /
699 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
700 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
701 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
702 baud = cdns_uart_set_baud_rate(port, baud);
703 if (tty_termios_baud_rate(termios))
704 tty_termios_encode_baud_rate(termios, baud, baud);
706 /* Update the per-port timeout. */
707 uart_update_timeout(port, termios->c_cflag, baud);
709 /* Set TX/RX Reset */
710 ctrl_reg = readl(port->membase + CDNS_UART_CR);
711 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
712 writel(ctrl_reg, port->membase + CDNS_UART_CR);
714 while (readl(port->membase + CDNS_UART_CR) &
715 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
719 * Clear the RX disable and TX disable bits and then set the TX enable
720 * bit and RX enable bit to enable the transmitter and receiver.
722 ctrl_reg = readl(port->membase + CDNS_UART_CR);
723 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
724 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
725 writel(ctrl_reg, port->membase + CDNS_UART_CR);
727 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
729 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
730 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
731 port->ignore_status_mask = 0;
733 if (termios->c_iflag & INPCK)
734 port->read_status_mask |= CDNS_UART_IXR_PARITY |
735 CDNS_UART_IXR_FRAMING;
737 if (termios->c_iflag & IGNPAR)
738 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
739 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
741 /* ignore all characters if CREAD is not set */
742 if ((termios->c_cflag & CREAD) == 0)
743 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
744 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
745 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
747 mode_reg = readl(port->membase + CDNS_UART_MR);
749 /* Handling Data Size */
750 switch (termios->c_cflag & CSIZE) {
752 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
755 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
759 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
760 termios->c_cflag &= ~CSIZE;
761 termios->c_cflag |= CS8;
765 /* Handling Parity and Stop Bits length */
766 if (termios->c_cflag & CSTOPB)
767 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
769 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
771 if (termios->c_cflag & PARENB) {
772 /* Mark or Space parity */
773 if (termios->c_cflag & CMSPAR) {
774 if (termios->c_cflag & PARODD)
775 cval |= CDNS_UART_MR_PARITY_MARK;
777 cval |= CDNS_UART_MR_PARITY_SPACE;
779 if (termios->c_cflag & PARODD)
780 cval |= CDNS_UART_MR_PARITY_ODD;
782 cval |= CDNS_UART_MR_PARITY_EVEN;
785 cval |= CDNS_UART_MR_PARITY_NONE;
787 cval |= mode_reg & 1;
788 writel(cval, port->membase + CDNS_UART_MR);
790 cval = readl(port->membase + CDNS_UART_MODEMCR);
791 if (termios->c_cflag & CRTSCTS)
792 cval |= CDNS_UART_MODEMCR_FCM;
794 cval &= ~CDNS_UART_MODEMCR_FCM;
795 writel(cval, port->membase + CDNS_UART_MODEMCR);
797 spin_unlock_irqrestore(&port->lock, flags);
801 * cdns_uart_startup - Called when an application opens a cdns_uart port
802 * @port: Handle to the uart port structure
804 * Return: 0 on success, negative errno otherwise
806 static int cdns_uart_startup(struct uart_port *port)
808 struct cdns_uart *cdns_uart = port->private_data;
812 unsigned int status = 0;
814 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
816 spin_lock_irqsave(&port->lock, flags);
818 /* Disable the TX and RX */
819 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
820 port->membase + CDNS_UART_CR);
822 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
825 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
826 port->membase + CDNS_UART_CR);
828 while (readl(port->membase + CDNS_UART_CR) &
829 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
833 * Clear the RX disable bit and then set the RX enable bit to enable
836 status = readl(port->membase + CDNS_UART_CR);
837 status &= ~CDNS_UART_CR_RX_DIS;
838 status |= CDNS_UART_CR_RX_EN;
839 writel(status, port->membase + CDNS_UART_CR);
841 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
844 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
845 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
846 port->membase + CDNS_UART_MR);
849 * Set the RX FIFO Trigger level to use most of the FIFO, but it
850 * can be tuned with a module parameter
852 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
855 * Receive Timeout register is enabled but it
856 * can be tuned with a module parameter
858 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
860 /* Clear out any pending interrupts before enabling them */
861 writel(readl(port->membase + CDNS_UART_ISR),
862 port->membase + CDNS_UART_ISR);
864 spin_unlock_irqrestore(&port->lock, flags);
866 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
868 dev_err(port->dev, "request_irq '%d' failed with %d\n",
873 /* Set the Interrupt Registers with desired interrupts */
875 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
876 port->membase + CDNS_UART_IER);
878 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
884 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
885 * @port: Handle to the uart port structure
887 static void cdns_uart_shutdown(struct uart_port *port)
892 spin_lock_irqsave(&port->lock, flags);
894 /* Disable interrupts */
895 status = readl(port->membase + CDNS_UART_IMR);
896 writel(status, port->membase + CDNS_UART_IDR);
897 writel(0xffffffff, port->membase + CDNS_UART_ISR);
899 /* Disable the TX and RX */
900 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
901 port->membase + CDNS_UART_CR);
903 spin_unlock_irqrestore(&port->lock, flags);
905 free_irq(port->irq, port);
909 * cdns_uart_type - Set UART type to cdns_uart port
910 * @port: Handle to the uart port structure
912 * Return: string on success, NULL otherwise
914 static const char *cdns_uart_type(struct uart_port *port)
916 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
920 * cdns_uart_verify_port - Verify the port params
921 * @port: Handle to the uart port structure
922 * @ser: Handle to the structure whose members are compared
924 * Return: 0 on success, negative errno otherwise.
926 static int cdns_uart_verify_port(struct uart_port *port,
927 struct serial_struct *ser)
929 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
931 if (port->irq != ser->irq)
933 if (ser->io_type != UPIO_MEM)
935 if (port->iobase != ser->port)
943 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
944 * called when the driver adds a cdns_uart port via
945 * uart_add_one_port()
946 * @port: Handle to the uart port structure
948 * Return: 0 on success, negative errno otherwise.
950 static int cdns_uart_request_port(struct uart_port *port)
952 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
957 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
958 if (!port->membase) {
959 dev_err(port->dev, "Unable to map registers\n");
960 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
967 * cdns_uart_release_port - Release UART port
968 * @port: Handle to the uart port structure
970 * Release the memory region attached to a cdns_uart port. Called when the
971 * driver removes a cdns_uart port via uart_remove_one_port().
973 static void cdns_uart_release_port(struct uart_port *port)
975 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
976 iounmap(port->membase);
977 port->membase = NULL;
981 * cdns_uart_config_port - Configure UART port
982 * @port: Handle to the uart port structure
985 static void cdns_uart_config_port(struct uart_port *port, int flags)
987 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
988 port->type = PORT_XUARTPS;
992 * cdns_uart_get_mctrl - Get the modem control state
993 * @port: Handle to the uart port structure
995 * Return: the modem control state
997 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1000 unsigned int mctrl = 0;
1001 struct cdns_uart *cdns_uart_data = port->private_data;
1003 if (cdns_uart_data->cts_override)
1004 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1006 val = readl(port->membase + CDNS_UART_MODEMSR);
1007 if (val & CDNS_UART_MODEMSR_CTS)
1009 if (val & CDNS_UART_MODEMSR_DSR)
1011 if (val & CDNS_UART_MODEMSR_RI)
1013 if (val & CDNS_UART_MODEMSR_DCD)
1019 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1023 struct cdns_uart *cdns_uart_data = port->private_data;
1025 if (cdns_uart_data->cts_override)
1028 val = readl(port->membase + CDNS_UART_MODEMCR);
1029 mode_reg = readl(port->membase + CDNS_UART_MR);
1031 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1032 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1034 if (mctrl & TIOCM_RTS)
1035 val |= CDNS_UART_MODEMCR_RTS;
1036 if (mctrl & TIOCM_DTR)
1037 val |= CDNS_UART_MODEMCR_DTR;
1038 if (mctrl & TIOCM_LOOP)
1039 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1041 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1043 writel(val, port->membase + CDNS_UART_MODEMCR);
1044 writel(mode_reg, port->membase + CDNS_UART_MR);
1047 #ifdef CONFIG_CONSOLE_POLL
1048 static int cdns_uart_poll_get_char(struct uart_port *port)
1051 unsigned long flags;
1053 spin_lock_irqsave(&port->lock, flags);
1055 /* Check if FIFO is empty */
1056 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1058 else /* Read a character */
1059 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1061 spin_unlock_irqrestore(&port->lock, flags);
1066 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1068 unsigned long flags;
1070 spin_lock_irqsave(&port->lock, flags);
1072 /* Wait until FIFO is empty */
1073 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1076 /* Write a character */
1077 writel(c, port->membase + CDNS_UART_FIFO);
1079 /* Wait until FIFO is empty */
1080 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1083 spin_unlock_irqrestore(&port->lock, flags);
1087 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1088 unsigned int oldstate)
1091 case UART_PM_STATE_OFF:
1092 pm_runtime_mark_last_busy(port->dev);
1093 pm_runtime_put_autosuspend(port->dev);
1096 pm_runtime_get_sync(port->dev);
1101 static const struct uart_ops cdns_uart_ops = {
1102 .set_mctrl = cdns_uart_set_mctrl,
1103 .get_mctrl = cdns_uart_get_mctrl,
1104 .start_tx = cdns_uart_start_tx,
1105 .stop_tx = cdns_uart_stop_tx,
1106 .stop_rx = cdns_uart_stop_rx,
1107 .tx_empty = cdns_uart_tx_empty,
1108 .break_ctl = cdns_uart_break_ctl,
1109 .set_termios = cdns_uart_set_termios,
1110 .startup = cdns_uart_startup,
1111 .shutdown = cdns_uart_shutdown,
1113 .type = cdns_uart_type,
1114 .verify_port = cdns_uart_verify_port,
1115 .request_port = cdns_uart_request_port,
1116 .release_port = cdns_uart_release_port,
1117 .config_port = cdns_uart_config_port,
1118 #ifdef CONFIG_CONSOLE_POLL
1119 .poll_get_char = cdns_uart_poll_get_char,
1120 .poll_put_char = cdns_uart_poll_put_char,
1124 static struct uart_driver cdns_uart_uart_driver;
1126 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1128 * cdns_uart_console_putchar - write the character to the FIFO buffer
1129 * @port: Handle to the uart port structure
1130 * @ch: Character to be written
1132 static void cdns_uart_console_putchar(struct uart_port *port, unsigned char ch)
1134 unsigned int ctrl_reg;
1135 unsigned long timeout;
1137 timeout = jiffies + msecs_to_jiffies(1000);
1139 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1140 if (!(ctrl_reg & CDNS_UART_CR_TX_DIS))
1142 if (time_after(jiffies, timeout)) {
1144 "timeout waiting for Enable\n");
1150 timeout = jiffies + msecs_to_jiffies(1000);
1152 ctrl_reg = readl(port->membase + CDNS_UART_SR);
1154 if (!(ctrl_reg & CDNS_UART_SR_TXFULL))
1156 if (time_after(jiffies, timeout)) {
1158 "timeout waiting for TX fifo\n");
1163 writel(ch, port->membase + CDNS_UART_FIFO);
1166 static void cdns_early_write(struct console *con, const char *s,
1169 struct earlycon_device *dev = con->data;
1171 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1174 static int __init cdns_early_console_setup(struct earlycon_device *device,
1177 struct uart_port *port = &device->port;
1182 /* initialise control register */
1183 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1184 port->membase + CDNS_UART_CR);
1186 /* only set baud if specified on command line - otherwise
1187 * assume it has been initialized by a boot loader.
1189 if (port->uartclk && device->baud) {
1190 u32 cd = 0, bdiv = 0;
1194 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1196 mr = CDNS_UART_MR_PARITY_NONE;
1198 mr |= CDNS_UART_MR_CLKSEL;
1200 writel(mr, port->membase + CDNS_UART_MR);
1201 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1202 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1205 device->con->write = cdns_early_write;
1209 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1210 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1211 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1212 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1215 /* Static pointer to console port */
1216 static struct uart_port *console_port;
1219 * cdns_uart_console_write - perform write operation
1220 * @co: Console handle
1221 * @s: Pointer to character array
1222 * @count: No of characters
1224 static void cdns_uart_console_write(struct console *co, const char *s,
1227 struct uart_port *port = console_port;
1228 unsigned long flags;
1229 unsigned int imr, ctrl;
1234 else if (oops_in_progress)
1235 locked = spin_trylock_irqsave(&port->lock, flags);
1237 spin_lock_irqsave(&port->lock, flags);
1239 /* save and disable interrupt */
1240 imr = readl(port->membase + CDNS_UART_IMR);
1241 writel(imr, port->membase + CDNS_UART_IDR);
1244 * Make sure that the tx part is enabled. Set the TX enable bit and
1245 * clear the TX disable bit to enable the transmitter.
1247 ctrl = readl(port->membase + CDNS_UART_CR);
1248 ctrl &= ~CDNS_UART_CR_TX_DIS;
1249 ctrl |= CDNS_UART_CR_TX_EN;
1250 writel(ctrl, port->membase + CDNS_UART_CR);
1252 uart_console_write(port, s, count, cdns_uart_console_putchar);
1253 while (cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1256 /* restore interrupt state */
1257 writel(imr, port->membase + CDNS_UART_IER);
1260 spin_unlock_irqrestore(&port->lock, flags);
1264 * cdns_uart_console_setup - Initialize the uart to default config
1265 * @co: Console handle
1266 * @options: Initial settings of uart
1268 * Return: 0 on success, negative errno otherwise.
1270 static int cdns_uart_console_setup(struct console *co, char *options)
1272 struct uart_port *port = console_port;
1278 unsigned long time_out;
1280 if (!port->membase) {
1281 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1287 uart_parse_options(options, &baud, &parity, &bits, &flow);
1289 /* Wait for tx_empty before setting up the console */
1290 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1292 while (time_before(jiffies, time_out) &&
1293 cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1296 return uart_set_options(port, co, baud, parity, bits, flow);
1299 static struct console cdns_uart_console = {
1300 .name = CDNS_UART_TTY_NAME,
1301 .write = cdns_uart_console_write,
1302 .device = uart_console_device,
1303 .setup = cdns_uart_console_setup,
1304 .flags = CON_PRINTBUFFER,
1305 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1306 .data = &cdns_uart_uart_driver,
1308 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1310 #ifdef CONFIG_PM_SLEEP
1312 * cdns_uart_suspend - suspend event
1313 * @device: Pointer to the device structure
1317 static int cdns_uart_suspend(struct device *device)
1319 struct uart_port *port = dev_get_drvdata(device);
1320 struct cdns_uart *cdns_uart = port->private_data;
1323 may_wake = device_may_wakeup(device);
1325 if (console_suspend_enabled && uart_console(port) && may_wake) {
1326 unsigned long flags;
1328 spin_lock_irqsave(&port->lock, flags);
1329 /* Empty the receive FIFO 1st before making changes */
1330 while (!(readl(port->membase + CDNS_UART_SR) &
1331 CDNS_UART_SR_RXEMPTY))
1332 readl(port->membase + CDNS_UART_FIFO);
1333 /* set RX trigger level to 1 */
1334 writel(1, port->membase + CDNS_UART_RXWM);
1335 /* disable RX timeout interrups */
1336 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1337 spin_unlock_irqrestore(&port->lock, flags);
1341 * Call the API provided in serial_core.c file which handles
1344 return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1348 * cdns_uart_resume - Resume after a previous suspend
1349 * @device: Pointer to the device structure
1353 static int cdns_uart_resume(struct device *device)
1355 struct uart_port *port = dev_get_drvdata(device);
1356 struct cdns_uart *cdns_uart = port->private_data;
1357 unsigned long flags;
1362 may_wake = device_may_wakeup(device);
1364 if (console_suspend_enabled && uart_console(port) && !may_wake) {
1365 ret = clk_enable(cdns_uart->pclk);
1369 ret = clk_enable(cdns_uart->uartclk);
1371 clk_disable(cdns_uart->pclk);
1375 spin_lock_irqsave(&port->lock, flags);
1377 /* Set TX/RX Reset */
1378 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1379 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1380 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1381 while (readl(port->membase + CDNS_UART_CR) &
1382 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1385 /* restore rx timeout value */
1386 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1388 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1389 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1390 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1391 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1393 clk_disable(cdns_uart->uartclk);
1394 clk_disable(cdns_uart->pclk);
1395 spin_unlock_irqrestore(&port->lock, flags);
1397 spin_lock_irqsave(&port->lock, flags);
1398 /* restore original rx trigger level */
1399 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1400 /* enable RX timeout interrupt */
1401 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1402 spin_unlock_irqrestore(&port->lock, flags);
1405 return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1407 #endif /* ! CONFIG_PM_SLEEP */
1408 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1410 struct uart_port *port = dev_get_drvdata(dev);
1411 struct cdns_uart *cdns_uart = port->private_data;
1413 clk_disable(cdns_uart->uartclk);
1414 clk_disable(cdns_uart->pclk);
1418 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1420 struct uart_port *port = dev_get_drvdata(dev);
1421 struct cdns_uart *cdns_uart = port->private_data;
1424 ret = clk_enable(cdns_uart->pclk);
1428 ret = clk_enable(cdns_uart->uartclk);
1430 clk_disable(cdns_uart->pclk);
1436 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1437 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1438 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1439 cdns_runtime_resume, NULL)
1442 static const struct cdns_platform_data zynqmp_uart_def = {
1443 .quirks = CDNS_UART_RXBS_SUPPORT, };
1445 /* Match table for of_platform binding */
1446 static const struct of_device_id cdns_uart_of_match[] = {
1447 { .compatible = "xlnx,xuartps", },
1448 { .compatible = "cdns,uart-r1p8", },
1449 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1450 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1453 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1455 /* Temporary variable for storing number of instances */
1456 static int instances;
1459 * cdns_uart_probe - Platform driver probe
1460 * @pdev: Pointer to the platform device structure
1462 * Return: 0 on success, negative errno otherwise
1464 static int cdns_uart_probe(struct platform_device *pdev)
1467 struct uart_port *port;
1468 struct resource *res;
1469 struct cdns_uart *cdns_uart_data;
1470 const struct of_device_id *match;
1472 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1474 if (!cdns_uart_data)
1476 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1480 /* Look for a serialN alias */
1481 id = of_alias_get_id(pdev->dev.of_node, "serial");
1485 if (id >= CDNS_UART_NR_PORTS) {
1486 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1490 if (!cdns_uart_uart_driver.state) {
1491 cdns_uart_uart_driver.owner = THIS_MODULE;
1492 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME;
1493 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME;
1494 cdns_uart_uart_driver.major = CDNS_UART_MAJOR;
1495 cdns_uart_uart_driver.minor = CDNS_UART_MINOR;
1496 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;
1497 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1498 cdns_uart_uart_driver.cons = &cdns_uart_console;
1501 rc = uart_register_driver(&cdns_uart_uart_driver);
1503 dev_err(&pdev->dev, "Failed to register driver\n");
1508 cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver;
1510 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1511 if (match && match->data) {
1512 const struct cdns_platform_data *data = match->data;
1514 cdns_uart_data->quirks = data->quirks;
1517 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1518 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1519 rc = PTR_ERR(cdns_uart_data->pclk);
1520 goto err_out_unregister_driver;
1523 if (IS_ERR(cdns_uart_data->pclk)) {
1524 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1525 if (IS_ERR(cdns_uart_data->pclk)) {
1526 rc = PTR_ERR(cdns_uart_data->pclk);
1527 goto err_out_unregister_driver;
1529 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1532 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1533 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1534 rc = PTR_ERR(cdns_uart_data->uartclk);
1535 goto err_out_unregister_driver;
1538 if (IS_ERR(cdns_uart_data->uartclk)) {
1539 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1540 if (IS_ERR(cdns_uart_data->uartclk)) {
1541 rc = PTR_ERR(cdns_uart_data->uartclk);
1542 goto err_out_unregister_driver;
1544 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1547 rc = clk_prepare_enable(cdns_uart_data->pclk);
1549 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1550 goto err_out_unregister_driver;
1552 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1554 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1555 goto err_out_clk_dis_pclk;
1558 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1561 goto err_out_clk_disable;
1564 irq = platform_get_irq(pdev, 0);
1567 goto err_out_clk_disable;
1570 #ifdef CONFIG_COMMON_CLK
1571 cdns_uart_data->clk_rate_change_nb.notifier_call =
1572 cdns_uart_clk_notifier_cb;
1573 if (clk_notifier_register(cdns_uart_data->uartclk,
1574 &cdns_uart_data->clk_rate_change_nb))
1575 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1578 /* At this point, we've got an empty uart_port struct, initialize it */
1579 spin_lock_init(&port->lock);
1580 port->type = PORT_UNKNOWN;
1581 port->iotype = UPIO_MEM32;
1582 port->flags = UPF_BOOT_AUTOCONF;
1583 port->ops = &cdns_uart_ops;
1584 port->fifosize = CDNS_UART_FIFO_SIZE;
1585 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);
1589 * Register the port.
1590 * This function also registers this device with the tty layer
1591 * and triggers invocation of the config_port() entry point.
1593 port->mapbase = res->start;
1595 port->dev = &pdev->dev;
1596 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1597 port->private_data = cdns_uart_data;
1598 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
1599 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
1600 cdns_uart_data->port = port;
1601 platform_set_drvdata(pdev, port);
1603 pm_runtime_use_autosuspend(&pdev->dev);
1604 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1605 pm_runtime_set_active(&pdev->dev);
1606 pm_runtime_enable(&pdev->dev);
1607 device_init_wakeup(port->dev, true);
1609 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1611 * If console hasn't been found yet try to assign this port
1612 * because it is required to be assigned for console setup function.
1613 * If register_console() don't assign value, then console_port pointer
1616 if (!console_port) {
1617 cdns_uart_console.index = id;
1618 console_port = port;
1622 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1625 "uart_add_one_port() failed; err=%i\n", rc);
1626 goto err_out_pm_disable;
1629 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1630 /* This is not port which is used for console that's why clean it up */
1631 if (console_port == port &&
1632 !console_is_registered(cdns_uart_uart_driver.cons)) {
1633 console_port = NULL;
1634 cdns_uart_console.index = -1;
1638 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1646 pm_runtime_disable(&pdev->dev);
1647 pm_runtime_set_suspended(&pdev->dev);
1648 pm_runtime_dont_use_autosuspend(&pdev->dev);
1649 #ifdef CONFIG_COMMON_CLK
1650 clk_notifier_unregister(cdns_uart_data->uartclk,
1651 &cdns_uart_data->clk_rate_change_nb);
1653 err_out_clk_disable:
1654 clk_disable_unprepare(cdns_uart_data->uartclk);
1655 err_out_clk_dis_pclk:
1656 clk_disable_unprepare(cdns_uart_data->pclk);
1657 err_out_unregister_driver:
1659 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1664 * cdns_uart_remove - called when the platform driver is unregistered
1665 * @pdev: Pointer to the platform device structure
1667 * Return: 0 on success, negative errno otherwise
1669 static int cdns_uart_remove(struct platform_device *pdev)
1671 struct uart_port *port = platform_get_drvdata(pdev);
1672 struct cdns_uart *cdns_uart_data = port->private_data;
1674 /* Remove the cdns_uart port from the serial core */
1675 #ifdef CONFIG_COMMON_CLK
1676 clk_notifier_unregister(cdns_uart_data->uartclk,
1677 &cdns_uart_data->clk_rate_change_nb);
1679 uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1681 clk_disable_unprepare(cdns_uart_data->uartclk);
1682 clk_disable_unprepare(cdns_uart_data->pclk);
1683 pm_runtime_disable(&pdev->dev);
1684 pm_runtime_set_suspended(&pdev->dev);
1685 pm_runtime_dont_use_autosuspend(&pdev->dev);
1686 device_init_wakeup(&pdev->dev, false);
1688 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1689 if (console_port == port)
1690 console_port = NULL;
1694 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1698 static struct platform_driver cdns_uart_platform_driver = {
1699 .probe = cdns_uart_probe,
1700 .remove = cdns_uart_remove,
1702 .name = CDNS_UART_NAME,
1703 .of_match_table = cdns_uart_of_match,
1704 .pm = &cdns_uart_dev_pm_ops,
1705 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1709 static int __init cdns_uart_init(void)
1711 /* Register the platform driver */
1712 return platform_driver_register(&cdns_uart_platform_driver);
1715 static void __exit cdns_uart_exit(void)
1717 /* Unregister the platform driver */
1718 platform_driver_unregister(&cdns_uart_platform_driver);
1721 arch_initcall(cdns_uart_init);
1722 module_exit(cdns_uart_exit);
1724 MODULE_DESCRIPTION("Driver for Cadence UART");
1725 MODULE_AUTHOR("Xilinx Inc.");
1726 MODULE_LICENSE("GPL");