drivers/tty/serial/uartlite.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * uartlite.c: Serial driver for Xilinx uartlite serial controller
   4  *
   5  * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
   6  * Copyright (C) 2007 Secret Lab Technologies Ltd.
   7  */
   8
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/bitfield.h>
  12 #include <linux/console.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_core.h>
  15 #include <linux/tty.h>
  16 #include <linux/tty_flip.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/of.h>
  23 #include <linux/clk.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #define ULITE_NAME              "ttyUL"
  27 #define ULITE_MAJOR             204
  28 #define ULITE_MINOR             187
  29 #define ULITE_NR_UARTS          CONFIG_SERIAL_UARTLITE_NR_UARTS
  30
  31 /* ---------------------------------------------------------------------
  32  * Register definitions
  33  *
  34  * For register details see datasheet:
  35  * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
  36  */
  37
  38 #define ULITE_RX                0x00
  39 #define ULITE_TX                0x04
  40 #define ULITE_STATUS            0x08
  41 #define ULITE_CONTROL           0x0c
  42
  43 #define ULITE_REGION            16
  44
  45 #define ULITE_STATUS_RXVALID    0x01
  46 #define ULITE_STATUS_RXFULL     0x02
  47 #define ULITE_STATUS_TXEMPTY    0x04
  48 #define ULITE_STATUS_TXFULL     0x08
  49 #define ULITE_STATUS_IE         0x10
  50 #define ULITE_STATUS_OVERRUN    0x20
  51 #define ULITE_STATUS_FRAME      0x40
  52 #define ULITE_STATUS_PARITY     0x80
  53
  54 #define ULITE_CONTROL_RST_TX    0x01
  55 #define ULITE_CONTROL_RST_RX    0x02
  56 #define ULITE_CONTROL_IE        0x10
  57 #define UART_AUTOSUSPEND_TIMEOUT        3000    /* ms */
  58
  59 /* Static pointer to console port */
  60 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
  61 static struct uart_port *console_port;
  62 #endif
  63
  64 /**
  65  * struct uartlite_data: Driver private data
  66  * reg_ops: Functions to read/write registers
  67  * clk: Our parent clock, if present
  68  * baud: The baud rate configured when this device was synthesized
  69  * cflags: The cflags for parity and data bits
  70  */
  71 struct uartlite_data {
  72         const struct uartlite_reg_ops *reg_ops;
  73         struct clk *clk;
  74         unsigned int baud;
  75         tcflag_t cflags;
  76 };
  77
  78 struct uartlite_reg_ops {
  79         u32 (*in)(void __iomem *addr);
  80         void (*out)(u32 val, void __iomem *addr);
  81 };
  82
  83 static u32 uartlite_inbe32(void __iomem *addr)
  84 {
  85         return ioread32be(addr);
  86 }
  87
  88 static void uartlite_outbe32(u32 val, void __iomem *addr)
  89 {
  90         iowrite32be(val, addr);
  91 }
  92
  93 static const struct uartlite_reg_ops uartlite_be = {
  94         .in = uartlite_inbe32,
  95         .out = uartlite_outbe32,
  96 };
  97
  98 static u32 uartlite_inle32(void __iomem *addr)
  99 {
 100         return ioread32(addr);
 101 }
 102
 103 static void uartlite_outle32(u32 val, void __iomem *addr)
 104 {
 105         iowrite32(val, addr);
 106 }
 107
 108 static const struct uartlite_reg_ops uartlite_le = {
 109         .in = uartlite_inle32,
 110         .out = uartlite_outle32,
 111 };
 112
 113 static inline u32 uart_in32(u32 offset, struct uart_port *port)
 114 {
 115         struct uartlite_data *pdata = port->private_data;
 116
 117         return pdata->reg_ops->in(port->membase + offset);
 118 }
 119
 120 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
 121 {
 122         struct uartlite_data *pdata = port->private_data;
 123
 124         pdata->reg_ops->out(val, port->membase + offset);
 125 }
 126
 127 static struct uart_port ulite_ports[ULITE_NR_UARTS];
 128
 129 static struct uart_driver ulite_uart_driver;
 130
 131 /* ---------------------------------------------------------------------
 132  * Core UART driver operations
 133  */
 134
 135 static int ulite_receive(struct uart_port *port, int stat)
 136 {
 137         struct tty_port *tport = &port->state->port;
 138         unsigned char ch = 0;
 139         char flag = TTY_NORMAL;
 140
 141         if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
 142                      | ULITE_STATUS_FRAME)) == 0)
 143                 return 0;
 144
 145         /* stats */
 146         if (stat & ULITE_STATUS_RXVALID) {
 147                 port->icount.rx++;
 148                 ch = uart_in32(ULITE_RX, port);
 149
 150                 if (stat & ULITE_STATUS_PARITY)
 151                         port->icount.parity++;
 152         }
 153
 154         if (stat & ULITE_STATUS_OVERRUN)
 155                 port->icount.overrun++;
 156
 157         if (stat & ULITE_STATUS_FRAME)
 158                 port->icount.frame++;
 159
 160
 161         /* drop byte with parity error if IGNPAR specificed */
 162         if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
 163                 stat &= ~ULITE_STATUS_RXVALID;
 164
 165         stat &= port->read_status_mask;
 166
 167         if (stat & ULITE_STATUS_PARITY)
 168                 flag = TTY_PARITY;
 169
 170
 171         stat &= ~port->ignore_status_mask;
 172
 173         if (stat & ULITE_STATUS_RXVALID)
 174                 tty_insert_flip_char(tport, ch, flag);
 175
 176         if (stat & ULITE_STATUS_FRAME)
 177                 tty_insert_flip_char(tport, 0, TTY_FRAME);
 178
 179         if (stat & ULITE_STATUS_OVERRUN)
 180                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 181
 182         return 1;
 183 }
 184
 185 static int ulite_transmit(struct uart_port *port, int stat)
 186 {
 187         struct circ_buf *xmit  = &port->state->xmit;
 188
 189         if (stat & ULITE_STATUS_TXFULL)
 190                 return 0;
 191
 192         if (port->x_char) {
 193                 uart_out32(port->x_char, ULITE_TX, port);
 194                 port->x_char = 0;
 195                 port->icount.tx++;
 196                 return 1;
 197         }
 198
 199         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 200                 return 0;
 201
 202         uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
 203         uart_xmit_advance(port, 1);
 204
 205         /* wake up */
 206         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 207                 uart_write_wakeup(port);
 208
 209         return 1;
 210 }
 211
 212 static irqreturn_t ulite_isr(int irq, void *dev_id)
 213 {
 214         struct uart_port *port = dev_id;
 215         int stat, busy, n = 0;
 216         unsigned long flags;
 217
 218         do {
 219                 spin_lock_irqsave(&port->lock, flags);
 220                 stat = uart_in32(ULITE_STATUS, port);
 221                 busy  = ulite_receive(port, stat);
 222                 busy |= ulite_transmit(port, stat);
 223                 spin_unlock_irqrestore(&port->lock, flags);
 224                 n++;
 225         } while (busy);
 226
 227         /* work done? */
 228         if (n > 1) {
 229                 tty_flip_buffer_push(&port->state->port);
 230                 return IRQ_HANDLED;
 231         } else {
 232                 return IRQ_NONE;
 233         }
 234 }
 235
 236 static unsigned int ulite_tx_empty(struct uart_port *port)
 237 {
 238         unsigned long flags;
 239         unsigned int ret;
 240
 241         spin_lock_irqsave(&port->lock, flags);
 242         ret = uart_in32(ULITE_STATUS, port);
 243         spin_unlock_irqrestore(&port->lock, flags);
 244
 245         return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
 246 }
 247
 248 static unsigned int ulite_get_mctrl(struct uart_port *port)
 249 {
 250         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
 251 }
 252
 253 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
 254 {
 255         /* N/A */
 256 }
 257
 258 static void ulite_stop_tx(struct uart_port *port)
 259 {
 260         /* N/A */
 261 }
 262
 263 static void ulite_start_tx(struct uart_port *port)
 264 {
 265         ulite_transmit(port, uart_in32(ULITE_STATUS, port));
 266 }
 267
 268 static void ulite_stop_rx(struct uart_port *port)
 269 {
 270         /* don't forward any more data (like !CREAD) */
 271         port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
 272                 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
 273 }
 274
 275 static void ulite_break_ctl(struct uart_port *port, int ctl)
 276 {
 277         /* N/A */
 278 }
 279
 280 static int ulite_startup(struct uart_port *port)
 281 {
 282         struct uartlite_data *pdata = port->private_data;
 283         int ret;
 284
 285         ret = clk_enable(pdata->clk);
 286         if (ret) {
 287                 dev_err(port->dev, "Failed to enable clock\n");
 288                 return ret;
 289         }
 290
 291         ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING,
 292                           "uartlite", port);
 293         if (ret)
 294                 return ret;
 295
 296         uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
 297                 ULITE_CONTROL, port);
 298         uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
 299
 300         return 0;
 301 }
 302
 303 static void ulite_shutdown(struct uart_port *port)
 304 {
 305         struct uartlite_data *pdata = port->private_data;
 306
 307         uart_out32(0, ULITE_CONTROL, port);
 308         uart_in32(ULITE_CONTROL, port); /* dummy */
 309         free_irq(port->irq, port);
 310         clk_disable(pdata->clk);
 311 }
 312
 313 static void ulite_set_termios(struct uart_port *port,
 314                               struct ktermios *termios,
 315                               const struct ktermios *old)
 316 {
 317         unsigned long flags;
 318         struct uartlite_data *pdata = port->private_data;
 319
 320         /* Set termios to what the hardware supports */
 321         termios->c_iflag &= ~BRKINT;
 322         termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CSIZE);
 323         termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE);
 324         tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud);
 325
 326         spin_lock_irqsave(&port->lock, flags);
 327
 328         port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
 329                 | ULITE_STATUS_TXFULL;
 330
 331         if (termios->c_iflag & INPCK)
 332                 port->read_status_mask |=
 333                         ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
 334
 335         port->ignore_status_mask = 0;
 336         if (termios->c_iflag & IGNPAR)
 337                 port->ignore_status_mask |= ULITE_STATUS_PARITY
 338                         | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
 339
 340         /* ignore all characters if CREAD is not set */
 341         if ((termios->c_cflag & CREAD) == 0)
 342                 port->ignore_status_mask |=
 343                         ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
 344                         | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
 345
 346         /* update timeout */
 347         uart_update_timeout(port, termios->c_cflag, pdata->baud);
 348
 349         spin_unlock_irqrestore(&port->lock, flags);
 350 }
 351
 352 static const char *ulite_type(struct uart_port *port)
 353 {
 354         return port->type == PORT_UARTLITE ? "uartlite" : NULL;
 355 }
 356
 357 static void ulite_release_port(struct uart_port *port)
 358 {
 359         release_mem_region(port->mapbase, ULITE_REGION);
 360         iounmap(port->membase);
 361         port->membase = NULL;
 362 }
 363
 364 static int ulite_request_port(struct uart_port *port)
 365 {
 366         struct uartlite_data *pdata = port->private_data;
 367         int ret;
 368
 369         pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
 370                  port, (unsigned long long) port->mapbase);
 371
 372         if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
 373                 dev_err(port->dev, "Memory region busy\n");
 374                 return -EBUSY;
 375         }
 376
 377         port->membase = ioremap(port->mapbase, ULITE_REGION);
 378         if (!port->membase) {
 379                 dev_err(port->dev, "Unable to map registers\n");
 380                 release_mem_region(port->mapbase, ULITE_REGION);
 381                 return -EBUSY;
 382         }
 383
 384         pdata->reg_ops = &uartlite_be;
 385         ret = uart_in32(ULITE_CONTROL, port);
 386         uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
 387         ret = uart_in32(ULITE_STATUS, port);
 388         /* Endianess detection */
 389         if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
 390                 pdata->reg_ops = &uartlite_le;
 391
 392         return 0;
 393 }
 394
 395 static void ulite_config_port(struct uart_port *port, int flags)
 396 {
 397         if (!ulite_request_port(port))
 398                 port->type = PORT_UARTLITE;
 399 }
 400
 401 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
 402 {
 403         /* we don't want the core code to modify any port params */
 404         return -EINVAL;
 405 }
 406
 407 static void ulite_pm(struct uart_port *port, unsigned int state,
 408                      unsigned int oldstate)
 409 {
 410         int ret;
 411
 412         if (!state) {
 413                 ret = pm_runtime_get_sync(port->dev);
 414                 if (ret < 0)
 415                         dev_err(port->dev, "Failed to enable clocks\n");
 416         } else {
 417                 pm_runtime_mark_last_busy(port->dev);
 418                 pm_runtime_put_autosuspend(port->dev);
 419         }
 420 }
 421
 422 #ifdef CONFIG_CONSOLE_POLL
 423 static int ulite_get_poll_char(struct uart_port *port)
 424 {
 425         if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
 426                 return NO_POLL_CHAR;
 427
 428         return uart_in32(ULITE_RX, port);
 429 }
 430
 431 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
 432 {
 433         while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
 434                 cpu_relax();
 435
 436         /* write char to device */
 437         uart_out32(ch, ULITE_TX, port);
 438 }
 439 #endif
 440
 441 static const struct uart_ops ulite_ops = {
 442         .tx_empty       = ulite_tx_empty,
 443         .set_mctrl      = ulite_set_mctrl,
 444         .get_mctrl      = ulite_get_mctrl,
 445         .stop_tx        = ulite_stop_tx,
 446         .start_tx       = ulite_start_tx,
 447         .stop_rx        = ulite_stop_rx,
 448         .break_ctl      = ulite_break_ctl,
 449         .startup        = ulite_startup,
 450         .shutdown       = ulite_shutdown,
 451         .set_termios    = ulite_set_termios,
 452         .type           = ulite_type,
 453         .release_port   = ulite_release_port,
 454         .request_port   = ulite_request_port,
 455         .config_port    = ulite_config_port,
 456         .verify_port    = ulite_verify_port,
 457         .pm             = ulite_pm,
 458 #ifdef CONFIG_CONSOLE_POLL
 459         .poll_get_char  = ulite_get_poll_char,
 460         .poll_put_char  = ulite_put_poll_char,
 461 #endif
 462 };
 463
 464 /* ---------------------------------------------------------------------
 465  * Console driver operations
 466  */
 467
 468 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
 469 static void ulite_console_wait_tx(struct uart_port *port)
 470 {
 471         u8 val;
 472
 473         /*
 474          * Spin waiting for TX fifo to have space available.
 475          * When using the Microblaze Debug Module this can take up to 1s
 476          */
 477         if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL),
 478                                      0, 1000000, false, ULITE_STATUS, port))
 479                 dev_warn(port->dev,
 480                          "timeout waiting for TX buffer empty\n");
 481 }
 482
 483 static void ulite_console_putchar(struct uart_port *port, unsigned char ch)
 484 {
 485         ulite_console_wait_tx(port);
 486         uart_out32(ch, ULITE_TX, port);
 487 }
 488
 489 static void ulite_console_write(struct console *co, const char *s,
 490                                 unsigned int count)
 491 {
 492         struct uart_port *port = console_port;
 493         unsigned long flags;
 494         unsigned int ier;
 495         int locked = 1;
 496
 497         if (oops_in_progress) {
 498                 locked = spin_trylock_irqsave(&port->lock, flags);
 499         } else
 500                 spin_lock_irqsave(&port->lock, flags);
 501
 502         /* save and disable interrupt */
 503         ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
 504         uart_out32(0, ULITE_CONTROL, port);
 505
 506         uart_console_write(port, s, count, ulite_console_putchar);
 507
 508         ulite_console_wait_tx(port);
 509
 510         /* restore interrupt state */
 511         if (ier)
 512                 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
 513
 514         if (locked)
 515                 spin_unlock_irqrestore(&port->lock, flags);
 516 }
 517
 518 static int ulite_console_setup(struct console *co, char *options)
 519 {
 520         struct uart_port *port = NULL;
 521         int baud = 9600;
 522         int bits = 8;
 523         int parity = 'n';
 524         int flow = 'n';
 525
 526         if (co->index >= 0 && co->index < ULITE_NR_UARTS)
 527                 port = ulite_ports + co->index;
 528
 529         /* Has the device been initialized yet? */
 530         if (!port || !port->mapbase) {
 531                 pr_debug("console on ttyUL%i not present\n", co->index);
 532                 return -ENODEV;
 533         }
 534
 535         console_port = port;
 536
 537         /* not initialized yet? */
 538         if (!port->membase) {
 539                 if (ulite_request_port(port))
 540                         return -ENODEV;
 541         }
 542
 543         if (options)
 544                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 545
 546         return uart_set_options(port, co, baud, parity, bits, flow);
 547 }
 548
 549 static struct console ulite_console = {
 550         .name   = ULITE_NAME,
 551         .write  = ulite_console_write,
 552         .device = uart_console_device,
 553         .setup  = ulite_console_setup,
 554         .flags  = CON_PRINTBUFFER,
 555         .index  = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
 556         .data   = &ulite_uart_driver,
 557 };
 558
 559 static void early_uartlite_putc(struct uart_port *port, unsigned char c)
 560 {
 561         /*
 562          * Limit how many times we'll spin waiting for TX FIFO status.
 563          * This will prevent lockups if the base address is incorrectly
 564          * set, or any other issue on the UARTLITE.
 565          * This limit is pretty arbitrary, unless we are at about 10 baud
 566          * we'll never timeout on a working UART.
 567          */
 568         unsigned retries = 1000000;
 569
 570         while (--retries &&
 571                (readl(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL))
 572                 ;
 573
 574         /* Only attempt the iowrite if we didn't timeout */
 575         if (retries)
 576                 writel(c & 0xff, port->membase + ULITE_TX);
 577 }
 578
 579 static void early_uartlite_write(struct console *console,
 580                                  const char *s, unsigned n)
 581 {
 582         struct earlycon_device *device = console->data;
 583         uart_console_write(&device->port, s, n, early_uartlite_putc);
 584 }
 585
 586 static int __init early_uartlite_setup(struct earlycon_device *device,
 587                                        const char *options)
 588 {
 589         if (!device->port.membase)
 590                 return -ENODEV;
 591
 592         device->con->write = early_uartlite_write;
 593         return 0;
 594 }
 595 EARLYCON_DECLARE(uartlite, early_uartlite_setup);
 596 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
 597 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
 598
 599 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
 600
 601 static struct uart_driver ulite_uart_driver = {
 602         .owner          = THIS_MODULE,
 603         .driver_name    = "uartlite",
 604         .dev_name       = ULITE_NAME,
 605         .major          = ULITE_MAJOR,
 606         .minor          = ULITE_MINOR,
 607         .nr             = ULITE_NR_UARTS,
 608 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
 609         .cons           = &ulite_console,
 610 #endif
 611 };
 612
 613 /* ---------------------------------------------------------------------
 614  * Port assignment functions (mapping devices to uart_port structures)
 615  */
 616
 617 /** ulite_assign: register a uartlite device with the driver
 618  *
 619  * @dev: pointer to device structure
 620  * @id: requested id number.  Pass -1 for automatic port assignment
 621  * @base: base address of uartlite registers
 622  * @irq: irq number for uartlite
 623  * @pdata: private data for uartlite
 624  *
 625  * Returns: 0 on success, <0 otherwise
 626  */
 627 static int ulite_assign(struct device *dev, int id, phys_addr_t base, int irq,
 628                         struct uartlite_data *pdata)
 629 {
 630         struct uart_port *port;
 631         int rc;
 632
 633         /* if id = -1; then scan for a free id and use that */
 634         if (id < 0) {
 635                 for (id = 0; id < ULITE_NR_UARTS; id++)
 636                         if (ulite_ports[id].mapbase == 0)
 637                                 break;
 638         }
 639         if (id < 0 || id >= ULITE_NR_UARTS) {
 640                 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
 641                 return -EINVAL;
 642         }
 643
 644         if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
 645                 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
 646                         ULITE_NAME, id);
 647                 return -EBUSY;
 648         }
 649
 650         port = &ulite_ports[id];
 651
 652         spin_lock_init(&port->lock);
 653         port->fifosize = 16;
 654         port->regshift = 2;
 655         port->iotype = UPIO_MEM;
 656         port->iobase = 1; /* mark port in use */
 657         port->mapbase = base;
 658         port->membase = NULL;
 659         port->ops = &ulite_ops;
 660         port->irq = irq;
 661         port->flags = UPF_BOOT_AUTOCONF;
 662         port->dev = dev;
 663         port->type = PORT_UNKNOWN;
 664         port->line = id;
 665         port->private_data = pdata;
 666
 667         dev_set_drvdata(dev, port);
 668
 669         /* Register the port */
 670         rc = uart_add_one_port(&ulite_uart_driver, port);
 671         if (rc) {
 672                 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
 673                 port->mapbase = 0;
 674                 dev_set_drvdata(dev, NULL);
 675                 return rc;
 676         }
 677
 678         return 0;
 679 }
 680
 681 /** ulite_release: register a uartlite device with the driver
 682  *
 683  * @dev: pointer to device structure
 684  */
 685 static void ulite_release(struct device *dev)
 686 {
 687         struct uart_port *port = dev_get_drvdata(dev);
 688
 689         if (port) {
 690                 uart_remove_one_port(&ulite_uart_driver, port);
 691                 dev_set_drvdata(dev, NULL);
 692                 port->mapbase = 0;
 693         }
 694 }
 695
 696 /**
 697  * ulite_suspend - Stop the device.
 698  *
 699  * @dev: handle to the device structure.
 700  * Return: 0 always.
 701  */
 702 static int __maybe_unused ulite_suspend(struct device *dev)
 703 {
 704         struct uart_port *port = dev_get_drvdata(dev);
 705
 706         if (port)
 707                 uart_suspend_port(&ulite_uart_driver, port);
 708
 709         return 0;
 710 }
 711
 712 /**
 713  * ulite_resume - Resume the device.
 714  *
 715  * @dev: handle to the device structure.
 716  * Return: 0 on success, errno otherwise.
 717  */
 718 static int __maybe_unused ulite_resume(struct device *dev)
 719 {
 720         struct uart_port *port = dev_get_drvdata(dev);
 721
 722         if (port)
 723                 uart_resume_port(&ulite_uart_driver, port);
 724
 725         return 0;
 726 }
 727
 728 static int __maybe_unused ulite_runtime_suspend(struct device *dev)
 729 {
 730         struct uart_port *port = dev_get_drvdata(dev);
 731         struct uartlite_data *pdata = port->private_data;
 732
 733         clk_disable(pdata->clk);
 734         return 0;
 735 };
 736
 737 static int __maybe_unused ulite_runtime_resume(struct device *dev)
 738 {
 739         struct uart_port *port = dev_get_drvdata(dev);
 740         struct uartlite_data *pdata = port->private_data;
 741         int ret;
 742
 743         ret = clk_enable(pdata->clk);
 744         if (ret) {
 745                 dev_err(dev, "Cannot enable clock.\n");
 746                 return ret;
 747         }
 748         return 0;
 749 }
 750
 751 /* ---------------------------------------------------------------------
 752  * Platform bus binding
 753  */
 754
 755 static const struct dev_pm_ops ulite_pm_ops = {
 756         SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume)
 757         SET_RUNTIME_PM_OPS(ulite_runtime_suspend,
 758                            ulite_runtime_resume, NULL)
 759 };
 760
 761 #if defined(CONFIG_OF)
 762 /* Match table for of_platform binding */
 763 static const struct of_device_id ulite_of_match[] = {
 764         { .compatible = "xlnx,opb-uartlite-1.00.b", },
 765         { .compatible = "xlnx,xps-uartlite-1.00.a", },
 766         {}
 767 };
 768 MODULE_DEVICE_TABLE(of, ulite_of_match);
 769 #endif /* CONFIG_OF */
 770
 771 static int ulite_probe(struct platform_device *pdev)
 772 {
 773         struct resource *res;
 774         struct uartlite_data *pdata;
 775         int irq, ret;
 776         int id = pdev->id;
 777
 778         pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data),
 779                              GFP_KERNEL);
 780         if (!pdata)
 781                 return -ENOMEM;
 782
 783         if (IS_ENABLED(CONFIG_OF)) {
 784                 const char *prop;
 785                 struct device_node *np = pdev->dev.of_node;
 786                 u32 val = 0;
 787
 788                 prop = "port-number";
 789                 ret = of_property_read_u32(np, prop, &id);
 790                 if (ret && ret != -EINVAL)
 791 of_err:
 792                         return dev_err_probe(&pdev->dev, ret,
 793                                              "could not read %s\n", prop);
 794
 795                 prop = "current-speed";
 796                 ret = of_property_read_u32(np, prop, &pdata->baud);
 797                 if (ret)
 798                         goto of_err;
 799
 800                 prop = "xlnx,use-parity";
 801                 ret = of_property_read_u32(np, prop, &val);
 802                 if (ret && ret != -EINVAL)
 803                         goto of_err;
 804
 805                 if (val) {
 806                         prop = "xlnx,odd-parity";
 807                         ret = of_property_read_u32(np, prop, &val);
 808                         if (ret)
 809                                 goto of_err;
 810
 811                         if (val)
 812                                 pdata->cflags |= PARODD;
 813                         pdata->cflags |= PARENB;
 814                 }
 815
 816                 val = 8;
 817                 prop = "xlnx,data-bits";
 818                 ret = of_property_read_u32(np, prop, &val);
 819                 if (ret && ret != -EINVAL)
 820                         goto of_err;
 821
 822                 switch (val) {
 823                 case 5:
 824                         pdata->cflags |= CS5;
 825                         break;
 826                 case 6:
 827                         pdata->cflags |= CS6;
 828                         break;
 829                 case 7:
 830                         pdata->cflags |= CS7;
 831                         break;
 832                 case 8:
 833                         pdata->cflags |= CS8;
 834                         break;
 835                 default:
 836                         return dev_err_probe(&pdev->dev, -EINVAL,
 837                                              "bad data bits %d\n", val);
 838                 }
 839         } else {
 840                 pdata->baud = 9600;
 841                 pdata->cflags = CS8;
 842         }
 843
 844         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 845         if (!res)
 846                 return -ENODEV;
 847
 848         irq = platform_get_irq(pdev, 0);
 849         if (irq < 0)
 850                 return irq;
 851
 852         pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
 853         if (IS_ERR(pdata->clk)) {
 854                 if (PTR_ERR(pdata->clk) != -ENOENT)
 855                         return PTR_ERR(pdata->clk);
 856
 857                 /*
 858                  * Clock framework support is optional, continue on
 859                  * anyways if we don't find a matching clock.
 860                  */
 861                 pdata->clk = NULL;
 862         }
 863
 864         ret = clk_prepare_enable(pdata->clk);
 865         if (ret) {
 866                 dev_err(&pdev->dev, "Failed to prepare clock\n");
 867                 return ret;
 868         }
 869
 870         pm_runtime_use_autosuspend(&pdev->dev);
 871         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
 872         pm_runtime_set_active(&pdev->dev);
 873         pm_runtime_enable(&pdev->dev);
 874
 875         if (!ulite_uart_driver.state) {
 876                 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n");
 877                 ret = uart_register_driver(&ulite_uart_driver);
 878                 if (ret < 0) {
 879                         dev_err(&pdev->dev, "Failed to register driver\n");
 880                         clk_disable_unprepare(pdata->clk);
 881                         return ret;
 882                 }
 883         }
 884
 885         ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);
 886
 887         pm_runtime_mark_last_busy(&pdev->dev);
 888         pm_runtime_put_autosuspend(&pdev->dev);
 889
 890         return ret;
 891 }
 892
 893 static int ulite_remove(struct platform_device *pdev)
 894 {
 895         struct uart_port *port = dev_get_drvdata(&pdev->dev);
 896         struct uartlite_data *pdata = port->private_data;
 897
 898         clk_disable_unprepare(pdata->clk);
 899         ulite_release(&pdev->dev);
 900         pm_runtime_disable(&pdev->dev);
 901         pm_runtime_set_suspended(&pdev->dev);
 902         pm_runtime_dont_use_autosuspend(&pdev->dev);
 903         return 0;
 904 }
 905
 906 /* work with hotplug and coldplug */
 907 MODULE_ALIAS("platform:uartlite");
 908
 909 static struct platform_driver ulite_platform_driver = {
 910         .probe = ulite_probe,
 911         .remove = ulite_remove,
 912         .driver = {
 913                 .name  = "uartlite",
 914                 .of_match_table = of_match_ptr(ulite_of_match),
 915                 .pm = &ulite_pm_ops,
 916         },
 917 };
 918
 919 /* ---------------------------------------------------------------------
 920  * Module setup/teardown
 921  */
 922
 923 static int __init ulite_init(void)
 924 {
 925
 926         pr_debug("uartlite: calling platform_driver_register()\n");
 927         return platform_driver_register(&ulite_platform_driver);
 928 }
 929
 930 static void __exit ulite_exit(void)
 931 {
 932         platform_driver_unregister(&ulite_platform_driver);
 933         if (ulite_uart_driver.state)
 934                 uart_unregister_driver(&ulite_uart_driver);
 935 }
 936
 937 module_init(ulite_init);
 938 module_exit(ulite_exit);
 939
 940 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
 941 MODULE_DESCRIPTION("Xilinx uartlite serial driver");
 942 MODULE_LICENSE("GPL");