drivers/tty/serial/stm32-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6  *           Gerald Baeza <gerald.baeza@st.com>
   7  *
   8  * Inspired by st-asc.c from STMicroelectronics (c)
   9  */
  10
  11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14
  15 #include <linux/clk.h>
  16 #include <linux/console.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-direction.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/irq.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pm_wakeirq.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/serial.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/sysrq.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/tty.h>
  36
  37 #include "stm32-usart.h"
  38
  39 static void stm32_stop_tx(struct uart_port *port);
  40 static void stm32_transmit_chars(struct uart_port *port);
  41
  42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
  43 {
  44         return container_of(port, struct stm32_port, port);
  45 }
  46
  47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
  48 {
  49         u32 val;
  50
  51         val = readl_relaxed(port->membase + reg);
  52         val |= bits;
  53         writel_relaxed(val, port->membase + reg);
  54 }
  55
  56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
  57 {
  58         u32 val;
  59
  60         val = readl_relaxed(port->membase + reg);
  61         val &= ~bits;
  62         writel_relaxed(val, port->membase + reg);
  63 }
  64
  65 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
  66                                    u32 delay_DDE, u32 baud)
  67 {
  68         u32 rs485_deat_dedt;
  69         u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
  70         bool over8;
  71
  72         *cr3 |= USART_CR3_DEM;
  73         over8 = *cr1 & USART_CR1_OVER8;
  74
  75         if (over8)
  76                 rs485_deat_dedt = delay_ADE * baud * 8;
  77         else
  78                 rs485_deat_dedt = delay_ADE * baud * 16;
  79
  80         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  81         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  82                           rs485_deat_dedt_max : rs485_deat_dedt;
  83         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
  84                            USART_CR1_DEAT_MASK;
  85         *cr1 |= rs485_deat_dedt;
  86
  87         if (over8)
  88                 rs485_deat_dedt = delay_DDE * baud * 8;
  89         else
  90                 rs485_deat_dedt = delay_DDE * baud * 16;
  91
  92         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  93         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  94                           rs485_deat_dedt_max : rs485_deat_dedt;
  95         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
  96                            USART_CR1_DEDT_MASK;
  97         *cr1 |= rs485_deat_dedt;
  98 }
  99
 100 static int stm32_config_rs485(struct uart_port *port,
 101                               struct serial_rs485 *rs485conf)
 102 {
 103         struct stm32_port *stm32_port = to_stm32_port(port);
 104         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 105         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 106         u32 usartdiv, baud, cr1, cr3;
 107         bool over8;
 108         unsigned long flags;
 109
 110         spin_lock_irqsave(&port->lock, flags);
 111         stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 112
 113         port->rs485 = *rs485conf;
 114
 115         rs485conf->flags |= SER_RS485_RX_DURING_TX;
 116
 117         if (rs485conf->flags & SER_RS485_ENABLED) {
 118                 cr1 = readl_relaxed(port->membase + ofs->cr1);
 119                 cr3 = readl_relaxed(port->membase + ofs->cr3);
 120                 usartdiv = readl_relaxed(port->membase + ofs->brr);
 121                 usartdiv = usartdiv & GENMASK(15, 0);
 122                 over8 = cr1 & USART_CR1_OVER8;
 123
 124                 if (over8)
 125                         usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
 126                                    << USART_BRR_04_R_SHIFT;
 127
 128                 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
 129                 stm32_config_reg_rs485(&cr1, &cr3,
 130                                        rs485conf->delay_rts_before_send,
 131                                        rs485conf->delay_rts_after_send, baud);
 132
 133                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 134                         cr3 &= ~USART_CR3_DEP;
 135                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 136                 } else {
 137                         cr3 |= USART_CR3_DEP;
 138                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 139                 }
 140
 141                 writel_relaxed(cr3, port->membase + ofs->cr3);
 142                 writel_relaxed(cr1, port->membase + ofs->cr1);
 143         } else {
 144                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
 145                 stm32_clr_bits(port, ofs->cr1,
 146                                USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 147         }
 148
 149         stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 150         spin_unlock_irqrestore(&port->lock, flags);
 151
 152         return 0;
 153 }
 154
 155 static int stm32_init_rs485(struct uart_port *port,
 156                             struct platform_device *pdev)
 157 {
 158         struct serial_rs485 *rs485conf = &port->rs485;
 159
 160         rs485conf->flags = 0;
 161         rs485conf->delay_rts_before_send = 0;
 162         rs485conf->delay_rts_after_send = 0;
 163
 164         if (!pdev->dev.of_node)
 165                 return -ENODEV;
 166
 167         uart_get_rs485_mode(&pdev->dev, rs485conf);
 168
 169         return 0;
 170 }
 171
 172 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
 173                             bool threaded)
 174 {
 175         struct stm32_port *stm32_port = to_stm32_port(port);
 176         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 177         enum dma_status status;
 178         struct dma_tx_state state;
 179
 180         *sr = readl_relaxed(port->membase + ofs->isr);
 181
 182         if (threaded && stm32_port->rx_ch) {
 183                 status = dmaengine_tx_status(stm32_port->rx_ch,
 184                                              stm32_port->rx_ch->cookie,
 185                                              &state);
 186                 if ((status == DMA_IN_PROGRESS) &&
 187                     (*last_res != state.residue))
 188                         return 1;
 189                 else
 190                         return 0;
 191         } else if (*sr & USART_SR_RXNE) {
 192                 return 1;
 193         }
 194         return 0;
 195 }
 196
 197 static unsigned long
 198 stm32_get_char(struct uart_port *port, u32 *sr, int *last_res)
 199 {
 200         struct stm32_port *stm32_port = to_stm32_port(port);
 201         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 202         unsigned long c;
 203
 204         if (stm32_port->rx_ch) {
 205                 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
 206                 if ((*last_res) == 0)
 207                         *last_res = RX_BUF_L;
 208                 return c;
 209         } else {
 210                 return readl_relaxed(port->membase + ofs->rdr);
 211         }
 212 }
 213
 214 static void stm32_receive_chars(struct uart_port *port, bool threaded)
 215 {
 216         struct tty_port *tport = &port->state->port;
 217         struct stm32_port *stm32_port = to_stm32_port(port);
 218         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 219         unsigned long c;
 220         u32 sr;
 221         char flag;
 222
 223         if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 224                 pm_wakeup_event(tport->tty->dev, 0);
 225
 226         while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
 227                 sr |= USART_SR_DUMMY_RX;
 228                 c = stm32_get_char(port, &sr, &stm32_port->last_res);
 229                 flag = TTY_NORMAL;
 230                 port->icount.rx++;
 231
 232                 if (sr & USART_SR_ERR_MASK) {
 233                         if (sr & USART_SR_LBD) {
 234                                 port->icount.brk++;
 235                                 if (uart_handle_break(port))
 236                                         continue;
 237                         } else if (sr & USART_SR_ORE) {
 238                                 if (ofs->icr != UNDEF_REG)
 239                                         writel_relaxed(USART_ICR_ORECF,
 240                                                        port->membase +
 241                                                        ofs->icr);
 242                                 port->icount.overrun++;
 243                         } else if (sr & USART_SR_PE) {
 244                                 port->icount.parity++;
 245                         } else if (sr & USART_SR_FE) {
 246                                 port->icount.frame++;
 247                         }
 248
 249                         sr &= port->read_status_mask;
 250
 251                         if (sr & USART_SR_LBD)
 252                                 flag = TTY_BREAK;
 253                         else if (sr & USART_SR_PE)
 254                                 flag = TTY_PARITY;
 255                         else if (sr & USART_SR_FE)
 256                                 flag = TTY_FRAME;
 257                 }
 258
 259                 if (uart_handle_sysrq_char(port, c))
 260                         continue;
 261                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 262         }
 263
 264         spin_unlock(&port->lock);
 265         tty_flip_buffer_push(tport);
 266         spin_lock(&port->lock);
 267 }
 268
 269 static void stm32_tx_dma_complete(void *arg)
 270 {
 271         struct uart_port *port = arg;
 272         struct stm32_port *stm32port = to_stm32_port(port);
 273         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 274         unsigned int isr;
 275         int ret;
 276
 277         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 278                                                 isr,
 279                                                 (isr & USART_SR_TC),
 280                                                 10, 100000);
 281
 282         if (ret)
 283                 dev_err(port->dev, "terminal count not set\n");
 284
 285         if (ofs->icr == UNDEF_REG)
 286                 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 287         else
 288                 stm32_set_bits(port, ofs->icr, USART_CR_TC);
 289
 290         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 291         stm32port->tx_dma_busy = false;
 292
 293         /* Let's see if we have pending data to send */
 294         stm32_transmit_chars(port);
 295 }
 296
 297 static void stm32_transmit_chars_pio(struct uart_port *port)
 298 {
 299         struct stm32_port *stm32_port = to_stm32_port(port);
 300         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 301         struct circ_buf *xmit = &port->state->xmit;
 302         unsigned int isr;
 303         int ret;
 304
 305         if (stm32_port->tx_dma_busy) {
 306                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 307                 stm32_port->tx_dma_busy = false;
 308         }
 309
 310         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 311                                                 isr,
 312                                                 (isr & USART_SR_TXE),
 313                                                 10, 100000);
 314
 315         if (ret)
 316                 dev_err(port->dev, "tx empty not set\n");
 317
 318         stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 319
 320         writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 321         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 322         port->icount.tx++;
 323 }
 324
 325 static void stm32_transmit_chars_dma(struct uart_port *port)
 326 {
 327         struct stm32_port *stm32port = to_stm32_port(port);
 328         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 329         struct circ_buf *xmit = &port->state->xmit;
 330         struct dma_async_tx_descriptor *desc = NULL;
 331         dma_cookie_t cookie;
 332         unsigned int count, i;
 333
 334         if (stm32port->tx_dma_busy)
 335                 return;
 336
 337         stm32port->tx_dma_busy = true;
 338
 339         count = uart_circ_chars_pending(xmit);
 340
 341         if (count > TX_BUF_L)
 342                 count = TX_BUF_L;
 343
 344         if (xmit->tail < xmit->head) {
 345                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 346         } else {
 347                 size_t one = UART_XMIT_SIZE - xmit->tail;
 348                 size_t two;
 349
 350                 if (one > count)
 351                         one = count;
 352                 two = count - one;
 353
 354                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 355                 if (two)
 356                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 357         }
 358
 359         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 360                                            stm32port->tx_dma_buf,
 361                                            count,
 362                                            DMA_MEM_TO_DEV,
 363                                            DMA_PREP_INTERRUPT);
 364
 365         if (!desc) {
 366                 for (i = count; i > 0; i--)
 367                         stm32_transmit_chars_pio(port);
 368                 return;
 369         }
 370
 371         desc->callback = stm32_tx_dma_complete;
 372         desc->callback_param = port;
 373
 374         /* Push current DMA TX transaction in the pending queue */
 375         cookie = dmaengine_submit(desc);
 376
 377         /* Issue pending DMA TX requests */
 378         dma_async_issue_pending(stm32port->tx_ch);
 379
 380         stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 381         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 382
 383         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 384         port->icount.tx += count;
 385 }
 386
 387 static void stm32_transmit_chars(struct uart_port *port)
 388 {
 389         struct stm32_port *stm32_port = to_stm32_port(port);
 390         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 391         struct circ_buf *xmit = &port->state->xmit;
 392
 393         if (port->x_char) {
 394                 if (stm32_port->tx_dma_busy)
 395                         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 396                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 397                 port->x_char = 0;
 398                 port->icount.tx++;
 399                 if (stm32_port->tx_dma_busy)
 400                         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 401                 return;
 402         }
 403
 404         if (uart_tx_stopped(port)) {
 405                 stm32_stop_tx(port);
 406                 return;
 407         }
 408
 409         if (uart_circ_empty(xmit)) {
 410                 stm32_stop_tx(port);
 411                 return;
 412         }
 413
 414         if (stm32_port->tx_ch)
 415                 stm32_transmit_chars_dma(port);
 416         else
 417                 stm32_transmit_chars_pio(port);
 418
 419         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 420                 uart_write_wakeup(port);
 421
 422         if (uart_circ_empty(xmit))
 423                 stm32_stop_tx(port);
 424 }
 425
 426 static irqreturn_t stm32_interrupt(int irq, void *ptr)
 427 {
 428         struct uart_port *port = ptr;
 429         struct stm32_port *stm32_port = to_stm32_port(port);
 430         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 431         u32 sr;
 432
 433         spin_lock(&port->lock);
 434
 435         sr = readl_relaxed(port->membase + ofs->isr);
 436
 437         if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
 438                 writel_relaxed(USART_ICR_WUCF,
 439                                port->membase + ofs->icr);
 440
 441         if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
 442                 stm32_receive_chars(port, false);
 443
 444         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
 445                 stm32_transmit_chars(port);
 446
 447         spin_unlock(&port->lock);
 448
 449         if (stm32_port->rx_ch)
 450                 return IRQ_WAKE_THREAD;
 451         else
 452                 return IRQ_HANDLED;
 453 }
 454
 455 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
 456 {
 457         struct uart_port *port = ptr;
 458         struct stm32_port *stm32_port = to_stm32_port(port);
 459
 460         spin_lock(&port->lock);
 461
 462         if (stm32_port->rx_ch)
 463                 stm32_receive_chars(port, true);
 464
 465         spin_unlock(&port->lock);
 466
 467         return IRQ_HANDLED;
 468 }
 469
 470 static unsigned int stm32_tx_empty(struct uart_port *port)
 471 {
 472         struct stm32_port *stm32_port = to_stm32_port(port);
 473         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 474
 475         return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
 476 }
 477
 478 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 479 {
 480         struct stm32_port *stm32_port = to_stm32_port(port);
 481         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 482
 483         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 484                 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 485         else
 486                 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 487 }
 488
 489 static unsigned int stm32_get_mctrl(struct uart_port *port)
 490 {
 491         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 492         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 493 }
 494
 495 /* Transmit stop */
 496 static void stm32_stop_tx(struct uart_port *port)
 497 {
 498         struct stm32_port *stm32_port = to_stm32_port(port);
 499         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 500
 501         stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 502 }
 503
 504 /* There are probably characters waiting to be transmitted. */
 505 static void stm32_start_tx(struct uart_port *port)
 506 {
 507         struct circ_buf *xmit = &port->state->xmit;
 508
 509         if (uart_circ_empty(xmit))
 510                 return;
 511
 512         stm32_transmit_chars(port);
 513 }
 514
 515 /* Throttle the remote when input buffer is about to overflow. */
 516 static void stm32_throttle(struct uart_port *port)
 517 {
 518         struct stm32_port *stm32_port = to_stm32_port(port);
 519         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 520         unsigned long flags;
 521
 522         spin_lock_irqsave(&port->lock, flags);
 523         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 524         spin_unlock_irqrestore(&port->lock, flags);
 525 }
 526
 527 /* Unthrottle the remote, the input buffer can now accept data. */
 528 static void stm32_unthrottle(struct uart_port *port)
 529 {
 530         struct stm32_port *stm32_port = to_stm32_port(port);
 531         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 532         unsigned long flags;
 533
 534         spin_lock_irqsave(&port->lock, flags);
 535         stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 536         spin_unlock_irqrestore(&port->lock, flags);
 537 }
 538
 539 /* Receive stop */
 540 static void stm32_stop_rx(struct uart_port *port)
 541 {
 542         struct stm32_port *stm32_port = to_stm32_port(port);
 543         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 544
 545         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 546 }
 547
 548 /* Handle breaks - ignored by us */
 549 static void stm32_break_ctl(struct uart_port *port, int break_state)
 550 {
 551 }
 552
 553 static int stm32_startup(struct uart_port *port)
 554 {
 555         struct stm32_port *stm32_port = to_stm32_port(port);
 556         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 557         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 558         const char *name = to_platform_device(port->dev)->name;
 559         u32 val;
 560         int ret;
 561
 562         ret = request_threaded_irq(port->irq, stm32_interrupt,
 563                                    stm32_threaded_interrupt,
 564                                    IRQF_NO_SUSPEND, name, port);
 565         if (ret)
 566                 return ret;
 567
 568         if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
 569                 ret = dev_pm_set_dedicated_wake_irq(port->dev,
 570                                                     stm32_port->wakeirq);
 571                 if (ret) {
 572                         free_irq(port->irq, port);
 573                         return ret;
 574                 }
 575         }
 576
 577         val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 578         if (stm32_port->fifoen)
 579                 val |= USART_CR1_FIFOEN;
 580         stm32_set_bits(port, ofs->cr1, val);
 581
 582         return 0;
 583 }
 584
 585 static void stm32_shutdown(struct uart_port *port)
 586 {
 587         struct stm32_port *stm32_port = to_stm32_port(port);
 588         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 589         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 590         u32 val;
 591
 592         val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 593         val |= BIT(cfg->uart_enable_bit);
 594         if (stm32_port->fifoen)
 595                 val |= USART_CR1_FIFOEN;
 596         stm32_clr_bits(port, ofs->cr1, val);
 597
 598         dev_pm_clear_wake_irq(port->dev);
 599         free_irq(port->irq, port);
 600 }
 601
 602 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
 603                             struct ktermios *old)
 604 {
 605         struct stm32_port *stm32_port = to_stm32_port(port);
 606         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 607         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 608         struct serial_rs485 *rs485conf = &port->rs485;
 609         unsigned int baud;
 610         u32 usartdiv, mantissa, fraction, oversampling;
 611         tcflag_t cflag = termios->c_cflag;
 612         u32 cr1, cr2, cr3;
 613         unsigned long flags;
 614
 615         if (!stm32_port->hw_flow_control)
 616                 cflag &= ~CRTSCTS;
 617
 618         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 619
 620         spin_lock_irqsave(&port->lock, flags);
 621
 622         /* Stop serial port and reset value */
 623         writel_relaxed(0, port->membase + ofs->cr1);
 624
 625         cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
 626
 627         if (stm32_port->fifoen)
 628                 cr1 |= USART_CR1_FIFOEN;
 629         cr2 = 0;
 630         cr3 = 0;
 631
 632         if (cflag & CSTOPB)
 633                 cr2 |= USART_CR2_STOP_2B;
 634
 635         if (cflag & PARENB) {
 636                 cr1 |= USART_CR1_PCE;
 637                 if ((cflag & CSIZE) == CS8) {
 638                         if (cfg->has_7bits_data)
 639                                 cr1 |= USART_CR1_M0;
 640                         else
 641                                 cr1 |= USART_CR1_M;
 642                 }
 643         }
 644
 645         if (cflag & PARODD)
 646                 cr1 |= USART_CR1_PS;
 647
 648         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
 649         if (cflag & CRTSCTS) {
 650                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 651                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
 652         }
 653
 654         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
 655
 656         /*
 657          * The USART supports 16 or 8 times oversampling.
 658          * By default we prefer 16 times oversampling, so that the receiver
 659          * has a better tolerance to clock deviations.
 660          * 8 times oversampling is only used to achieve higher speeds.
 661          */
 662         if (usartdiv < 16) {
 663                 oversampling = 8;
 664                 cr1 |= USART_CR1_OVER8;
 665                 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
 666         } else {
 667                 oversampling = 16;
 668                 cr1 &= ~USART_CR1_OVER8;
 669                 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
 670         }
 671
 672         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
 673         fraction = usartdiv % oversampling;
 674         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
 675
 676         uart_update_timeout(port, cflag, baud);
 677
 678         port->read_status_mask = USART_SR_ORE;
 679         if (termios->c_iflag & INPCK)
 680                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
 681         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 682                 port->read_status_mask |= USART_SR_LBD;
 683
 684         /* Characters to ignore */
 685         port->ignore_status_mask = 0;
 686         if (termios->c_iflag & IGNPAR)
 687                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
 688         if (termios->c_iflag & IGNBRK) {
 689                 port->ignore_status_mask |= USART_SR_LBD;
 690                 /*
 691                  * If we're ignoring parity and break indicators,
 692                  * ignore overruns too (for real raw support).
 693                  */
 694                 if (termios->c_iflag & IGNPAR)
 695                         port->ignore_status_mask |= USART_SR_ORE;
 696         }
 697
 698         /* Ignore all characters if CREAD is not set */
 699         if ((termios->c_cflag & CREAD) == 0)
 700                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
 701
 702         if (stm32_port->rx_ch)
 703                 cr3 |= USART_CR3_DMAR;
 704
 705         if (rs485conf->flags & SER_RS485_ENABLED) {
 706                 stm32_config_reg_rs485(&cr1, &cr3,
 707                                        rs485conf->delay_rts_before_send,
 708                                        rs485conf->delay_rts_after_send, baud);
 709                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 710                         cr3 &= ~USART_CR3_DEP;
 711                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 712                 } else {
 713                         cr3 |= USART_CR3_DEP;
 714                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 715                 }
 716
 717         } else {
 718                 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
 719                 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 720         }
 721
 722         writel_relaxed(cr3, port->membase + ofs->cr3);
 723         writel_relaxed(cr2, port->membase + ofs->cr2);
 724         writel_relaxed(cr1, port->membase + ofs->cr1);
 725
 726         stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 727         spin_unlock_irqrestore(&port->lock, flags);
 728 }
 729
 730 static const char *stm32_type(struct uart_port *port)
 731 {
 732         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
 733 }
 734
 735 static void stm32_release_port(struct uart_port *port)
 736 {
 737 }
 738
 739 static int stm32_request_port(struct uart_port *port)
 740 {
 741         return 0;
 742 }
 743
 744 static void stm32_config_port(struct uart_port *port, int flags)
 745 {
 746         if (flags & UART_CONFIG_TYPE)
 747                 port->type = PORT_STM32;
 748 }
 749
 750 static int
 751 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
 752 {
 753         /* No user changeable parameters */
 754         return -EINVAL;
 755 }
 756
 757 static void stm32_pm(struct uart_port *port, unsigned int state,
 758                 unsigned int oldstate)
 759 {
 760         struct stm32_port *stm32port = container_of(port,
 761                         struct stm32_port, port);
 762         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 763         struct stm32_usart_config *cfg = &stm32port->info->cfg;
 764         unsigned long flags = 0;
 765
 766         switch (state) {
 767         case UART_PM_STATE_ON:
 768                 clk_prepare_enable(stm32port->clk);
 769                 break;
 770         case UART_PM_STATE_OFF:
 771                 spin_lock_irqsave(&port->lock, flags);
 772                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 773                 spin_unlock_irqrestore(&port->lock, flags);
 774                 clk_disable_unprepare(stm32port->clk);
 775                 break;
 776         }
 777 }
 778
 779 static const struct uart_ops stm32_uart_ops = {
 780         .tx_empty       = stm32_tx_empty,
 781         .set_mctrl      = stm32_set_mctrl,
 782         .get_mctrl      = stm32_get_mctrl,
 783         .stop_tx        = stm32_stop_tx,
 784         .start_tx       = stm32_start_tx,
 785         .throttle       = stm32_throttle,
 786         .unthrottle     = stm32_unthrottle,
 787         .stop_rx        = stm32_stop_rx,
 788         .break_ctl      = stm32_break_ctl,
 789         .startup        = stm32_startup,
 790         .shutdown       = stm32_shutdown,
 791         .set_termios    = stm32_set_termios,
 792         .pm             = stm32_pm,
 793         .type           = stm32_type,
 794         .release_port   = stm32_release_port,
 795         .request_port   = stm32_request_port,
 796         .config_port    = stm32_config_port,
 797         .verify_port    = stm32_verify_port,
 798 };
 799
 800 static int stm32_init_port(struct stm32_port *stm32port,
 801                           struct platform_device *pdev)
 802 {
 803         struct uart_port *port = &stm32port->port;
 804         struct resource *res;
 805         int ret;
 806
 807         port->iotype    = UPIO_MEM;
 808         port->flags     = UPF_BOOT_AUTOCONF;
 809         port->ops       = &stm32_uart_ops;
 810         port->dev       = &pdev->dev;
 811         port->irq       = platform_get_irq(pdev, 0);
 812         port->rs485_config = stm32_config_rs485;
 813
 814         stm32_init_rs485(port, pdev);
 815
 816         stm32port->wakeirq = platform_get_irq(pdev, 1);
 817         stm32port->fifoen = stm32port->info->cfg.has_fifo;
 818
 819         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 820         port->membase = devm_ioremap_resource(&pdev->dev, res);
 821         if (IS_ERR(port->membase))
 822                 return PTR_ERR(port->membase);
 823         port->mapbase = res->start;
 824
 825         spin_lock_init(&port->lock);
 826
 827         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
 828         if (IS_ERR(stm32port->clk))
 829                 return PTR_ERR(stm32port->clk);
 830
 831         /* Ensure that clk rate is correct by enabling the clk */
 832         ret = clk_prepare_enable(stm32port->clk);
 833         if (ret)
 834                 return ret;
 835
 836         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
 837         if (!stm32port->port.uartclk) {
 838                 clk_disable_unprepare(stm32port->clk);
 839                 ret = -EINVAL;
 840         }
 841
 842         return ret;
 843 }
 844
 845 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
 846 {
 847         struct device_node *np = pdev->dev.of_node;
 848         int id;
 849
 850         if (!np)
 851                 return NULL;
 852
 853         id = of_alias_get_id(np, "serial");
 854         if (id < 0) {
 855                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
 856                 return NULL;
 857         }
 858
 859         if (WARN_ON(id >= STM32_MAX_PORTS))
 860                 return NULL;
 861
 862         stm32_ports[id].hw_flow_control = of_property_read_bool(np,
 863                                                         "st,hw-flow-ctrl");
 864         stm32_ports[id].port.line = id;
 865         stm32_ports[id].last_res = RX_BUF_L;
 866         return &stm32_ports[id];
 867 }
 868
 869 #ifdef CONFIG_OF
 870 static const struct of_device_id stm32_match[] = {
 871         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
 872         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
 873         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
 874         {},
 875 };
 876
 877 MODULE_DEVICE_TABLE(of, stm32_match);
 878 #endif
 879
 880 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
 881                                  struct platform_device *pdev)
 882 {
 883         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 884         struct uart_port *port = &stm32port->port;
 885         struct device *dev = &pdev->dev;
 886         struct dma_slave_config config;
 887         struct dma_async_tx_descriptor *desc = NULL;
 888         dma_cookie_t cookie;
 889         int ret;
 890
 891         /* Request DMA RX channel */
 892         stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
 893         if (!stm32port->rx_ch) {
 894                 dev_info(dev, "rx dma alloc failed\n");
 895                 return -ENODEV;
 896         }
 897         stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
 898                                                  &stm32port->rx_dma_buf,
 899                                                  GFP_KERNEL);
 900         if (!stm32port->rx_buf) {
 901                 ret = -ENOMEM;
 902                 goto alloc_err;
 903         }
 904
 905         /* Configure DMA channel */
 906         memset(&config, 0, sizeof(config));
 907         config.src_addr = port->mapbase + ofs->rdr;
 908         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 909
 910         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
 911         if (ret < 0) {
 912                 dev_err(dev, "rx dma channel config failed\n");
 913                 ret = -ENODEV;
 914                 goto config_err;
 915         }
 916
 917         /* Prepare a DMA cyclic transaction */
 918         desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
 919                                          stm32port->rx_dma_buf,
 920                                          RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
 921                                          DMA_PREP_INTERRUPT);
 922         if (!desc) {
 923                 dev_err(dev, "rx dma prep cyclic failed\n");
 924                 ret = -ENODEV;
 925                 goto config_err;
 926         }
 927
 928         /* No callback as dma buffer is drained on usart interrupt */
 929         desc->callback = NULL;
 930         desc->callback_param = NULL;
 931
 932         /* Push current DMA transaction in the pending queue */
 933         cookie = dmaengine_submit(desc);
 934
 935         /* Issue pending DMA requests */
 936         dma_async_issue_pending(stm32port->rx_ch);
 937
 938         return 0;
 939
 940 config_err:
 941         dma_free_coherent(&pdev->dev,
 942                           RX_BUF_L, stm32port->rx_buf,
 943                           stm32port->rx_dma_buf);
 944
 945 alloc_err:
 946         dma_release_channel(stm32port->rx_ch);
 947         stm32port->rx_ch = NULL;
 948
 949         return ret;
 950 }
 951
 952 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
 953                                  struct platform_device *pdev)
 954 {
 955         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 956         struct uart_port *port = &stm32port->port;
 957         struct device *dev = &pdev->dev;
 958         struct dma_slave_config config;
 959         int ret;
 960
 961         stm32port->tx_dma_busy = false;
 962
 963         /* Request DMA TX channel */
 964         stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
 965         if (!stm32port->tx_ch) {
 966                 dev_info(dev, "tx dma alloc failed\n");
 967                 return -ENODEV;
 968         }
 969         stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
 970                                                  &stm32port->tx_dma_buf,
 971                                                  GFP_KERNEL);
 972         if (!stm32port->tx_buf) {
 973                 ret = -ENOMEM;
 974                 goto alloc_err;
 975         }
 976
 977         /* Configure DMA channel */
 978         memset(&config, 0, sizeof(config));
 979         config.dst_addr = port->mapbase + ofs->tdr;
 980         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 981
 982         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
 983         if (ret < 0) {
 984                 dev_err(dev, "tx dma channel config failed\n");
 985                 ret = -ENODEV;
 986                 goto config_err;
 987         }
 988
 989         return 0;
 990
 991 config_err:
 992         dma_free_coherent(&pdev->dev,
 993                           TX_BUF_L, stm32port->tx_buf,
 994                           stm32port->tx_dma_buf);
 995
 996 alloc_err:
 997         dma_release_channel(stm32port->tx_ch);
 998         stm32port->tx_ch = NULL;
 999
1000         return ret;
1001 }
1002
1003 static int stm32_serial_probe(struct platform_device *pdev)
1004 {
1005         const struct of_device_id *match;
1006         struct stm32_port *stm32port;
1007         int ret;
1008
1009         stm32port = stm32_of_get_stm32_port(pdev);
1010         if (!stm32port)
1011                 return -ENODEV;
1012
1013         match = of_match_device(stm32_match, &pdev->dev);
1014         if (match && match->data)
1015                 stm32port->info = (struct stm32_usart_info *)match->data;
1016         else
1017                 return -EINVAL;
1018
1019         ret = stm32_init_port(stm32port, pdev);
1020         if (ret)
1021                 return ret;
1022
1023         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
1024                 ret = device_init_wakeup(&pdev->dev, true);
1025                 if (ret)
1026                         goto err_uninit;
1027         }
1028
1029         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1030         if (ret)
1031                 goto err_nowup;
1032
1033         ret = stm32_of_dma_rx_probe(stm32port, pdev);
1034         if (ret)
1035                 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1036
1037         ret = stm32_of_dma_tx_probe(stm32port, pdev);
1038         if (ret)
1039                 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1040
1041         platform_set_drvdata(pdev, &stm32port->port);
1042
1043         return 0;
1044
1045 err_nowup:
1046         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1047                 device_init_wakeup(&pdev->dev, false);
1048
1049 err_uninit:
1050         clk_disable_unprepare(stm32port->clk);
1051
1052         return ret;
1053 }
1054
1055 static int stm32_serial_remove(struct platform_device *pdev)
1056 {
1057         struct uart_port *port = platform_get_drvdata(pdev);
1058         struct stm32_port *stm32_port = to_stm32_port(port);
1059         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1060         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1061
1062         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1063
1064         if (stm32_port->rx_ch)
1065                 dma_release_channel(stm32_port->rx_ch);
1066
1067         if (stm32_port->rx_dma_buf)
1068                 dma_free_coherent(&pdev->dev,
1069                                   RX_BUF_L, stm32_port->rx_buf,
1070                                   stm32_port->rx_dma_buf);
1071
1072         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1073
1074         if (stm32_port->tx_ch)
1075                 dma_release_channel(stm32_port->tx_ch);
1076
1077         if (stm32_port->tx_dma_buf)
1078                 dma_free_coherent(&pdev->dev,
1079                                   TX_BUF_L, stm32_port->tx_buf,
1080                                   stm32_port->tx_dma_buf);
1081
1082         if (cfg->has_wakeup && stm32_port->wakeirq >= 0)
1083                 device_init_wakeup(&pdev->dev, false);
1084
1085         clk_disable_unprepare(stm32_port->clk);
1086
1087         return uart_remove_one_port(&stm32_usart_driver, port);
1088 }
1089
1090
1091 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1092 static void stm32_console_putchar(struct uart_port *port, int ch)
1093 {
1094         struct stm32_port *stm32_port = to_stm32_port(port);
1095         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1096
1097         while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1098                 cpu_relax();
1099
1100         writel_relaxed(ch, port->membase + ofs->tdr);
1101 }
1102
1103 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1104 {
1105         struct uart_port *port = &stm32_ports[co->index].port;
1106         struct stm32_port *stm32_port = to_stm32_port(port);
1107         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1108         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1109         unsigned long flags;
1110         u32 old_cr1, new_cr1;
1111         int locked = 1;
1112
1113         local_irq_save(flags);
1114         if (port->sysrq)
1115                 locked = 0;
1116         else if (oops_in_progress)
1117                 locked = spin_trylock(&port->lock);
1118         else
1119                 spin_lock(&port->lock);
1120
1121         /* Save and disable interrupts, enable the transmitter */
1122         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1123         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1124         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1125         writel_relaxed(new_cr1, port->membase + ofs->cr1);
1126
1127         uart_console_write(port, s, cnt, stm32_console_putchar);
1128
1129         /* Restore interrupt state */
1130         writel_relaxed(old_cr1, port->membase + ofs->cr1);
1131
1132         if (locked)
1133                 spin_unlock(&port->lock);
1134         local_irq_restore(flags);
1135 }
1136
1137 static int stm32_console_setup(struct console *co, char *options)
1138 {
1139         struct stm32_port *stm32port;
1140         int baud = 9600;
1141         int bits = 8;
1142         int parity = 'n';
1143         int flow = 'n';
1144
1145         if (co->index >= STM32_MAX_PORTS)
1146                 return -ENODEV;
1147
1148         stm32port = &stm32_ports[co->index];
1149
1150         /*
1151          * This driver does not support early console initialization
1152          * (use ARM early printk support instead), so we only expect
1153          * this to be called during the uart port registration when the
1154          * driver gets probed and the port should be mapped at that point.
1155          */
1156         if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1157                 return -ENXIO;
1158
1159         if (options)
1160                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1161
1162         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1163 }
1164
1165 static struct console stm32_console = {
1166         .name           = STM32_SERIAL_NAME,
1167         .device         = uart_console_device,
1168         .write          = stm32_console_write,
1169         .setup          = stm32_console_setup,
1170         .flags          = CON_PRINTBUFFER,
1171         .index          = -1,
1172         .data           = &stm32_usart_driver,
1173 };
1174
1175 #define STM32_SERIAL_CONSOLE (&stm32_console)
1176
1177 #else
1178 #define STM32_SERIAL_CONSOLE NULL
1179 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1180
1181 static struct uart_driver stm32_usart_driver = {
1182         .driver_name    = DRIVER_NAME,
1183         .dev_name       = STM32_SERIAL_NAME,
1184         .major          = 0,
1185         .minor          = 0,
1186         .nr             = STM32_MAX_PORTS,
1187         .cons           = STM32_SERIAL_CONSOLE,
1188 };
1189
1190 #ifdef CONFIG_PM_SLEEP
1191 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1192 {
1193         struct stm32_port *stm32_port = to_stm32_port(port);
1194         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1195         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1196         u32 val;
1197
1198         if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1199                 return;
1200
1201         if (enable) {
1202                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1203                 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1204                 val = readl_relaxed(port->membase + ofs->cr3);
1205                 val &= ~USART_CR3_WUS_MASK;
1206                 /* Enable Wake up interrupt from low power on start bit */
1207                 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1208                 writel_relaxed(val, port->membase + ofs->cr3);
1209                 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1210         } else {
1211                 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1212         }
1213 }
1214
1215 static int stm32_serial_suspend(struct device *dev)
1216 {
1217         struct uart_port *port = dev_get_drvdata(dev);
1218
1219         uart_suspend_port(&stm32_usart_driver, port);
1220
1221         if (device_may_wakeup(dev))
1222                 stm32_serial_enable_wakeup(port, true);
1223         else
1224                 stm32_serial_enable_wakeup(port, false);
1225
1226         return 0;
1227 }
1228
1229 static int stm32_serial_resume(struct device *dev)
1230 {
1231         struct uart_port *port = dev_get_drvdata(dev);
1232
1233         if (device_may_wakeup(dev))
1234                 stm32_serial_enable_wakeup(port, false);
1235
1236         return uart_resume_port(&stm32_usart_driver, port);
1237 }
1238 #endif /* CONFIG_PM_SLEEP */
1239
1240 static const struct dev_pm_ops stm32_serial_pm_ops = {
1241         SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1242 };
1243
1244 static struct platform_driver stm32_serial_driver = {
1245         .probe          = stm32_serial_probe,
1246         .remove         = stm32_serial_remove,
1247         .driver = {
1248                 .name   = DRIVER_NAME,
1249                 .pm     = &stm32_serial_pm_ops,
1250                 .of_match_table = of_match_ptr(stm32_match),
1251         },
1252 };
1253
1254 static int __init usart_init(void)
1255 {
1256         static char banner[] __initdata = "STM32 USART driver initialized";
1257         int ret;
1258
1259         pr_info("%s\n", banner);
1260
1261         ret = uart_register_driver(&stm32_usart_driver);
1262         if (ret)
1263                 return ret;
1264
1265         ret = platform_driver_register(&stm32_serial_driver);
1266         if (ret)
1267                 uart_unregister_driver(&stm32_usart_driver);
1268
1269         return ret;
1270 }
1271
1272 static void __exit usart_exit(void)
1273 {
1274         platform_driver_unregister(&stm32_serial_driver);
1275         uart_unregister_driver(&stm32_usart_driver);
1276 }
1277
1278 module_init(usart_init);
1279 module_exit(usart_exit);
1280
1281 MODULE_ALIAS("platform:" DRIVER_NAME);
1282 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1283 MODULE_LICENSE("GPL v2");