drivers/tty/serial/stm32-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6  *           Gerald Baeza <gerald.baeza@st.com>
   7  *
   8  * Inspired by st-asc.c from STMicroelectronics (c)
   9  */
  10
  11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14
  15 #include <linux/clk.h>
  16 #include <linux/console.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-direction.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/irq.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pm_wakeirq.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/serial.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/sysrq.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/tty.h>
  36
  37 #include "stm32-usart.h"
  38
  39 static void stm32_stop_tx(struct uart_port *port);
  40 static void stm32_transmit_chars(struct uart_port *port);
  41
  42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
  43 {
  44         return container_of(port, struct stm32_port, port);
  45 }
  46
  47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
  48 {
  49         u32 val;
  50
  51         val = readl_relaxed(port->membase + reg);
  52         val |= bits;
  53         writel_relaxed(val, port->membase + reg);
  54 }
  55
  56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
  57 {
  58         u32 val;
  59
  60         val = readl_relaxed(port->membase + reg);
  61         val &= ~bits;
  62         writel_relaxed(val, port->membase + reg);
  63 }
  64
  65 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
  66                                    u32 delay_DDE, u32 baud)
  67 {
  68         u32 rs485_deat_dedt;
  69         u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
  70         bool over8;
  71
  72         *cr3 |= USART_CR3_DEM;
  73         over8 = *cr1 & USART_CR1_OVER8;
  74
  75         if (over8)
  76                 rs485_deat_dedt = delay_ADE * baud * 8;
  77         else
  78                 rs485_deat_dedt = delay_ADE * baud * 16;
  79
  80         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  81         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  82                           rs485_deat_dedt_max : rs485_deat_dedt;
  83         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
  84                            USART_CR1_DEAT_MASK;
  85         *cr1 |= rs485_deat_dedt;
  86
  87         if (over8)
  88                 rs485_deat_dedt = delay_DDE * baud * 8;
  89         else
  90                 rs485_deat_dedt = delay_DDE * baud * 16;
  91
  92         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  93         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  94                           rs485_deat_dedt_max : rs485_deat_dedt;
  95         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
  96                            USART_CR1_DEDT_MASK;
  97         *cr1 |= rs485_deat_dedt;
  98 }
  99
 100 static int stm32_config_rs485(struct uart_port *port,
 101                               struct serial_rs485 *rs485conf)
 102 {
 103         struct stm32_port *stm32_port = to_stm32_port(port);
 104         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 105         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 106         u32 usartdiv, baud, cr1, cr3;
 107         bool over8;
 108         unsigned long flags;
 109
 110         spin_lock_irqsave(&port->lock, flags);
 111         stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 112
 113         port->rs485 = *rs485conf;
 114
 115         rs485conf->flags |= SER_RS485_RX_DURING_TX;
 116
 117         if (rs485conf->flags & SER_RS485_ENABLED) {
 118                 cr1 = readl_relaxed(port->membase + ofs->cr1);
 119                 cr3 = readl_relaxed(port->membase + ofs->cr3);
 120                 usartdiv = readl_relaxed(port->membase + ofs->brr);
 121                 usartdiv = usartdiv & GENMASK(15, 0);
 122                 over8 = cr1 & USART_CR1_OVER8;
 123
 124                 if (over8)
 125                         usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
 126                                    << USART_BRR_04_R_SHIFT;
 127
 128                 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
 129                 stm32_config_reg_rs485(&cr1, &cr3,
 130                                        rs485conf->delay_rts_before_send,
 131                                        rs485conf->delay_rts_after_send, baud);
 132
 133                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 134                         cr3 &= ~USART_CR3_DEP;
 135                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 136                 } else {
 137                         cr3 |= USART_CR3_DEP;
 138                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 139                 }
 140
 141                 writel_relaxed(cr3, port->membase + ofs->cr3);
 142                 writel_relaxed(cr1, port->membase + ofs->cr1);
 143         } else {
 144                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
 145                 stm32_clr_bits(port, ofs->cr1,
 146                                USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 147         }
 148
 149         stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 150         spin_unlock_irqrestore(&port->lock, flags);
 151
 152         return 0;
 153 }
 154
 155 static int stm32_init_rs485(struct uart_port *port,
 156                             struct platform_device *pdev)
 157 {
 158         struct serial_rs485 *rs485conf = &port->rs485;
 159
 160         rs485conf->flags = 0;
 161         rs485conf->delay_rts_before_send = 0;
 162         rs485conf->delay_rts_after_send = 0;
 163
 164         if (!pdev->dev.of_node)
 165                 return -ENODEV;
 166
 167         uart_get_rs485_mode(&pdev->dev, rs485conf);
 168
 169         return 0;
 170 }
 171
 172 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
 173                             bool threaded)
 174 {
 175         struct stm32_port *stm32_port = to_stm32_port(port);
 176         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 177         enum dma_status status;
 178         struct dma_tx_state state;
 179
 180         *sr = readl_relaxed(port->membase + ofs->isr);
 181
 182         if (threaded && stm32_port->rx_ch) {
 183                 status = dmaengine_tx_status(stm32_port->rx_ch,
 184                                              stm32_port->rx_ch->cookie,
 185                                              &state);
 186                 if ((status == DMA_IN_PROGRESS) &&
 187                     (*last_res != state.residue))
 188                         return 1;
 189                 else
 190                         return 0;
 191         } else if (*sr & USART_SR_RXNE) {
 192                 return 1;
 193         }
 194         return 0;
 195 }
 196
 197 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
 198                                     int *last_res)
 199 {
 200         struct stm32_port *stm32_port = to_stm32_port(port);
 201         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 202         unsigned long c;
 203
 204         if (stm32_port->rx_ch) {
 205                 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
 206                 if ((*last_res) == 0)
 207                         *last_res = RX_BUF_L;
 208         } else {
 209                 c = readl_relaxed(port->membase + ofs->rdr);
 210                 /* apply RDR data mask */
 211                 c &= stm32_port->rdr_mask;
 212         }
 213
 214         return c;
 215 }
 216
 217 static void stm32_receive_chars(struct uart_port *port, bool threaded)
 218 {
 219         struct tty_port *tport = &port->state->port;
 220         struct stm32_port *stm32_port = to_stm32_port(port);
 221         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 222         unsigned long c;
 223         u32 sr;
 224         char flag;
 225
 226         if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 227                 pm_wakeup_event(tport->tty->dev, 0);
 228
 229         while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
 230                 sr |= USART_SR_DUMMY_RX;
 231                 flag = TTY_NORMAL;
 232
 233                 /*
 234                  * Status bits has to be cleared before reading the RDR:
 235                  * In FIFO mode, reading the RDR will pop the next data
 236                  * (if any) along with its status bits into the SR.
 237                  * Not doing so leads to misalignement between RDR and SR,
 238                  * and clear status bits of the next rx data.
 239                  *
 240                  * Clear errors flags for stm32f7 and stm32h7 compatible
 241                  * devices. On stm32f4 compatible devices, the error bit is
 242                  * cleared by the sequence [read SR - read DR].
 243                  */
 244                 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
 245                         stm32_clr_bits(port, ofs->icr, USART_ICR_ORECF |
 246                                        USART_ICR_PECF | USART_ICR_FECF);
 247
 248                 c = stm32_get_char(port, &sr, &stm32_port->last_res);
 249                 port->icount.rx++;
 250                 if (sr & USART_SR_ERR_MASK) {
 251                         if (sr & USART_SR_ORE) {
 252                                 port->icount.overrun++;
 253                         } else if (sr & USART_SR_PE) {
 254                                 port->icount.parity++;
 255                         } else if (sr & USART_SR_FE) {
 256                                 /* Break detection if character is null */
 257                                 if (!c) {
 258                                         port->icount.brk++;
 259                                         if (uart_handle_break(port))
 260                                                 continue;
 261                                 } else {
 262                                         port->icount.frame++;
 263                                 }
 264                         }
 265
 266                         sr &= port->read_status_mask;
 267
 268                         if (sr & USART_SR_PE) {
 269                                 flag = TTY_PARITY;
 270                         } else if (sr & USART_SR_FE) {
 271                                 if (!c)
 272                                         flag = TTY_BREAK;
 273                                 else
 274                                         flag = TTY_FRAME;
 275                         }
 276                 }
 277
 278                 if (uart_handle_sysrq_char(port, c))
 279                         continue;
 280                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 281         }
 282
 283         spin_unlock(&port->lock);
 284         tty_flip_buffer_push(tport);
 285         spin_lock(&port->lock);
 286 }
 287
 288 static void stm32_tx_dma_complete(void *arg)
 289 {
 290         struct uart_port *port = arg;
 291         struct stm32_port *stm32port = to_stm32_port(port);
 292         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 293
 294         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 295         stm32port->tx_dma_busy = false;
 296
 297         /* Let's see if we have pending data to send */
 298         stm32_transmit_chars(port);
 299 }
 300
 301 static void stm32_transmit_chars_pio(struct uart_port *port)
 302 {
 303         struct stm32_port *stm32_port = to_stm32_port(port);
 304         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 305         struct circ_buf *xmit = &port->state->xmit;
 306         unsigned int isr;
 307         int ret;
 308
 309         if (stm32_port->tx_dma_busy) {
 310                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 311                 stm32_port->tx_dma_busy = false;
 312         }
 313
 314         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 315                                                 isr,
 316                                                 (isr & USART_SR_TXE),
 317                                                 10, 100000);
 318
 319         if (ret)
 320                 dev_err(port->dev, "tx empty not set\n");
 321
 322         stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 323
 324         writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 325         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 326         port->icount.tx++;
 327 }
 328
 329 static void stm32_transmit_chars_dma(struct uart_port *port)
 330 {
 331         struct stm32_port *stm32port = to_stm32_port(port);
 332         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 333         struct circ_buf *xmit = &port->state->xmit;
 334         struct dma_async_tx_descriptor *desc = NULL;
 335         dma_cookie_t cookie;
 336         unsigned int count, i;
 337
 338         if (stm32port->tx_dma_busy)
 339                 return;
 340
 341         stm32port->tx_dma_busy = true;
 342
 343         count = uart_circ_chars_pending(xmit);
 344
 345         if (count > TX_BUF_L)
 346                 count = TX_BUF_L;
 347
 348         if (xmit->tail < xmit->head) {
 349                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 350         } else {
 351                 size_t one = UART_XMIT_SIZE - xmit->tail;
 352                 size_t two;
 353
 354                 if (one > count)
 355                         one = count;
 356                 two = count - one;
 357
 358                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 359                 if (two)
 360                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 361         }
 362
 363         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 364                                            stm32port->tx_dma_buf,
 365                                            count,
 366                                            DMA_MEM_TO_DEV,
 367                                            DMA_PREP_INTERRUPT);
 368
 369         if (!desc) {
 370                 for (i = count; i > 0; i--)
 371                         stm32_transmit_chars_pio(port);
 372                 return;
 373         }
 374
 375         desc->callback = stm32_tx_dma_complete;
 376         desc->callback_param = port;
 377
 378         /* Push current DMA TX transaction in the pending queue */
 379         cookie = dmaengine_submit(desc);
 380
 381         /* Issue pending DMA TX requests */
 382         dma_async_issue_pending(stm32port->tx_ch);
 383
 384         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 385
 386         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 387         port->icount.tx += count;
 388 }
 389
 390 static void stm32_transmit_chars(struct uart_port *port)
 391 {
 392         struct stm32_port *stm32_port = to_stm32_port(port);
 393         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 394         struct circ_buf *xmit = &port->state->xmit;
 395
 396         if (port->x_char) {
 397                 if (stm32_port->tx_dma_busy)
 398                         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 399                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 400                 port->x_char = 0;
 401                 port->icount.tx++;
 402                 if (stm32_port->tx_dma_busy)
 403                         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 404                 return;
 405         }
 406
 407         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 408                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 409                 return;
 410         }
 411
 412         if (ofs->icr == UNDEF_REG)
 413                 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 414         else
 415                 stm32_set_bits(port, ofs->icr, USART_ICR_TCCF);
 416
 417         if (stm32_port->tx_ch)
 418                 stm32_transmit_chars_dma(port);
 419         else
 420                 stm32_transmit_chars_pio(port);
 421
 422         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 423                 uart_write_wakeup(port);
 424
 425         if (uart_circ_empty(xmit))
 426                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 427 }
 428
 429 static irqreturn_t stm32_interrupt(int irq, void *ptr)
 430 {
 431         struct uart_port *port = ptr;
 432         struct stm32_port *stm32_port = to_stm32_port(port);
 433         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 434         u32 sr;
 435
 436         spin_lock(&port->lock);
 437
 438         sr = readl_relaxed(port->membase + ofs->isr);
 439
 440         if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
 441                 writel_relaxed(USART_ICR_WUCF,
 442                                port->membase + ofs->icr);
 443
 444         if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
 445                 stm32_receive_chars(port, false);
 446
 447         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
 448                 stm32_transmit_chars(port);
 449
 450         spin_unlock(&port->lock);
 451
 452         if (stm32_port->rx_ch)
 453                 return IRQ_WAKE_THREAD;
 454         else
 455                 return IRQ_HANDLED;
 456 }
 457
 458 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
 459 {
 460         struct uart_port *port = ptr;
 461         struct stm32_port *stm32_port = to_stm32_port(port);
 462
 463         spin_lock(&port->lock);
 464
 465         if (stm32_port->rx_ch)
 466                 stm32_receive_chars(port, true);
 467
 468         spin_unlock(&port->lock);
 469
 470         return IRQ_HANDLED;
 471 }
 472
 473 static unsigned int stm32_tx_empty(struct uart_port *port)
 474 {
 475         struct stm32_port *stm32_port = to_stm32_port(port);
 476         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 477
 478         return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
 479 }
 480
 481 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 482 {
 483         struct stm32_port *stm32_port = to_stm32_port(port);
 484         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 485
 486         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 487                 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 488         else
 489                 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 490 }
 491
 492 static unsigned int stm32_get_mctrl(struct uart_port *port)
 493 {
 494         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 495         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 496 }
 497
 498 /* Transmit stop */
 499 static void stm32_stop_tx(struct uart_port *port)
 500 {
 501         struct stm32_port *stm32_port = to_stm32_port(port);
 502         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 503
 504         stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 505 }
 506
 507 /* There are probably characters waiting to be transmitted. */
 508 static void stm32_start_tx(struct uart_port *port)
 509 {
 510         struct circ_buf *xmit = &port->state->xmit;
 511
 512         if (uart_circ_empty(xmit))
 513                 return;
 514
 515         stm32_transmit_chars(port);
 516 }
 517
 518 /* Throttle the remote when input buffer is about to overflow. */
 519 static void stm32_throttle(struct uart_port *port)
 520 {
 521         struct stm32_port *stm32_port = to_stm32_port(port);
 522         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 523         unsigned long flags;
 524
 525         spin_lock_irqsave(&port->lock, flags);
 526         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 527         spin_unlock_irqrestore(&port->lock, flags);
 528 }
 529
 530 /* Unthrottle the remote, the input buffer can now accept data. */
 531 static void stm32_unthrottle(struct uart_port *port)
 532 {
 533         struct stm32_port *stm32_port = to_stm32_port(port);
 534         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 535         unsigned long flags;
 536
 537         spin_lock_irqsave(&port->lock, flags);
 538         stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 539         spin_unlock_irqrestore(&port->lock, flags);
 540 }
 541
 542 /* Receive stop */
 543 static void stm32_stop_rx(struct uart_port *port)
 544 {
 545         struct stm32_port *stm32_port = to_stm32_port(port);
 546         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 547
 548         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 549 }
 550
 551 /* Handle breaks - ignored by us */
 552 static void stm32_break_ctl(struct uart_port *port, int break_state)
 553 {
 554 }
 555
 556 static int stm32_startup(struct uart_port *port)
 557 {
 558         struct stm32_port *stm32_port = to_stm32_port(port);
 559         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 560         const char *name = to_platform_device(port->dev)->name;
 561         u32 val;
 562         int ret;
 563
 564         ret = request_threaded_irq(port->irq, stm32_interrupt,
 565                                    stm32_threaded_interrupt,
 566                                    IRQF_NO_SUSPEND, name, port);
 567         if (ret)
 568                 return ret;
 569
 570         val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 571         if (stm32_port->fifoen)
 572                 val |= USART_CR1_FIFOEN;
 573         stm32_set_bits(port, ofs->cr1, val);
 574
 575         return 0;
 576 }
 577
 578 static void stm32_shutdown(struct uart_port *port)
 579 {
 580         struct stm32_port *stm32_port = to_stm32_port(port);
 581         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 582         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 583         u32 val, isr;
 584         int ret;
 585
 586         val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 587         val |= BIT(cfg->uart_enable_bit);
 588         if (stm32_port->fifoen)
 589                 val |= USART_CR1_FIFOEN;
 590
 591         ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
 592                                          isr, (isr & USART_SR_TC),
 593                                          10, 100000);
 594
 595         if (ret)
 596                 dev_err(port->dev, "transmission complete not set\n");
 597
 598         stm32_clr_bits(port, ofs->cr1, val);
 599
 600         free_irq(port->irq, port);
 601 }
 602
 603 unsigned int stm32_get_databits(struct ktermios *termios)
 604 {
 605         unsigned int bits;
 606
 607         tcflag_t cflag = termios->c_cflag;
 608
 609         switch (cflag & CSIZE) {
 610         /*
 611          * CSIZE settings are not necessarily supported in hardware.
 612          * CSIZE unsupported configurations are handled here to set word length
 613          * to 8 bits word as default configuration and to print debug message.
 614          */
 615         case CS5:
 616                 bits = 5;
 617                 break;
 618         case CS6:
 619                 bits = 6;
 620                 break;
 621         case CS7:
 622                 bits = 7;
 623                 break;
 624         /* default including CS8 */
 625         default:
 626                 bits = 8;
 627                 break;
 628         }
 629
 630         return bits;
 631 }
 632
 633 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
 634                             struct ktermios *old)
 635 {
 636         struct stm32_port *stm32_port = to_stm32_port(port);
 637         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 638         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 639         struct serial_rs485 *rs485conf = &port->rs485;
 640         unsigned int baud, bits;
 641         u32 usartdiv, mantissa, fraction, oversampling;
 642         tcflag_t cflag = termios->c_cflag;
 643         u32 cr1, cr2, cr3;
 644         unsigned long flags;
 645
 646         if (!stm32_port->hw_flow_control)
 647                 cflag &= ~CRTSCTS;
 648
 649         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 650
 651         spin_lock_irqsave(&port->lock, flags);
 652
 653         /* Stop serial port and reset value */
 654         writel_relaxed(0, port->membase + ofs->cr1);
 655
 656         cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
 657
 658         if (stm32_port->fifoen)
 659                 cr1 |= USART_CR1_FIFOEN;
 660         cr2 = 0;
 661         cr3 = 0;
 662
 663         if (cflag & CSTOPB)
 664                 cr2 |= USART_CR2_STOP_2B;
 665
 666         bits = stm32_get_databits(termios);
 667         stm32_port->rdr_mask = (BIT(bits) - 1);
 668
 669         if (cflag & PARENB) {
 670                 bits++;
 671                 cr1 |= USART_CR1_PCE;
 672         }
 673
 674         /*
 675          * Word length configuration:
 676          * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
 677          * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
 678          * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
 679          * M0 and M1 already cleared by cr1 initialization.
 680          */
 681         if (bits == 9)
 682                 cr1 |= USART_CR1_M0;
 683         else if ((bits == 7) && cfg->has_7bits_data)
 684                 cr1 |= USART_CR1_M1;
 685         else if (bits != 8)
 686                 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
 687                         , bits);
 688
 689         if (cflag & PARODD)
 690                 cr1 |= USART_CR1_PS;
 691
 692         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
 693         if (cflag & CRTSCTS) {
 694                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 695                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
 696         }
 697
 698         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
 699
 700         /*
 701          * The USART supports 16 or 8 times oversampling.
 702          * By default we prefer 16 times oversampling, so that the receiver
 703          * has a better tolerance to clock deviations.
 704          * 8 times oversampling is only used to achieve higher speeds.
 705          */
 706         if (usartdiv < 16) {
 707                 oversampling = 8;
 708                 cr1 |= USART_CR1_OVER8;
 709                 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
 710         } else {
 711                 oversampling = 16;
 712                 cr1 &= ~USART_CR1_OVER8;
 713                 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
 714         }
 715
 716         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
 717         fraction = usartdiv % oversampling;
 718         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
 719
 720         uart_update_timeout(port, cflag, baud);
 721
 722         port->read_status_mask = USART_SR_ORE;
 723         if (termios->c_iflag & INPCK)
 724                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
 725         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 726                 port->read_status_mask |= USART_SR_FE;
 727
 728         /* Characters to ignore */
 729         port->ignore_status_mask = 0;
 730         if (termios->c_iflag & IGNPAR)
 731                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
 732         if (termios->c_iflag & IGNBRK) {
 733                 port->ignore_status_mask |= USART_SR_FE;
 734                 /*
 735                  * If we're ignoring parity and break indicators,
 736                  * ignore overruns too (for real raw support).
 737                  */
 738                 if (termios->c_iflag & IGNPAR)
 739                         port->ignore_status_mask |= USART_SR_ORE;
 740         }
 741
 742         /* Ignore all characters if CREAD is not set */
 743         if ((termios->c_cflag & CREAD) == 0)
 744                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
 745
 746         if (stm32_port->rx_ch)
 747                 cr3 |= USART_CR3_DMAR;
 748
 749         if (rs485conf->flags & SER_RS485_ENABLED) {
 750                 stm32_config_reg_rs485(&cr1, &cr3,
 751                                        rs485conf->delay_rts_before_send,
 752                                        rs485conf->delay_rts_after_send, baud);
 753                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 754                         cr3 &= ~USART_CR3_DEP;
 755                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 756                 } else {
 757                         cr3 |= USART_CR3_DEP;
 758                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 759                 }
 760
 761         } else {
 762                 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
 763                 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 764         }
 765
 766         writel_relaxed(cr3, port->membase + ofs->cr3);
 767         writel_relaxed(cr2, port->membase + ofs->cr2);
 768         writel_relaxed(cr1, port->membase + ofs->cr1);
 769
 770         stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 771         spin_unlock_irqrestore(&port->lock, flags);
 772 }
 773
 774 static const char *stm32_type(struct uart_port *port)
 775 {
 776         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
 777 }
 778
 779 static void stm32_release_port(struct uart_port *port)
 780 {
 781 }
 782
 783 static int stm32_request_port(struct uart_port *port)
 784 {
 785         return 0;
 786 }
 787
 788 static void stm32_config_port(struct uart_port *port, int flags)
 789 {
 790         if (flags & UART_CONFIG_TYPE)
 791                 port->type = PORT_STM32;
 792 }
 793
 794 static int
 795 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
 796 {
 797         /* No user changeable parameters */
 798         return -EINVAL;
 799 }
 800
 801 static void stm32_pm(struct uart_port *port, unsigned int state,
 802                 unsigned int oldstate)
 803 {
 804         struct stm32_port *stm32port = container_of(port,
 805                         struct stm32_port, port);
 806         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 807         struct stm32_usart_config *cfg = &stm32port->info->cfg;
 808         unsigned long flags = 0;
 809
 810         switch (state) {
 811         case UART_PM_STATE_ON:
 812                 clk_prepare_enable(stm32port->clk);
 813                 break;
 814         case UART_PM_STATE_OFF:
 815                 spin_lock_irqsave(&port->lock, flags);
 816                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 817                 spin_unlock_irqrestore(&port->lock, flags);
 818                 clk_disable_unprepare(stm32port->clk);
 819                 break;
 820         }
 821 }
 822
 823 static const struct uart_ops stm32_uart_ops = {
 824         .tx_empty       = stm32_tx_empty,
 825         .set_mctrl      = stm32_set_mctrl,
 826         .get_mctrl      = stm32_get_mctrl,
 827         .stop_tx        = stm32_stop_tx,
 828         .start_tx       = stm32_start_tx,
 829         .throttle       = stm32_throttle,
 830         .unthrottle     = stm32_unthrottle,
 831         .stop_rx        = stm32_stop_rx,
 832         .break_ctl      = stm32_break_ctl,
 833         .startup        = stm32_startup,
 834         .shutdown       = stm32_shutdown,
 835         .set_termios    = stm32_set_termios,
 836         .pm             = stm32_pm,
 837         .type           = stm32_type,
 838         .release_port   = stm32_release_port,
 839         .request_port   = stm32_request_port,
 840         .config_port    = stm32_config_port,
 841         .verify_port    = stm32_verify_port,
 842 };
 843
 844 static int stm32_init_port(struct stm32_port *stm32port,
 845                           struct platform_device *pdev)
 846 {
 847         struct uart_port *port = &stm32port->port;
 848         struct resource *res;
 849         int ret;
 850
 851         port->iotype    = UPIO_MEM;
 852         port->flags     = UPF_BOOT_AUTOCONF;
 853         port->ops       = &stm32_uart_ops;
 854         port->dev       = &pdev->dev;
 855         port->irq       = platform_get_irq(pdev, 0);
 856         port->rs485_config = stm32_config_rs485;
 857
 858         stm32_init_rs485(port, pdev);
 859
 860         stm32port->wakeirq = platform_get_irq(pdev, 1);
 861         stm32port->fifoen = stm32port->info->cfg.has_fifo;
 862
 863         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 864         port->membase = devm_ioremap_resource(&pdev->dev, res);
 865         if (IS_ERR(port->membase))
 866                 return PTR_ERR(port->membase);
 867         port->mapbase = res->start;
 868
 869         spin_lock_init(&port->lock);
 870
 871         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
 872         if (IS_ERR(stm32port->clk))
 873                 return PTR_ERR(stm32port->clk);
 874
 875         /* Ensure that clk rate is correct by enabling the clk */
 876         ret = clk_prepare_enable(stm32port->clk);
 877         if (ret)
 878                 return ret;
 879
 880         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
 881         if (!stm32port->port.uartclk) {
 882                 clk_disable_unprepare(stm32port->clk);
 883                 ret = -EINVAL;
 884         }
 885
 886         return ret;
 887 }
 888
 889 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
 890 {
 891         struct device_node *np = pdev->dev.of_node;
 892         int id;
 893
 894         if (!np)
 895                 return NULL;
 896
 897         id = of_alias_get_id(np, "serial");
 898         if (id < 0) {
 899                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
 900                 return NULL;
 901         }
 902
 903         if (WARN_ON(id >= STM32_MAX_PORTS))
 904                 return NULL;
 905
 906         stm32_ports[id].hw_flow_control = of_property_read_bool(np,
 907                                                         "st,hw-flow-ctrl");
 908         stm32_ports[id].port.line = id;
 909         stm32_ports[id].last_res = RX_BUF_L;
 910         return &stm32_ports[id];
 911 }
 912
 913 #ifdef CONFIG_OF
 914 static const struct of_device_id stm32_match[] = {
 915         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
 916         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
 917         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
 918         {},
 919 };
 920
 921 MODULE_DEVICE_TABLE(of, stm32_match);
 922 #endif
 923
 924 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
 925                                  struct platform_device *pdev)
 926 {
 927         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 928         struct uart_port *port = &stm32port->port;
 929         struct device *dev = &pdev->dev;
 930         struct dma_slave_config config;
 931         struct dma_async_tx_descriptor *desc = NULL;
 932         dma_cookie_t cookie;
 933         int ret;
 934
 935         /* Request DMA RX channel */
 936         stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
 937         if (!stm32port->rx_ch) {
 938                 dev_info(dev, "rx dma alloc failed\n");
 939                 return -ENODEV;
 940         }
 941         stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
 942                                                  &stm32port->rx_dma_buf,
 943                                                  GFP_KERNEL);
 944         if (!stm32port->rx_buf) {
 945                 ret = -ENOMEM;
 946                 goto alloc_err;
 947         }
 948
 949         /* Configure DMA channel */
 950         memset(&config, 0, sizeof(config));
 951         config.src_addr = port->mapbase + ofs->rdr;
 952         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 953
 954         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
 955         if (ret < 0) {
 956                 dev_err(dev, "rx dma channel config failed\n");
 957                 ret = -ENODEV;
 958                 goto config_err;
 959         }
 960
 961         /* Prepare a DMA cyclic transaction */
 962         desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
 963                                          stm32port->rx_dma_buf,
 964                                          RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
 965                                          DMA_PREP_INTERRUPT);
 966         if (!desc) {
 967                 dev_err(dev, "rx dma prep cyclic failed\n");
 968                 ret = -ENODEV;
 969                 goto config_err;
 970         }
 971
 972         /* No callback as dma buffer is drained on usart interrupt */
 973         desc->callback = NULL;
 974         desc->callback_param = NULL;
 975
 976         /* Push current DMA transaction in the pending queue */
 977         cookie = dmaengine_submit(desc);
 978
 979         /* Issue pending DMA requests */
 980         dma_async_issue_pending(stm32port->rx_ch);
 981
 982         return 0;
 983
 984 config_err:
 985         dma_free_coherent(&pdev->dev,
 986                           RX_BUF_L, stm32port->rx_buf,
 987                           stm32port->rx_dma_buf);
 988
 989 alloc_err:
 990         dma_release_channel(stm32port->rx_ch);
 991         stm32port->rx_ch = NULL;
 992
 993         return ret;
 994 }
 995
 996 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
 997                                  struct platform_device *pdev)
 998 {
 999         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1000         struct uart_port *port = &stm32port->port;
1001         struct device *dev = &pdev->dev;
1002         struct dma_slave_config config;
1003         int ret;
1004
1005         stm32port->tx_dma_busy = false;
1006
1007         /* Request DMA TX channel */
1008         stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1009         if (!stm32port->tx_ch) {
1010                 dev_info(dev, "tx dma alloc failed\n");
1011                 return -ENODEV;
1012         }
1013         stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1014                                                  &stm32port->tx_dma_buf,
1015                                                  GFP_KERNEL);
1016         if (!stm32port->tx_buf) {
1017                 ret = -ENOMEM;
1018                 goto alloc_err;
1019         }
1020
1021         /* Configure DMA channel */
1022         memset(&config, 0, sizeof(config));
1023         config.dst_addr = port->mapbase + ofs->tdr;
1024         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1025
1026         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1027         if (ret < 0) {
1028                 dev_err(dev, "tx dma channel config failed\n");
1029                 ret = -ENODEV;
1030                 goto config_err;
1031         }
1032
1033         return 0;
1034
1035 config_err:
1036         dma_free_coherent(&pdev->dev,
1037                           TX_BUF_L, stm32port->tx_buf,
1038                           stm32port->tx_dma_buf);
1039
1040 alloc_err:
1041         dma_release_channel(stm32port->tx_ch);
1042         stm32port->tx_ch = NULL;
1043
1044         return ret;
1045 }
1046
1047 static int stm32_serial_probe(struct platform_device *pdev)
1048 {
1049         const struct of_device_id *match;
1050         struct stm32_port *stm32port;
1051         int ret;
1052
1053         stm32port = stm32_of_get_stm32_port(pdev);
1054         if (!stm32port)
1055                 return -ENODEV;
1056
1057         match = of_match_device(stm32_match, &pdev->dev);
1058         if (match && match->data)
1059                 stm32port->info = (struct stm32_usart_info *)match->data;
1060         else
1061                 return -EINVAL;
1062
1063         ret = stm32_init_port(stm32port, pdev);
1064         if (ret)
1065                 return ret;
1066
1067         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
1068                 ret = device_init_wakeup(&pdev->dev, true);
1069                 if (ret)
1070                         goto err_uninit;
1071
1072                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1073                                                     stm32port->wakeirq);
1074                 if (ret)
1075                         goto err_nowup;
1076
1077                 device_set_wakeup_enable(&pdev->dev, false);
1078         }
1079
1080         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1081         if (ret)
1082                 goto err_wirq;
1083
1084         ret = stm32_of_dma_rx_probe(stm32port, pdev);
1085         if (ret)
1086                 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1087
1088         ret = stm32_of_dma_tx_probe(stm32port, pdev);
1089         if (ret)
1090                 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1091
1092         platform_set_drvdata(pdev, &stm32port->port);
1093
1094         return 0;
1095
1096 err_wirq:
1097         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1098                 dev_pm_clear_wake_irq(&pdev->dev);
1099
1100 err_nowup:
1101         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1102                 device_init_wakeup(&pdev->dev, false);
1103
1104 err_uninit:
1105         clk_disable_unprepare(stm32port->clk);
1106
1107         return ret;
1108 }
1109
1110 static int stm32_serial_remove(struct platform_device *pdev)
1111 {
1112         struct uart_port *port = platform_get_drvdata(pdev);
1113         struct stm32_port *stm32_port = to_stm32_port(port);
1114         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1115         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1116
1117         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1118
1119         if (stm32_port->rx_ch)
1120                 dma_release_channel(stm32_port->rx_ch);
1121
1122         if (stm32_port->rx_dma_buf)
1123                 dma_free_coherent(&pdev->dev,
1124                                   RX_BUF_L, stm32_port->rx_buf,
1125                                   stm32_port->rx_dma_buf);
1126
1127         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1128
1129         if (stm32_port->tx_ch)
1130                 dma_release_channel(stm32_port->tx_ch);
1131
1132         if (stm32_port->tx_dma_buf)
1133                 dma_free_coherent(&pdev->dev,
1134                                   TX_BUF_L, stm32_port->tx_buf,
1135                                   stm32_port->tx_dma_buf);
1136
1137         if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
1138                 dev_pm_clear_wake_irq(&pdev->dev);
1139                 device_init_wakeup(&pdev->dev, false);
1140         }
1141
1142         clk_disable_unprepare(stm32_port->clk);
1143
1144         return uart_remove_one_port(&stm32_usart_driver, port);
1145 }
1146
1147
1148 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1149 static void stm32_console_putchar(struct uart_port *port, int ch)
1150 {
1151         struct stm32_port *stm32_port = to_stm32_port(port);
1152         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1153
1154         while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1155                 cpu_relax();
1156
1157         writel_relaxed(ch, port->membase + ofs->tdr);
1158 }
1159
1160 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1161 {
1162         struct uart_port *port = &stm32_ports[co->index].port;
1163         struct stm32_port *stm32_port = to_stm32_port(port);
1164         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1165         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1166         unsigned long flags;
1167         u32 old_cr1, new_cr1;
1168         int locked = 1;
1169
1170         local_irq_save(flags);
1171         if (port->sysrq)
1172                 locked = 0;
1173         else if (oops_in_progress)
1174                 locked = spin_trylock(&port->lock);
1175         else
1176                 spin_lock(&port->lock);
1177
1178         /* Save and disable interrupts, enable the transmitter */
1179         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1180         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1181         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1182         writel_relaxed(new_cr1, port->membase + ofs->cr1);
1183
1184         uart_console_write(port, s, cnt, stm32_console_putchar);
1185
1186         /* Restore interrupt state */
1187         writel_relaxed(old_cr1, port->membase + ofs->cr1);
1188
1189         if (locked)
1190                 spin_unlock(&port->lock);
1191         local_irq_restore(flags);
1192 }
1193
1194 static int stm32_console_setup(struct console *co, char *options)
1195 {
1196         struct stm32_port *stm32port;
1197         int baud = 9600;
1198         int bits = 8;
1199         int parity = 'n';
1200         int flow = 'n';
1201
1202         if (co->index >= STM32_MAX_PORTS)
1203                 return -ENODEV;
1204
1205         stm32port = &stm32_ports[co->index];
1206
1207         /*
1208          * This driver does not support early console initialization
1209          * (use ARM early printk support instead), so we only expect
1210          * this to be called during the uart port registration when the
1211          * driver gets probed and the port should be mapped at that point.
1212          */
1213         if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1214                 return -ENXIO;
1215
1216         if (options)
1217                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1218
1219         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1220 }
1221
1222 static struct console stm32_console = {
1223         .name           = STM32_SERIAL_NAME,
1224         .device         = uart_console_device,
1225         .write          = stm32_console_write,
1226         .setup          = stm32_console_setup,
1227         .flags          = CON_PRINTBUFFER,
1228         .index          = -1,
1229         .data           = &stm32_usart_driver,
1230 };
1231
1232 #define STM32_SERIAL_CONSOLE (&stm32_console)
1233
1234 #else
1235 #define STM32_SERIAL_CONSOLE NULL
1236 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1237
1238 static struct uart_driver stm32_usart_driver = {
1239         .driver_name    = DRIVER_NAME,
1240         .dev_name       = STM32_SERIAL_NAME,
1241         .major          = 0,
1242         .minor          = 0,
1243         .nr             = STM32_MAX_PORTS,
1244         .cons           = STM32_SERIAL_CONSOLE,
1245 };
1246
1247 #ifdef CONFIG_PM_SLEEP
1248 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1249 {
1250         struct stm32_port *stm32_port = to_stm32_port(port);
1251         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1252         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1253         u32 val;
1254
1255         if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1256                 return;
1257
1258         if (enable) {
1259                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1260                 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1261                 val = readl_relaxed(port->membase + ofs->cr3);
1262                 val &= ~USART_CR3_WUS_MASK;
1263                 /* Enable Wake up interrupt from low power on start bit */
1264                 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1265                 writel_relaxed(val, port->membase + ofs->cr3);
1266                 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1267         } else {
1268                 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1269         }
1270 }
1271
1272 static int stm32_serial_suspend(struct device *dev)
1273 {
1274         struct uart_port *port = dev_get_drvdata(dev);
1275
1276         uart_suspend_port(&stm32_usart_driver, port);
1277
1278         if (device_may_wakeup(dev))
1279                 stm32_serial_enable_wakeup(port, true);
1280         else
1281                 stm32_serial_enable_wakeup(port, false);
1282
1283         return 0;
1284 }
1285
1286 static int stm32_serial_resume(struct device *dev)
1287 {
1288         struct uart_port *port = dev_get_drvdata(dev);
1289
1290         if (device_may_wakeup(dev))
1291                 stm32_serial_enable_wakeup(port, false);
1292
1293         return uart_resume_port(&stm32_usart_driver, port);
1294 }
1295 #endif /* CONFIG_PM_SLEEP */
1296
1297 static const struct dev_pm_ops stm32_serial_pm_ops = {
1298         SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1299 };
1300
1301 static struct platform_driver stm32_serial_driver = {
1302         .probe          = stm32_serial_probe,
1303         .remove         = stm32_serial_remove,
1304         .driver = {
1305                 .name   = DRIVER_NAME,
1306                 .pm     = &stm32_serial_pm_ops,
1307                 .of_match_table = of_match_ptr(stm32_match),
1308         },
1309 };
1310
1311 static int __init usart_init(void)
1312 {
1313         static char banner[] __initdata = "STM32 USART driver initialized";
1314         int ret;
1315
1316         pr_info("%s\n", banner);
1317
1318         ret = uart_register_driver(&stm32_usart_driver);
1319         if (ret)
1320                 return ret;
1321
1322         ret = platform_driver_register(&stm32_serial_driver);
1323         if (ret)
1324                 uart_unregister_driver(&stm32_usart_driver);
1325
1326         return ret;
1327 }
1328
1329 static void __exit usart_exit(void)
1330 {
1331         platform_driver_unregister(&stm32_serial_driver);
1332         uart_unregister_driver(&stm32_usart_driver);
1333 }
1334
1335 module_init(usart_init);
1336 module_exit(usart_exit);
1337
1338 MODULE_ALIAS("platform:" DRIVER_NAME);
1339 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1340 MODULE_LICENSE("GPL v2");