2 * Driver for CSR SiRFprimaII onboard UARTs.
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/module.h>
10 #include <linux/ioport.h>
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/sysrq.h>
14 #include <linux/console.h>
15 #include <linux/tty.h>
16 #include <linux/tty_flip.h>
17 #include <linux/serial_core.h>
18 #include <linux/serial.h>
19 #include <linux/clk.h>
21 #include <linux/slab.h>
24 #include <asm/mach/irq.h>
25 #include <linux/pinctrl/consumer.h>
27 #include "sirfsoc_uart.h"
30 sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
32 sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
33 static struct uart_driver sirfsoc_uart_drv;
35 static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
56 static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
60 .flags = UPF_BOOT_AUTOCONF,
67 .flags = UPF_BOOT_AUTOCONF,
74 .flags = UPF_BOOT_AUTOCONF,
81 .flags = UPF_BOOT_AUTOCONF,
88 .flags = UPF_BOOT_AUTOCONF,
94 static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
96 return container_of(port, struct sirfsoc_uart_port, port);
99 static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
102 reg = rd_regl(port, SIRFUART_TX_FIFO_STATUS);
103 if (reg & SIRFUART_FIFOEMPTY_MASK(port))
109 static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
111 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
112 if (!(sirfport->ms_enabled)) {
114 } else if (sirfport->hw_flow_ctrl) {
115 if (!(rd_regl(port, SIRFUART_AFC_CTRL) &
116 SIRFUART_CTS_IN_STATUS))
122 return TIOCM_CAR | TIOCM_DSR;
124 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
127 static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
129 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
130 unsigned int assert = mctrl & TIOCM_RTS;
131 unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
132 unsigned int current_val;
133 if (sirfport->hw_flow_ctrl) {
134 current_val = rd_regl(port, SIRFUART_AFC_CTRL) & ~0xFF;
136 wr_regl(port, SIRFUART_AFC_CTRL, val);
140 static void sirfsoc_uart_stop_tx(struct uart_port *port)
143 regv = rd_regl(port, SIRFUART_INT_EN);
144 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_TX_INT_EN);
147 void sirfsoc_uart_start_tx(struct uart_port *port)
149 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
151 sirfsoc_uart_pio_tx_chars(sirfport, 1);
152 wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_START);
153 regv = rd_regl(port, SIRFUART_INT_EN);
154 wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_TX_INT_EN);
157 static void sirfsoc_uart_stop_rx(struct uart_port *port)
160 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
161 regv = rd_regl(port, SIRFUART_INT_EN);
162 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_RX_IO_INT_EN);
165 static void sirfsoc_uart_disable_ms(struct uart_port *port)
167 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
169 sirfport->ms_enabled = 0;
170 if (!sirfport->hw_flow_ctrl)
172 reg = rd_regl(port, SIRFUART_AFC_CTRL);
173 wr_regl(port, SIRFUART_AFC_CTRL, reg & ~0x3FF);
174 reg = rd_regl(port, SIRFUART_INT_EN);
175 wr_regl(port, SIRFUART_INT_EN, reg & ~SIRFUART_CTS_INT_EN);
178 static void sirfsoc_uart_enable_ms(struct uart_port *port)
180 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
183 if (!sirfport->hw_flow_ctrl)
185 flg = SIRFUART_AFC_RX_EN | SIRFUART_AFC_TX_EN;
186 reg = rd_regl(port, SIRFUART_AFC_CTRL);
187 wr_regl(port, SIRFUART_AFC_CTRL, reg | flg);
188 reg = rd_regl(port, SIRFUART_INT_EN);
189 wr_regl(port, SIRFUART_INT_EN, reg | SIRFUART_CTS_INT_EN);
190 uart_handle_cts_change(port,
191 !(rd_regl(port, SIRFUART_AFC_CTRL) & SIRFUART_CTS_IN_STATUS));
192 sirfport->ms_enabled = 1;
195 static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
197 unsigned long ulcon = rd_regl(port, SIRFUART_LINE_CTRL);
199 ulcon |= SIRFUART_SET_BREAK;
201 ulcon &= ~SIRFUART_SET_BREAK;
202 wr_regl(port, SIRFUART_LINE_CTRL, ulcon);
206 sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
208 unsigned int ch, rx_count = 0;
210 while (!(rd_regl(port, SIRFUART_RX_FIFO_STATUS) &
211 SIRFUART_FIFOEMPTY_MASK(port))) {
212 ch = rd_regl(port, SIRFUART_RX_FIFO_DATA) | SIRFUART_DUMMY_READ;
213 if (unlikely(uart_handle_sysrq_char(port, ch)))
215 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
217 if (rx_count >= max_rx_count)
221 port->icount.rx += rx_count;
222 tty_flip_buffer_push(&port->state->port);
228 sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
230 struct uart_port *port = &sirfport->port;
231 struct circ_buf *xmit = &port->state->xmit;
232 unsigned int num_tx = 0;
233 while (!uart_circ_empty(xmit) &&
234 !(rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
235 SIRFUART_FIFOFULL_MASK(port)) &&
237 wr_regl(port, SIRFUART_TX_FIFO_DATA, xmit->buf[xmit->tail]);
238 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
242 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
243 uart_write_wakeup(port);
247 static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
249 unsigned long intr_status;
250 unsigned long cts_status;
251 unsigned long flag = TTY_NORMAL;
252 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
253 struct uart_port *port = &sirfport->port;
254 struct uart_state *state = port->state;
255 struct circ_buf *xmit = &port->state->xmit;
256 spin_lock(&port->lock);
257 intr_status = rd_regl(port, SIRFUART_INT_STATUS);
258 wr_regl(port, SIRFUART_INT_STATUS, intr_status);
259 intr_status &= rd_regl(port, SIRFUART_INT_EN);
260 if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT))) {
261 if (intr_status & SIRFUART_RXD_BREAK) {
262 if (uart_handle_break(port))
264 uart_insert_char(port, intr_status,
265 SIRFUART_RX_OFLOW, 0, TTY_BREAK);
266 spin_unlock(&port->lock);
269 if (intr_status & SIRFUART_RX_OFLOW)
270 port->icount.overrun++;
271 if (intr_status & SIRFUART_FRM_ERR) {
272 port->icount.frame++;
275 if (intr_status & SIRFUART_PARITY_ERR)
277 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
278 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
279 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
280 intr_status &= port->read_status_mask;
281 uart_insert_char(port, intr_status,
282 SIRFUART_RX_OFLOW_INT, 0, flag);
285 if (intr_status & SIRFUART_CTS_INT_EN) {
286 cts_status = !(rd_regl(port, SIRFUART_AFC_CTRL) &
287 SIRFUART_CTS_IN_STATUS);
288 if (cts_status != 0) {
289 uart_handle_cts_change(port, 1);
291 uart_handle_cts_change(port, 0);
292 wake_up_interruptible(&state->port.delta_msr_wait);
295 if (intr_status & SIRFUART_RX_IO_INT_EN)
296 sirfsoc_uart_pio_rx_chars(port, SIRFSOC_UART_IO_RX_MAX_CNT);
297 if (intr_status & SIRFUART_TX_INT_EN) {
298 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
299 spin_unlock(&port->lock);
302 sirfsoc_uart_pio_tx_chars(sirfport,
303 SIRFSOC_UART_IO_TX_REASONABLE_CNT);
304 if ((uart_circ_empty(xmit)) &&
305 (rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
306 SIRFUART_FIFOEMPTY_MASK(port)))
307 sirfsoc_uart_stop_tx(port);
310 spin_unlock(&port->lock);
314 static void sirfsoc_uart_start_rx(struct uart_port *port)
317 regv = rd_regl(port, SIRFUART_INT_EN);
318 wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_RX_IO_INT_EN);
319 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
320 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
321 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
325 sirfsoc_calc_sample_div(unsigned long baud_rate,
326 unsigned long ioclk_rate, unsigned long *setted_baud)
328 unsigned long min_delta = ~0UL;
329 unsigned short sample_div;
330 unsigned int regv = 0;
331 unsigned long ioclk_div;
332 unsigned long baud_tmp;
335 for (sample_div = SIRF_MIN_SAMPLE_DIV;
336 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
337 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
338 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
340 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
341 temp_delta = baud_tmp - baud_rate;
342 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
343 if (temp_delta < min_delta) {
344 regv = regv & (~SIRF_IOCLK_DIV_MASK);
345 regv = regv | ioclk_div;
346 regv = regv & (~SIRF_SAMPLE_DIV_MASK);
347 regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
348 min_delta = temp_delta;
349 *setted_baud = baud_tmp;
355 static void sirfsoc_uart_set_termios(struct uart_port *port,
356 struct ktermios *termios,
357 struct ktermios *old)
359 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
360 unsigned long config_reg = 0;
361 unsigned long baud_rate;
362 unsigned long setted_baud;
365 unsigned int clk_div_reg = 0;
366 unsigned long temp_reg_val;
367 unsigned long rx_time_out;
371 switch (termios->c_cflag & CSIZE) {
374 config_reg |= SIRFUART_DATA_BIT_LEN_8;
377 config_reg |= SIRFUART_DATA_BIT_LEN_7;
380 config_reg |= SIRFUART_DATA_BIT_LEN_6;
383 config_reg |= SIRFUART_DATA_BIT_LEN_5;
386 if (termios->c_cflag & CSTOPB)
387 config_reg |= SIRFUART_STOP_BIT_LEN_2;
388 baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
389 spin_lock_irqsave(&port->lock, flags);
390 port->read_status_mask = SIRFUART_RX_OFLOW_INT;
391 port->ignore_status_mask = 0;
393 if (termios->c_iflag & INPCK)
394 port->read_status_mask |=
395 SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
396 if (termios->c_iflag & (BRKINT | PARMRK))
397 port->read_status_mask |= SIRFUART_RXD_BREAK_INT;
399 if (termios->c_iflag & IGNPAR)
400 port->ignore_status_mask |=
401 SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
402 if ((termios->c_cflag & CREAD) == 0)
403 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
404 /* enable parity if PARENB is set*/
405 if (termios->c_cflag & PARENB) {
406 if (termios->c_cflag & CMSPAR) {
407 if (termios->c_cflag & PARODD)
408 config_reg |= SIRFUART_STICK_BIT_MARK;
410 config_reg |= SIRFUART_STICK_BIT_SPACE;
411 } else if (termios->c_cflag & PARODD) {
412 config_reg |= SIRFUART_STICK_BIT_ODD;
414 config_reg |= SIRFUART_STICK_BIT_EVEN;
417 /* Hardware Flow Control Settings */
418 if (UART_ENABLE_MS(port, termios->c_cflag)) {
419 if (!sirfport->ms_enabled)
420 sirfsoc_uart_enable_ms(port);
422 if (sirfport->ms_enabled)
423 sirfsoc_uart_disable_ms(port);
426 if (port->uartclk == 150000000) {
427 /* common rate: fast calculation */
428 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
429 if (baud_rate == baudrate_to_regv[ic].baud_rate)
430 clk_div_reg = baudrate_to_regv[ic].reg_val;
433 setted_baud = baud_rate;
434 /* arbitary rate setting */
435 if (unlikely(clk_div_reg == 0))
436 clk_div_reg = sirfsoc_calc_sample_div(baud_rate, port->uartclk,
438 wr_regl(port, SIRFUART_DIVISOR, clk_div_reg);
440 if (tty_termios_baud_rate(termios))
441 tty_termios_encode_baud_rate(termios, setted_baud, setted_baud);
443 /* set receive timeout */
444 rx_time_out = SIRFSOC_UART_RX_TIMEOUT(baud_rate, 20000);
445 rx_time_out = (rx_time_out > 0xFFFF) ? 0xFFFF : rx_time_out;
446 config_reg |= SIRFUART_RECV_TIMEOUT(rx_time_out);
447 temp_reg_val = rd_regl(port, SIRFUART_TX_FIFO_OP);
448 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
449 wr_regl(port, SIRFUART_TX_FIFO_OP,
450 temp_reg_val & ~SIRFUART_TX_FIFO_START);
451 wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, SIRFUART_TX_MODE_IO);
452 wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, SIRFUART_RX_MODE_IO);
453 wr_regl(port, SIRFUART_LINE_CTRL, config_reg);
455 /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
456 if (baud_rate < 1000000)
460 temp = port->line == 1 ? 16 : 64;
461 wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp / threshold_div);
462 wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp / threshold_div);
463 temp_reg_val |= SIRFUART_TX_FIFO_START;
464 wr_regl(port, SIRFUART_TX_FIFO_OP, temp_reg_val);
465 uart_update_timeout(port, termios->c_cflag, baud_rate);
466 sirfsoc_uart_start_rx(port);
467 wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_TX_EN | SIRFUART_RX_EN);
468 spin_unlock_irqrestore(&port->lock, flags);
471 static void startup_uart_controller(struct uart_port *port)
473 unsigned long temp_regv;
475 temp_regv = rd_regl(port, SIRFUART_TX_DMA_IO_CTRL);
476 wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, temp_regv | SIRFUART_TX_MODE_IO);
477 temp_regv = rd_regl(port, SIRFUART_RX_DMA_IO_CTRL);
478 wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, temp_regv | SIRFUART_RX_MODE_IO);
479 wr_regl(port, SIRFUART_TX_DMA_IO_LEN, 0);
480 wr_regl(port, SIRFUART_RX_DMA_IO_LEN, 0);
481 wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_RX_EN | SIRFUART_TX_EN);
482 wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_RESET);
483 wr_regl(port, SIRFUART_TX_FIFO_OP, 0);
484 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
485 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
486 temp = port->line == 1 ? 16 : 64;
487 wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp);
488 wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp);
491 static int sirfsoc_uart_startup(struct uart_port *port)
493 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
494 unsigned int index = port->line;
496 set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
497 ret = request_irq(port->irq,
503 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
507 startup_uart_controller(port);
508 enable_irq(port->irq);
513 static void sirfsoc_uart_shutdown(struct uart_port *port)
515 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
516 wr_regl(port, SIRFUART_INT_EN, 0);
517 free_irq(port->irq, sirfport);
518 if (sirfport->ms_enabled) {
519 sirfsoc_uart_disable_ms(port);
520 sirfport->ms_enabled = 0;
524 static const char *sirfsoc_uart_type(struct uart_port *port)
526 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
529 static int sirfsoc_uart_request_port(struct uart_port *port)
532 ret = request_mem_region(port->mapbase,
533 SIRFUART_MAP_SIZE, SIRFUART_PORT_NAME);
534 return ret ? 0 : -EBUSY;
537 static void sirfsoc_uart_release_port(struct uart_port *port)
539 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
542 static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
544 if (flags & UART_CONFIG_TYPE) {
545 port->type = SIRFSOC_PORT_TYPE;
546 sirfsoc_uart_request_port(port);
550 static struct uart_ops sirfsoc_uart_ops = {
551 .tx_empty = sirfsoc_uart_tx_empty,
552 .get_mctrl = sirfsoc_uart_get_mctrl,
553 .set_mctrl = sirfsoc_uart_set_mctrl,
554 .stop_tx = sirfsoc_uart_stop_tx,
555 .start_tx = sirfsoc_uart_start_tx,
556 .stop_rx = sirfsoc_uart_stop_rx,
557 .enable_ms = sirfsoc_uart_enable_ms,
558 .break_ctl = sirfsoc_uart_break_ctl,
559 .startup = sirfsoc_uart_startup,
560 .shutdown = sirfsoc_uart_shutdown,
561 .set_termios = sirfsoc_uart_set_termios,
562 .type = sirfsoc_uart_type,
563 .release_port = sirfsoc_uart_release_port,
564 .request_port = sirfsoc_uart_request_port,
565 .config_port = sirfsoc_uart_config_port,
568 #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
569 static int __init sirfsoc_uart_console_setup(struct console *co, char *options)
571 unsigned int baud = 115200;
572 unsigned int bits = 8;
573 unsigned int parity = 'n';
574 unsigned int flow = 'n';
575 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
577 if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
584 uart_parse_options(options, &baud, &parity, &bits, &flow);
586 return uart_set_options(port, co, baud, parity, bits, flow);
589 static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
592 SIRFUART_TX_FIFO_STATUS) & SIRFUART_FIFOFULL_MASK(port))
594 wr_regb(port, SIRFUART_TX_FIFO_DATA, ch);
597 static void sirfsoc_uart_console_write(struct console *co, const char *s,
600 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
601 uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
604 static struct console sirfsoc_uart_console = {
605 .name = SIRFSOC_UART_NAME,
606 .device = uart_console_device,
607 .flags = CON_PRINTBUFFER,
609 .write = sirfsoc_uart_console_write,
610 .setup = sirfsoc_uart_console_setup,
611 .data = &sirfsoc_uart_drv,
614 static int __init sirfsoc_uart_console_init(void)
616 register_console(&sirfsoc_uart_console);
619 console_initcall(sirfsoc_uart_console_init);
622 static struct uart_driver sirfsoc_uart_drv = {
623 .owner = THIS_MODULE,
624 .driver_name = SIRFUART_PORT_NAME,
625 .nr = SIRFSOC_UART_NR,
626 .dev_name = SIRFSOC_UART_NAME,
627 .major = SIRFSOC_UART_MAJOR,
628 .minor = SIRFSOC_UART_MINOR,
629 #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
630 .cons = &sirfsoc_uart_console,
636 int sirfsoc_uart_probe(struct platform_device *pdev)
638 struct sirfsoc_uart_port *sirfport;
639 struct uart_port *port;
640 struct resource *res;
643 if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
645 "Unable to find cell-index in uart node.\n");
650 sirfport = &sirfsoc_uart_ports[pdev->id];
651 port = &sirfport->port;
652 port->dev = &pdev->dev;
653 port->private_data = sirfport;
655 if (of_find_property(pdev->dev.of_node, "hw_flow_ctrl", NULL))
656 sirfport->hw_flow_ctrl = 1;
658 if (of_property_read_u32(pdev->dev.of_node,
662 "Unable to find fifosize in uart node.\n");
667 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
669 dev_err(&pdev->dev, "Insufficient resources.\n");
673 port->mapbase = res->start;
674 port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
675 if (!port->membase) {
676 dev_err(&pdev->dev, "Cannot remap resource.\n");
680 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
682 dev_err(&pdev->dev, "Insufficient resources.\n");
686 port->irq = res->start;
688 if (sirfport->hw_flow_ctrl) {
689 sirfport->p = pinctrl_get_select_default(&pdev->dev);
690 ret = IS_ERR(sirfport->p);
695 sirfport->clk = clk_get(&pdev->dev, NULL);
696 if (IS_ERR(sirfport->clk)) {
697 ret = PTR_ERR(sirfport->clk);
700 clk_prepare_enable(sirfport->clk);
701 port->uartclk = clk_get_rate(sirfport->clk);
703 port->ops = &sirfsoc_uart_ops;
704 spin_lock_init(&port->lock);
706 platform_set_drvdata(pdev, sirfport);
707 ret = uart_add_one_port(&sirfsoc_uart_drv, port);
709 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
716 clk_disable_unprepare(sirfport->clk);
717 clk_put(sirfport->clk);
719 platform_set_drvdata(pdev, NULL);
720 if (sirfport->hw_flow_ctrl)
721 pinctrl_put(sirfport->p);
726 static int sirfsoc_uart_remove(struct platform_device *pdev)
728 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
729 struct uart_port *port = &sirfport->port;
730 platform_set_drvdata(pdev, NULL);
731 if (sirfport->hw_flow_ctrl)
732 pinctrl_put(sirfport->p);
733 clk_disable_unprepare(sirfport->clk);
734 clk_put(sirfport->clk);
735 uart_remove_one_port(&sirfsoc_uart_drv, port);
740 sirfsoc_uart_suspend(struct platform_device *pdev, pm_message_t state)
742 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
743 struct uart_port *port = &sirfport->port;
744 uart_suspend_port(&sirfsoc_uart_drv, port);
748 static int sirfsoc_uart_resume(struct platform_device *pdev)
750 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
751 struct uart_port *port = &sirfport->port;
752 uart_resume_port(&sirfsoc_uart_drv, port);
756 static struct of_device_id sirfsoc_uart_ids[] = {
757 { .compatible = "sirf,prima2-uart", },
758 { .compatible = "sirf,marco-uart", },
761 MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
763 static struct platform_driver sirfsoc_uart_driver = {
764 .probe = sirfsoc_uart_probe,
765 .remove = sirfsoc_uart_remove,
766 .suspend = sirfsoc_uart_suspend,
767 .resume = sirfsoc_uart_resume,
769 .name = SIRFUART_PORT_NAME,
770 .owner = THIS_MODULE,
771 .of_match_table = sirfsoc_uart_ids,
775 static int __init sirfsoc_uart_init(void)
779 ret = uart_register_driver(&sirfsoc_uart_drv);
783 ret = platform_driver_register(&sirfsoc_uart_driver);
785 uart_unregister_driver(&sirfsoc_uart_drv);
789 module_init(sirfsoc_uart_init);
791 static void __exit sirfsoc_uart_exit(void)
793 platform_driver_unregister(&sirfsoc_uart_driver);
794 uart_unregister_driver(&sirfsoc_uart_drv);
796 module_exit(sirfsoc_uart_exit);
798 MODULE_LICENSE("GPL v2");
799 MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
800 MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");