1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/minmax.h>
35 #include <linux/module.h>
38 #include <linux/of_device.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/reset.h>
42 #include <linux/scatterlist.h>
43 #include <linux/serial.h>
44 #include <linux/serial_sci.h>
45 #include <linux/sh_dma.h>
46 #include <linux/slab.h>
47 #include <linux/string.h>
48 #include <linux/sysrq.h>
49 #include <linux/timer.h>
50 #include <linux/tty.h>
51 #include <linux/tty_flip.h>
54 #include <asm/sh_bios.h>
55 #include <asm/platform_early.h>
58 #include "serial_mctrl_gpio.h"
61 /* Offsets into the sci_port->irqs array */
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
74 #define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
81 SCI_FCK, /* Functional Clock */
82 SCI_SCK, /* Optional External Clock */
83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
88 /* Bit x set means sampling rate x + 1 is supported */
89 #define SCI_SR(x) BIT((x) - 1)
90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
96 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
97 #define max_sr(_port) fls((_port)->sampling_rate_mask)
99 /* Iterate over all supported sampling rates, from high to low */
100 #define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104 struct plat_sci_reg {
108 struct sci_port_params {
109 const struct plat_sci_reg regs[SCIx_NR_REGS];
110 unsigned int fifosize;
111 unsigned int overrun_reg;
112 unsigned int overrun_mask;
113 unsigned int sampling_rate_mask;
114 unsigned int error_mask;
115 unsigned int error_clear;
119 struct uart_port port;
121 /* Platform configuration */
122 const struct sci_port_params *params;
123 const struct plat_sci_port *cfg;
124 unsigned int sampling_rate_mask;
125 resource_size_t reg_size;
126 struct mctrl_gpios *gpios;
129 struct clk *clks[SCI_NUM_CLKS];
130 unsigned long clk_rates[SCI_NUM_CLKS];
132 int irqs[SCIx_NR_IRQS];
133 char *irqstr[SCIx_NR_IRQS];
135 struct dma_chan *chan_tx;
136 struct dma_chan *chan_rx;
138 #ifdef CONFIG_SERIAL_SH_SCI_DMA
139 struct dma_chan *chan_tx_saved;
140 struct dma_chan *chan_rx_saved;
141 dma_cookie_t cookie_tx;
142 dma_cookie_t cookie_rx[2];
143 dma_cookie_t active_rx;
144 dma_addr_t tx_dma_addr;
145 unsigned int tx_dma_len;
146 struct scatterlist sg_rx[2];
149 struct work_struct work_tx;
150 struct hrtimer rx_timer;
151 unsigned int rx_timeout; /* microseconds */
153 unsigned int rx_frame;
155 struct timer_list rx_fifo_timer;
163 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
165 static struct sci_port sci_ports[SCI_NPORTS];
166 static unsigned long sci_ports_in_use;
167 static struct uart_driver sci_uart_driver;
169 static inline struct sci_port *
170 to_sci_port(struct uart_port *uart)
172 return container_of(uart, struct sci_port, port);
175 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
177 * Common SCI definitions, dependent on the port's regshift
180 [SCIx_SCI_REGTYPE] = {
182 [SCSMR] = { 0x00, 8 },
183 [SCBRR] = { 0x01, 8 },
184 [SCSCR] = { 0x02, 8 },
185 [SCxTDR] = { 0x03, 8 },
186 [SCxSR] = { 0x04, 8 },
187 [SCxRDR] = { 0x05, 8 },
190 .overrun_reg = SCxSR,
191 .overrun_mask = SCI_ORER,
192 .sampling_rate_mask = SCI_SR(32),
193 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
194 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
198 * Common definitions for legacy IrDA ports.
200 [SCIx_IRDA_REGTYPE] = {
202 [SCSMR] = { 0x00, 8 },
203 [SCBRR] = { 0x02, 8 },
204 [SCSCR] = { 0x04, 8 },
205 [SCxTDR] = { 0x06, 8 },
206 [SCxSR] = { 0x08, 16 },
207 [SCxRDR] = { 0x0a, 8 },
208 [SCFCR] = { 0x0c, 8 },
209 [SCFDR] = { 0x0e, 16 },
212 .overrun_reg = SCxSR,
213 .overrun_mask = SCI_ORER,
214 .sampling_rate_mask = SCI_SR(32),
215 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
216 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
220 * Common SCIFA definitions.
222 [SCIx_SCIFA_REGTYPE] = {
224 [SCSMR] = { 0x00, 16 },
225 [SCBRR] = { 0x04, 8 },
226 [SCSCR] = { 0x08, 16 },
227 [SCxTDR] = { 0x20, 8 },
228 [SCxSR] = { 0x14, 16 },
229 [SCxRDR] = { 0x24, 8 },
230 [SCFCR] = { 0x18, 16 },
231 [SCFDR] = { 0x1c, 16 },
232 [SCPCR] = { 0x30, 16 },
233 [SCPDR] = { 0x34, 16 },
236 .overrun_reg = SCxSR,
237 .overrun_mask = SCIFA_ORER,
238 .sampling_rate_mask = SCI_SR_SCIFAB,
239 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
240 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
244 * Common SCIFB definitions.
246 [SCIx_SCIFB_REGTYPE] = {
248 [SCSMR] = { 0x00, 16 },
249 [SCBRR] = { 0x04, 8 },
250 [SCSCR] = { 0x08, 16 },
251 [SCxTDR] = { 0x40, 8 },
252 [SCxSR] = { 0x14, 16 },
253 [SCxRDR] = { 0x60, 8 },
254 [SCFCR] = { 0x18, 16 },
255 [SCTFDR] = { 0x38, 16 },
256 [SCRFDR] = { 0x3c, 16 },
257 [SCPCR] = { 0x30, 16 },
258 [SCPDR] = { 0x34, 16 },
261 .overrun_reg = SCxSR,
262 .overrun_mask = SCIFA_ORER,
263 .sampling_rate_mask = SCI_SR_SCIFAB,
264 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
265 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
269 * Common SH-2(A) SCIF definitions for ports with FIFO data
272 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
274 [SCSMR] = { 0x00, 16 },
275 [SCBRR] = { 0x04, 8 },
276 [SCSCR] = { 0x08, 16 },
277 [SCxTDR] = { 0x0c, 8 },
278 [SCxSR] = { 0x10, 16 },
279 [SCxRDR] = { 0x14, 8 },
280 [SCFCR] = { 0x18, 16 },
281 [SCFDR] = { 0x1c, 16 },
282 [SCSPTR] = { 0x20, 16 },
283 [SCLSR] = { 0x24, 16 },
286 .overrun_reg = SCLSR,
287 .overrun_mask = SCLSR_ORER,
288 .sampling_rate_mask = SCI_SR(32),
289 .error_mask = SCIF_DEFAULT_ERROR_MASK,
290 .error_clear = SCIF_ERROR_CLEAR,
294 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
295 * It looks like a normal SCIF with FIFO data, but with a
296 * compressed address space. Also, the break out of interrupts
297 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
299 [SCIx_RZ_SCIFA_REGTYPE] = {
301 [SCSMR] = { 0x00, 16 },
302 [SCBRR] = { 0x02, 8 },
303 [SCSCR] = { 0x04, 16 },
304 [SCxTDR] = { 0x06, 8 },
305 [SCxSR] = { 0x08, 16 },
306 [SCxRDR] = { 0x0A, 8 },
307 [SCFCR] = { 0x0C, 16 },
308 [SCFDR] = { 0x0E, 16 },
309 [SCSPTR] = { 0x10, 16 },
310 [SCLSR] = { 0x12, 16 },
311 [SEMR] = { 0x14, 8 },
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
322 * Common SH-3 SCIF definitions.
324 [SCIx_SH3_SCIF_REGTYPE] = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
344 * Common SH-4(A) SCIF(B) definitions.
346 [SCIx_SH4_SCIF_REGTYPE] = {
348 [SCSMR] = { 0x00, 16 },
349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
368 * Common SCIF definitions for ports with a Baud Rate Generator for
369 * External Clock (BRG).
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
395 * Common HSCIF definitions.
397 [SCIx_HSCIF_REGTYPE] = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
478 [SCIx_SH7705_SCIF_REGTYPE] = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
501 * The "offset" here is rather misleading, in that it refers to an enum
502 * value relative to the port mapping rather than the fixed offset
503 * itself, which needs to be manually retrieved from the platform's
504 * register map for the given port.
506 static unsigned int sci_serial_in(struct uart_port *p, int offset)
508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
515 WARN(1, "Invalid register access\n");
520 static void sci_serial_out(struct uart_port *p, int offset, int value)
522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
529 WARN(1, "Invalid register access\n");
532 static void sci_port_enable(struct sci_port *sci_port)
536 if (!sci_port->port.dev)
539 pm_runtime_get_sync(sci_port->port.dev);
541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
548 static void sci_port_disable(struct sci_port *sci_port)
552 if (!sci_port->port.dev)
555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
558 pm_runtime_put_sync(sci_port->port.dev);
561 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
573 static void sci_start_tx(struct uart_port *port)
575 struct sci_port *s = to_sci_port(port);
578 #ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
582 new = scr | SCSCR_TDRQE;
584 new = scr & ~SCSCR_TDRQE;
586 serial_port_out(port, SCSCR, new);
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
592 schedule_work(&s->work_tx);
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
603 static void sci_stop_tx(struct uart_port *port)
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
615 serial_port_out(port, SCSCR, ctrl);
617 #ifdef CONFIG_SERIAL_SH_SCI_DMA
618 if (to_sci_port(port)->chan_tx &&
619 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
620 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
621 to_sci_port(port)->cookie_tx = -EINVAL;
626 static void sci_start_rx(struct uart_port *port)
630 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
632 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
633 ctrl &= ~SCSCR_RDRQE;
635 serial_port_out(port, SCSCR, ctrl);
638 static void sci_stop_rx(struct uart_port *port)
642 ctrl = serial_port_in(port, SCSCR);
644 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
645 ctrl &= ~SCSCR_RDRQE;
647 ctrl &= ~port_rx_irq_mask(port);
649 serial_port_out(port, SCSCR, ctrl);
652 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
654 if (port->type == PORT_SCI) {
655 /* Just store the mask */
656 serial_port_out(port, SCxSR, mask);
657 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
658 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
659 /* Only clear the status bits we want to clear */
660 serial_port_out(port, SCxSR,
661 serial_port_in(port, SCxSR) & mask);
663 /* Store the mask, clear parity/framing errors */
664 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
668 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
669 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
671 #ifdef CONFIG_CONSOLE_POLL
672 static int sci_poll_get_char(struct uart_port *port)
674 unsigned short status;
678 status = serial_port_in(port, SCxSR);
679 if (status & SCxSR_ERRORS(port)) {
680 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
686 if (!(status & SCxSR_RDxF(port)))
689 c = serial_port_in(port, SCxRDR);
692 serial_port_in(port, SCxSR);
693 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
699 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
701 unsigned short status;
704 status = serial_port_in(port, SCxSR);
705 } while (!(status & SCxSR_TDxE(port)));
707 serial_port_out(port, SCxTDR, c);
708 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
710 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
711 CONFIG_SERIAL_SH_SCI_EARLYCON */
713 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
715 struct sci_port *s = to_sci_port(port);
718 * Use port-specific handler if provided.
720 if (s->cfg->ops && s->cfg->ops->init_pins) {
721 s->cfg->ops->init_pins(port, cflag);
725 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
726 u16 data = serial_port_in(port, SCPDR);
727 u16 ctrl = serial_port_in(port, SCPCR);
729 /* Enable RXD and TXD pin functions */
730 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
731 if (to_sci_port(port)->has_rtscts) {
732 /* RTS# is output, active low, unless autorts */
733 if (!(port->mctrl & TIOCM_RTS)) {
736 } else if (!s->autorts) {
740 /* Enable RTS# pin function */
743 /* Enable CTS# pin function */
746 serial_port_out(port, SCPDR, data);
747 serial_port_out(port, SCPCR, ctrl);
748 } else if (sci_getreg(port, SCSPTR)->size) {
749 u16 status = serial_port_in(port, SCSPTR);
751 /* RTS# is always output; and active low, unless autorts */
752 status |= SCSPTR_RTSIO;
753 if (!(port->mctrl & TIOCM_RTS))
754 status |= SCSPTR_RTSDT;
755 else if (!s->autorts)
756 status &= ~SCSPTR_RTSDT;
757 /* CTS# and SCK are inputs */
758 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
759 serial_port_out(port, SCSPTR, status);
763 static int sci_txfill(struct uart_port *port)
765 struct sci_port *s = to_sci_port(port);
766 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
767 const struct plat_sci_reg *reg;
769 reg = sci_getreg(port, SCTFDR);
771 return serial_port_in(port, SCTFDR) & fifo_mask;
773 reg = sci_getreg(port, SCFDR);
775 return serial_port_in(port, SCFDR) >> 8;
777 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
780 static int sci_txroom(struct uart_port *port)
782 return port->fifosize - sci_txfill(port);
785 static int sci_rxfill(struct uart_port *port)
787 struct sci_port *s = to_sci_port(port);
788 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
789 const struct plat_sci_reg *reg;
791 reg = sci_getreg(port, SCRFDR);
793 return serial_port_in(port, SCRFDR) & fifo_mask;
795 reg = sci_getreg(port, SCFDR);
797 return serial_port_in(port, SCFDR) & fifo_mask;
799 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
802 /* ********************************************************************** *
803 * the interrupt related routines *
804 * ********************************************************************** */
806 static void sci_transmit_chars(struct uart_port *port)
808 struct circ_buf *xmit = &port->state->xmit;
809 unsigned int stopped = uart_tx_stopped(port);
810 unsigned short status;
814 status = serial_port_in(port, SCxSR);
815 if (!(status & SCxSR_TDxE(port))) {
816 ctrl = serial_port_in(port, SCSCR);
817 if (uart_circ_empty(xmit))
821 serial_port_out(port, SCSCR, ctrl);
825 count = sci_txroom(port);
833 } else if (!uart_circ_empty(xmit) && !stopped) {
834 c = xmit->buf[xmit->tail];
835 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
840 serial_port_out(port, SCxTDR, c);
843 } while (--count > 0);
845 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
847 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
848 uart_write_wakeup(port);
849 if (uart_circ_empty(xmit))
854 static void sci_receive_chars(struct uart_port *port)
856 struct tty_port *tport = &port->state->port;
857 int i, count, copied = 0;
858 unsigned short status;
861 status = serial_port_in(port, SCxSR);
862 if (!(status & SCxSR_RDxF(port)))
866 /* Don't copy more bytes than there is room for in the buffer */
867 count = tty_buffer_request_room(tport, sci_rxfill(port));
869 /* If for any reason we can't copy more data, we're done! */
873 if (port->type == PORT_SCI) {
874 char c = serial_port_in(port, SCxRDR);
875 if (uart_handle_sysrq_char(port, c))
878 tty_insert_flip_char(tport, c, TTY_NORMAL);
880 for (i = 0; i < count; i++) {
883 if (port->type == PORT_SCIF ||
884 port->type == PORT_HSCIF) {
885 status = serial_port_in(port, SCxSR);
886 c = serial_port_in(port, SCxRDR);
888 c = serial_port_in(port, SCxRDR);
889 status = serial_port_in(port, SCxSR);
891 if (uart_handle_sysrq_char(port, c)) {
896 /* Store data and status */
897 if (status & SCxSR_FER(port)) {
899 port->icount.frame++;
900 } else if (status & SCxSR_PER(port)) {
902 port->icount.parity++;
906 tty_insert_flip_char(tport, c, flag);
910 serial_port_in(port, SCxSR); /* dummy read */
911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
914 port->icount.rx += count;
918 /* Tell the rest of the system the news. New characters! */
919 tty_flip_buffer_push(tport);
921 /* TTY buffers full; read from RX reg to prevent lockup */
922 serial_port_in(port, SCxRDR);
923 serial_port_in(port, SCxSR); /* dummy read */
924 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
928 static int sci_handle_errors(struct uart_port *port)
931 unsigned short status = serial_port_in(port, SCxSR);
932 struct tty_port *tport = &port->state->port;
933 struct sci_port *s = to_sci_port(port);
935 /* Handle overruns */
936 if (status & s->params->overrun_mask) {
937 port->icount.overrun++;
940 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
944 if (status & SCxSR_FER(port)) {
946 port->icount.frame++;
948 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
952 if (status & SCxSR_PER(port)) {
954 port->icount.parity++;
956 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
961 tty_flip_buffer_push(tport);
966 static int sci_handle_fifo_overrun(struct uart_port *port)
968 struct tty_port *tport = &port->state->port;
969 struct sci_port *s = to_sci_port(port);
970 const struct plat_sci_reg *reg;
974 reg = sci_getreg(port, s->params->overrun_reg);
978 status = serial_port_in(port, s->params->overrun_reg);
979 if (status & s->params->overrun_mask) {
980 status &= ~s->params->overrun_mask;
981 serial_port_out(port, s->params->overrun_reg, status);
983 port->icount.overrun++;
985 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
986 tty_flip_buffer_push(tport);
993 static int sci_handle_breaks(struct uart_port *port)
996 unsigned short status = serial_port_in(port, SCxSR);
997 struct tty_port *tport = &port->state->port;
999 if (uart_handle_break(port))
1002 if (status & SCxSR_BRK(port)) {
1005 /* Notify of BREAK */
1006 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1011 tty_flip_buffer_push(tport);
1013 copied += sci_handle_fifo_overrun(port);
1018 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1022 if (rx_trig >= port->fifosize)
1023 rx_trig = port->fifosize - 1;
1027 /* HSCIF can be set to an arbitrary level. */
1028 if (sci_getreg(port, HSRTRGR)->size) {
1029 serial_port_out(port, HSRTRGR, rx_trig);
1033 switch (port->type) {
1038 } else if (rx_trig < 8) {
1041 } else if (rx_trig < 14) {
1045 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1054 } else if (rx_trig < 32) {
1057 } else if (rx_trig < 48) {
1061 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1066 WARN(1, "unknown FIFO configuration");
1070 serial_port_out(port, SCFCR,
1071 (serial_port_in(port, SCFCR) &
1072 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1077 static int scif_rtrg_enabled(struct uart_port *port)
1079 if (sci_getreg(port, HSRTRGR)->size)
1080 return serial_port_in(port, HSRTRGR) != 0;
1082 return (serial_port_in(port, SCFCR) &
1083 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1086 static void rx_fifo_timer_fn(struct timer_list *t)
1088 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1089 struct uart_port *port = &s->port;
1091 dev_dbg(port->dev, "Rx timed out\n");
1092 scif_set_rtrg(port, 1);
1095 static ssize_t rx_fifo_trigger_show(struct device *dev,
1096 struct device_attribute *attr, char *buf)
1098 struct uart_port *port = dev_get_drvdata(dev);
1099 struct sci_port *sci = to_sci_port(port);
1101 return sprintf(buf, "%d\n", sci->rx_trigger);
1104 static ssize_t rx_fifo_trigger_store(struct device *dev,
1105 struct device_attribute *attr,
1106 const char *buf, size_t count)
1108 struct uart_port *port = dev_get_drvdata(dev);
1109 struct sci_port *sci = to_sci_port(port);
1113 ret = kstrtol(buf, 0, &r);
1117 sci->rx_trigger = scif_set_rtrg(port, r);
1118 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1119 scif_set_rtrg(port, 1);
1124 static DEVICE_ATTR_RW(rx_fifo_trigger);
1126 static ssize_t rx_fifo_timeout_show(struct device *dev,
1127 struct device_attribute *attr,
1130 struct uart_port *port = dev_get_drvdata(dev);
1131 struct sci_port *sci = to_sci_port(port);
1134 if (port->type == PORT_HSCIF)
1135 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1137 v = sci->rx_fifo_timeout;
1139 return sprintf(buf, "%d\n", v);
1142 static ssize_t rx_fifo_timeout_store(struct device *dev,
1143 struct device_attribute *attr,
1147 struct uart_port *port = dev_get_drvdata(dev);
1148 struct sci_port *sci = to_sci_port(port);
1152 ret = kstrtol(buf, 0, &r);
1156 if (port->type == PORT_HSCIF) {
1159 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1161 sci->rx_fifo_timeout = r;
1162 scif_set_rtrg(port, 1);
1164 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1170 static DEVICE_ATTR_RW(rx_fifo_timeout);
1173 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1174 static void sci_dma_tx_complete(void *arg)
1176 struct sci_port *s = arg;
1177 struct uart_port *port = &s->port;
1178 struct circ_buf *xmit = &port->state->xmit;
1179 unsigned long flags;
1181 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1183 spin_lock_irqsave(&port->lock, flags);
1185 uart_xmit_advance(port, s->tx_dma_len);
1187 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1188 uart_write_wakeup(port);
1190 if (!uart_circ_empty(xmit)) {
1192 schedule_work(&s->work_tx);
1194 s->cookie_tx = -EINVAL;
1195 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1196 u16 ctrl = serial_port_in(port, SCSCR);
1197 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1201 spin_unlock_irqrestore(&port->lock, flags);
1204 /* Locking: called with port lock held */
1205 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1207 struct uart_port *port = &s->port;
1208 struct tty_port *tport = &port->state->port;
1211 copied = tty_insert_flip_string(tport, buf, count);
1213 port->icount.buf_overrun++;
1215 port->icount.rx += copied;
1220 static int sci_dma_rx_find_active(struct sci_port *s)
1224 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1225 if (s->active_rx == s->cookie_rx[i])
1231 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1236 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1237 s->cookie_rx[i] = -EINVAL;
1241 static void sci_dma_rx_release(struct sci_port *s)
1243 struct dma_chan *chan = s->chan_rx_saved;
1245 s->chan_rx_saved = NULL;
1246 sci_dma_rx_chan_invalidate(s);
1247 dmaengine_terminate_sync(chan);
1248 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1249 sg_dma_address(&s->sg_rx[0]));
1250 dma_release_channel(chan);
1253 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1255 long sec = usec / 1000000;
1256 long nsec = (usec % 1000000) * 1000;
1257 ktime_t t = ktime_set(sec, nsec);
1259 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1262 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1264 struct uart_port *port = &s->port;
1267 /* Direct new serial port interrupts back to CPU */
1268 scr = serial_port_in(port, SCSCR);
1269 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1270 scr &= ~SCSCR_RDRQE;
1271 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1273 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1276 static void sci_dma_rx_complete(void *arg)
1278 struct sci_port *s = arg;
1279 struct dma_chan *chan = s->chan_rx;
1280 struct uart_port *port = &s->port;
1281 struct dma_async_tx_descriptor *desc;
1282 unsigned long flags;
1283 int active, count = 0;
1285 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1288 spin_lock_irqsave(&port->lock, flags);
1290 active = sci_dma_rx_find_active(s);
1292 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1294 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1297 tty_flip_buffer_push(&port->state->port);
1299 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1301 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1305 desc->callback = sci_dma_rx_complete;
1306 desc->callback_param = s;
1307 s->cookie_rx[active] = dmaengine_submit(desc);
1308 if (dma_submit_error(s->cookie_rx[active]))
1311 s->active_rx = s->cookie_rx[!active];
1313 dma_async_issue_pending(chan);
1315 spin_unlock_irqrestore(&port->lock, flags);
1316 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1317 __func__, s->cookie_rx[active], active, s->active_rx);
1321 spin_unlock_irqrestore(&port->lock, flags);
1322 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1324 spin_lock_irqsave(&port->lock, flags);
1325 dmaengine_terminate_async(chan);
1326 sci_dma_rx_chan_invalidate(s);
1327 sci_dma_rx_reenable_irq(s);
1328 spin_unlock_irqrestore(&port->lock, flags);
1331 static void sci_dma_tx_release(struct sci_port *s)
1333 struct dma_chan *chan = s->chan_tx_saved;
1335 cancel_work_sync(&s->work_tx);
1336 s->chan_tx_saved = s->chan_tx = NULL;
1337 s->cookie_tx = -EINVAL;
1338 dmaengine_terminate_sync(chan);
1339 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1341 dma_release_channel(chan);
1344 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1346 struct dma_chan *chan = s->chan_rx;
1347 struct uart_port *port = &s->port;
1348 unsigned long flags;
1351 for (i = 0; i < 2; i++) {
1352 struct scatterlist *sg = &s->sg_rx[i];
1353 struct dma_async_tx_descriptor *desc;
1355 desc = dmaengine_prep_slave_sg(chan,
1356 sg, 1, DMA_DEV_TO_MEM,
1357 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1361 desc->callback = sci_dma_rx_complete;
1362 desc->callback_param = s;
1363 s->cookie_rx[i] = dmaengine_submit(desc);
1364 if (dma_submit_error(s->cookie_rx[i]))
1369 s->active_rx = s->cookie_rx[0];
1371 dma_async_issue_pending(chan);
1376 if (!port_lock_held)
1377 spin_lock_irqsave(&port->lock, flags);
1379 dmaengine_terminate_async(chan);
1380 sci_dma_rx_chan_invalidate(s);
1382 if (!port_lock_held)
1383 spin_unlock_irqrestore(&port->lock, flags);
1387 static void sci_dma_tx_work_fn(struct work_struct *work)
1389 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1390 struct dma_async_tx_descriptor *desc;
1391 struct dma_chan *chan = s->chan_tx;
1392 struct uart_port *port = &s->port;
1393 struct circ_buf *xmit = &port->state->xmit;
1394 unsigned long flags;
1400 * Port xmit buffer is already mapped, and it is one page... Just adjust
1401 * offsets and lengths. Since it is a circular buffer, we have to
1402 * transmit till the end, and then the rest. Take the port lock to get a
1403 * consistent xmit buffer state.
1405 spin_lock_irq(&port->lock);
1408 buf = s->tx_dma_addr + tail;
1409 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE);
1410 if (!s->tx_dma_len) {
1411 /* Transmit buffer has been flushed */
1412 spin_unlock_irq(&port->lock);
1416 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1418 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1420 spin_unlock_irq(&port->lock);
1421 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1425 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1428 desc->callback = sci_dma_tx_complete;
1429 desc->callback_param = s;
1430 s->cookie_tx = dmaengine_submit(desc);
1431 if (dma_submit_error(s->cookie_tx)) {
1432 spin_unlock_irq(&port->lock);
1433 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1437 spin_unlock_irq(&port->lock);
1438 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1439 __func__, xmit->buf, tail, head, s->cookie_tx);
1441 dma_async_issue_pending(chan);
1445 spin_lock_irqsave(&port->lock, flags);
1448 spin_unlock_irqrestore(&port->lock, flags);
1452 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1454 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1455 struct dma_chan *chan = s->chan_rx;
1456 struct uart_port *port = &s->port;
1457 struct dma_tx_state state;
1458 enum dma_status status;
1459 unsigned long flags;
1463 dev_dbg(port->dev, "DMA Rx timed out\n");
1465 spin_lock_irqsave(&port->lock, flags);
1467 active = sci_dma_rx_find_active(s);
1469 spin_unlock_irqrestore(&port->lock, flags);
1470 return HRTIMER_NORESTART;
1473 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1474 if (status == DMA_COMPLETE) {
1475 spin_unlock_irqrestore(&port->lock, flags);
1476 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1477 s->active_rx, active);
1479 /* Let packet complete handler take care of the packet */
1480 return HRTIMER_NORESTART;
1483 dmaengine_pause(chan);
1486 * sometimes DMA transfer doesn't stop even if it is stopped and
1487 * data keeps on coming until transaction is complete so check
1488 * for DMA_COMPLETE again
1489 * Let packet complete handler take care of the packet
1491 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1492 if (status == DMA_COMPLETE) {
1493 spin_unlock_irqrestore(&port->lock, flags);
1494 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1495 return HRTIMER_NORESTART;
1498 /* Handle incomplete DMA receive */
1499 dmaengine_terminate_async(s->chan_rx);
1500 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1503 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1505 tty_flip_buffer_push(&port->state->port);
1508 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1509 sci_dma_rx_submit(s, true);
1511 sci_dma_rx_reenable_irq(s);
1513 spin_unlock_irqrestore(&port->lock, flags);
1515 return HRTIMER_NORESTART;
1518 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1519 enum dma_transfer_direction dir)
1521 struct dma_chan *chan;
1522 struct dma_slave_config cfg;
1525 chan = dma_request_slave_channel(port->dev,
1526 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1528 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1532 memset(&cfg, 0, sizeof(cfg));
1533 cfg.direction = dir;
1534 cfg.dst_addr = port->mapbase +
1535 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1536 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1537 cfg.src_addr = port->mapbase +
1538 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1539 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1541 ret = dmaengine_slave_config(chan, &cfg);
1543 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1544 dma_release_channel(chan);
1551 static void sci_request_dma(struct uart_port *port)
1553 struct sci_port *s = to_sci_port(port);
1554 struct dma_chan *chan;
1556 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1559 * DMA on console may interfere with Kernel log messages which use
1560 * plain putchar(). So, simply don't use it with a console.
1562 if (uart_console(port))
1565 if (!port->dev->of_node)
1568 s->cookie_tx = -EINVAL;
1571 * Don't request a dma channel if no channel was specified
1572 * in the device tree.
1574 if (!of_property_present(port->dev->of_node, "dmas"))
1577 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1578 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1580 /* UART circular tx buffer is an aligned page. */
1581 s->tx_dma_addr = dma_map_single(chan->device->dev,
1582 port->state->xmit.buf,
1585 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1586 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1587 dma_release_channel(chan);
1589 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1590 __func__, UART_XMIT_SIZE,
1591 port->state->xmit.buf, &s->tx_dma_addr);
1593 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1594 s->chan_tx_saved = s->chan_tx = chan;
1598 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1599 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1605 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1606 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1610 "Failed to allocate Rx dma buffer, using PIO\n");
1611 dma_release_channel(chan);
1615 for (i = 0; i < 2; i++) {
1616 struct scatterlist *sg = &s->sg_rx[i];
1618 sg_init_table(sg, 1);
1620 sg_dma_address(sg) = dma;
1621 sg_dma_len(sg) = s->buf_len_rx;
1623 buf += s->buf_len_rx;
1624 dma += s->buf_len_rx;
1627 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1628 s->rx_timer.function = sci_dma_rx_timer_fn;
1630 s->chan_rx_saved = s->chan_rx = chan;
1632 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1633 sci_dma_rx_submit(s, false);
1637 static void sci_free_dma(struct uart_port *port)
1639 struct sci_port *s = to_sci_port(port);
1641 if (s->chan_tx_saved)
1642 sci_dma_tx_release(s);
1643 if (s->chan_rx_saved)
1644 sci_dma_rx_release(s);
1647 static void sci_flush_buffer(struct uart_port *port)
1649 struct sci_port *s = to_sci_port(port);
1652 * In uart_flush_buffer(), the xmit circular buffer has just been
1653 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1658 dmaengine_terminate_async(s->chan_tx);
1659 s->cookie_tx = -EINVAL;
1662 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1663 static inline void sci_request_dma(struct uart_port *port)
1667 static inline void sci_free_dma(struct uart_port *port)
1671 #define sci_flush_buffer NULL
1672 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1674 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1676 struct uart_port *port = ptr;
1677 struct sci_port *s = to_sci_port(port);
1679 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1681 u16 scr = serial_port_in(port, SCSCR);
1682 u16 ssr = serial_port_in(port, SCxSR);
1684 /* Disable future Rx interrupts */
1685 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1686 disable_irq_nosync(irq);
1689 if (sci_dma_rx_submit(s, false) < 0)
1694 serial_port_out(port, SCSCR, scr);
1695 /* Clear current interrupt */
1696 serial_port_out(port, SCxSR,
1697 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1698 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1699 jiffies, s->rx_timeout);
1700 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1708 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1709 if (!scif_rtrg_enabled(port))
1710 scif_set_rtrg(port, s->rx_trigger);
1712 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1713 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1716 /* I think sci_receive_chars has to be called irrespective
1717 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1720 sci_receive_chars(port);
1725 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1727 struct uart_port *port = ptr;
1728 unsigned long flags;
1730 spin_lock_irqsave(&port->lock, flags);
1731 sci_transmit_chars(port);
1732 spin_unlock_irqrestore(&port->lock, flags);
1737 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1739 struct uart_port *port = ptr;
1742 sci_handle_breaks(port);
1744 /* drop invalid character received before break was detected */
1745 serial_port_in(port, SCxRDR);
1747 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1752 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1754 struct uart_port *port = ptr;
1755 struct sci_port *s = to_sci_port(port);
1757 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1758 /* Break and Error interrupts are muxed */
1759 unsigned short ssr_status = serial_port_in(port, SCxSR);
1761 /* Break Interrupt */
1762 if (ssr_status & SCxSR_BRK(port))
1763 sci_br_interrupt(irq, ptr);
1766 if (!(ssr_status & SCxSR_ERRORS(port)))
1771 if (port->type == PORT_SCI) {
1772 if (sci_handle_errors(port)) {
1773 /* discard character in rx buffer */
1774 serial_port_in(port, SCxSR);
1775 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1778 sci_handle_fifo_overrun(port);
1780 sci_receive_chars(port);
1783 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1785 /* Kick the transmission */
1787 sci_tx_interrupt(irq, ptr);
1792 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1794 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1795 struct uart_port *port = ptr;
1796 struct sci_port *s = to_sci_port(port);
1797 irqreturn_t ret = IRQ_NONE;
1799 ssr_status = serial_port_in(port, SCxSR);
1800 scr_status = serial_port_in(port, SCSCR);
1801 if (s->params->overrun_reg == SCxSR)
1802 orer_status = ssr_status;
1803 else if (sci_getreg(port, s->params->overrun_reg)->size)
1804 orer_status = serial_port_in(port, s->params->overrun_reg);
1806 err_enabled = scr_status & port_rx_irq_mask(port);
1809 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1811 ret = sci_tx_interrupt(irq, ptr);
1814 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1817 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1818 (scr_status & SCSCR_RIE))
1819 ret = sci_rx_interrupt(irq, ptr);
1821 /* Error Interrupt */
1822 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1823 ret = sci_er_interrupt(irq, ptr);
1825 /* Break Interrupt */
1826 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1827 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1828 ret = sci_br_interrupt(irq, ptr);
1830 /* Overrun Interrupt */
1831 if (orer_status & s->params->overrun_mask) {
1832 sci_handle_fifo_overrun(port);
1839 static const struct sci_irq_desc {
1841 irq_handler_t handler;
1842 } sci_irq_desc[] = {
1844 * Split out handlers, the default case.
1848 .handler = sci_er_interrupt,
1853 .handler = sci_rx_interrupt,
1858 .handler = sci_tx_interrupt,
1863 .handler = sci_br_interrupt,
1868 .handler = sci_rx_interrupt,
1873 .handler = sci_tx_interrupt,
1877 * Special muxed handler.
1881 .handler = sci_mpxed_interrupt,
1885 static int sci_request_irq(struct sci_port *port)
1887 struct uart_port *up = &port->port;
1888 int i, j, w, ret = 0;
1890 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1891 const struct sci_irq_desc *desc;
1894 /* Check if already registered (muxed) */
1895 for (w = 0; w < i; w++)
1896 if (port->irqs[w] == port->irqs[i])
1901 if (SCIx_IRQ_IS_MUXED(port)) {
1905 irq = port->irqs[i];
1908 * Certain port types won't support all of the
1909 * available interrupt sources.
1911 if (unlikely(irq < 0))
1915 desc = sci_irq_desc + i;
1916 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1917 dev_name(up->dev), desc->desc);
1918 if (!port->irqstr[j]) {
1923 ret = request_irq(irq, desc->handler, up->irqflags,
1924 port->irqstr[j], port);
1925 if (unlikely(ret)) {
1926 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1935 free_irq(port->irqs[i], port);
1939 kfree(port->irqstr[j]);
1944 static void sci_free_irq(struct sci_port *port)
1949 * Intentionally in reverse order so we iterate over the muxed
1952 for (i = 0; i < SCIx_NR_IRQS; i++) {
1953 int irq = port->irqs[i];
1956 * Certain port types won't support all of the available
1957 * interrupt sources.
1959 if (unlikely(irq < 0))
1962 /* Check if already freed (irq was muxed) */
1963 for (j = 0; j < i; j++)
1964 if (port->irqs[j] == irq)
1969 free_irq(port->irqs[i], port);
1970 kfree(port->irqstr[i]);
1972 if (SCIx_IRQ_IS_MUXED(port)) {
1973 /* If there's only one IRQ, we're done. */
1979 static unsigned int sci_tx_empty(struct uart_port *port)
1981 unsigned short status = serial_port_in(port, SCxSR);
1982 unsigned short in_tx_fifo = sci_txfill(port);
1984 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1987 static void sci_set_rts(struct uart_port *port, bool state)
1989 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1990 u16 data = serial_port_in(port, SCPDR);
1994 data &= ~SCPDR_RTSD;
1997 serial_port_out(port, SCPDR, data);
1999 /* RTS# is output */
2000 serial_port_out(port, SCPCR,
2001 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2002 } else if (sci_getreg(port, SCSPTR)->size) {
2003 u16 ctrl = serial_port_in(port, SCSPTR);
2007 ctrl &= ~SCSPTR_RTSDT;
2009 ctrl |= SCSPTR_RTSDT;
2010 serial_port_out(port, SCSPTR, ctrl);
2014 static bool sci_get_cts(struct uart_port *port)
2016 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2018 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2019 } else if (sci_getreg(port, SCSPTR)->size) {
2021 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2028 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2029 * CTS/RTS is supported in hardware by at least one port and controlled
2030 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2031 * handled via the ->init_pins() op, which is a bit of a one-way street,
2032 * lacking any ability to defer pin control -- this will later be
2033 * converted over to the GPIO framework).
2035 * Other modes (such as loopback) are supported generically on certain
2036 * port types, but not others. For these it's sufficient to test for the
2037 * existence of the support register and simply ignore the port type.
2039 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2041 struct sci_port *s = to_sci_port(port);
2043 if (mctrl & TIOCM_LOOP) {
2044 const struct plat_sci_reg *reg;
2047 * Standard loopback mode for SCFCR ports.
2049 reg = sci_getreg(port, SCFCR);
2051 serial_port_out(port, SCFCR,
2052 serial_port_in(port, SCFCR) |
2056 mctrl_gpio_set(s->gpios, mctrl);
2061 if (!(mctrl & TIOCM_RTS)) {
2062 /* Disable Auto RTS */
2063 serial_port_out(port, SCFCR,
2064 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2067 sci_set_rts(port, 0);
2068 } else if (s->autorts) {
2069 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2070 /* Enable RTS# pin function */
2071 serial_port_out(port, SCPCR,
2072 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2075 /* Enable Auto RTS */
2076 serial_port_out(port, SCFCR,
2077 serial_port_in(port, SCFCR) | SCFCR_MCE);
2080 sci_set_rts(port, 1);
2084 static unsigned int sci_get_mctrl(struct uart_port *port)
2086 struct sci_port *s = to_sci_port(port);
2087 struct mctrl_gpios *gpios = s->gpios;
2088 unsigned int mctrl = 0;
2090 mctrl_gpio_get(gpios, &mctrl);
2093 * CTS/RTS is handled in hardware when supported, while nothing
2097 if (sci_get_cts(port))
2099 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2102 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2104 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2110 static void sci_enable_ms(struct uart_port *port)
2112 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2115 static void sci_break_ctl(struct uart_port *port, int break_state)
2117 unsigned short scscr, scsptr;
2118 unsigned long flags;
2120 /* check whether the port has SCSPTR */
2121 if (!sci_getreg(port, SCSPTR)->size) {
2123 * Not supported by hardware. Most parts couple break and rx
2124 * interrupts together, with break detection always enabled.
2129 spin_lock_irqsave(&port->lock, flags);
2130 scsptr = serial_port_in(port, SCSPTR);
2131 scscr = serial_port_in(port, SCSCR);
2133 if (break_state == -1) {
2134 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2137 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2141 serial_port_out(port, SCSPTR, scsptr);
2142 serial_port_out(port, SCSCR, scscr);
2143 spin_unlock_irqrestore(&port->lock, flags);
2146 static int sci_startup(struct uart_port *port)
2148 struct sci_port *s = to_sci_port(port);
2151 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2153 sci_request_dma(port);
2155 ret = sci_request_irq(s);
2156 if (unlikely(ret < 0)) {
2164 static void sci_shutdown(struct uart_port *port)
2166 struct sci_port *s = to_sci_port(port);
2167 unsigned long flags;
2170 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2173 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2175 spin_lock_irqsave(&port->lock, flags);
2179 * Stop RX and TX, disable related interrupts, keep clock source
2180 * and HSCIF TOT bits
2182 scr = serial_port_in(port, SCSCR);
2183 serial_port_out(port, SCSCR, scr &
2184 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2185 spin_unlock_irqrestore(&port->lock, flags);
2187 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2188 if (s->chan_rx_saved) {
2189 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2191 hrtimer_cancel(&s->rx_timer);
2195 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2196 del_timer_sync(&s->rx_fifo_timer);
2201 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2204 unsigned long freq = s->clk_rates[SCI_SCK];
2205 int err, min_err = INT_MAX;
2208 if (s->port.type != PORT_HSCIF)
2211 for_each_sr(sr, s) {
2212 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2213 if (abs(err) >= abs(min_err))
2223 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2228 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2229 unsigned long freq, unsigned int *dlr,
2232 int err, min_err = INT_MAX;
2233 unsigned int sr, dl;
2235 if (s->port.type != PORT_HSCIF)
2238 for_each_sr(sr, s) {
2239 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2240 dl = clamp(dl, 1U, 65535U);
2242 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2243 if (abs(err) >= abs(min_err))
2254 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2255 min_err, *dlr, *srr + 1);
2259 /* calculate sample rate, BRR, and clock select */
2260 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2261 unsigned int *brr, unsigned int *srr,
2264 unsigned long freq = s->clk_rates[SCI_FCK];
2265 unsigned int sr, br, prediv, scrate, c;
2266 int err, min_err = INT_MAX;
2268 if (s->port.type != PORT_HSCIF)
2272 * Find the combination of sample rate and clock select with the
2273 * smallest deviation from the desired baud rate.
2274 * Prefer high sample rates to maximise the receive margin.
2276 * M: Receive margin (%)
2277 * N: Ratio of bit rate to clock (N = sampling rate)
2278 * D: Clock duty (D = 0 to 1.0)
2279 * L: Frame length (L = 9 to 12)
2280 * F: Absolute value of clock frequency deviation
2282 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2283 * (|D - 0.5| / N * (1 + F))|
2284 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2286 for_each_sr(sr, s) {
2287 for (c = 0; c <= 3; c++) {
2288 /* integerized formulas from HSCIF documentation */
2289 prediv = sr << (2 * c + 1);
2292 * We need to calculate:
2294 * br = freq / (prediv * bps) clamped to [1..256]
2295 * err = freq / (br * prediv) - bps
2297 * Watch out for overflow when calculating the desired
2298 * sampling clock rate!
2300 if (bps > UINT_MAX / prediv)
2303 scrate = prediv * bps;
2304 br = DIV_ROUND_CLOSEST(freq, scrate);
2305 br = clamp(br, 1U, 256U);
2307 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2308 if (abs(err) >= abs(min_err))
2322 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2323 min_err, *brr, *srr + 1, *cks);
2327 static void sci_reset(struct uart_port *port)
2329 const struct plat_sci_reg *reg;
2330 unsigned int status;
2331 struct sci_port *s = to_sci_port(port);
2333 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2335 reg = sci_getreg(port, SCFCR);
2337 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2339 sci_clear_SCxSR(port,
2340 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2341 SCxSR_BREAK_CLEAR(port));
2342 if (sci_getreg(port, SCLSR)->size) {
2343 status = serial_port_in(port, SCLSR);
2344 status &= ~(SCLSR_TO | SCLSR_ORER);
2345 serial_port_out(port, SCLSR, status);
2348 if (s->rx_trigger > 1) {
2349 if (s->rx_fifo_timeout) {
2350 scif_set_rtrg(port, 1);
2351 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2353 if (port->type == PORT_SCIFA ||
2354 port->type == PORT_SCIFB)
2355 scif_set_rtrg(port, 1);
2357 scif_set_rtrg(port, s->rx_trigger);
2362 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2363 const struct ktermios *old)
2365 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2366 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2367 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2368 struct sci_port *s = to_sci_port(port);
2369 const struct plat_sci_reg *reg;
2370 int min_err = INT_MAX, err;
2371 unsigned long max_freq = 0;
2373 unsigned long flags;
2375 if ((termios->c_cflag & CSIZE) == CS7) {
2376 smr_val |= SCSMR_CHR;
2378 termios->c_cflag &= ~CSIZE;
2379 termios->c_cflag |= CS8;
2381 if (termios->c_cflag & PARENB)
2382 smr_val |= SCSMR_PE;
2383 if (termios->c_cflag & PARODD)
2384 smr_val |= SCSMR_PE | SCSMR_ODD;
2385 if (termios->c_cflag & CSTOPB)
2386 smr_val |= SCSMR_STOP;
2389 * earlyprintk comes here early on with port->uartclk set to zero.
2390 * the clock framework is not up and running at this point so here
2391 * we assume that 115200 is the maximum baud rate. please note that
2392 * the baud rate is not programmed during earlyprintk - it is assumed
2393 * that the previous boot loader has enabled required clocks and
2394 * setup the baud rate generator hardware for us already.
2396 if (!port->uartclk) {
2397 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2401 for (i = 0; i < SCI_NUM_CLKS; i++)
2402 max_freq = max(max_freq, s->clk_rates[i]);
2404 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2409 * There can be multiple sources for the sampling clock. Find the one
2410 * that gives us the smallest deviation from the desired baud rate.
2413 /* Optional Undivided External Clock */
2414 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2415 port->type != PORT_SCIFB) {
2416 err = sci_sck_calc(s, baud, &srr1);
2417 if (abs(err) < abs(min_err)) {
2419 scr_val = SCSCR_CKE1;
2428 /* Optional BRG Frequency Divided External Clock */
2429 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2430 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2432 if (abs(err) < abs(min_err)) {
2433 best_clk = SCI_SCIF_CLK;
2434 scr_val = SCSCR_CKE1;
2444 /* Optional BRG Frequency Divided Internal Clock */
2445 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2446 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2448 if (abs(err) < abs(min_err)) {
2449 best_clk = SCI_BRG_INT;
2450 scr_val = SCSCR_CKE1;
2460 /* Divided Functional Clock using standard Bit Rate Register */
2461 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2462 if (abs(err) < abs(min_err)) {
2473 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2474 s->clks[best_clk], baud, min_err);
2479 * Program the optional External Baud Rate Generator (BRG) first.
2480 * It controls the mux to select (H)SCK or frequency divided clock.
2482 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2483 serial_port_out(port, SCDL, dl);
2484 serial_port_out(port, SCCKS, sccks);
2487 spin_lock_irqsave(&port->lock, flags);
2491 uart_update_timeout(port, termios->c_cflag, baud);
2493 /* byte size and parity */
2494 bits = tty_get_frame_size(termios->c_cflag);
2496 if (sci_getreg(port, SEMR)->size)
2497 serial_port_out(port, SEMR, 0);
2499 if (best_clk >= 0) {
2500 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2502 case 5: smr_val |= SCSMR_SRC_5; break;
2503 case 7: smr_val |= SCSMR_SRC_7; break;
2504 case 11: smr_val |= SCSMR_SRC_11; break;
2505 case 13: smr_val |= SCSMR_SRC_13; break;
2506 case 16: smr_val |= SCSMR_SRC_16; break;
2507 case 17: smr_val |= SCSMR_SRC_17; break;
2508 case 19: smr_val |= SCSMR_SRC_19; break;
2509 case 27: smr_val |= SCSMR_SRC_27; break;
2512 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2513 serial_port_out(port, SCSMR, smr_val);
2514 serial_port_out(port, SCBRR, brr);
2515 if (sci_getreg(port, HSSRR)->size) {
2516 unsigned int hssrr = srr | HSCIF_SRE;
2517 /* Calculate deviation from intended rate at the
2518 * center of the last stop bit in sampling clocks.
2520 int last_stop = bits * 2 - 1;
2521 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2525 if (abs(deviation) >= 2) {
2526 /* At least two sampling clocks off at the
2527 * last stop bit; we can increase the error
2528 * margin by shifting the sampling point.
2530 int shift = clamp(deviation / 2, -8, 7);
2532 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2534 hssrr |= HSCIF_SRDE;
2536 serial_port_out(port, HSSRR, hssrr);
2539 /* Wait one bit interval */
2540 udelay((1000000 + (baud - 1)) / baud);
2542 /* Don't touch the bit rate configuration */
2543 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2544 smr_val |= serial_port_in(port, SCSMR) &
2545 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2546 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2547 serial_port_out(port, SCSMR, smr_val);
2550 sci_init_pins(port, termios->c_cflag);
2552 port->status &= ~UPSTAT_AUTOCTS;
2554 reg = sci_getreg(port, SCFCR);
2556 unsigned short ctrl = serial_port_in(port, SCFCR);
2558 if ((port->flags & UPF_HARD_FLOW) &&
2559 (termios->c_cflag & CRTSCTS)) {
2560 /* There is no CTS interrupt to restart the hardware */
2561 port->status |= UPSTAT_AUTOCTS;
2562 /* MCE is enabled when RTS is raised */
2567 * As we've done a sci_reset() above, ensure we don't
2568 * interfere with the FIFOs while toggling MCE. As the
2569 * reset values could still be set, simply mask them out.
2571 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2573 serial_port_out(port, SCFCR, ctrl);
2575 if (port->flags & UPF_HARD_FLOW) {
2576 /* Refresh (Auto) RTS */
2577 sci_set_mctrl(port, port->mctrl);
2580 scr_val |= SCSCR_RE | SCSCR_TE |
2581 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2582 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2583 if ((srr + 1 == 5) &&
2584 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2586 * In asynchronous mode, when the sampling rate is 1/5, first
2587 * received data may become invalid on some SCIFA and SCIFB.
2588 * To avoid this problem wait more than 1 serial data time (1
2589 * bit time x serial data number) after setting SCSCR.RE = 1.
2591 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2594 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2595 s->rx_frame = (10000 * bits) / (baud / 100);
2596 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2597 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2600 if ((termios->c_cflag & CREAD) != 0)
2603 spin_unlock_irqrestore(&port->lock, flags);
2605 sci_port_disable(s);
2607 if (UART_ENABLE_MS(port, termios->c_cflag))
2608 sci_enable_ms(port);
2611 static void sci_pm(struct uart_port *port, unsigned int state,
2612 unsigned int oldstate)
2614 struct sci_port *sci_port = to_sci_port(port);
2617 case UART_PM_STATE_OFF:
2618 sci_port_disable(sci_port);
2621 sci_port_enable(sci_port);
2626 static const char *sci_type(struct uart_port *port)
2628 switch (port->type) {
2646 static int sci_remap_port(struct uart_port *port)
2648 struct sci_port *sport = to_sci_port(port);
2651 * Nothing to do if there's already an established membase.
2656 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2657 port->membase = ioremap(port->mapbase, sport->reg_size);
2658 if (unlikely(!port->membase)) {
2659 dev_err(port->dev, "can't remap port#%d\n", port->line);
2664 * For the simple (and majority of) cases where we don't
2665 * need to do any remapping, just cast the cookie
2668 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2674 static void sci_release_port(struct uart_port *port)
2676 struct sci_port *sport = to_sci_port(port);
2678 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2679 iounmap(port->membase);
2680 port->membase = NULL;
2683 release_mem_region(port->mapbase, sport->reg_size);
2686 static int sci_request_port(struct uart_port *port)
2688 struct resource *res;
2689 struct sci_port *sport = to_sci_port(port);
2692 res = request_mem_region(port->mapbase, sport->reg_size,
2693 dev_name(port->dev));
2694 if (unlikely(res == NULL)) {
2695 dev_err(port->dev, "request_mem_region failed.");
2699 ret = sci_remap_port(port);
2700 if (unlikely(ret != 0)) {
2701 release_resource(res);
2708 static void sci_config_port(struct uart_port *port, int flags)
2710 if (flags & UART_CONFIG_TYPE) {
2711 struct sci_port *sport = to_sci_port(port);
2713 port->type = sport->cfg->type;
2714 sci_request_port(port);
2718 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2720 if (ser->baud_base < 2400)
2721 /* No paper tape reader for Mitch.. */
2727 static const struct uart_ops sci_uart_ops = {
2728 .tx_empty = sci_tx_empty,
2729 .set_mctrl = sci_set_mctrl,
2730 .get_mctrl = sci_get_mctrl,
2731 .start_tx = sci_start_tx,
2732 .stop_tx = sci_stop_tx,
2733 .stop_rx = sci_stop_rx,
2734 .enable_ms = sci_enable_ms,
2735 .break_ctl = sci_break_ctl,
2736 .startup = sci_startup,
2737 .shutdown = sci_shutdown,
2738 .flush_buffer = sci_flush_buffer,
2739 .set_termios = sci_set_termios,
2742 .release_port = sci_release_port,
2743 .request_port = sci_request_port,
2744 .config_port = sci_config_port,
2745 .verify_port = sci_verify_port,
2746 #ifdef CONFIG_CONSOLE_POLL
2747 .poll_get_char = sci_poll_get_char,
2748 .poll_put_char = sci_poll_put_char,
2752 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2754 const char *clk_names[] = {
2757 [SCI_BRG_INT] = "brg_int",
2758 [SCI_SCIF_CLK] = "scif_clk",
2763 if (sci_port->cfg->type == PORT_HSCIF)
2764 clk_names[SCI_SCK] = "hsck";
2766 for (i = 0; i < SCI_NUM_CLKS; i++) {
2767 clk = devm_clk_get_optional(dev, clk_names[i]);
2769 return PTR_ERR(clk);
2771 if (!clk && i == SCI_FCK) {
2773 * Not all SH platforms declare a clock lookup entry
2774 * for SCI devices, in which case we need to get the
2775 * global "peripheral_clk" clock.
2777 clk = devm_clk_get(dev, "peripheral_clk");
2779 return dev_err_probe(dev, PTR_ERR(clk),
2780 "failed to get %s\n",
2785 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2787 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2788 clk, clk_get_rate(clk));
2789 sci_port->clks[i] = clk;
2794 static const struct sci_port_params *
2795 sci_probe_regmap(const struct plat_sci_port *cfg)
2797 unsigned int regtype;
2799 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2800 return &sci_port_params[cfg->regtype];
2802 switch (cfg->type) {
2804 regtype = SCIx_SCI_REGTYPE;
2807 regtype = SCIx_IRDA_REGTYPE;
2810 regtype = SCIx_SCIFA_REGTYPE;
2813 regtype = SCIx_SCIFB_REGTYPE;
2817 * The SH-4 is a bit of a misnomer here, although that's
2818 * where this particular port layout originated. This
2819 * configuration (or some slight variation thereof)
2820 * remains the dominant model for all SCIFs.
2822 regtype = SCIx_SH4_SCIF_REGTYPE;
2825 regtype = SCIx_HSCIF_REGTYPE;
2828 pr_err("Can't probe register map for given port\n");
2832 return &sci_port_params[regtype];
2835 static int sci_init_single(struct platform_device *dev,
2836 struct sci_port *sci_port, unsigned int index,
2837 const struct plat_sci_port *p, bool early)
2839 struct uart_port *port = &sci_port->port;
2840 const struct resource *res;
2846 port->ops = &sci_uart_ops;
2847 port->iotype = UPIO_MEM;
2849 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2851 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2855 port->mapbase = res->start;
2856 sci_port->reg_size = resource_size(res);
2858 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2860 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2862 sci_port->irqs[i] = platform_get_irq(dev, i);
2866 * The fourth interrupt on SCI port is transmit end interrupt, so
2867 * shuffle the interrupts.
2869 if (p->type == PORT_SCI)
2870 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
2872 /* The SCI generates several interrupts. They can be muxed together or
2873 * connected to different interrupt lines. In the muxed case only one
2874 * interrupt resource is specified as there is only one interrupt ID.
2875 * In the non-muxed case, up to 6 interrupt signals might be generated
2876 * from the SCI, however those signals might have their own individual
2877 * interrupt ID numbers, or muxed together with another interrupt.
2879 if (sci_port->irqs[0] < 0)
2882 if (sci_port->irqs[1] < 0)
2883 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2884 sci_port->irqs[i] = sci_port->irqs[0];
2886 sci_port->params = sci_probe_regmap(p);
2887 if (unlikely(sci_port->params == NULL))
2892 sci_port->rx_trigger = 48;
2895 sci_port->rx_trigger = 64;
2898 sci_port->rx_trigger = 32;
2901 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2902 /* RX triggering not implemented for this IP */
2903 sci_port->rx_trigger = 1;
2905 sci_port->rx_trigger = 8;
2908 sci_port->rx_trigger = 1;
2912 sci_port->rx_fifo_timeout = 0;
2913 sci_port->hscif_tot = 0;
2915 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2916 * match the SoC datasheet, this should be investigated. Let platform
2917 * data override the sampling rate for now.
2919 sci_port->sampling_rate_mask = p->sampling_rate
2920 ? SCI_SR(p->sampling_rate)
2921 : sci_port->params->sampling_rate_mask;
2924 ret = sci_init_clocks(sci_port, &dev->dev);
2928 port->dev = &dev->dev;
2930 pm_runtime_enable(&dev->dev);
2933 port->type = p->type;
2934 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2935 port->fifosize = sci_port->params->fifosize;
2937 if (port->type == PORT_SCI && !dev->dev.of_node) {
2938 if (sci_port->reg_size >= 0x20)
2945 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2946 * for the multi-IRQ ports, which is where we are primarily
2947 * concerned with the shutdown path synchronization.
2949 * For the muxed case there's nothing more to do.
2951 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2954 port->serial_in = sci_serial_in;
2955 port->serial_out = sci_serial_out;
2960 static void sci_cleanup_single(struct sci_port *port)
2962 pm_runtime_disable(port->port.dev);
2965 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2966 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2967 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
2969 sci_poll_put_char(port, ch);
2973 * Print a string to the serial port trying not to disturb
2974 * any possible real use of the port...
2976 static void serial_console_write(struct console *co, const char *s,
2979 struct sci_port *sci_port = &sci_ports[co->index];
2980 struct uart_port *port = &sci_port->port;
2981 unsigned short bits, ctrl, ctrl_temp;
2982 unsigned long flags;
2987 else if (oops_in_progress)
2988 locked = spin_trylock_irqsave(&port->lock, flags);
2990 spin_lock_irqsave(&port->lock, flags);
2992 /* first save SCSCR then disable interrupts, keep clock source */
2993 ctrl = serial_port_in(port, SCSCR);
2994 ctrl_temp = SCSCR_RE | SCSCR_TE |
2995 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2996 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2997 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
2999 uart_console_write(port, s, count, serial_console_putchar);
3001 /* wait until fifo is empty and last bit has been transmitted */
3002 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3003 while ((serial_port_in(port, SCxSR) & bits) != bits)
3006 /* restore the SCSCR */
3007 serial_port_out(port, SCSCR, ctrl);
3010 spin_unlock_irqrestore(&port->lock, flags);
3013 static int serial_console_setup(struct console *co, char *options)
3015 struct sci_port *sci_port;
3016 struct uart_port *port;
3024 * Refuse to handle any bogus ports.
3026 if (co->index < 0 || co->index >= SCI_NPORTS)
3029 sci_port = &sci_ports[co->index];
3030 port = &sci_port->port;
3033 * Refuse to handle uninitialized ports.
3038 ret = sci_remap_port(port);
3039 if (unlikely(ret != 0))
3043 uart_parse_options(options, &baud, &parity, &bits, &flow);
3045 return uart_set_options(port, co, baud, parity, bits, flow);
3048 static struct console serial_console = {
3050 .device = uart_console_device,
3051 .write = serial_console_write,
3052 .setup = serial_console_setup,
3053 .flags = CON_PRINTBUFFER,
3055 .data = &sci_uart_driver,
3058 #ifdef CONFIG_SUPERH
3059 static char early_serial_buf[32];
3061 static int early_serial_console_setup(struct console *co, char *options)
3064 * This early console is always registered using the earlyprintk=
3065 * parameter, which does not call add_preferred_console(). Thus
3066 * @options is always NULL and the options for this early console
3067 * are passed using a custom buffer.
3071 return serial_console_setup(co, early_serial_buf);
3074 static struct console early_serial_console = {
3075 .name = "early_ttySC",
3076 .write = serial_console_write,
3077 .setup = early_serial_console_setup,
3078 .flags = CON_PRINTBUFFER,
3082 static int sci_probe_earlyprintk(struct platform_device *pdev)
3084 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3086 if (early_serial_console.data)
3089 early_serial_console.index = pdev->id;
3091 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3093 if (!strstr(early_serial_buf, "keep"))
3094 early_serial_console.flags |= CON_BOOT;
3096 register_console(&early_serial_console);
3101 #define SCI_CONSOLE (&serial_console)
3104 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3109 #define SCI_CONSOLE NULL
3111 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3113 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3115 static DEFINE_MUTEX(sci_uart_registration_lock);
3116 static struct uart_driver sci_uart_driver = {
3117 .owner = THIS_MODULE,
3118 .driver_name = "sci",
3119 .dev_name = "ttySC",
3121 .minor = SCI_MINOR_START,
3123 .cons = SCI_CONSOLE,
3126 static int sci_remove(struct platform_device *dev)
3128 struct sci_port *port = platform_get_drvdata(dev);
3129 unsigned int type = port->port.type; /* uart_remove_... clears it */
3131 sci_ports_in_use &= ~BIT(port->port.line);
3132 uart_remove_one_port(&sci_uart_driver, &port->port);
3134 sci_cleanup_single(port);
3136 if (port->port.fifosize > 1)
3137 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3138 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3139 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3145 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3146 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3147 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3149 static const struct of_device_id of_sci_match[] __maybe_unused = {
3150 /* SoC-specific types */
3152 .compatible = "renesas,scif-r7s72100",
3153 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3156 .compatible = "renesas,scif-r7s9210",
3157 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3160 .compatible = "renesas,scif-r9a07g044",
3161 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3163 /* Family-specific types */
3165 .compatible = "renesas,rcar-gen1-scif",
3166 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3168 .compatible = "renesas,rcar-gen2-scif",
3169 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3171 .compatible = "renesas,rcar-gen3-scif",
3172 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3174 .compatible = "renesas,rcar-gen4-scif",
3175 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3179 .compatible = "renesas,scif",
3180 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3182 .compatible = "renesas,scifa",
3183 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3185 .compatible = "renesas,scifb",
3186 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3188 .compatible = "renesas,hscif",
3189 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3191 .compatible = "renesas,sci",
3192 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3197 MODULE_DEVICE_TABLE(of, of_sci_match);
3199 static void sci_reset_control_assert(void *data)
3201 reset_control_assert(data);
3204 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3205 unsigned int *dev_id)
3207 struct device_node *np = pdev->dev.of_node;
3208 struct reset_control *rstc;
3209 struct plat_sci_port *p;
3210 struct sci_port *sp;
3214 if (!IS_ENABLED(CONFIG_OF) || !np)
3215 return ERR_PTR(-EINVAL);
3217 data = of_device_get_match_data(&pdev->dev);
3219 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3221 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3222 "failed to get reset ctrl\n"));
3224 ret = reset_control_deassert(rstc);
3226 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3227 return ERR_PTR(ret);
3230 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3232 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3234 return ERR_PTR(ret);
3237 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3239 return ERR_PTR(-ENOMEM);
3241 /* Get the line number from the aliases node. */
3242 id = of_alias_get_id(np, "serial");
3243 if (id < 0 && ~sci_ports_in_use)
3244 id = ffz(sci_ports_in_use);
3246 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3247 return ERR_PTR(-EINVAL);
3249 if (id >= ARRAY_SIZE(sci_ports)) {
3250 dev_err(&pdev->dev, "serial%d out of range\n", id);
3251 return ERR_PTR(-EINVAL);
3254 sp = &sci_ports[id];
3257 p->type = SCI_OF_TYPE(data);
3258 p->regtype = SCI_OF_REGTYPE(data);
3260 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3265 static int sci_probe_single(struct platform_device *dev,
3267 struct plat_sci_port *p,
3268 struct sci_port *sciport)
3273 if (unlikely(index >= SCI_NPORTS)) {
3274 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3275 index+1, SCI_NPORTS);
3276 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3279 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3280 if (sci_ports_in_use & BIT(index))
3283 mutex_lock(&sci_uart_registration_lock);
3284 if (!sci_uart_driver.state) {
3285 ret = uart_register_driver(&sci_uart_driver);
3287 mutex_unlock(&sci_uart_registration_lock);
3291 mutex_unlock(&sci_uart_registration_lock);
3293 ret = sci_init_single(dev, sciport, index, p, false);
3297 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3298 if (IS_ERR(sciport->gpios))
3299 return PTR_ERR(sciport->gpios);
3301 if (sciport->has_rtscts) {
3302 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3303 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3304 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3307 sciport->port.flags |= UPF_HARD_FLOW;
3310 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3312 sci_cleanup_single(sciport);
3319 static int sci_probe(struct platform_device *dev)
3321 struct plat_sci_port *p;
3322 struct sci_port *sp;
3323 unsigned int dev_id;
3327 * If we've come here via earlyprintk initialization, head off to
3328 * the special early probe. We don't have sufficient device state
3329 * to make it beyond this yet.
3331 #ifdef CONFIG_SUPERH
3332 if (is_sh_early_platform_device(dev))
3333 return sci_probe_earlyprintk(dev);
3336 if (dev->dev.of_node) {
3337 p = sci_parse_dt(dev, &dev_id);
3341 p = dev->dev.platform_data;
3343 dev_err(&dev->dev, "no platform data supplied\n");
3350 sp = &sci_ports[dev_id];
3351 platform_set_drvdata(dev, sp);
3353 ret = sci_probe_single(dev, dev_id, p, sp);
3357 if (sp->port.fifosize > 1) {
3358 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3362 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3363 sp->port.type == PORT_HSCIF) {
3364 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3366 if (sp->port.fifosize > 1) {
3367 device_remove_file(&dev->dev,
3368 &dev_attr_rx_fifo_trigger);
3374 #ifdef CONFIG_SH_STANDARD_BIOS
3375 sh_bios_gdb_detach();
3378 sci_ports_in_use |= BIT(dev_id);
3382 static __maybe_unused int sci_suspend(struct device *dev)
3384 struct sci_port *sport = dev_get_drvdata(dev);
3387 uart_suspend_port(&sci_uart_driver, &sport->port);
3392 static __maybe_unused int sci_resume(struct device *dev)
3394 struct sci_port *sport = dev_get_drvdata(dev);
3397 uart_resume_port(&sci_uart_driver, &sport->port);
3402 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3404 static struct platform_driver sci_driver = {
3406 .remove = sci_remove,
3409 .pm = &sci_dev_pm_ops,
3410 .of_match_table = of_match_ptr(of_sci_match),
3414 static int __init sci_init(void)
3416 pr_info("%s\n", banner);
3418 return platform_driver_register(&sci_driver);
3421 static void __exit sci_exit(void)
3423 platform_driver_unregister(&sci_driver);
3425 if (sci_uart_driver.state)
3426 uart_unregister_driver(&sci_uart_driver);
3429 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3430 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3431 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3433 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3434 static struct plat_sci_port port_cfg __initdata;
3436 static int __init early_console_setup(struct earlycon_device *device,
3439 if (!device->port.membase)
3442 device->port.serial_in = sci_serial_in;
3443 device->port.serial_out = sci_serial_out;
3444 device->port.type = type;
3445 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3446 port_cfg.type = type;
3447 sci_ports[0].cfg = &port_cfg;
3448 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3449 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3450 sci_serial_out(&sci_ports[0].port, SCSCR,
3451 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3453 device->con->write = serial_console_write;
3456 static int __init sci_early_console_setup(struct earlycon_device *device,
3459 return early_console_setup(device, PORT_SCI);
3461 static int __init scif_early_console_setup(struct earlycon_device *device,
3464 return early_console_setup(device, PORT_SCIF);
3466 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3469 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3470 return early_console_setup(device, PORT_SCIF);
3473 static int __init scifa_early_console_setup(struct earlycon_device *device,
3476 return early_console_setup(device, PORT_SCIFA);
3478 static int __init scifb_early_console_setup(struct earlycon_device *device,
3481 return early_console_setup(device, PORT_SCIFB);
3483 static int __init hscif_early_console_setup(struct earlycon_device *device,
3486 return early_console_setup(device, PORT_HSCIF);
3489 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3490 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3491 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3492 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3493 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3494 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3495 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3496 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3498 module_init(sci_init);
3499 module_exit(sci_exit);
3501 MODULE_LICENSE("GPL");
3502 MODULE_ALIAS("platform:sh-sci");
3503 MODULE_AUTHOR("Paul Mundt");
3504 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");