4 * High-speed serial driver for NVIDIA Tegra SoCs
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/clk.h>
24 #include <linux/debugfs.h>
25 #include <linux/delay.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmapool.h>
30 #include <linux/irq.h>
31 #include <linux/module.h>
33 #include <linux/of_device.h>
34 #include <linux/pagemap.h>
35 #include <linux/platform_device.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/serial_core.h>
39 #include <linux/serial_reg.h>
40 #include <linux/slab.h>
41 #include <linux/string.h>
42 #include <linux/termios.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
46 #include <linux/clk/tegra.h>
48 #define TEGRA_UART_TYPE "TEGRA_UART"
49 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
50 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
52 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
53 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
54 #define TEGRA_UART_IER_EORD 0x20
55 #define TEGRA_UART_MCR_RTS_EN 0x40
56 #define TEGRA_UART_MCR_CTS_EN 0x20
57 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
58 UART_LSR_PE | UART_LSR_FE)
59 #define TEGRA_UART_IRDA_CSR 0x08
60 #define TEGRA_UART_SIR_ENABLED 0x80
62 #define TEGRA_UART_TX_PIO 1
63 #define TEGRA_UART_TX_DMA 2
64 #define TEGRA_UART_MIN_DMA 16
65 #define TEGRA_UART_FIFO_SIZE 32
68 * Tx fifo trigger level setting in tegra uart is in
69 * reverse way then conventional uart.
71 #define TEGRA_UART_TX_TRIG_16B 0x00
72 #define TEGRA_UART_TX_TRIG_8B 0x10
73 #define TEGRA_UART_TX_TRIG_4B 0x20
74 #define TEGRA_UART_TX_TRIG_1B 0x30
76 #define TEGRA_UART_MAXIMUM 5
78 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
79 #define TEGRA_UART_DEFAULT_BAUD 115200
80 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
82 /* Tx transfer mode */
83 #define TEGRA_TX_PIO 1
84 #define TEGRA_TX_DMA 2
87 * tegra_uart_chip_data: SOC specific data.
89 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
90 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
91 * Tegra30 does not allow this.
92 * @support_clk_src_div: Clock source support the clock divider.
94 struct tegra_uart_chip_data {
95 bool tx_fifo_full_status;
96 bool allow_txfifo_reset_fifo_mode;
97 bool support_clk_src_div;
100 struct tegra_uart_port {
101 struct uart_port uport;
102 const struct tegra_uart_chip_data *cdata;
104 struct clk *uart_clk;
105 unsigned int current_baud;
107 /* Register shadow */
108 unsigned long fcr_shadow;
109 unsigned long mcr_shadow;
110 unsigned long lcr_shadow;
111 unsigned long ier_shadow;
115 unsigned int tx_bytes;
117 bool enable_modem_interrupt;
124 struct dma_chan *rx_dma_chan;
125 struct dma_chan *tx_dma_chan;
126 dma_addr_t rx_dma_buf_phys;
127 dma_addr_t tx_dma_buf_phys;
128 unsigned char *rx_dma_buf_virt;
129 unsigned char *tx_dma_buf_virt;
130 struct dma_async_tx_descriptor *tx_dma_desc;
131 struct dma_async_tx_descriptor *rx_dma_desc;
132 dma_cookie_t tx_cookie;
133 dma_cookie_t rx_cookie;
134 int tx_bytes_requested;
135 int rx_bytes_requested;
138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
144 return readl(tup->uport.membase + (reg << tup->uport.regshift));
147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
150 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
153 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
155 return container_of(u, struct tegra_uart_port, uport);
158 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
160 struct tegra_uart_port *tup = to_tegra_uport(u);
163 * RI - Ring detector is active
164 * CD/DCD/CAR - Carrier detect is always active. For some reason
165 * linux has different names for carrier detect.
166 * DSR - Data Set ready is active as the hardware doesn't support it.
167 * Don't know if the linux support this yet?
168 * CTS - Clear to send. Always set to active, as the hardware handles
171 if (tup->enable_modem_interrupt)
172 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
176 static void set_rts(struct tegra_uart_port *tup, bool active)
180 mcr = tup->mcr_shadow;
182 mcr |= TEGRA_UART_MCR_RTS_EN;
184 mcr &= ~TEGRA_UART_MCR_RTS_EN;
185 if (mcr != tup->mcr_shadow) {
186 tegra_uart_write(tup, mcr, UART_MCR);
187 tup->mcr_shadow = mcr;
192 static void set_dtr(struct tegra_uart_port *tup, bool active)
196 mcr = tup->mcr_shadow;
200 mcr &= ~UART_MCR_DTR;
201 if (mcr != tup->mcr_shadow) {
202 tegra_uart_write(tup, mcr, UART_MCR);
203 tup->mcr_shadow = mcr;
208 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
210 struct tegra_uart_port *tup = to_tegra_uport(u);
214 mcr = tup->mcr_shadow;
215 tup->rts_active = !!(mctrl & TIOCM_RTS);
216 set_rts(tup, tup->rts_active);
218 dtr_enable = !!(mctrl & TIOCM_DTR);
219 set_dtr(tup, dtr_enable);
223 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
225 struct tegra_uart_port *tup = to_tegra_uport(u);
228 lcr = tup->lcr_shadow;
232 lcr &= ~UART_LCR_SBC;
233 tegra_uart_write(tup, lcr, UART_LCR);
234 tup->lcr_shadow = lcr;
237 /* Wait for a symbol-time. */
238 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
241 if (tup->current_baud)
242 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
246 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
248 unsigned long fcr = tup->fcr_shadow;
250 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
251 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
252 tegra_uart_write(tup, fcr, UART_FCR);
254 fcr &= ~UART_FCR_ENABLE_FIFO;
255 tegra_uart_write(tup, fcr, UART_FCR);
257 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
258 tegra_uart_write(tup, fcr, UART_FCR);
259 fcr |= UART_FCR_ENABLE_FIFO;
260 tegra_uart_write(tup, fcr, UART_FCR);
263 /* Dummy read to ensure the write is posted */
264 tegra_uart_read(tup, UART_SCR);
266 /* Wait for the flush to propagate. */
267 tegra_uart_wait_sym_time(tup, 1);
270 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
273 unsigned int divisor;
277 if (tup->current_baud == baud)
280 if (tup->cdata->support_clk_src_div) {
282 ret = clk_set_rate(tup->uart_clk, rate);
284 dev_err(tup->uport.dev,
285 "clk_set_rate() failed for rate %lu\n", rate);
290 rate = clk_get_rate(tup->uart_clk);
291 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
294 lcr = tup->lcr_shadow;
295 lcr |= UART_LCR_DLAB;
296 tegra_uart_write(tup, lcr, UART_LCR);
298 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
299 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
301 lcr &= ~UART_LCR_DLAB;
302 tegra_uart_write(tup, lcr, UART_LCR);
304 /* Dummy read to ensure the write is posted */
305 tegra_uart_read(tup, UART_SCR);
307 tup->current_baud = baud;
309 /* wait two character intervals at new rate */
310 tegra_uart_wait_sym_time(tup, 2);
314 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
317 char flag = TTY_NORMAL;
319 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
320 if (lsr & UART_LSR_OE) {
323 tup->uport.icount.overrun++;
324 dev_err(tup->uport.dev, "Got overrun errors\n");
325 } else if (lsr & UART_LSR_PE) {
328 tup->uport.icount.parity++;
329 dev_err(tup->uport.dev, "Got Parity errors\n");
330 } else if (lsr & UART_LSR_FE) {
332 tup->uport.icount.frame++;
333 dev_err(tup->uport.dev, "Got frame errors\n");
334 } else if (lsr & UART_LSR_BI) {
335 dev_err(tup->uport.dev, "Got Break\n");
336 tup->uport.icount.brk++;
337 /* If FIFO read error without any data, reset Rx FIFO */
338 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
339 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
345 static int tegra_uart_request_port(struct uart_port *u)
350 static void tegra_uart_release_port(struct uart_port *u)
352 /* Nothing to do here */
355 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
357 struct circ_buf *xmit = &tup->uport.state->xmit;
360 for (i = 0; i < max_bytes; i++) {
361 BUG_ON(uart_circ_empty(xmit));
362 if (tup->cdata->tx_fifo_full_status) {
363 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
364 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
367 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
368 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
369 tup->uport.icount.tx++;
373 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
376 if (bytes > TEGRA_UART_MIN_DMA)
377 bytes = TEGRA_UART_MIN_DMA;
379 tup->tx_in_progress = TEGRA_UART_TX_PIO;
380 tup->tx_bytes = bytes;
381 tup->ier_shadow |= UART_IER_THRI;
382 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
385 static void tegra_uart_tx_dma_complete(void *args)
387 struct tegra_uart_port *tup = args;
388 struct circ_buf *xmit = &tup->uport.state->xmit;
389 struct dma_tx_state state;
393 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state);
394 count = tup->tx_bytes_requested - state.residue;
395 async_tx_ack(tup->tx_dma_desc);
396 spin_lock_irqsave(&tup->uport.lock, flags);
397 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
398 tup->tx_in_progress = 0;
399 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
400 uart_write_wakeup(&tup->uport);
401 tegra_uart_start_next_tx(tup);
402 spin_unlock_irqrestore(&tup->uport.lock, flags);
405 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
408 struct circ_buf *xmit = &tup->uport.state->xmit;
409 dma_addr_t tx_phys_addr;
411 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
412 UART_XMIT_SIZE, DMA_TO_DEVICE);
414 tup->tx_bytes = count & ~(0xF);
415 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
416 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
417 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
419 if (!tup->tx_dma_desc) {
420 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
424 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
425 tup->tx_dma_desc->callback_param = tup;
426 tup->tx_in_progress = TEGRA_UART_TX_DMA;
427 tup->tx_bytes_requested = tup->tx_bytes;
428 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
429 dma_async_issue_pending(tup->tx_dma_chan);
433 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
437 struct circ_buf *xmit = &tup->uport.state->xmit;
439 tail = (unsigned long)&xmit->buf[xmit->tail];
440 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
444 if (count < TEGRA_UART_MIN_DMA)
445 tegra_uart_start_pio_tx(tup, count);
446 else if (BYTES_TO_ALIGN(tail) > 0)
447 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
449 tegra_uart_start_tx_dma(tup, count);
452 /* Called by serial core driver with u->lock taken. */
453 static void tegra_uart_start_tx(struct uart_port *u)
455 struct tegra_uart_port *tup = to_tegra_uport(u);
456 struct circ_buf *xmit = &u->state->xmit;
458 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
459 tegra_uart_start_next_tx(tup);
462 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
464 struct tegra_uart_port *tup = to_tegra_uport(u);
465 unsigned int ret = 0;
468 spin_lock_irqsave(&u->lock, flags);
469 if (!tup->tx_in_progress) {
470 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
471 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
474 spin_unlock_irqrestore(&u->lock, flags);
478 static void tegra_uart_stop_tx(struct uart_port *u)
480 struct tegra_uart_port *tup = to_tegra_uport(u);
481 struct circ_buf *xmit = &tup->uport.state->xmit;
482 struct dma_tx_state state;
485 dmaengine_terminate_all(tup->tx_dma_chan);
486 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
487 count = tup->tx_bytes_requested - state.residue;
488 async_tx_ack(tup->tx_dma_desc);
489 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
490 tup->tx_in_progress = 0;
494 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
496 struct circ_buf *xmit = &tup->uport.state->xmit;
498 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
499 tup->tx_in_progress = 0;
500 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
501 uart_write_wakeup(&tup->uport);
502 tegra_uart_start_next_tx(tup);
506 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
507 struct tty_port *tty)
510 char flag = TTY_NORMAL;
511 unsigned long lsr = 0;
514 lsr = tegra_uart_read(tup, UART_LSR);
515 if (!(lsr & UART_LSR_DR))
518 flag = tegra_uart_decode_rx_error(tup, lsr);
519 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
520 tup->uport.icount.rx++;
522 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
523 tty_insert_flip_char(tty, ch, flag);
529 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
530 struct tty_port *tty, int count)
534 tup->uport.icount.rx += count;
536 dev_err(tup->uport.dev, "No tty port\n");
539 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
540 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
541 copied = tty_insert_flip_string(tty,
542 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
543 if (copied != count) {
545 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
547 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
548 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
551 static void tegra_uart_rx_dma_complete(void *args)
553 struct tegra_uart_port *tup = args;
554 struct uart_port *u = &tup->uport;
555 int count = tup->rx_bytes_requested;
556 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
557 struct tty_port *port = &u->state->port;
560 async_tx_ack(tup->rx_dma_desc);
561 spin_lock_irqsave(&u->lock, flags);
563 /* Deactivate flow control to stop sender */
567 /* If we are here, DMA is stopped */
569 tegra_uart_copy_rx_to_tty(tup, port, count);
571 tegra_uart_handle_rx_pio(tup, port);
573 tty_flip_buffer_push(port);
576 tegra_uart_start_rx_dma(tup);
578 /* Activate flow control to start transfer */
582 spin_unlock_irqrestore(&u->lock, flags);
585 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
587 struct dma_tx_state state;
588 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
589 struct tty_port *port = &tup->uport.state->port;
592 /* Deactivate flow control to stop sender */
596 dmaengine_terminate_all(tup->rx_dma_chan);
597 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
598 count = tup->rx_bytes_requested - state.residue;
600 /* If we are here, DMA is stopped */
602 tegra_uart_copy_rx_to_tty(tup, port, count);
604 tegra_uart_handle_rx_pio(tup, port);
606 tty_flip_buffer_push(port);
609 tegra_uart_start_rx_dma(tup);
615 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
617 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
619 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
620 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
622 if (!tup->rx_dma_desc) {
623 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
627 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
628 tup->rx_dma_desc->callback_param = tup;
629 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
630 count, DMA_TO_DEVICE);
631 tup->rx_bytes_requested = count;
632 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
633 dma_async_issue_pending(tup->rx_dma_chan);
637 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
639 struct tegra_uart_port *tup = to_tegra_uport(u);
642 msr = tegra_uart_read(tup, UART_MSR);
643 if (!(msr & UART_MSR_ANY_DELTA))
646 if (msr & UART_MSR_TERI)
647 tup->uport.icount.rng++;
648 if (msr & UART_MSR_DDSR)
649 tup->uport.icount.dsr++;
650 /* We may only get DDCD when HW init and reset */
651 if (msr & UART_MSR_DDCD)
652 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
653 /* Will start/stop_tx accordingly */
654 if (msr & UART_MSR_DCTS)
655 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
659 static irqreturn_t tegra_uart_isr(int irq, void *data)
661 struct tegra_uart_port *tup = data;
662 struct uart_port *u = &tup->uport;
665 bool is_rx_int = false;
668 spin_lock_irqsave(&u->lock, flags);
670 iir = tegra_uart_read(tup, UART_IIR);
671 if (iir & UART_IIR_NO_INT) {
673 tegra_uart_handle_rx_dma(tup);
674 if (tup->rx_in_progress) {
675 ier = tup->ier_shadow;
676 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
677 TEGRA_UART_IER_EORD);
678 tup->ier_shadow = ier;
679 tegra_uart_write(tup, ier, UART_IER);
682 spin_unlock_irqrestore(&u->lock, flags);
686 switch ((iir >> 1) & 0x7) {
687 case 0: /* Modem signal change interrupt */
688 tegra_uart_handle_modem_signal_change(u);
691 case 1: /* Transmit interrupt only triggered when using PIO */
692 tup->ier_shadow &= ~UART_IER_THRI;
693 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
694 tegra_uart_handle_tx_pio(tup);
697 case 4: /* End of data */
698 case 6: /* Rx timeout */
699 case 2: /* Receive */
702 /* Disable Rx interrupts */
703 ier = tup->ier_shadow;
705 tegra_uart_write(tup, ier, UART_IER);
706 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
707 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
708 tup->ier_shadow = ier;
709 tegra_uart_write(tup, ier, UART_IER);
713 case 3: /* Receive error */
714 tegra_uart_decode_rx_error(tup,
715 tegra_uart_read(tup, UART_LSR));
718 case 5: /* break nothing to handle */
719 case 7: /* break nothing to handle */
725 static void tegra_uart_stop_rx(struct uart_port *u)
727 struct tegra_uart_port *tup = to_tegra_uport(u);
728 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
729 struct tty_port *port = &u->state->port;
730 struct dma_tx_state state;
737 if (!tup->rx_in_progress)
740 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
742 ier = tup->ier_shadow;
743 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
744 TEGRA_UART_IER_EORD);
745 tup->ier_shadow = ier;
746 tegra_uart_write(tup, ier, UART_IER);
747 tup->rx_in_progress = 0;
748 if (tup->rx_dma_chan) {
749 dmaengine_terminate_all(tup->rx_dma_chan);
750 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
751 async_tx_ack(tup->rx_dma_desc);
752 count = tup->rx_bytes_requested - state.residue;
753 tegra_uart_copy_rx_to_tty(tup, port, count);
754 tegra_uart_handle_rx_pio(tup, port);
756 tegra_uart_handle_rx_pio(tup, port);
759 tty_flip_buffer_push(port);
765 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
768 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
769 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
770 unsigned long wait_time;
775 /* Disable interrupts */
776 tegra_uart_write(tup, 0, UART_IER);
778 lsr = tegra_uart_read(tup, UART_LSR);
779 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
780 msr = tegra_uart_read(tup, UART_MSR);
781 mcr = tegra_uart_read(tup, UART_MCR);
782 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
783 dev_err(tup->uport.dev,
784 "Tx Fifo not empty, CTS disabled, waiting\n");
786 /* Wait for Tx fifo to be empty */
787 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
788 wait_time = min(fifo_empty_time, 100lu);
790 fifo_empty_time -= wait_time;
791 if (!fifo_empty_time) {
792 msr = tegra_uart_read(tup, UART_MSR);
793 mcr = tegra_uart_read(tup, UART_MCR);
794 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
795 (msr & UART_MSR_CTS))
796 dev_err(tup->uport.dev,
797 "Slave not ready\n");
800 lsr = tegra_uart_read(tup, UART_LSR);
804 spin_lock_irqsave(&tup->uport.lock, flags);
805 /* Reset the Rx and Tx FIFOs */
806 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
807 tup->current_baud = 0;
808 spin_unlock_irqrestore(&tup->uport.lock, flags);
810 clk_disable_unprepare(tup->uart_clk);
813 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
821 tup->current_baud = 0;
823 clk_prepare_enable(tup->uart_clk);
825 /* Reset the UART controller to clear all previous status.*/
826 tegra_periph_reset_assert(tup->uart_clk);
828 tegra_periph_reset_deassert(tup->uart_clk);
830 tup->rx_in_progress = 0;
831 tup->tx_in_progress = 0;
834 * Set the trigger level
838 * For receive, this will interrupt the CPU after that many number of
839 * bytes are received, for the remaining bytes the receive timeout
840 * interrupt is received. Rx high watermark is set to 4.
842 * For transmit, if the trasnmit interrupt is enabled, this will
843 * interrupt the CPU when the number of entries in the FIFO reaches the
844 * low watermark. Tx low watermark is set to 16 bytes.
848 * Set the Tx trigger to 16. This should match the DMA burst size that
849 * programmed in the DMA registers.
851 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
852 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
853 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
854 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
857 * Initialize the UART with default configuration
858 * (115200, N, 8, 1) so that the receive DMA buffer may be
861 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
862 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
863 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
864 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
866 ret = tegra_uart_start_rx_dma(tup);
868 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
871 tup->rx_in_progress = 1;
874 * Enable IE_RXS for the receive status interrupts like line errros.
875 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
877 * If using DMA mode, enable EORD instead of receive interrupt which
878 * will interrupt after the UART is done with the receive instead of
879 * the interrupt when the FIFO "threshold" is reached.
881 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
882 * the DATA is sitting in the FIFO and couldn't be transferred to the
883 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
884 * triggered when there is a pause of the incomming data stream for 4
887 * For pauses in the data which is not aligned to 4 bytes, we get
888 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
891 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
892 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
896 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
899 struct dma_chan *dma_chan;
900 unsigned char *dma_buf;
903 struct dma_slave_config dma_sconfig;
907 dma_cap_set(DMA_SLAVE, mask);
908 dma_chan = dma_request_channel(mask, NULL, NULL);
910 dev_err(tup->uport.dev,
911 "Dma channel is not available, will try later\n");
912 return -EPROBE_DEFER;
916 dma_buf = dma_alloc_coherent(tup->uport.dev,
917 TEGRA_UART_RX_DMA_BUFFER_SIZE,
918 &dma_phys, GFP_KERNEL);
920 dev_err(tup->uport.dev,
921 "Not able to allocate the dma buffer\n");
922 dma_release_channel(dma_chan);
926 dma_phys = dma_map_single(tup->uport.dev,
927 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
929 dma_buf = tup->uport.state->xmit.buf;
932 dma_sconfig.slave_id = tup->dma_req_sel;
934 dma_sconfig.src_addr = tup->uport.mapbase;
935 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
936 dma_sconfig.src_maxburst = 4;
938 dma_sconfig.dst_addr = tup->uport.mapbase;
939 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
940 dma_sconfig.dst_maxburst = 16;
943 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
945 dev_err(tup->uport.dev,
946 "Dma slave config failed, err = %d\n", ret);
951 tup->rx_dma_chan = dma_chan;
952 tup->rx_dma_buf_virt = dma_buf;
953 tup->rx_dma_buf_phys = dma_phys;
955 tup->tx_dma_chan = dma_chan;
956 tup->tx_dma_buf_virt = dma_buf;
957 tup->tx_dma_buf_phys = dma_phys;
962 dma_release_channel(dma_chan);
966 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
969 struct dma_chan *dma_chan;
972 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
973 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
974 dma_chan = tup->rx_dma_chan;
975 tup->rx_dma_chan = NULL;
976 tup->rx_dma_buf_phys = 0;
977 tup->rx_dma_buf_virt = NULL;
979 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
980 UART_XMIT_SIZE, DMA_TO_DEVICE);
981 dma_chan = tup->tx_dma_chan;
982 tup->tx_dma_chan = NULL;
983 tup->tx_dma_buf_phys = 0;
984 tup->tx_dma_buf_virt = NULL;
986 dma_release_channel(dma_chan);
989 static int tegra_uart_startup(struct uart_port *u)
991 struct tegra_uart_port *tup = to_tegra_uport(u);
994 ret = tegra_uart_dma_channel_allocate(tup, false);
996 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
1000 ret = tegra_uart_dma_channel_allocate(tup, true);
1002 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1006 ret = tegra_uart_hw_init(tup);
1008 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1012 ret = request_irq(u->irq, tegra_uart_isr, IRQF_DISABLED,
1013 dev_name(u->dev), tup);
1015 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1021 tegra_uart_dma_channel_free(tup, true);
1023 tegra_uart_dma_channel_free(tup, false);
1027 static void tegra_uart_shutdown(struct uart_port *u)
1029 struct tegra_uart_port *tup = to_tegra_uport(u);
1031 tegra_uart_hw_deinit(tup);
1033 tup->rx_in_progress = 0;
1034 tup->tx_in_progress = 0;
1036 tegra_uart_dma_channel_free(tup, true);
1037 tegra_uart_dma_channel_free(tup, false);
1038 free_irq(u->irq, tup);
1041 static void tegra_uart_enable_ms(struct uart_port *u)
1043 struct tegra_uart_port *tup = to_tegra_uport(u);
1045 if (tup->enable_modem_interrupt) {
1046 tup->ier_shadow |= UART_IER_MSI;
1047 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1051 static void tegra_uart_set_termios(struct uart_port *u,
1052 struct ktermios *termios, struct ktermios *oldtermios)
1054 struct tegra_uart_port *tup = to_tegra_uport(u);
1056 unsigned long flags;
1059 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1060 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1061 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1064 spin_lock_irqsave(&u->lock, flags);
1066 /* Changing configuration, it is safe to stop any rx now */
1067 if (tup->rts_active)
1068 set_rts(tup, false);
1070 /* Clear all interrupts as configuration is going to be change */
1071 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1072 tegra_uart_read(tup, UART_IER);
1073 tegra_uart_write(tup, 0, UART_IER);
1074 tegra_uart_read(tup, UART_IER);
1077 lcr = tup->lcr_shadow;
1078 lcr &= ~UART_LCR_PARITY;
1080 /* CMSPAR isn't supported by this driver */
1081 termios->c_cflag &= ~CMSPAR;
1083 if ((termios->c_cflag & PARENB) == PARENB) {
1085 if (termios->c_cflag & PARODD) {
1086 lcr |= UART_LCR_PARITY;
1087 lcr &= ~UART_LCR_EPAR;
1088 lcr &= ~UART_LCR_SPAR;
1090 lcr |= UART_LCR_PARITY;
1091 lcr |= UART_LCR_EPAR;
1092 lcr &= ~UART_LCR_SPAR;
1096 lcr &= ~UART_LCR_WLEN8;
1097 switch (termios->c_cflag & CSIZE) {
1099 lcr |= UART_LCR_WLEN5;
1103 lcr |= UART_LCR_WLEN6;
1107 lcr |= UART_LCR_WLEN7;
1111 lcr |= UART_LCR_WLEN8;
1117 if (termios->c_cflag & CSTOPB) {
1118 lcr |= UART_LCR_STOP;
1121 lcr &= ~UART_LCR_STOP;
1125 tegra_uart_write(tup, lcr, UART_LCR);
1126 tup->lcr_shadow = lcr;
1127 tup->symb_bit = symb_bit;
1130 baud = uart_get_baud_rate(u, termios, oldtermios,
1131 parent_clk_rate/max_divider,
1132 parent_clk_rate/16);
1133 spin_unlock_irqrestore(&u->lock, flags);
1134 tegra_set_baudrate(tup, baud);
1135 if (tty_termios_baud_rate(termios))
1136 tty_termios_encode_baud_rate(termios, baud, baud);
1137 spin_lock_irqsave(&u->lock, flags);
1140 if (termios->c_cflag & CRTSCTS) {
1141 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1142 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1143 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1144 /* if top layer has asked to set rts active then do so here */
1145 if (tup->rts_active)
1148 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1149 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1150 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1153 /* update the port timeout based on new settings */
1154 uart_update_timeout(u, termios->c_cflag, baud);
1156 /* Make sure all write has completed */
1157 tegra_uart_read(tup, UART_IER);
1159 /* Reenable interrupt */
1160 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1161 tegra_uart_read(tup, UART_IER);
1163 spin_unlock_irqrestore(&u->lock, flags);
1168 * Flush any TX data submitted for DMA and PIO. Called when the
1169 * TX circular buffer is reset.
1171 static void tegra_uart_flush_buffer(struct uart_port *u)
1173 struct tegra_uart_port *tup = to_tegra_uport(u);
1176 if (tup->tx_dma_chan)
1177 dmaengine_terminate_all(tup->tx_dma_chan);
1181 static const char *tegra_uart_type(struct uart_port *u)
1183 return TEGRA_UART_TYPE;
1186 static struct uart_ops tegra_uart_ops = {
1187 .tx_empty = tegra_uart_tx_empty,
1188 .set_mctrl = tegra_uart_set_mctrl,
1189 .get_mctrl = tegra_uart_get_mctrl,
1190 .stop_tx = tegra_uart_stop_tx,
1191 .start_tx = tegra_uart_start_tx,
1192 .stop_rx = tegra_uart_stop_rx,
1193 .flush_buffer = tegra_uart_flush_buffer,
1194 .enable_ms = tegra_uart_enable_ms,
1195 .break_ctl = tegra_uart_break_ctl,
1196 .startup = tegra_uart_startup,
1197 .shutdown = tegra_uart_shutdown,
1198 .set_termios = tegra_uart_set_termios,
1199 .type = tegra_uart_type,
1200 .request_port = tegra_uart_request_port,
1201 .release_port = tegra_uart_release_port,
1204 static struct uart_driver tegra_uart_driver = {
1205 .owner = THIS_MODULE,
1206 .driver_name = "tegra_hsuart",
1207 .dev_name = "ttyTHS",
1209 .nr = TEGRA_UART_MAXIMUM,
1212 static int tegra_uart_parse_dt(struct platform_device *pdev,
1213 struct tegra_uart_port *tup)
1215 struct device_node *np = pdev->dev.of_node;
1219 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1221 tup->dma_req_sel = of_dma[1];
1223 dev_err(&pdev->dev, "missing dma requestor in device tree\n");
1227 port = of_alias_get_id(np, "serial");
1229 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1232 tup->uport.line = port;
1234 tup->enable_modem_interrupt = of_property_read_bool(np,
1235 "nvidia,enable-modem-interrupt");
1239 struct tegra_uart_chip_data tegra20_uart_chip_data = {
1240 .tx_fifo_full_status = false,
1241 .allow_txfifo_reset_fifo_mode = true,
1242 .support_clk_src_div = false,
1245 struct tegra_uart_chip_data tegra30_uart_chip_data = {
1246 .tx_fifo_full_status = true,
1247 .allow_txfifo_reset_fifo_mode = false,
1248 .support_clk_src_div = true,
1251 static struct of_device_id tegra_uart_of_match[] = {
1253 .compatible = "nvidia,tegra30-hsuart",
1254 .data = &tegra30_uart_chip_data,
1256 .compatible = "nvidia,tegra20-hsuart",
1257 .data = &tegra20_uart_chip_data,
1261 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1263 static int tegra_uart_probe(struct platform_device *pdev)
1265 struct tegra_uart_port *tup;
1266 struct uart_port *u;
1267 struct resource *resource;
1269 const struct tegra_uart_chip_data *cdata;
1270 const struct of_device_id *match;
1272 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1274 dev_err(&pdev->dev, "Error: No device match found\n");
1277 cdata = match->data;
1279 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1281 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1285 ret = tegra_uart_parse_dt(pdev, tup);
1290 u->dev = &pdev->dev;
1291 u->ops = &tegra_uart_ops;
1292 u->type = PORT_TEGRA;
1296 platform_set_drvdata(pdev, tup);
1297 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1299 dev_err(&pdev->dev, "No IO memory resource\n");
1303 u->mapbase = resource->start;
1304 u->membase = devm_request_and_ioremap(&pdev->dev, resource);
1306 dev_err(&pdev->dev, "memregion/iomap address req failed\n");
1307 return -EADDRNOTAVAIL;
1310 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1311 if (IS_ERR(tup->uart_clk)) {
1312 dev_err(&pdev->dev, "Couldn't get the clock\n");
1313 return PTR_ERR(tup->uart_clk);
1316 u->iotype = UPIO_MEM32;
1317 u->irq = platform_get_irq(pdev, 0);
1319 ret = uart_add_one_port(&tegra_uart_driver, u);
1321 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1327 static int tegra_uart_remove(struct platform_device *pdev)
1329 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1330 struct uart_port *u = &tup->uport;
1332 uart_remove_one_port(&tegra_uart_driver, u);
1336 #ifdef CONFIG_PM_SLEEP
1337 static int tegra_uart_suspend(struct device *dev)
1339 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1340 struct uart_port *u = &tup->uport;
1342 return uart_suspend_port(&tegra_uart_driver, u);
1345 static int tegra_uart_resume(struct device *dev)
1347 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1348 struct uart_port *u = &tup->uport;
1350 return uart_resume_port(&tegra_uart_driver, u);
1354 static const struct dev_pm_ops tegra_uart_pm_ops = {
1355 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1358 static struct platform_driver tegra_uart_platform_driver = {
1359 .probe = tegra_uart_probe,
1360 .remove = tegra_uart_remove,
1362 .name = "serial-tegra",
1363 .of_match_table = tegra_uart_of_match,
1364 .pm = &tegra_uart_pm_ops,
1368 static int __init tegra_uart_init(void)
1372 ret = uart_register_driver(&tegra_uart_driver);
1374 pr_err("Could not register %s driver\n",
1375 tegra_uart_driver.driver_name);
1379 ret = platform_driver_register(&tegra_uart_platform_driver);
1381 pr_err("Uart platfrom driver register failed, e = %d\n", ret);
1382 uart_unregister_driver(&tegra_uart_driver);
1388 static void __exit tegra_uart_exit(void)
1390 pr_info("Unloading tegra uart driver\n");
1391 platform_driver_unregister(&tegra_uart_platform_driver);
1392 uart_unregister_driver(&tegra_uart_driver);
1395 module_init(tegra_uart_init);
1396 module_exit(tegra_uart_exit);
1398 MODULE_ALIAS("platform:serial-tegra");
1399 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1400 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1401 MODULE_LICENSE("GPL v2");