1 // SPDX-License-Identifier: GPL-2.0+
3 * NXP (Philips) SCC+++(SCN+++) serial driver
5 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
7 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
10 #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/module.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/device.h>
20 #include <linux/console.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/platform_data/serial-sccnxp.h>
29 #include <linux/regulator/consumer.h>
31 #define SCCNXP_NAME "uart-sccnxp"
32 #define SCCNXP_MAJOR 204
33 #define SCCNXP_MINOR 205
35 #define SCCNXP_MR_REG (0x00)
36 # define MR0_BAUD_NORMAL (0 << 0)
37 # define MR0_BAUD_EXT1 (1 << 0)
38 # define MR0_BAUD_EXT2 (5 << 0)
39 # define MR0_FIFO (1 << 3)
40 # define MR0_TXLVL (1 << 4)
41 # define MR1_BITS_5 (0 << 0)
42 # define MR1_BITS_6 (1 << 0)
43 # define MR1_BITS_7 (2 << 0)
44 # define MR1_BITS_8 (3 << 0)
45 # define MR1_PAR_EVN (0 << 2)
46 # define MR1_PAR_ODD (1 << 2)
47 # define MR1_PAR_NO (4 << 2)
48 # define MR2_STOP1 (7 << 0)
49 # define MR2_STOP2 (0xf << 0)
50 #define SCCNXP_SR_REG (0x01)
51 # define SR_RXRDY (1 << 0)
52 # define SR_FULL (1 << 1)
53 # define SR_TXRDY (1 << 2)
54 # define SR_TXEMT (1 << 3)
55 # define SR_OVR (1 << 4)
56 # define SR_PE (1 << 5)
57 # define SR_FE (1 << 6)
58 # define SR_BRK (1 << 7)
59 #define SCCNXP_CSR_REG (SCCNXP_SR_REG)
60 # define CSR_TIMER_MODE (0x0d)
61 #define SCCNXP_CR_REG (0x02)
62 # define CR_RX_ENABLE (1 << 0)
63 # define CR_RX_DISABLE (1 << 1)
64 # define CR_TX_ENABLE (1 << 2)
65 # define CR_TX_DISABLE (1 << 3)
66 # define CR_CMD_MRPTR1 (0x01 << 4)
67 # define CR_CMD_RX_RESET (0x02 << 4)
68 # define CR_CMD_TX_RESET (0x03 << 4)
69 # define CR_CMD_STATUS_RESET (0x04 << 4)
70 # define CR_CMD_BREAK_RESET (0x05 << 4)
71 # define CR_CMD_START_BREAK (0x06 << 4)
72 # define CR_CMD_STOP_BREAK (0x07 << 4)
73 # define CR_CMD_MRPTR0 (0x0b << 4)
74 #define SCCNXP_RHR_REG (0x03)
75 #define SCCNXP_THR_REG SCCNXP_RHR_REG
76 #define SCCNXP_IPCR_REG (0x04)
77 #define SCCNXP_ACR_REG SCCNXP_IPCR_REG
78 # define ACR_BAUD0 (0 << 7)
79 # define ACR_BAUD1 (1 << 7)
80 # define ACR_TIMER_MODE (6 << 4)
81 #define SCCNXP_ISR_REG (0x05)
82 #define SCCNXP_IMR_REG SCCNXP_ISR_REG
83 # define IMR_TXRDY (1 << 0)
84 # define IMR_RXRDY (1 << 1)
85 # define ISR_TXRDY(x) (1 << ((x * 4) + 0))
86 # define ISR_RXRDY(x) (1 << ((x * 4) + 1))
87 #define SCCNXP_CTPU_REG (0x06)
88 #define SCCNXP_CTPL_REG (0x07)
89 #define SCCNXP_IPR_REG (0x0d)
90 #define SCCNXP_OPCR_REG SCCNXP_IPR_REG
91 #define SCCNXP_SOP_REG (0x0e)
92 #define SCCNXP_START_COUNTER_REG SCCNXP_SOP_REG
93 #define SCCNXP_ROP_REG (0x0f)
96 #define MCTRL_MASK(sig) (0xf << (sig))
97 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
98 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
100 #define SCCNXP_HAVE_IO 0x00000001
101 #define SCCNXP_HAVE_MR0 0x00000002
106 unsigned long freq_min;
107 unsigned long freq_std;
108 unsigned long freq_max;
110 unsigned int fifosize;
111 /* Time between read/write cycles */
116 struct uart_driver uart;
117 struct uart_port port[SCCNXP_MAX_UARTS];
118 bool opened[SCCNXP_MAX_UARTS];
123 struct sccnxp_chip *chip;
125 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
126 struct console console;
132 struct timer_list timer;
134 struct sccnxp_pdata pdata;
136 struct regulator *regulator;
139 static const struct sccnxp_chip sc2681 = {
145 .flags = SCCNXP_HAVE_IO,
150 static const struct sccnxp_chip sc2691 = {
161 static const struct sccnxp_chip sc2692 = {
167 .flags = SCCNXP_HAVE_IO,
172 static const struct sccnxp_chip sc2891 = {
178 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
183 static const struct sccnxp_chip sc2892 = {
189 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
194 static const struct sccnxp_chip sc28202 = {
198 .freq_std = 14745600,
199 .freq_max = 50000000,
200 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
205 static const struct sccnxp_chip sc68681 = {
211 .flags = SCCNXP_HAVE_IO,
216 static const struct sccnxp_chip sc68692 = {
222 .flags = SCCNXP_HAVE_IO,
227 static u8 sccnxp_read(struct uart_port *port, u8 reg)
229 struct sccnxp_port *s = dev_get_drvdata(port->dev);
232 ret = readb(port->membase + (reg << port->regshift));
234 ndelay(s->chip->trwd);
239 static void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
241 struct sccnxp_port *s = dev_get_drvdata(port->dev);
243 writeb(v, port->membase + (reg << port->regshift));
245 ndelay(s->chip->trwd);
248 static u8 sccnxp_port_read(struct uart_port *port, u8 reg)
250 return sccnxp_read(port, (port->line << 3) + reg);
253 static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
255 sccnxp_write(port, (port->line << 3) + reg, v);
258 static int sccnxp_update_best_err(int a, int b, int *besterr)
260 int err = abs(a - b);
262 if (*besterr > err) {
270 static const struct {
276 { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, },
277 { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, },
278 { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, },
279 { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, },
280 { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, },
281 { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, },
282 { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, },
283 { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, },
284 { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, },
285 { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, },
286 { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, },
287 { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, },
288 { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, },
289 { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, },
290 { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, },
291 { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, },
292 { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, },
293 { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, },
294 { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, },
295 { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, },
296 { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, },
297 { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, },
298 { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, },
299 { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, },
300 { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, },
301 { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, },
302 { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, },
303 { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, },
307 static int sccnxp_set_baud(struct uart_port *port, int baud)
309 struct sccnxp_port *s = dev_get_drvdata(port->dev);
310 int div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;
311 struct sccnxp_chip *chip = s->chip;
312 u8 i, acr = 0, csr = 0, mr0 = 0;
314 /* Find divisor to load to the timer preset registers */
315 div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud);
316 if ((div_std >= 2) && (div_std <= 0xffff)) {
317 bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std);
318 sccnxp_update_best_err(baud, bestbaud, &besterr);
319 csr = CSR_TIMER_MODE;
320 sccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8);
321 sccnxp_port_write(port, SCCNXP_CTPL_REG, div_std);
322 /* Issue start timer/counter command */
323 sccnxp_port_read(port, SCCNXP_START_COUNTER_REG);
326 /* Find best baud from table */
327 for (i = 0; baud_std[i].baud && besterr; i++) {
328 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
330 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
331 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
332 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
333 acr = baud_std[i].acr;
334 csr = baud_std[i].csr;
335 mr0 = baud_std[i].mr0;
340 if (chip->flags & SCCNXP_HAVE_MR0) {
341 /* Enable FIFO, set half level for TX */
342 mr0 |= MR0_FIFO | MR0_TXLVL;
344 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
345 sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
348 sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
349 sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
351 if (baud != bestbaud)
352 dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
358 static void sccnxp_enable_irq(struct uart_port *port, int mask)
360 struct sccnxp_port *s = dev_get_drvdata(port->dev);
362 s->imr |= mask << (port->line * 4);
363 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
366 static void sccnxp_disable_irq(struct uart_port *port, int mask)
368 struct sccnxp_port *s = dev_get_drvdata(port->dev);
370 s->imr &= ~(mask << (port->line * 4));
371 sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
374 static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
377 struct sccnxp_port *s = dev_get_drvdata(port->dev);
379 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
380 bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
382 sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
384 sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
388 static void sccnxp_handle_rx(struct uart_port *port)
391 unsigned int ch, flag;
394 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
395 if (!(sr & SR_RXRDY))
397 sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
399 ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
407 sccnxp_port_write(port, SCCNXP_CR_REG,
409 if (uart_handle_break(port))
411 } else if (sr & SR_PE)
412 port->icount.parity++;
414 port->icount.frame++;
415 else if (sr & SR_OVR) {
416 port->icount.overrun++;
417 sccnxp_port_write(port, SCCNXP_CR_REG,
418 CR_CMD_STATUS_RESET);
421 sr &= port->read_status_mask;
428 else if (sr & SR_OVR)
432 if (uart_handle_sysrq_char(port, ch))
435 if (sr & port->ignore_status_mask)
438 uart_insert_char(port, sr, SR_OVR, ch, flag);
441 tty_flip_buffer_push(&port->state->port);
444 static void sccnxp_handle_tx(struct uart_port *port)
447 struct circ_buf *xmit = &port->state->xmit;
448 struct sccnxp_port *s = dev_get_drvdata(port->dev);
450 if (unlikely(port->x_char)) {
451 sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
457 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
458 /* Disable TX if FIFO is empty */
459 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
460 sccnxp_disable_irq(port, IMR_TXRDY);
462 /* Set direction to input */
463 if (s->chip->flags & SCCNXP_HAVE_IO)
464 sccnxp_set_bit(port, DIR_OP, 0);
469 while (!uart_circ_empty(xmit)) {
470 sr = sccnxp_port_read(port, SCCNXP_SR_REG);
471 if (!(sr & SR_TXRDY))
474 sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
475 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
479 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
480 uart_write_wakeup(port);
483 static void sccnxp_handle_events(struct sccnxp_port *s)
489 isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
494 for (i = 0; i < s->uart.nr; i++) {
495 if (s->opened[i] && (isr & ISR_RXRDY(i)))
496 sccnxp_handle_rx(&s->port[i]);
497 if (s->opened[i] && (isr & ISR_TXRDY(i)))
498 sccnxp_handle_tx(&s->port[i]);
503 static void sccnxp_timer(struct timer_list *t)
505 struct sccnxp_port *s = from_timer(s, t, timer);
508 spin_lock_irqsave(&s->lock, flags);
509 sccnxp_handle_events(s);
510 spin_unlock_irqrestore(&s->lock, flags);
512 mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
515 static irqreturn_t sccnxp_ist(int irq, void *dev_id)
517 struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
520 spin_lock_irqsave(&s->lock, flags);
521 sccnxp_handle_events(s);
522 spin_unlock_irqrestore(&s->lock, flags);
527 static void sccnxp_start_tx(struct uart_port *port)
529 struct sccnxp_port *s = dev_get_drvdata(port->dev);
532 spin_lock_irqsave(&s->lock, flags);
534 /* Set direction to output */
535 if (s->chip->flags & SCCNXP_HAVE_IO)
536 sccnxp_set_bit(port, DIR_OP, 1);
538 sccnxp_enable_irq(port, IMR_TXRDY);
540 spin_unlock_irqrestore(&s->lock, flags);
543 static void sccnxp_stop_tx(struct uart_port *port)
548 static void sccnxp_stop_rx(struct uart_port *port)
550 struct sccnxp_port *s = dev_get_drvdata(port->dev);
553 spin_lock_irqsave(&s->lock, flags);
554 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
555 spin_unlock_irqrestore(&s->lock, flags);
558 static unsigned int sccnxp_tx_empty(struct uart_port *port)
562 struct sccnxp_port *s = dev_get_drvdata(port->dev);
564 spin_lock_irqsave(&s->lock, flags);
565 val = sccnxp_port_read(port, SCCNXP_SR_REG);
566 spin_unlock_irqrestore(&s->lock, flags);
568 return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
571 static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
573 struct sccnxp_port *s = dev_get_drvdata(port->dev);
576 if (!(s->chip->flags & SCCNXP_HAVE_IO))
579 spin_lock_irqsave(&s->lock, flags);
581 sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
582 sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
584 spin_unlock_irqrestore(&s->lock, flags);
587 static unsigned int sccnxp_get_mctrl(struct uart_port *port)
591 struct sccnxp_port *s = dev_get_drvdata(port->dev);
592 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
594 if (!(s->chip->flags & SCCNXP_HAVE_IO))
597 spin_lock_irqsave(&s->lock, flags);
599 ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
601 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
602 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
605 mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
607 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
608 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
611 mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
613 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
614 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
617 mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
619 if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
620 bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
623 mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
626 spin_unlock_irqrestore(&s->lock, flags);
631 static void sccnxp_break_ctl(struct uart_port *port, int break_state)
633 struct sccnxp_port *s = dev_get_drvdata(port->dev);
636 spin_lock_irqsave(&s->lock, flags);
637 sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
638 CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
639 spin_unlock_irqrestore(&s->lock, flags);
642 static void sccnxp_set_termios(struct uart_port *port,
643 struct ktermios *termios, struct ktermios *old)
645 struct sccnxp_port *s = dev_get_drvdata(port->dev);
650 spin_lock_irqsave(&s->lock, flags);
652 /* Mask termios capabilities we don't support */
653 termios->c_cflag &= ~CMSPAR;
655 /* Disable RX & TX, reset break condition, status and FIFOs */
656 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
657 CR_RX_DISABLE | CR_TX_DISABLE);
658 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
659 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
660 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
663 switch (termios->c_cflag & CSIZE) {
680 if (termios->c_cflag & PARENB) {
681 if (termios->c_cflag & PARODD)
687 mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
689 /* Update desired format */
690 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
691 sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
692 sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
694 /* Set read status mask */
695 port->read_status_mask = SR_OVR;
696 if (termios->c_iflag & INPCK)
697 port->read_status_mask |= SR_PE | SR_FE;
698 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
699 port->read_status_mask |= SR_BRK;
701 /* Set status ignore mask */
702 port->ignore_status_mask = 0;
703 if (termios->c_iflag & IGNBRK)
704 port->ignore_status_mask |= SR_BRK;
705 if (termios->c_iflag & IGNPAR)
706 port->ignore_status_mask |= SR_PE;
707 if (!(termios->c_cflag & CREAD))
708 port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
711 baud = uart_get_baud_rate(port, termios, old, 50,
712 (s->chip->flags & SCCNXP_HAVE_MR0) ?
714 baud = sccnxp_set_baud(port, baud);
716 /* Update timeout according to new baud rate */
717 uart_update_timeout(port, termios->c_cflag, baud);
719 /* Report actual baudrate back to core */
720 if (tty_termios_baud_rate(termios))
721 tty_termios_encode_baud_rate(termios, baud, baud);
724 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
726 spin_unlock_irqrestore(&s->lock, flags);
729 static int sccnxp_startup(struct uart_port *port)
731 struct sccnxp_port *s = dev_get_drvdata(port->dev);
734 spin_lock_irqsave(&s->lock, flags);
736 if (s->chip->flags & SCCNXP_HAVE_IO) {
737 /* Outputs are controlled manually */
738 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
741 /* Reset break condition, status and FIFOs */
742 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
743 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
744 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
745 sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
748 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
750 /* Enable RX interrupt */
751 sccnxp_enable_irq(port, IMR_RXRDY);
753 s->opened[port->line] = 1;
755 spin_unlock_irqrestore(&s->lock, flags);
760 static void sccnxp_shutdown(struct uart_port *port)
762 struct sccnxp_port *s = dev_get_drvdata(port->dev);
765 spin_lock_irqsave(&s->lock, flags);
767 s->opened[port->line] = 0;
769 /* Disable interrupts */
770 sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
772 /* Disable TX & RX */
773 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
775 /* Leave direction to input */
776 if (s->chip->flags & SCCNXP_HAVE_IO)
777 sccnxp_set_bit(port, DIR_OP, 0);
779 spin_unlock_irqrestore(&s->lock, flags);
782 static const char *sccnxp_type(struct uart_port *port)
784 struct sccnxp_port *s = dev_get_drvdata(port->dev);
786 return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
789 static void sccnxp_release_port(struct uart_port *port)
794 static int sccnxp_request_port(struct uart_port *port)
800 static void sccnxp_config_port(struct uart_port *port, int flags)
802 if (flags & UART_CONFIG_TYPE)
803 port->type = PORT_SC26XX;
806 static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
808 if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
810 if (s->irq == port->irq)
816 static const struct uart_ops sccnxp_ops = {
817 .tx_empty = sccnxp_tx_empty,
818 .set_mctrl = sccnxp_set_mctrl,
819 .get_mctrl = sccnxp_get_mctrl,
820 .stop_tx = sccnxp_stop_tx,
821 .start_tx = sccnxp_start_tx,
822 .stop_rx = sccnxp_stop_rx,
823 .break_ctl = sccnxp_break_ctl,
824 .startup = sccnxp_startup,
825 .shutdown = sccnxp_shutdown,
826 .set_termios = sccnxp_set_termios,
828 .release_port = sccnxp_release_port,
829 .request_port = sccnxp_request_port,
830 .config_port = sccnxp_config_port,
831 .verify_port = sccnxp_verify_port,
834 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
835 static void sccnxp_console_putchar(struct uart_port *port, int c)
840 if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
841 sccnxp_port_write(port, SCCNXP_THR_REG, c);
848 static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
850 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
851 struct uart_port *port = &s->port[co->index];
854 spin_lock_irqsave(&s->lock, flags);
855 uart_console_write(port, c, n, sccnxp_console_putchar);
856 spin_unlock_irqrestore(&s->lock, flags);
859 static int sccnxp_console_setup(struct console *co, char *options)
861 struct sccnxp_port *s = (struct sccnxp_port *)co->data;
862 struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
863 int baud = 9600, bits = 8, parity = 'n', flow = 'n';
866 uart_parse_options(options, &baud, &parity, &bits, &flow);
868 return uart_set_options(port, co, baud, parity, bits, flow);
872 static const struct platform_device_id sccnxp_id_table[] = {
873 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },
874 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },
875 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },
876 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },
877 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },
878 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, },
879 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, },
880 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, },
883 MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
885 static int sccnxp_probe(struct platform_device *pdev)
887 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
888 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
890 struct sccnxp_port *s;
891 void __iomem *membase;
894 membase = devm_ioremap_resource(&pdev->dev, res);
896 return PTR_ERR(membase);
898 s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
900 dev_err(&pdev->dev, "Error allocating port structure\n");
903 platform_set_drvdata(pdev, s);
905 spin_lock_init(&s->lock);
907 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
909 s->regulator = devm_regulator_get(&pdev->dev, "vcc");
910 if (!IS_ERR(s->regulator)) {
911 ret = regulator_enable(s->regulator);
914 "Failed to enable regulator: %i\n", ret);
917 } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
918 return -EPROBE_DEFER;
920 clk = devm_clk_get(&pdev->dev, NULL);
923 if (ret == -EPROBE_DEFER)
927 ret = clk_prepare_enable(clk);
931 ret = devm_add_action_or_reset(&pdev->dev,
932 (void(*)(void *))clk_disable_unprepare,
937 uartclk = clk_get_rate(clk);
941 dev_notice(&pdev->dev, "Using default clock frequency\n");
942 uartclk = s->chip->freq_std;
945 /* Check input frequency */
946 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
947 dev_err(&pdev->dev, "Frequency out of bounds\n");
953 memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
955 if (s->pdata.poll_time_us) {
956 dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
957 s->pdata.poll_time_us);
962 s->irq = platform_get_irq(pdev, 0);
969 s->uart.owner = THIS_MODULE;
970 s->uart.dev_name = "ttySC";
971 s->uart.major = SCCNXP_MAJOR;
972 s->uart.minor = SCCNXP_MINOR;
973 s->uart.nr = s->chip->nr;
974 #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
975 s->uart.cons = &s->console;
976 s->uart.cons->device = uart_console_device;
977 s->uart.cons->write = sccnxp_console_write;
978 s->uart.cons->setup = sccnxp_console_setup;
979 s->uart.cons->flags = CON_PRINTBUFFER;
980 s->uart.cons->index = -1;
981 s->uart.cons->data = s;
982 strcpy(s->uart.cons->name, "ttySC");
984 ret = uart_register_driver(&s->uart);
986 dev_err(&pdev->dev, "Registering UART driver failed\n");
990 for (i = 0; i < s->uart.nr; i++) {
992 s->port[i].dev = &pdev->dev;
993 s->port[i].irq = s->irq;
994 s->port[i].type = PORT_SC26XX;
995 s->port[i].fifosize = s->chip->fifosize;
996 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
997 s->port[i].iotype = UPIO_MEM;
998 s->port[i].mapbase = res->start;
999 s->port[i].membase = membase;
1000 s->port[i].regshift = s->pdata.reg_shift;
1001 s->port[i].uartclk = uartclk;
1002 s->port[i].ops = &sccnxp_ops;
1003 uart_add_one_port(&s->uart, &s->port[i]);
1004 /* Set direction to input */
1005 if (s->chip->flags & SCCNXP_HAVE_IO)
1006 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
1009 /* Disable interrupts */
1011 sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
1014 ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
1016 IRQF_TRIGGER_FALLING |
1018 dev_name(&pdev->dev), s);
1022 dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
1024 timer_setup(&s->timer, sccnxp_timer, 0);
1025 mod_timer(&s->timer, jiffies +
1026 usecs_to_jiffies(s->pdata.poll_time_us));
1030 uart_unregister_driver(&s->uart);
1032 if (!IS_ERR(s->regulator))
1033 regulator_disable(s->regulator);
1038 static int sccnxp_remove(struct platform_device *pdev)
1041 struct sccnxp_port *s = platform_get_drvdata(pdev);
1044 devm_free_irq(&pdev->dev, s->irq, s);
1046 del_timer_sync(&s->timer);
1048 for (i = 0; i < s->uart.nr; i++)
1049 uart_remove_one_port(&s->uart, &s->port[i]);
1051 uart_unregister_driver(&s->uart);
1053 if (!IS_ERR(s->regulator))
1054 return regulator_disable(s->regulator);
1059 static struct platform_driver sccnxp_uart_driver = {
1061 .name = SCCNXP_NAME,
1063 .probe = sccnxp_probe,
1064 .remove = sccnxp_remove,
1065 .id_table = sccnxp_id_table,
1067 module_platform_driver(sccnxp_uart_driver);
1069 MODULE_LICENSE("GPL v2");
1070 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1071 MODULE_DESCRIPTION("SCCNXP serial driver");