1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
4 * Author: Jon Ringle <jringle@gridpoint.com>
6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/i2c.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/spi/spi.h>
26 #include <linux/uaccess.h>
27 #include <uapi/linux/sched/types.h>
29 #define SC16IS7XX_NAME "sc16is7xx"
30 #define SC16IS7XX_MAX_DEVS 8
32 /* SC16IS7XX register definitions */
33 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
34 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
35 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
36 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
37 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
38 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
39 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
40 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
41 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
42 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
43 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
44 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
45 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
48 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
51 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
54 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
57 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
60 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
61 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
64 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
65 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67 /* Enhanced Register set: Only if (LCR == 0xBF) */
68 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
69 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
70 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
71 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
72 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74 /* IER register bits */
75 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
76 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
83 /* IER register bits - write only if (EFR[4] == 1) */
84 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
85 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
86 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
87 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89 /* FCR register bits */
90 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
91 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
92 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
93 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
94 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96 /* FCR register bits - write only if (EFR[4] == 1) */
97 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
98 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100 /* IIR register bits */
101 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
102 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
103 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
104 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
105 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
106 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
107 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
110 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
113 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
114 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
118 /* LCR register bits */
119 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
120 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 * Word length bits table:
128 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 * STOP length bit table:
132 * 1 -> 1-1.5 stop bits if
134 * 2 stop bits otherwise
136 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
137 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
138 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
139 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
140 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
141 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
142 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
143 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
144 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
145 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
150 /* MCR register bits */
151 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
154 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
155 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
156 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
157 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
161 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
165 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
170 /* LSR register bits */
171 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
172 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
173 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
174 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
175 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
176 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
177 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
178 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
179 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181 /* MSR register bits */
182 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
183 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
187 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
191 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
195 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
196 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
199 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
202 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
205 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
209 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
212 * no built-in hardware check to make sure this condition is met. Also, the TCR
213 * must be programmed with this condition before auto RTS or software flow
214 * control is enabled to avoid spurious operation of the device.
216 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
217 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
223 * trigger levels. Trigger levels from 4 characters to 60 characters are
224 * available with a granularity of four.
226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
228 * the trigger level defined in FCR is discarded. This applies to both transmit
229 * FIFO and receive FIFO trigger level setting.
231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
232 * default state, that is, '00'.
234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237 /* IOControl register bits (Only 750/760) */
238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
239 #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
240 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242 /* EFCR register bits */
243 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
246 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
247 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
248 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
249 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
250 * 0 = rate upto 115.2 kbit/s
252 * 1 = rate upto 1.152 Mbit/s
256 /* EFR register bits */
257 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
258 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
259 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
260 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
261 * and writing to IER[7:4],
264 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
265 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 * SWFLOW bits 3 & 2 table:
268 * 00 -> no transmitter flow
270 * 01 -> transmitter generates
272 * 10 -> transmitter generates
274 * 11 -> transmitter generates
275 * XON1, XON2, XOFF1 and
278 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
279 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 * SWFLOW bits 3 & 2 table:
282 * 00 -> no received flow
284 * 01 -> receiver compares
286 * 10 -> receiver compares
288 * 11 -> receiver compares
289 * XON1, XON2, XOFF1 and
293 /* Misc definitions */
294 #define SC16IS7XX_FIFO_SIZE (64)
295 #define SC16IS7XX_REG_SHIFT 2
297 struct sc16is7xx_devtype {
303 #define SC16IS7XX_RECONF_MD (1 << 0)
304 #define SC16IS7XX_RECONF_IER (1 << 1)
305 #define SC16IS7XX_RECONF_RS485 (1 << 2)
307 struct sc16is7xx_one_config {
312 struct sc16is7xx_one {
313 struct uart_port port;
315 struct kthread_work tx_work;
316 struct kthread_work reg_work;
317 struct sc16is7xx_one_config config;
321 struct sc16is7xx_port {
322 const struct sc16is7xx_devtype *devtype;
323 struct regmap *regmap;
325 #ifdef CONFIG_GPIOLIB
326 struct gpio_chip gpio;
328 unsigned char buf[SC16IS7XX_FIFO_SIZE];
329 struct kthread_worker kworker;
330 struct task_struct *kworker_task;
331 struct mutex efr_lock;
332 struct sc16is7xx_one p[];
335 static unsigned long sc16is7xx_lines;
337 static struct uart_driver sc16is7xx_uart = {
338 .owner = THIS_MODULE,
340 .nr = SC16IS7XX_MAX_DEVS,
343 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
344 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
346 static int sc16is7xx_line(struct uart_port *port)
348 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
353 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
355 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
356 unsigned int val = 0;
357 const u8 line = sc16is7xx_line(port);
359 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
364 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
366 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
367 const u8 line = sc16is7xx_line(port);
369 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
372 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
374 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
375 const u8 line = sc16is7xx_line(port);
376 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
378 regcache_cache_bypass(s->regmap, true);
379 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
380 regcache_cache_bypass(s->regmap, false);
383 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
385 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
386 const u8 line = sc16is7xx_line(port);
387 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
390 * Don't send zero-length data, at least on SPI it confuses the chip
391 * delivering wrong TXLVL data.
393 if (unlikely(!to_send))
396 regcache_cache_bypass(s->regmap, true);
397 regmap_raw_write(s->regmap, addr, s->buf, to_send);
398 regcache_cache_bypass(s->regmap, false);
401 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
404 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
405 const u8 line = sc16is7xx_line(port);
407 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
411 static int sc16is7xx_alloc_line(void)
415 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
417 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
418 if (!test_and_set_bit(i, &sc16is7xx_lines))
424 static void sc16is7xx_power(struct uart_port *port, int on)
426 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
427 SC16IS7XX_IER_SLEEP_BIT,
428 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
431 static const struct sc16is7xx_devtype sc16is74x_devtype = {
437 static const struct sc16is7xx_devtype sc16is750_devtype = {
443 static const struct sc16is7xx_devtype sc16is752_devtype = {
449 static const struct sc16is7xx_devtype sc16is760_devtype = {
455 static const struct sc16is7xx_devtype sc16is762_devtype = {
461 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
463 switch (reg >> SC16IS7XX_REG_SHIFT) {
464 case SC16IS7XX_RHR_REG:
465 case SC16IS7XX_IIR_REG:
466 case SC16IS7XX_LSR_REG:
467 case SC16IS7XX_MSR_REG:
468 case SC16IS7XX_TXLVL_REG:
469 case SC16IS7XX_RXLVL_REG:
470 case SC16IS7XX_IOSTATE_REG:
479 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
481 switch (reg >> SC16IS7XX_REG_SHIFT) {
482 case SC16IS7XX_RHR_REG:
491 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
493 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
496 unsigned long clk = port->uartclk, div = clk / 16 / baud;
499 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
503 /* In an amazing feat of design, the Enhanced Features Register shares
504 * the address of the Interrupt Identification Register, and is
505 * switched in by writing a magic value (0xbf) to the Line Control
506 * Register. Any interrupt firing during this time will see the EFR
507 * where it expects the IIR to be, leading to "Unexpected interrupt"
510 * Prevent this possibility by claiming a mutex while accessing the
511 * EFR, and claiming the same mutex from within the interrupt handler.
512 * This is similar to disabling the interrupt, but that doesn't work
513 * because the bulk of the interrupt processing is run as a workqueue
514 * job in thread context.
516 mutex_lock(&s->efr_lock);
518 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
520 /* Open the LCR divisors for configuration */
521 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
522 SC16IS7XX_LCR_CONF_MODE_B);
524 /* Enable enhanced features */
525 regcache_cache_bypass(s->regmap, true);
526 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
527 SC16IS7XX_EFR_ENABLE_BIT,
528 SC16IS7XX_EFR_ENABLE_BIT);
529 regcache_cache_bypass(s->regmap, false);
531 /* Put LCR back to the normal mode */
532 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
534 mutex_unlock(&s->efr_lock);
536 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
537 SC16IS7XX_MCR_CLKSEL_BIT,
540 /* Open the LCR divisors for configuration */
541 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
542 SC16IS7XX_LCR_CONF_MODE_A);
544 /* Write the new divisor */
545 regcache_cache_bypass(s->regmap, true);
546 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
547 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
548 regcache_cache_bypass(s->regmap, false);
550 /* Put LCR back to the normal mode */
551 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
553 return DIV_ROUND_CLOSEST(clk / 16, div);
556 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
559 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
560 unsigned int lsr = 0, ch, flag, bytes_read, i;
561 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
563 if (unlikely(rxlen >= sizeof(s->buf))) {
564 dev_warn_ratelimited(port->dev,
565 "ttySC%i: Possible RX FIFO overrun: %d\n",
567 port->icount.buf_overrun++;
568 /* Ensure sanity of RX level */
569 rxlen = sizeof(s->buf);
573 /* Only read lsr if there are possible errors in FIFO */
575 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
576 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
577 read_lsr = false; /* No errors left in FIFO */
582 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
585 sc16is7xx_fifo_read(port, rxlen);
589 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
595 if (lsr & SC16IS7XX_LSR_BI_BIT) {
597 if (uart_handle_break(port))
599 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
600 port->icount.parity++;
601 else if (lsr & SC16IS7XX_LSR_FE_BIT)
602 port->icount.frame++;
603 else if (lsr & SC16IS7XX_LSR_OE_BIT)
604 port->icount.overrun++;
606 lsr &= port->read_status_mask;
607 if (lsr & SC16IS7XX_LSR_BI_BIT)
609 else if (lsr & SC16IS7XX_LSR_PE_BIT)
611 else if (lsr & SC16IS7XX_LSR_FE_BIT)
613 else if (lsr & SC16IS7XX_LSR_OE_BIT)
617 for (i = 0; i < bytes_read; ++i) {
619 if (uart_handle_sysrq_char(port, ch))
622 if (lsr & port->ignore_status_mask)
625 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
631 tty_flip_buffer_push(&port->state->port);
634 static void sc16is7xx_handle_tx(struct uart_port *port)
636 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
637 struct circ_buf *xmit = &port->state->xmit;
638 unsigned int txlen, to_send, i;
640 if (unlikely(port->x_char)) {
641 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
647 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
650 /* Get length of data pending in circular buffer */
651 to_send = uart_circ_chars_pending(xmit);
652 if (likely(to_send)) {
653 /* Limit to size of TX FIFO */
654 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
655 if (txlen > SC16IS7XX_FIFO_SIZE) {
656 dev_err_ratelimited(port->dev,
657 "chip reports %d free bytes in TX fifo, but it only has %d",
658 txlen, SC16IS7XX_FIFO_SIZE);
661 to_send = (to_send > txlen) ? txlen : to_send;
663 /* Add data to send */
664 port->icount.tx += to_send;
666 /* Convert to linear buffer */
667 for (i = 0; i < to_send; ++i) {
668 s->buf[i] = xmit->buf[xmit->tail];
669 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
672 sc16is7xx_fifo_write(port, to_send);
675 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
676 uart_write_wakeup(port);
679 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
681 struct uart_port *port = &s->p[portno].port;
684 unsigned int iir, rxlen;
686 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
687 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
690 iir &= SC16IS7XX_IIR_ID_MASK;
693 case SC16IS7XX_IIR_RDI_SRC:
694 case SC16IS7XX_IIR_RLSE_SRC:
695 case SC16IS7XX_IIR_RTOI_SRC:
696 case SC16IS7XX_IIR_XOFFI_SRC:
697 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
699 sc16is7xx_handle_rx(port, rxlen, iir);
703 case SC16IS7XX_IIR_THRI_SRC:
704 sc16is7xx_handle_tx(port);
707 dev_err_ratelimited(port->dev,
708 "ttySC%i: Unexpected interrupt: %x",
716 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
718 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
720 mutex_lock(&s->efr_lock);
723 bool keep_polling = false;
726 for (i = 0; i < s->devtype->nr_uart; ++i)
727 keep_polling |= sc16is7xx_port_irq(s, i);
732 mutex_unlock(&s->efr_lock);
737 static void sc16is7xx_tx_proc(struct kthread_work *ws)
739 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
740 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
742 if ((port->rs485.flags & SER_RS485_ENABLED) &&
743 (port->rs485.delay_rts_before_send > 0))
744 msleep(port->rs485.delay_rts_before_send);
746 mutex_lock(&s->efr_lock);
747 sc16is7xx_handle_tx(port);
748 mutex_unlock(&s->efr_lock);
751 static void sc16is7xx_reconf_rs485(struct uart_port *port)
753 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
754 SC16IS7XX_EFCR_RTS_INVERT_BIT;
756 struct serial_rs485 *rs485 = &port->rs485;
757 unsigned long irqflags;
759 spin_lock_irqsave(&port->lock, irqflags);
760 if (rs485->flags & SER_RS485_ENABLED) {
761 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
763 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
764 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
766 spin_unlock_irqrestore(&port->lock, irqflags);
768 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
771 static void sc16is7xx_reg_proc(struct kthread_work *ws)
773 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
774 struct sc16is7xx_one_config config;
775 unsigned long irqflags;
777 spin_lock_irqsave(&one->port.lock, irqflags);
778 config = one->config;
779 memset(&one->config, 0, sizeof(one->config));
780 spin_unlock_irqrestore(&one->port.lock, irqflags);
782 if (config.flags & SC16IS7XX_RECONF_MD) {
783 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
784 SC16IS7XX_MCR_LOOP_BIT,
785 (one->port.mctrl & TIOCM_LOOP) ?
786 SC16IS7XX_MCR_LOOP_BIT : 0);
787 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
788 SC16IS7XX_MCR_RTS_BIT,
789 (one->port.mctrl & TIOCM_RTS) ?
790 SC16IS7XX_MCR_RTS_BIT : 0);
791 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
792 SC16IS7XX_MCR_DTR_BIT,
793 (one->port.mctrl & TIOCM_DTR) ?
794 SC16IS7XX_MCR_DTR_BIT : 0);
796 if (config.flags & SC16IS7XX_RECONF_IER)
797 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
798 config.ier_clear, 0);
800 if (config.flags & SC16IS7XX_RECONF_RS485)
801 sc16is7xx_reconf_rs485(&one->port);
804 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
806 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
807 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
809 one->config.flags |= SC16IS7XX_RECONF_IER;
810 one->config.ier_clear |= bit;
811 kthread_queue_work(&s->kworker, &one->reg_work);
814 static void sc16is7xx_stop_tx(struct uart_port *port)
816 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
819 static void sc16is7xx_stop_rx(struct uart_port *port)
821 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
824 static void sc16is7xx_start_tx(struct uart_port *port)
826 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
827 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
829 kthread_queue_work(&s->kworker, &one->tx_work);
832 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
836 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
838 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
841 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
843 /* DCD and DSR are not wired and CTS/RTS is handled automatically
844 * so just indicate DSR and CAR asserted
846 return TIOCM_DSR | TIOCM_CAR | TIOCM_RI | TIOCM_CTS;
849 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
851 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
852 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
854 one->config.flags |= SC16IS7XX_RECONF_MD;
855 kthread_queue_work(&s->kworker, &one->reg_work);
858 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
860 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
861 SC16IS7XX_LCR_TXBREAK_BIT,
862 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
865 static void sc16is7xx_set_termios(struct uart_port *port,
866 struct ktermios *termios,
867 struct ktermios *old)
869 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
870 unsigned int lcr, flow = 0;
873 /* Mask termios capabilities we don't support */
874 termios->c_cflag &= ~CMSPAR;
877 switch (termios->c_cflag & CSIZE) {
879 lcr = SC16IS7XX_LCR_WORD_LEN_5;
882 lcr = SC16IS7XX_LCR_WORD_LEN_6;
885 lcr = SC16IS7XX_LCR_WORD_LEN_7;
888 lcr = SC16IS7XX_LCR_WORD_LEN_8;
891 lcr = SC16IS7XX_LCR_WORD_LEN_8;
892 termios->c_cflag &= ~CSIZE;
893 termios->c_cflag |= CS8;
898 if (termios->c_cflag & PARENB) {
899 lcr |= SC16IS7XX_LCR_PARITY_BIT;
900 if (!(termios->c_cflag & PARODD))
901 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
905 if (termios->c_cflag & CSTOPB)
906 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
908 /* Set read status mask */
909 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
910 if (termios->c_iflag & INPCK)
911 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
912 SC16IS7XX_LSR_FE_BIT;
913 if (termios->c_iflag & (BRKINT | PARMRK))
914 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
916 /* Set status ignore mask */
917 port->ignore_status_mask = 0;
918 if (termios->c_iflag & IGNBRK)
919 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
920 if (!(termios->c_cflag & CREAD))
921 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
923 /* As above, claim the mutex while accessing the EFR. */
924 mutex_lock(&s->efr_lock);
926 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
927 SC16IS7XX_LCR_CONF_MODE_B);
929 /* Configure flow control */
930 regcache_cache_bypass(s->regmap, true);
931 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
932 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
933 if (termios->c_cflag & CRTSCTS) {
934 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
935 SC16IS7XX_EFR_AUTORTS_BIT;
936 port->status |= UPSTAT_AUTOCTS;
938 if (termios->c_iflag & IXON)
939 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
940 if (termios->c_iflag & IXOFF)
941 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
943 /* Always set enable enhanced */
944 flow |= SC16IS7XX_EFR_ENABLE_BIT;
946 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
947 regcache_cache_bypass(s->regmap, false);
949 /* Update LCR register */
950 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
952 mutex_unlock(&s->efr_lock);
954 /* Get baud rate generator configuration */
955 baud = uart_get_baud_rate(port, termios, old,
956 port->uartclk / 16 / 4 / 0xffff,
959 /* Setup baudrate generator */
960 baud = sc16is7xx_set_baud(port, baud);
962 /* Update timeout according to new baud rate */
963 uart_update_timeout(port, termios->c_cflag, baud);
966 static int sc16is7xx_config_rs485(struct uart_port *port,
967 struct serial_rs485 *rs485)
969 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
970 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
972 if (rs485->flags & SER_RS485_ENABLED) {
973 bool rts_during_rx, rts_during_tx;
975 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
976 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
978 if (rts_during_rx == rts_during_tx)
980 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
981 rts_during_tx, rts_during_rx);
984 * RTS signal is handled by HW, it's timing can't be influenced.
985 * However, it's sometimes useful to delay TX even without RTS
986 * control therefore we try to handle .delay_rts_before_send.
988 if (rs485->delay_rts_after_send)
992 port->rs485 = *rs485;
993 one->config.flags |= SC16IS7XX_RECONF_RS485;
994 kthread_queue_work(&s->kworker, &one->reg_work);
999 static int sc16is7xx_startup(struct uart_port *port)
1001 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1002 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1005 sc16is7xx_power(port, 1);
1008 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1009 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1011 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1012 SC16IS7XX_FCR_FIFO_BIT);
1015 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1016 SC16IS7XX_LCR_CONF_MODE_B);
1018 regcache_cache_bypass(s->regmap, true);
1020 /* Enable write access to enhanced features and internal clock div */
1021 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
1022 SC16IS7XX_EFR_ENABLE_BIT);
1024 /* Enable TCR/TLR */
1025 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1026 SC16IS7XX_MCR_TCRTLR_BIT,
1027 SC16IS7XX_MCR_TCRTLR_BIT);
1029 /* Configure flow control levels */
1030 /* Flow control halt level 48, resume level 24 */
1031 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1032 SC16IS7XX_TCR_RX_RESUME(24) |
1033 SC16IS7XX_TCR_RX_HALT(48));
1035 regcache_cache_bypass(s->regmap, false);
1037 /* Now, initialize the UART */
1038 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1040 /* Enable IrDA mode if requested in DT */
1041 /* This bit must be written with LCR[7] = 0 */
1042 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1043 SC16IS7XX_MCR_IRDA_BIT,
1045 SC16IS7XX_MCR_IRDA_BIT : 0);
1047 /* Enable the Rx and Tx FIFO */
1048 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1049 SC16IS7XX_EFCR_RXDISABLE_BIT |
1050 SC16IS7XX_EFCR_TXDISABLE_BIT,
1053 /* Enable RX, TX interrupts */
1054 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT;
1055 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1060 static void sc16is7xx_shutdown(struct uart_port *port)
1062 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1064 /* Disable all interrupts */
1065 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1067 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1068 SC16IS7XX_EFCR_RXDISABLE_BIT |
1069 SC16IS7XX_EFCR_TXDISABLE_BIT,
1070 SC16IS7XX_EFCR_RXDISABLE_BIT |
1071 SC16IS7XX_EFCR_TXDISABLE_BIT);
1073 sc16is7xx_power(port, 0);
1075 kthread_flush_worker(&s->kworker);
1078 static const char *sc16is7xx_type(struct uart_port *port)
1080 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1082 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1085 static int sc16is7xx_request_port(struct uart_port *port)
1091 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1093 if (flags & UART_CONFIG_TYPE)
1094 port->type = PORT_SC16IS7XX;
1097 static int sc16is7xx_verify_port(struct uart_port *port,
1098 struct serial_struct *s)
1100 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1102 if (s->irq != port->irq)
1108 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1109 unsigned int oldstate)
1111 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1114 static void sc16is7xx_null_void(struct uart_port *port)
1119 static const struct uart_ops sc16is7xx_ops = {
1120 .tx_empty = sc16is7xx_tx_empty,
1121 .set_mctrl = sc16is7xx_set_mctrl,
1122 .get_mctrl = sc16is7xx_get_mctrl,
1123 .stop_tx = sc16is7xx_stop_tx,
1124 .start_tx = sc16is7xx_start_tx,
1125 .stop_rx = sc16is7xx_stop_rx,
1126 .break_ctl = sc16is7xx_break_ctl,
1127 .startup = sc16is7xx_startup,
1128 .shutdown = sc16is7xx_shutdown,
1129 .set_termios = sc16is7xx_set_termios,
1130 .type = sc16is7xx_type,
1131 .request_port = sc16is7xx_request_port,
1132 .release_port = sc16is7xx_null_void,
1133 .config_port = sc16is7xx_config_port,
1134 .verify_port = sc16is7xx_verify_port,
1138 #ifdef CONFIG_GPIOLIB
1139 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1142 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1143 struct uart_port *port = &s->p[0].port;
1145 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1147 return !!(val & BIT(offset));
1150 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1152 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1153 struct uart_port *port = &s->p[0].port;
1155 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1156 val ? BIT(offset) : 0);
1159 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1162 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1163 struct uart_port *port = &s->p[0].port;
1165 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1170 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1171 unsigned offset, int val)
1173 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1174 struct uart_port *port = &s->p[0].port;
1175 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1178 state |= BIT(offset);
1180 state &= ~BIT(offset);
1181 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1182 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1189 static int sc16is7xx_probe(struct device *dev,
1190 const struct sc16is7xx_devtype *devtype,
1191 struct regmap *regmap, int irq)
1193 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1197 struct sc16is7xx_port *s;
1200 return PTR_ERR(regmap);
1203 * This device does not have an identification register that would
1204 * tell us if we are really connected to the correct device.
1205 * The best we can do is to check if communication is at all possible.
1207 ret = regmap_read(regmap,
1208 SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val);
1210 return -EPROBE_DEFER;
1212 /* Alloc port structure */
1213 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1215 dev_err(dev, "Error allocating port structure\n");
1219 /* Always ask for fixed clock rate from a property. */
1220 device_property_read_u32(dev, "clock-frequency", &uartclk);
1222 s->clk = devm_clk_get_optional(dev, NULL);
1224 return PTR_ERR(s->clk);
1226 ret = clk_prepare_enable(s->clk);
1230 freq = clk_get_rate(s->clk);
1237 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1243 s->devtype = devtype;
1244 dev_set_drvdata(dev, s);
1245 mutex_init(&s->efr_lock);
1247 kthread_init_worker(&s->kworker);
1248 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1250 if (IS_ERR(s->kworker_task)) {
1251 ret = PTR_ERR(s->kworker_task);
1254 sched_set_fifo(s->kworker_task);
1256 #ifdef CONFIG_GPIOLIB
1257 if (devtype->nr_gpio) {
1258 /* Setup GPIO cotroller */
1259 s->gpio.owner = THIS_MODULE;
1260 s->gpio.parent = dev;
1261 s->gpio.label = dev_name(dev);
1262 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1263 s->gpio.get = sc16is7xx_gpio_get;
1264 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1265 s->gpio.set = sc16is7xx_gpio_set;
1267 s->gpio.ngpio = devtype->nr_gpio;
1268 s->gpio.can_sleep = 1;
1269 ret = gpiochip_add_data(&s->gpio, s);
1275 /* reset device, purging any pending irq / data */
1276 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1277 SC16IS7XX_IOCONTROL_SRESET_BIT);
1279 for (i = 0; i < devtype->nr_uart; ++i) {
1281 /* Initialize port data */
1282 s->p[i].port.dev = dev;
1283 s->p[i].port.irq = irq;
1284 s->p[i].port.type = PORT_SC16IS7XX;
1285 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1286 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1287 s->p[i].port.iobase = i;
1288 s->p[i].port.iotype = UPIO_PORT;
1289 s->p[i].port.uartclk = freq;
1290 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1291 s->p[i].port.ops = &sc16is7xx_ops;
1292 s->p[i].port.line = sc16is7xx_alloc_line();
1293 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1298 /* Disable all interrupts */
1299 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1301 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1302 SC16IS7XX_EFCR_RXDISABLE_BIT |
1303 SC16IS7XX_EFCR_TXDISABLE_BIT);
1304 /* Initialize kthread work structs */
1305 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1306 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1308 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1311 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1312 SC16IS7XX_LCR_CONF_MODE_B);
1314 regcache_cache_bypass(s->regmap, true);
1316 /* Enable write access to enhanced features */
1317 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1318 SC16IS7XX_EFR_ENABLE_BIT);
1320 regcache_cache_bypass(s->regmap, false);
1322 /* Restore access to general registers */
1323 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1325 /* Go to suspend mode */
1326 sc16is7xx_power(&s->p[i].port, 0);
1330 struct property *prop;
1334 of_property_for_each_u32(dev->of_node, "irda-mode-ports",
1336 if (u < devtype->nr_uart)
1337 s->p[u].irda_mode = true;
1341 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1342 * If that succeeds, we can allow sharing the interrupt as well.
1343 * In case the interrupt controller doesn't support that, we fall
1344 * back to a non-shared falling-edge trigger.
1346 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1347 IRQF_TRIGGER_LOW | IRQF_SHARED |
1353 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1354 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1360 for (i--; i >= 0; i--) {
1361 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1362 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1365 #ifdef CONFIG_GPIOLIB
1366 if (devtype->nr_gpio)
1367 gpiochip_remove(&s->gpio);
1371 kthread_stop(s->kworker_task);
1374 clk_disable_unprepare(s->clk);
1379 static int sc16is7xx_remove(struct device *dev)
1381 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1384 #ifdef CONFIG_GPIOLIB
1385 if (s->devtype->nr_gpio)
1386 gpiochip_remove(&s->gpio);
1389 for (i = 0; i < s->devtype->nr_uart; i++) {
1390 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1391 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1392 sc16is7xx_power(&s->p[i].port, 0);
1395 kthread_flush_worker(&s->kworker);
1396 kthread_stop(s->kworker_task);
1398 clk_disable_unprepare(s->clk);
1403 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1404 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1405 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1406 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1407 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1408 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1409 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1412 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1414 static struct regmap_config regcfg = {
1418 .cache_type = REGCACHE_RBTREE,
1419 .volatile_reg = sc16is7xx_regmap_volatile,
1420 .precious_reg = sc16is7xx_regmap_precious,
1423 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1424 static int sc16is7xx_spi_probe(struct spi_device *spi)
1426 const struct sc16is7xx_devtype *devtype;
1427 struct regmap *regmap;
1431 spi->bits_per_word = 8;
1432 /* only supports mode 0 on SC16IS762 */
1433 spi->mode = spi->mode ? : SPI_MODE_0;
1434 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1435 ret = spi_setup(spi);
1439 if (spi->dev.of_node) {
1440 devtype = device_get_match_data(&spi->dev);
1444 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1446 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1449 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1450 (devtype->nr_uart - 1);
1451 regmap = devm_regmap_init_spi(spi, ®cfg);
1453 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq);
1456 static int sc16is7xx_spi_remove(struct spi_device *spi)
1458 return sc16is7xx_remove(&spi->dev);
1461 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1462 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1463 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1464 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1465 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1466 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1467 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1468 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1472 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1474 static struct spi_driver sc16is7xx_spi_uart_driver = {
1476 .name = SC16IS7XX_NAME,
1477 .of_match_table = sc16is7xx_dt_ids,
1479 .probe = sc16is7xx_spi_probe,
1480 .remove = sc16is7xx_spi_remove,
1481 .id_table = sc16is7xx_spi_id_table,
1484 MODULE_ALIAS("spi:sc16is7xx");
1487 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1488 static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1489 const struct i2c_device_id *id)
1491 const struct sc16is7xx_devtype *devtype;
1492 struct regmap *regmap;
1494 if (i2c->dev.of_node) {
1495 devtype = device_get_match_data(&i2c->dev);
1499 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1502 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1503 (devtype->nr_uart - 1);
1504 regmap = devm_regmap_init_i2c(i2c, ®cfg);
1506 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq);
1509 static int sc16is7xx_i2c_remove(struct i2c_client *client)
1511 return sc16is7xx_remove(&client->dev);
1514 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1515 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1516 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1517 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1518 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1519 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1520 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1521 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1524 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1526 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1528 .name = SC16IS7XX_NAME,
1529 .of_match_table = sc16is7xx_dt_ids,
1531 .probe = sc16is7xx_i2c_probe,
1532 .remove = sc16is7xx_i2c_remove,
1533 .id_table = sc16is7xx_i2c_id_table,
1538 static int __init sc16is7xx_init(void)
1542 ret = uart_register_driver(&sc16is7xx_uart);
1544 pr_err("Registering UART driver failed\n");
1548 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1549 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1551 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1556 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1557 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1559 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1565 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1568 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1569 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1572 uart_unregister_driver(&sc16is7xx_uart);
1575 module_init(sc16is7xx_init);
1577 static void __exit sc16is7xx_exit(void)
1579 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1580 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1583 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1584 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1586 uart_unregister_driver(&sc16is7xx_uart);
1588 module_exit(sc16is7xx_exit);
1590 MODULE_LICENSE("GPL");
1591 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1592 MODULE_DESCRIPTION("SC16IS7XX serial driver");