1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
4 * Author: Jon Ringle <jringle@gridpoint.com>
6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/i2c.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/spi/spi.h>
26 #include <linux/uaccess.h>
27 #include <linux/units.h>
28 #include <uapi/linux/sched/types.h>
30 #define SC16IS7XX_NAME "sc16is7xx"
31 #define SC16IS7XX_MAX_DEVS 8
33 /* SC16IS7XX register definitions */
34 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
49 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
52 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
55 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
58 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
60 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
64 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
68 /* Enhanced Register set: Only if (LCR == 0xBF) */
69 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
75 /* IER register bits */
76 #define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77 #define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
79 #define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
81 #define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
84 /* IER register bits - write only if (EFR[4] == 1) */
85 #define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86 #define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87 #define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88 #define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
90 /* FCR register bits */
91 #define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92 #define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93 #define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94 #define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95 #define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
97 /* FCR register bits - write only if (EFR[4] == 1) */
98 #define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99 #define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
101 /* IIR register bits */
102 #define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103 #define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
111 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
114 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
119 /* LCR register bits */
120 #define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121 #define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
123 * Word length bits table:
129 #define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
131 * STOP length bit table:
133 * 1 -> 1-1.5 stop bits if
135 * 2 stop bits otherwise
137 #define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138 #define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139 #define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140 #define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141 #define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
148 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
151 /* MCR register bits */
152 #define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
155 #define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156 #define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157 #define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158 #define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
162 #define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
166 #define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
171 /* LSR register bits */
172 #define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173 #define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174 #define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175 #define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176 #define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177 #define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178 #define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179 #define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180 #define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
182 /* MSR register bits */
183 #define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184 #define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
188 #define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
192 #define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
196 #define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
197 #define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
200 #define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
203 #define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
206 #define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
217 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
235 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
238 /* IOControl register bits (Only 750/760) */
239 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */
241 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */
242 #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
244 /* EFCR register bits */
245 #define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
247 #define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
248 #define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
249 #define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
250 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
251 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
252 * 0 = rate upto 115.2 kbit/s
254 * 1 = rate upto 1.152 Mbit/s
258 /* EFR register bits */
259 #define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
260 #define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
261 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
262 #define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
263 * and writing to IER[7:4],
266 #define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
267 #define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
269 * SWFLOW bits 3 & 2 table:
270 * 00 -> no transmitter flow
272 * 01 -> transmitter generates
274 * 10 -> transmitter generates
276 * 11 -> transmitter generates
277 * XON1, XON2, XOFF1 and
280 #define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
281 #define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
283 * SWFLOW bits 3 & 2 table:
284 * 00 -> no received flow
286 * 01 -> receiver compares
288 * 10 -> receiver compares
290 * 11 -> receiver compares
291 * XON1, XON2, XOFF1 and
294 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
295 SC16IS7XX_EFR_AUTOCTS_BIT | \
296 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
297 SC16IS7XX_EFR_SWFLOW3_BIT | \
298 SC16IS7XX_EFR_SWFLOW2_BIT | \
299 SC16IS7XX_EFR_SWFLOW1_BIT | \
300 SC16IS7XX_EFR_SWFLOW0_BIT)
303 /* Misc definitions */
304 #define SC16IS7XX_SPI_READ_BIT BIT(7)
305 #define SC16IS7XX_FIFO_SIZE (64)
306 #define SC16IS7XX_GPIOS_PER_BANK 4
308 struct sc16is7xx_devtype {
314 #define SC16IS7XX_RECONF_MD (1 << 0)
315 #define SC16IS7XX_RECONF_IER (1 << 1)
316 #define SC16IS7XX_RECONF_RS485 (1 << 2)
318 struct sc16is7xx_one_config {
324 struct sc16is7xx_one {
325 struct uart_port port;
326 struct regmap *regmap;
327 struct mutex efr_lock; /* EFR registers access */
328 struct kthread_work tx_work;
329 struct kthread_work reg_work;
330 struct kthread_delayed_work ms_work;
331 struct sc16is7xx_one_config config;
333 unsigned int old_mctrl;
336 struct sc16is7xx_port {
337 const struct sc16is7xx_devtype *devtype;
339 #ifdef CONFIG_GPIOLIB
340 struct gpio_chip gpio;
341 unsigned long gpio_valid_mask;
344 unsigned char buf[SC16IS7XX_FIFO_SIZE];
345 struct kthread_worker kworker;
346 struct task_struct *kworker_task;
347 struct sc16is7xx_one p[];
350 static unsigned long sc16is7xx_lines;
352 static struct uart_driver sc16is7xx_uart = {
353 .owner = THIS_MODULE,
355 .nr = SC16IS7XX_MAX_DEVS,
358 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit);
359 static void sc16is7xx_stop_tx(struct uart_port *port);
361 #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
362 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
364 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
366 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
367 unsigned int val = 0;
369 regmap_read(one->regmap, reg, &val);
374 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
376 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
378 regmap_write(one->regmap, reg, val);
381 static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
383 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
384 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
386 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, s->buf, rxlen);
389 static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
391 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
392 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
395 * Don't send zero-length data, at least on SPI it confuses the chip
396 * delivering wrong TXLVL data.
398 if (unlikely(!to_send))
401 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
404 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
407 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
409 regmap_update_bits(one->regmap, reg, mask, val);
412 static void sc16is7xx_power(struct uart_port *port, int on)
414 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
415 SC16IS7XX_IER_SLEEP_BIT,
416 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
419 static const struct sc16is7xx_devtype sc16is74x_devtype = {
425 static const struct sc16is7xx_devtype sc16is750_devtype = {
431 static const struct sc16is7xx_devtype sc16is752_devtype = {
437 static const struct sc16is7xx_devtype sc16is760_devtype = {
443 static const struct sc16is7xx_devtype sc16is762_devtype = {
449 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
452 case SC16IS7XX_RHR_REG:
453 case SC16IS7XX_IIR_REG:
454 case SC16IS7XX_LSR_REG:
455 case SC16IS7XX_MSR_REG:
456 case SC16IS7XX_TXLVL_REG:
457 case SC16IS7XX_RXLVL_REG:
458 case SC16IS7XX_IOSTATE_REG:
459 case SC16IS7XX_IOCONTROL_REG:
468 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
471 case SC16IS7XX_RHR_REG:
480 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
482 return reg == SC16IS7XX_RHR_REG;
485 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
487 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
490 unsigned long clk = port->uartclk, div = clk / 16 / baud;
493 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
497 /* In an amazing feat of design, the Enhanced Features Register shares
498 * the address of the Interrupt Identification Register, and is
499 * switched in by writing a magic value (0xbf) to the Line Control
500 * Register. Any interrupt firing during this time will see the EFR
501 * where it expects the IIR to be, leading to "Unexpected interrupt"
504 * Prevent this possibility by claiming a mutex while accessing the
505 * EFR, and claiming the same mutex from within the interrupt handler.
506 * This is similar to disabling the interrupt, but that doesn't work
507 * because the bulk of the interrupt processing is run as a workqueue
508 * job in thread context.
510 mutex_lock(&one->efr_lock);
512 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
514 /* Open the LCR divisors for configuration */
515 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
516 SC16IS7XX_LCR_CONF_MODE_B);
518 /* Enable enhanced features */
519 regcache_cache_bypass(one->regmap, true);
520 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
521 SC16IS7XX_EFR_ENABLE_BIT,
522 SC16IS7XX_EFR_ENABLE_BIT);
524 regcache_cache_bypass(one->regmap, false);
526 /* Put LCR back to the normal mode */
527 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
529 mutex_unlock(&one->efr_lock);
531 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
532 SC16IS7XX_MCR_CLKSEL_BIT,
535 /* Open the LCR divisors for configuration */
536 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
537 SC16IS7XX_LCR_CONF_MODE_A);
539 /* Write the new divisor */
540 regcache_cache_bypass(one->regmap, true);
541 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
542 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
543 regcache_cache_bypass(one->regmap, false);
545 /* Put LCR back to the normal mode */
546 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
548 return DIV_ROUND_CLOSEST(clk / 16, div);
551 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
554 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
555 unsigned int lsr = 0, bytes_read, i;
556 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
559 if (unlikely(rxlen >= sizeof(s->buf))) {
560 dev_warn_ratelimited(port->dev,
561 "ttySC%i: Possible RX FIFO overrun: %d\n",
563 port->icount.buf_overrun++;
564 /* Ensure sanity of RX level */
565 rxlen = sizeof(s->buf);
569 /* Only read lsr if there are possible errors in FIFO */
571 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
572 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
573 read_lsr = false; /* No errors left in FIFO */
578 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
581 sc16is7xx_fifo_read(port, rxlen);
585 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
591 if (lsr & SC16IS7XX_LSR_BI_BIT) {
593 if (uart_handle_break(port))
595 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
596 port->icount.parity++;
597 else if (lsr & SC16IS7XX_LSR_FE_BIT)
598 port->icount.frame++;
599 else if (lsr & SC16IS7XX_LSR_OE_BIT)
600 port->icount.overrun++;
602 lsr &= port->read_status_mask;
603 if (lsr & SC16IS7XX_LSR_BI_BIT)
605 else if (lsr & SC16IS7XX_LSR_PE_BIT)
607 else if (lsr & SC16IS7XX_LSR_FE_BIT)
609 else if (lsr & SC16IS7XX_LSR_OE_BIT)
613 for (i = 0; i < bytes_read; ++i) {
615 if (uart_handle_sysrq_char(port, ch))
618 if (lsr & port->ignore_status_mask)
621 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
627 tty_flip_buffer_push(&port->state->port);
630 static void sc16is7xx_handle_tx(struct uart_port *port)
632 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
633 struct circ_buf *xmit = &port->state->xmit;
634 unsigned int txlen, to_send, i;
637 if (unlikely(port->x_char)) {
638 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
644 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
645 uart_port_lock_irqsave(port, &flags);
646 sc16is7xx_stop_tx(port);
647 uart_port_unlock_irqrestore(port, flags);
651 /* Get length of data pending in circular buffer */
652 to_send = uart_circ_chars_pending(xmit);
653 if (likely(to_send)) {
654 /* Limit to size of TX FIFO */
655 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
656 if (txlen > SC16IS7XX_FIFO_SIZE) {
657 dev_err_ratelimited(port->dev,
658 "chip reports %d free bytes in TX fifo, but it only has %d",
659 txlen, SC16IS7XX_FIFO_SIZE);
662 to_send = (to_send > txlen) ? txlen : to_send;
664 /* Convert to linear buffer */
665 for (i = 0; i < to_send; ++i) {
666 s->buf[i] = xmit->buf[xmit->tail];
667 uart_xmit_advance(port, 1);
670 sc16is7xx_fifo_write(port, to_send);
673 uart_port_lock_irqsave(port, &flags);
674 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
675 uart_write_wakeup(port);
677 if (uart_circ_empty(xmit))
678 sc16is7xx_stop_tx(port);
680 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
681 uart_port_unlock_irqrestore(port, flags);
684 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
686 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
687 unsigned int mctrl = 0;
689 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
690 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
691 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0;
692 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0;
696 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
698 struct uart_port *port = &one->port;
700 unsigned int status, changed;
702 lockdep_assert_held_once(&one->efr_lock);
704 status = sc16is7xx_get_hwmctrl(port);
705 changed = status ^ one->old_mctrl;
710 one->old_mctrl = status;
712 uart_port_lock_irqsave(port, &flags);
713 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
715 if (changed & TIOCM_DSR)
717 if (changed & TIOCM_CAR)
718 uart_handle_dcd_change(port, status & TIOCM_CAR);
719 if (changed & TIOCM_CTS)
720 uart_handle_cts_change(port, status & TIOCM_CTS);
722 wake_up_interruptible(&port->state->port.delta_msr_wait);
723 uart_port_unlock_irqrestore(port, flags);
726 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
729 unsigned int iir, rxlen;
730 struct uart_port *port = &s->p[portno].port;
731 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
733 mutex_lock(&one->efr_lock);
735 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
736 if (iir & SC16IS7XX_IIR_NO_INT_BIT) {
741 iir &= SC16IS7XX_IIR_ID_MASK;
744 case SC16IS7XX_IIR_RDI_SRC:
745 case SC16IS7XX_IIR_RLSE_SRC:
746 case SC16IS7XX_IIR_RTOI_SRC:
747 case SC16IS7XX_IIR_XOFFI_SRC:
748 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
751 * There is a silicon bug that makes the chip report a
752 * time-out interrupt but no data in the FIFO. This is
753 * described in errata section 18.1.4.
755 * When this happens, read one byte from the FIFO to
756 * clear the interrupt.
758 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
762 sc16is7xx_handle_rx(port, rxlen, iir);
766 /* CTSRTS interrupt comes only when CTS goes inactive */
767 case SC16IS7XX_IIR_CTSRTS_SRC:
768 case SC16IS7XX_IIR_MSI_SRC:
769 sc16is7xx_update_mlines(one);
771 case SC16IS7XX_IIR_THRI_SRC:
772 sc16is7xx_handle_tx(port);
775 dev_err_ratelimited(port->dev,
776 "ttySC%i: Unexpected interrupt: %x",
782 mutex_unlock(&one->efr_lock);
787 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
791 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
796 keep_polling = false;
798 for (i = 0; i < s->devtype->nr_uart; ++i)
799 keep_polling |= sc16is7xx_port_irq(s, i);
800 } while (keep_polling);
805 static void sc16is7xx_tx_proc(struct kthread_work *ws)
807 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
808 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
811 if ((port->rs485.flags & SER_RS485_ENABLED) &&
812 (port->rs485.delay_rts_before_send > 0))
813 msleep(port->rs485.delay_rts_before_send);
815 mutex_lock(&one->efr_lock);
816 sc16is7xx_handle_tx(port);
817 mutex_unlock(&one->efr_lock);
819 uart_port_lock_irqsave(port, &flags);
820 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
821 uart_port_unlock_irqrestore(port, flags);
824 static void sc16is7xx_reconf_rs485(struct uart_port *port)
826 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
827 SC16IS7XX_EFCR_RTS_INVERT_BIT;
829 struct serial_rs485 *rs485 = &port->rs485;
830 unsigned long irqflags;
832 uart_port_lock_irqsave(port, &irqflags);
833 if (rs485->flags & SER_RS485_ENABLED) {
834 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
836 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
837 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
839 uart_port_unlock_irqrestore(port, irqflags);
841 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
844 static void sc16is7xx_reg_proc(struct kthread_work *ws)
846 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
847 struct sc16is7xx_one_config config;
848 unsigned long irqflags;
850 uart_port_lock_irqsave(&one->port, &irqflags);
851 config = one->config;
852 memset(&one->config, 0, sizeof(one->config));
853 uart_port_unlock_irqrestore(&one->port, irqflags);
855 if (config.flags & SC16IS7XX_RECONF_MD) {
858 /* Device ignores RTS setting when hardware flow is enabled */
859 if (one->port.mctrl & TIOCM_RTS)
860 mcr |= SC16IS7XX_MCR_RTS_BIT;
862 if (one->port.mctrl & TIOCM_DTR)
863 mcr |= SC16IS7XX_MCR_DTR_BIT;
865 if (one->port.mctrl & TIOCM_LOOP)
866 mcr |= SC16IS7XX_MCR_LOOP_BIT;
867 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
868 SC16IS7XX_MCR_RTS_BIT |
869 SC16IS7XX_MCR_DTR_BIT |
870 SC16IS7XX_MCR_LOOP_BIT,
874 if (config.flags & SC16IS7XX_RECONF_IER)
875 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
876 config.ier_mask, config.ier_val);
878 if (config.flags & SC16IS7XX_RECONF_RS485)
879 sc16is7xx_reconf_rs485(&one->port);
882 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
884 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
885 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
887 lockdep_assert_held_once(&port->lock);
889 one->config.flags |= SC16IS7XX_RECONF_IER;
890 one->config.ier_mask |= bit;
891 one->config.ier_val &= ~bit;
892 kthread_queue_work(&s->kworker, &one->reg_work);
895 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
897 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
898 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
900 lockdep_assert_held_once(&port->lock);
902 one->config.flags |= SC16IS7XX_RECONF_IER;
903 one->config.ier_mask |= bit;
904 one->config.ier_val |= bit;
905 kthread_queue_work(&s->kworker, &one->reg_work);
908 static void sc16is7xx_stop_tx(struct uart_port *port)
910 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
913 static void sc16is7xx_stop_rx(struct uart_port *port)
915 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
918 static void sc16is7xx_ms_proc(struct kthread_work *ws)
920 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
921 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
923 if (one->port.state) {
924 mutex_lock(&one->efr_lock);
925 sc16is7xx_update_mlines(one);
926 mutex_unlock(&one->efr_lock);
928 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
932 static void sc16is7xx_enable_ms(struct uart_port *port)
934 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
935 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
937 lockdep_assert_held_once(&port->lock);
939 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
942 static void sc16is7xx_start_tx(struct uart_port *port)
944 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
945 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
947 kthread_queue_work(&s->kworker, &one->tx_work);
950 static void sc16is7xx_throttle(struct uart_port *port)
955 * Hardware flow control is enabled and thus the device ignores RTS
956 * value set in MCR register. Stop reading data from RX FIFO so the
957 * AutoRTS feature will de-activate RTS output.
959 uart_port_lock_irqsave(port, &flags);
960 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
961 uart_port_unlock_irqrestore(port, flags);
964 static void sc16is7xx_unthrottle(struct uart_port *port)
968 uart_port_lock_irqsave(port, &flags);
969 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
970 uart_port_unlock_irqrestore(port, flags);
973 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
977 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
979 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
982 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
984 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
986 /* Called with port lock taken so we can only return cached value */
987 return one->old_mctrl;
990 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
992 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
993 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
995 one->config.flags |= SC16IS7XX_RECONF_MD;
996 kthread_queue_work(&s->kworker, &one->reg_work);
999 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
1001 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
1002 SC16IS7XX_LCR_TXBREAK_BIT,
1003 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
1006 static void sc16is7xx_set_termios(struct uart_port *port,
1007 struct ktermios *termios,
1008 const struct ktermios *old)
1010 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1011 unsigned int lcr, flow = 0;
1013 unsigned long flags;
1015 kthread_cancel_delayed_work_sync(&one->ms_work);
1017 /* Mask termios capabilities we don't support */
1018 termios->c_cflag &= ~CMSPAR;
1021 switch (termios->c_cflag & CSIZE) {
1023 lcr = SC16IS7XX_LCR_WORD_LEN_5;
1026 lcr = SC16IS7XX_LCR_WORD_LEN_6;
1029 lcr = SC16IS7XX_LCR_WORD_LEN_7;
1032 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1035 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1036 termios->c_cflag &= ~CSIZE;
1037 termios->c_cflag |= CS8;
1042 if (termios->c_cflag & PARENB) {
1043 lcr |= SC16IS7XX_LCR_PARITY_BIT;
1044 if (!(termios->c_cflag & PARODD))
1045 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1049 if (termios->c_cflag & CSTOPB)
1050 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1052 /* Set read status mask */
1053 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1054 if (termios->c_iflag & INPCK)
1055 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1056 SC16IS7XX_LSR_FE_BIT;
1057 if (termios->c_iflag & (BRKINT | PARMRK))
1058 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1060 /* Set status ignore mask */
1061 port->ignore_status_mask = 0;
1062 if (termios->c_iflag & IGNBRK)
1063 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1064 if (!(termios->c_cflag & CREAD))
1065 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1067 /* As above, claim the mutex while accessing the EFR. */
1068 mutex_lock(&one->efr_lock);
1070 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1071 SC16IS7XX_LCR_CONF_MODE_B);
1073 /* Configure flow control */
1074 regcache_cache_bypass(one->regmap, true);
1075 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1076 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1078 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1079 if (termios->c_cflag & CRTSCTS) {
1080 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1081 SC16IS7XX_EFR_AUTORTS_BIT;
1082 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1084 if (termios->c_iflag & IXON)
1085 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1086 if (termios->c_iflag & IXOFF)
1087 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1089 sc16is7xx_port_update(port,
1091 SC16IS7XX_EFR_FLOWCTRL_BITS,
1093 regcache_cache_bypass(one->regmap, false);
1095 /* Update LCR register */
1096 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1098 mutex_unlock(&one->efr_lock);
1100 /* Get baud rate generator configuration */
1101 baud = uart_get_baud_rate(port, termios, old,
1102 port->uartclk / 16 / 4 / 0xffff,
1103 port->uartclk / 16);
1105 /* Setup baudrate generator */
1106 baud = sc16is7xx_set_baud(port, baud);
1108 uart_port_lock_irqsave(port, &flags);
1110 /* Update timeout according to new baud rate */
1111 uart_update_timeout(port, termios->c_cflag, baud);
1113 if (UART_ENABLE_MS(port, termios->c_cflag))
1114 sc16is7xx_enable_ms(port);
1116 uart_port_unlock_irqrestore(port, flags);
1119 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1120 struct serial_rs485 *rs485)
1122 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1123 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1125 if (rs485->flags & SER_RS485_ENABLED) {
1127 * RTS signal is handled by HW, it's timing can't be influenced.
1128 * However, it's sometimes useful to delay TX even without RTS
1129 * control therefore we try to handle .delay_rts_before_send.
1131 if (rs485->delay_rts_after_send)
1135 one->config.flags |= SC16IS7XX_RECONF_RS485;
1136 kthread_queue_work(&s->kworker, &one->reg_work);
1141 static int sc16is7xx_startup(struct uart_port *port)
1143 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1145 unsigned long flags;
1147 sc16is7xx_power(port, 1);
1150 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1151 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1153 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1154 SC16IS7XX_FCR_FIFO_BIT);
1157 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1158 SC16IS7XX_LCR_CONF_MODE_B);
1160 regcache_cache_bypass(one->regmap, true);
1162 /* Enable write access to enhanced features and internal clock div */
1163 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1164 SC16IS7XX_EFR_ENABLE_BIT,
1165 SC16IS7XX_EFR_ENABLE_BIT);
1167 /* Enable TCR/TLR */
1168 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1169 SC16IS7XX_MCR_TCRTLR_BIT,
1170 SC16IS7XX_MCR_TCRTLR_BIT);
1172 /* Configure flow control levels */
1173 /* Flow control halt level 48, resume level 24 */
1174 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1175 SC16IS7XX_TCR_RX_RESUME(24) |
1176 SC16IS7XX_TCR_RX_HALT(48));
1178 regcache_cache_bypass(one->regmap, false);
1180 /* Now, initialize the UART */
1181 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1183 /* Enable IrDA mode if requested in DT */
1184 /* This bit must be written with LCR[7] = 0 */
1185 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1186 SC16IS7XX_MCR_IRDA_BIT,
1188 SC16IS7XX_MCR_IRDA_BIT : 0);
1190 /* Enable the Rx and Tx FIFO */
1191 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1192 SC16IS7XX_EFCR_RXDISABLE_BIT |
1193 SC16IS7XX_EFCR_TXDISABLE_BIT,
1196 /* Enable RX, CTS change and modem lines interrupts */
1197 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1198 SC16IS7XX_IER_MSI_BIT;
1199 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1201 /* Initialize the Modem Control signals to current status */
1202 one->old_mctrl = sc16is7xx_get_hwmctrl(port);
1204 /* Enable modem status polling */
1205 uart_port_lock_irqsave(port, &flags);
1206 sc16is7xx_enable_ms(port);
1207 uart_port_unlock_irqrestore(port, flags);
1212 static void sc16is7xx_shutdown(struct uart_port *port)
1214 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1215 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1217 kthread_cancel_delayed_work_sync(&one->ms_work);
1219 /* Disable all interrupts */
1220 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1222 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1223 SC16IS7XX_EFCR_RXDISABLE_BIT |
1224 SC16IS7XX_EFCR_TXDISABLE_BIT,
1225 SC16IS7XX_EFCR_RXDISABLE_BIT |
1226 SC16IS7XX_EFCR_TXDISABLE_BIT);
1228 sc16is7xx_power(port, 0);
1230 kthread_flush_worker(&s->kworker);
1233 static const char *sc16is7xx_type(struct uart_port *port)
1235 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1237 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1240 static int sc16is7xx_request_port(struct uart_port *port)
1246 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1248 if (flags & UART_CONFIG_TYPE)
1249 port->type = PORT_SC16IS7XX;
1252 static int sc16is7xx_verify_port(struct uart_port *port,
1253 struct serial_struct *s)
1255 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1257 if (s->irq != port->irq)
1263 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1264 unsigned int oldstate)
1266 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1269 static void sc16is7xx_null_void(struct uart_port *port)
1274 static const struct uart_ops sc16is7xx_ops = {
1275 .tx_empty = sc16is7xx_tx_empty,
1276 .set_mctrl = sc16is7xx_set_mctrl,
1277 .get_mctrl = sc16is7xx_get_mctrl,
1278 .stop_tx = sc16is7xx_stop_tx,
1279 .start_tx = sc16is7xx_start_tx,
1280 .throttle = sc16is7xx_throttle,
1281 .unthrottle = sc16is7xx_unthrottle,
1282 .stop_rx = sc16is7xx_stop_rx,
1283 .enable_ms = sc16is7xx_enable_ms,
1284 .break_ctl = sc16is7xx_break_ctl,
1285 .startup = sc16is7xx_startup,
1286 .shutdown = sc16is7xx_shutdown,
1287 .set_termios = sc16is7xx_set_termios,
1288 .type = sc16is7xx_type,
1289 .request_port = sc16is7xx_request_port,
1290 .release_port = sc16is7xx_null_void,
1291 .config_port = sc16is7xx_config_port,
1292 .verify_port = sc16is7xx_verify_port,
1296 #ifdef CONFIG_GPIOLIB
1297 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1300 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1301 struct uart_port *port = &s->p[0].port;
1303 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1305 return !!(val & BIT(offset));
1308 static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1310 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1311 struct uart_port *port = &s->p[0].port;
1313 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1314 val ? BIT(offset) : 0);
1317 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1320 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1321 struct uart_port *port = &s->p[0].port;
1323 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1328 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1329 unsigned offset, int val)
1331 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1332 struct uart_port *port = &s->p[0].port;
1333 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1336 state |= BIT(offset);
1338 state &= ~BIT(offset);
1341 * If we write IOSTATE first, and then IODIR, the output value is not
1342 * transferred to the corresponding I/O pin.
1343 * The datasheet states that each register bit will be transferred to
1344 * the corresponding I/O pin programmed as output when writing to
1345 * IOSTATE. Therefore, configure direction first with IODIR, and then
1346 * set value after with IOSTATE.
1348 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1350 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1355 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,
1356 unsigned long *valid_mask,
1357 unsigned int ngpios)
1359 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1361 *valid_mask = s->gpio_valid_mask;
1366 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)
1368 struct device *dev = s->p[0].port.dev;
1370 if (!s->devtype->nr_gpio)
1373 switch (s->mctrl_mask) {
1375 s->gpio_valid_mask = GENMASK(7, 0);
1377 case SC16IS7XX_IOCONTROL_MODEM_A_BIT:
1378 s->gpio_valid_mask = GENMASK(3, 0);
1380 case SC16IS7XX_IOCONTROL_MODEM_B_BIT:
1381 s->gpio_valid_mask = GENMASK(7, 4);
1387 if (s->gpio_valid_mask == 0)
1390 s->gpio.owner = THIS_MODULE;
1391 s->gpio.parent = dev;
1392 s->gpio.label = dev_name(dev);
1393 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask;
1394 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1395 s->gpio.get = sc16is7xx_gpio_get;
1396 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1397 s->gpio.set = sc16is7xx_gpio_set;
1399 s->gpio.ngpio = s->devtype->nr_gpio;
1400 s->gpio.can_sleep = 1;
1402 return gpiochip_add_data(&s->gpio, s);
1407 * Configure ports designated to operate as modem control lines.
1409 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,
1410 struct regmap *regmap)
1416 struct device *dev = s->p[0].port.dev;
1418 count = device_property_count_u32(dev, "nxp,modem-control-line-ports");
1419 if (count < 0 || count > ARRAY_SIZE(mctrl_port))
1422 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",
1429 for (i = 0; i < count; i++) {
1430 /* Use GPIO lines as modem control lines */
1431 if (mctrl_port[i] == 0)
1432 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;
1433 else if (mctrl_port[i] == 1)
1434 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;
1440 SC16IS7XX_IOCONTROL_REG,
1441 SC16IS7XX_IOCONTROL_MODEM_A_BIT |
1442 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);
1447 static const struct serial_rs485 sc16is7xx_rs485_supported = {
1448 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND,
1449 .delay_rts_before_send = 1,
1450 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */
1453 static int sc16is7xx_probe(struct device *dev,
1454 const struct sc16is7xx_devtype *devtype,
1455 struct regmap *regmaps[], int irq)
1457 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1461 struct sc16is7xx_port *s;
1463 for (i = 0; i < devtype->nr_uart; i++)
1464 if (IS_ERR(regmaps[i]))
1465 return PTR_ERR(regmaps[i]);
1468 * This device does not have an identification register that would
1469 * tell us if we are really connected to the correct device.
1470 * The best we can do is to check if communication is at all possible.
1472 * Note: regmap[0] is used in the probe function to access registers
1473 * common to all channels/ports, as it is guaranteed to be present on
1476 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);
1478 return -EPROBE_DEFER;
1480 /* Alloc port structure */
1481 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1483 dev_err(dev, "Error allocating port structure\n");
1487 /* Always ask for fixed clock rate from a property. */
1488 device_property_read_u32(dev, "clock-frequency", &uartclk);
1490 s->clk = devm_clk_get_optional(dev, NULL);
1492 return PTR_ERR(s->clk);
1494 ret = clk_prepare_enable(s->clk);
1498 freq = clk_get_rate(s->clk);
1505 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1510 s->devtype = devtype;
1511 dev_set_drvdata(dev, s);
1513 kthread_init_worker(&s->kworker);
1514 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1516 if (IS_ERR(s->kworker_task)) {
1517 ret = PTR_ERR(s->kworker_task);
1520 sched_set_fifo(s->kworker_task);
1522 /* reset device, purging any pending irq / data */
1523 regmap_write(regmaps[0], SC16IS7XX_IOCONTROL_REG,
1524 SC16IS7XX_IOCONTROL_SRESET_BIT);
1526 for (i = 0; i < devtype->nr_uart; ++i) {
1527 s->p[i].port.line = find_first_zero_bit(&sc16is7xx_lines,
1528 SC16IS7XX_MAX_DEVS);
1529 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1534 /* Initialize port data */
1535 s->p[i].port.dev = dev;
1536 s->p[i].port.irq = irq;
1537 s->p[i].port.type = PORT_SC16IS7XX;
1538 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1539 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1540 s->p[i].port.iobase = i;
1542 * Use all ones as membase to make sure uart_configure_port() in
1543 * serial_core.c does not abort for SPI/I2C devices where the
1544 * membase address is not applicable.
1546 s->p[i].port.membase = (void __iomem *)~0;
1547 s->p[i].port.iotype = UPIO_PORT;
1548 s->p[i].port.uartclk = freq;
1549 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1550 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;
1551 s->p[i].port.ops = &sc16is7xx_ops;
1552 s->p[i].old_mctrl = 0;
1553 s->p[i].regmap = regmaps[i];
1555 mutex_init(&s->p[i].efr_lock);
1557 ret = uart_get_rs485_mode(&s->p[i].port);
1561 /* Disable all interrupts */
1562 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1564 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1565 SC16IS7XX_EFCR_RXDISABLE_BIT |
1566 SC16IS7XX_EFCR_TXDISABLE_BIT);
1568 /* Initialize kthread work structs */
1569 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1570 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1571 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);
1574 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1578 set_bit(s->p[i].port.line, &sc16is7xx_lines);
1581 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1582 SC16IS7XX_LCR_CONF_MODE_B);
1584 regcache_cache_bypass(regmaps[i], true);
1586 /* Enable write access to enhanced features */
1587 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1588 SC16IS7XX_EFR_ENABLE_BIT);
1590 regcache_cache_bypass(regmaps[i], false);
1592 /* Restore access to general registers */
1593 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1595 /* Go to suspend mode */
1596 sc16is7xx_power(&s->p[i].port, 0);
1600 struct property *prop;
1604 of_property_for_each_u32(dev->of_node, "irda-mode-ports",
1606 if (u < devtype->nr_uart)
1607 s->p[u].irda_mode = true;
1610 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);
1614 #ifdef CONFIG_GPIOLIB
1615 ret = sc16is7xx_setup_gpio_chip(s);
1621 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1622 * If that succeeds, we can allow sharing the interrupt as well.
1623 * In case the interrupt controller doesn't support that, we fall
1624 * back to a non-shared falling-edge trigger.
1626 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1627 IRQF_TRIGGER_LOW | IRQF_SHARED |
1633 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1634 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1639 #ifdef CONFIG_GPIOLIB
1640 if (s->gpio_valid_mask)
1641 gpiochip_remove(&s->gpio);
1645 for (i = 0; i < devtype->nr_uart; i++)
1646 if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines))
1647 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1649 kthread_stop(s->kworker_task);
1652 clk_disable_unprepare(s->clk);
1657 static void sc16is7xx_remove(struct device *dev)
1659 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1662 #ifdef CONFIG_GPIOLIB
1663 if (s->gpio_valid_mask)
1664 gpiochip_remove(&s->gpio);
1667 for (i = 0; i < s->devtype->nr_uart; i++) {
1668 kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1669 if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines))
1670 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1671 sc16is7xx_power(&s->p[i].port, 0);
1674 kthread_flush_worker(&s->kworker);
1675 kthread_stop(s->kworker_task);
1677 clk_disable_unprepare(s->clk);
1680 static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1681 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1682 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1683 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1684 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1685 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1686 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1689 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1691 static struct regmap_config regcfg = {
1695 .cache_type = REGCACHE_RBTREE,
1696 .volatile_reg = sc16is7xx_regmap_volatile,
1697 .precious_reg = sc16is7xx_regmap_precious,
1698 .writeable_noinc_reg = sc16is7xx_regmap_noinc,
1699 .readable_noinc_reg = sc16is7xx_regmap_noinc,
1700 .max_raw_read = SC16IS7XX_FIFO_SIZE,
1701 .max_raw_write = SC16IS7XX_FIFO_SIZE,
1702 .max_register = SC16IS7XX_EFCR_REG,
1705 static const char *sc16is7xx_regmap_name(u8 port_id)
1708 case 0: return "port0";
1709 case 1: return "port1";
1716 static unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)
1718 /* CH1,CH0 are at bits 2:1. */
1719 return port_id << 1;
1722 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1723 static int sc16is7xx_spi_probe(struct spi_device *spi)
1725 const struct sc16is7xx_devtype *devtype;
1726 struct regmap *regmaps[2];
1731 spi->bits_per_word = 8;
1732 /* For all variants, only mode 0 is supported */
1733 if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0)
1734 return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n");
1736 spi->mode = spi->mode ? : SPI_MODE_0;
1737 spi->max_speed_hz = spi->max_speed_hz ? : 4 * HZ_PER_MHZ;
1738 ret = spi_setup(spi);
1742 if (spi->dev.of_node) {
1743 devtype = device_get_match_data(&spi->dev);
1747 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1749 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1752 for (i = 0; i < devtype->nr_uart; i++) {
1753 regcfg.name = sc16is7xx_regmap_name(i);
1755 * If read_flag_mask is 0, the regmap code sets it to a default
1756 * of 0x80. Since we specify our own mask, we must add the READ
1759 regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i) |
1760 SC16IS7XX_SPI_READ_BIT;
1761 regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i);
1762 regmaps[i] = devm_regmap_init_spi(spi, ®cfg);
1765 return sc16is7xx_probe(&spi->dev, devtype, regmaps, spi->irq);
1768 static void sc16is7xx_spi_remove(struct spi_device *spi)
1770 sc16is7xx_remove(&spi->dev);
1773 static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1774 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1775 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1776 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1777 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1778 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1779 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1780 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1784 MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1786 static struct spi_driver sc16is7xx_spi_uart_driver = {
1788 .name = SC16IS7XX_NAME,
1789 .of_match_table = sc16is7xx_dt_ids,
1791 .probe = sc16is7xx_spi_probe,
1792 .remove = sc16is7xx_spi_remove,
1793 .id_table = sc16is7xx_spi_id_table,
1796 MODULE_ALIAS("spi:sc16is7xx");
1799 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1800 static int sc16is7xx_i2c_probe(struct i2c_client *i2c)
1802 const struct i2c_device_id *id = i2c_client_get_device_id(i2c);
1803 const struct sc16is7xx_devtype *devtype;
1804 struct regmap *regmaps[2];
1807 if (i2c->dev.of_node) {
1808 devtype = device_get_match_data(&i2c->dev);
1812 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1815 for (i = 0; i < devtype->nr_uart; i++) {
1816 regcfg.name = sc16is7xx_regmap_name(i);
1817 regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i);
1818 regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i);
1819 regmaps[i] = devm_regmap_init_i2c(i2c, ®cfg);
1822 return sc16is7xx_probe(&i2c->dev, devtype, regmaps, i2c->irq);
1825 static void sc16is7xx_i2c_remove(struct i2c_client *client)
1827 sc16is7xx_remove(&client->dev);
1830 static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1831 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1832 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1833 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
1834 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1835 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1836 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1837 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1840 MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1842 static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1844 .name = SC16IS7XX_NAME,
1845 .of_match_table = sc16is7xx_dt_ids,
1847 .probe = sc16is7xx_i2c_probe,
1848 .remove = sc16is7xx_i2c_remove,
1849 .id_table = sc16is7xx_i2c_id_table,
1854 static int __init sc16is7xx_init(void)
1858 ret = uart_register_driver(&sc16is7xx_uart);
1860 pr_err("Registering UART driver failed\n");
1864 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1865 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1867 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1872 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1873 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1875 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1881 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1884 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1885 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1888 uart_unregister_driver(&sc16is7xx_uart);
1891 module_init(sc16is7xx_init);
1893 static void __exit sc16is7xx_exit(void)
1895 #ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1896 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1899 #ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1900 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1902 uart_unregister_driver(&sc16is7xx_uart);
1904 module_exit(sc16is7xx_exit);
1906 MODULE_LICENSE("GPL");
1907 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1908 MODULE_DESCRIPTION("SC16IS7XX serial driver");