2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/delay.h>
43 #include <linux/clk.h>
44 #include <linux/cpufreq.h>
49 #include <mach/hardware.h>
51 #include <plat/regs-serial.h>
52 #include <plat/clock.h>
56 /* UART name and device definitions */
58 #define S3C24XX_SERIAL_NAME "ttySAC"
59 #define S3C24XX_SERIAL_MAJOR 204
60 #define S3C24XX_SERIAL_MINOR 64
62 /* macros to change one thing to another */
64 #define tx_enabled(port) ((port)->unused[0])
65 #define rx_enabled(port) ((port)->unused[1])
67 /* flag to ignore all characters coming in */
68 #define RXSTAT_DUMMY_READ (0x10000000)
70 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
72 return container_of(port, struct s3c24xx_uart_port, port);
75 /* translate a port to the device name */
77 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
79 return to_platform_device(port->dev)->name;
82 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
84 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
92 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
94 return to_ourport(port)->info->type == PORT_S3C6400;
97 static void s3c24xx_serial_rx_enable(struct uart_port *port)
100 unsigned int ucon, ufcon;
103 spin_lock_irqsave(&port->lock, flags);
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
120 static void s3c24xx_serial_rx_disable(struct uart_port *port)
125 spin_lock_irqsave(&port->lock, flags);
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
135 static void s3c24xx_serial_stop_tx(struct uart_port *port)
137 struct s3c24xx_uart_port *ourport = to_ourport(port);
139 if (tx_enabled(port)) {
140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
144 disable_irq_nosync(ourport->tx_irq);
145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
151 static void s3c24xx_serial_start_tx(struct uart_port *port)
153 struct s3c24xx_uart_port *ourport = to_ourport(port);
155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
163 enable_irq(ourport->tx_irq);
164 tx_enabled(port) = 1;
168 static void s3c24xx_serial_stop_rx(struct uart_port *port)
170 struct s3c24xx_uart_port *ourport = to_ourport(port);
172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
178 disable_irq_nosync(ourport->rx_irq);
179 rx_enabled(port) = 0;
183 static void s3c24xx_serial_enable_ms(struct uart_port *port)
187 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
189 return to_ourport(port)->info;
192 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
194 struct s3c24xx_uart_port *ourport;
196 if (port->dev == NULL)
199 ourport = container_of(port, struct s3c24xx_uart_port, port);
203 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
206 struct s3c24xx_uart_info *info = ourport->info;
208 if (ufstat & info->rx_fifofull)
209 return ourport->port.fifosize;
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
215 /* ? - where has parity gone?? */
216 #define S3C2410_UERSTAT_PARITY (0x1000)
219 s3c24xx_serial_rx_chars(int irq, void *dev_id)
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
223 unsigned int ufcon, ch, flag, ufstat, uerstat;
227 spin_lock_irqsave(&port->lock, flags);
229 while (max_count-- > 0) {
230 ufcon = rd_regl(port, S3C2410_UFCON);
231 ufstat = rd_regl(port, S3C2410_UFSTAT);
233 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
236 uerstat = rd_regl(port, S3C2410_UERSTAT);
237 ch = rd_regb(port, S3C2410_URXH);
239 if (port->flags & UPF_CONS_FLOW) {
240 int txe = s3c24xx_serial_txempty_nofifo(port);
242 if (rx_enabled(port)) {
244 rx_enabled(port) = 0;
249 ufcon |= S3C2410_UFCON_RESETRX;
250 wr_regl(port, S3C2410_UFCON, ufcon);
251 rx_enabled(port) = 1;
258 /* insert the character into the buffer */
263 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
264 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
267 /* check for break */
268 if (uerstat & S3C2410_UERSTAT_BREAK) {
271 if (uart_handle_break(port))
275 if (uerstat & S3C2410_UERSTAT_FRAME)
276 port->icount.frame++;
277 if (uerstat & S3C2410_UERSTAT_OVERRUN)
278 port->icount.overrun++;
280 uerstat &= port->read_status_mask;
282 if (uerstat & S3C2410_UERSTAT_BREAK)
284 else if (uerstat & S3C2410_UERSTAT_PARITY)
286 else if (uerstat & (S3C2410_UERSTAT_FRAME |
287 S3C2410_UERSTAT_OVERRUN))
291 if (uart_handle_sysrq_char(port, ch))
294 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
300 tty_flip_buffer_push(&port->state->port);
303 spin_unlock_irqrestore(&port->lock, flags);
307 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
309 struct s3c24xx_uart_port *ourport = id;
310 struct uart_port *port = &ourport->port;
311 struct circ_buf *xmit = &port->state->xmit;
315 spin_lock_irqsave(&port->lock, flags);
318 wr_regb(port, S3C2410_UTXH, port->x_char);
324 /* if there isn't anything more to transmit, or the uart is now
325 * stopped, disable the uart and exit
328 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
329 s3c24xx_serial_stop_tx(port);
333 /* try and drain the buffer... */
335 while (!uart_circ_empty(xmit) && count-- > 0) {
336 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
339 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
340 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
344 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
345 spin_unlock(&port->lock);
346 uart_write_wakeup(port);
347 spin_lock(&port->lock);
350 if (uart_circ_empty(xmit))
351 s3c24xx_serial_stop_tx(port);
354 spin_unlock_irqrestore(&port->lock, flags);
358 /* interrupt handler for s3c64xx and later SoC's.*/
359 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
361 struct s3c24xx_uart_port *ourport = id;
362 struct uart_port *port = &ourport->port;
363 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
364 irqreturn_t ret = IRQ_HANDLED;
366 if (pend & S3C64XX_UINTM_RXD_MSK) {
367 ret = s3c24xx_serial_rx_chars(irq, id);
368 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
370 if (pend & S3C64XX_UINTM_TXD_MSK) {
371 ret = s3c24xx_serial_tx_chars(irq, id);
372 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
377 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
379 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
380 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
381 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
383 if (ufcon & S3C2410_UFCON_FIFOMODE) {
384 if ((ufstat & info->tx_fifomask) != 0 ||
385 (ufstat & info->tx_fifofull))
391 return s3c24xx_serial_txempty_nofifo(port);
394 /* no modem control lines */
395 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
397 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
399 if (umstat & S3C2410_UMSTAT_CTS)
400 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
402 return TIOCM_CAR | TIOCM_DSR;
405 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
407 /* todo - possibly remove AFC and do manual CTS */
410 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
415 spin_lock_irqsave(&port->lock, flags);
417 ucon = rd_regl(port, S3C2410_UCON);
420 ucon |= S3C2410_UCON_SBREAK;
422 ucon &= ~S3C2410_UCON_SBREAK;
424 wr_regl(port, S3C2410_UCON, ucon);
426 spin_unlock_irqrestore(&port->lock, flags);
429 static void s3c24xx_serial_shutdown(struct uart_port *port)
431 struct s3c24xx_uart_port *ourport = to_ourport(port);
433 if (ourport->tx_claimed) {
434 if (!s3c24xx_serial_has_interrupt_mask(port))
435 free_irq(ourport->tx_irq, ourport);
436 tx_enabled(port) = 0;
437 ourport->tx_claimed = 0;
440 if (ourport->rx_claimed) {
441 if (!s3c24xx_serial_has_interrupt_mask(port))
442 free_irq(ourport->rx_irq, ourport);
443 ourport->rx_claimed = 0;
444 rx_enabled(port) = 0;
447 /* Clear pending interrupts and mask all interrupts */
448 if (s3c24xx_serial_has_interrupt_mask(port)) {
449 wr_regl(port, S3C64XX_UINTP, 0xf);
450 wr_regl(port, S3C64XX_UINTM, 0xf);
454 static int s3c24xx_serial_startup(struct uart_port *port)
456 struct s3c24xx_uart_port *ourport = to_ourport(port);
459 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
460 port->mapbase, port->membase);
462 rx_enabled(port) = 1;
464 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
465 s3c24xx_serial_portname(port), ourport);
468 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
472 ourport->rx_claimed = 1;
474 dbg("requesting tx irq...\n");
476 tx_enabled(port) = 1;
478 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
479 s3c24xx_serial_portname(port), ourport);
482 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
486 ourport->tx_claimed = 1;
488 dbg("s3c24xx_serial_startup ok\n");
490 /* the port reset code should have done the correct
491 * register setup for the port controls */
496 s3c24xx_serial_shutdown(port);
500 static int s3c64xx_serial_startup(struct uart_port *port)
502 struct s3c24xx_uart_port *ourport = to_ourport(port);
505 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
506 port->mapbase, port->membase);
508 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
509 s3c24xx_serial_portname(port), ourport);
511 dev_err(port->dev, "cannot get irq %d\n", port->irq);
515 /* For compatibility with s3c24xx Soc's */
516 rx_enabled(port) = 1;
517 ourport->rx_claimed = 1;
518 tx_enabled(port) = 0;
519 ourport->tx_claimed = 1;
521 /* Enable Rx Interrupt */
522 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
523 dbg("s3c64xx_serial_startup ok\n");
527 /* power power management control */
529 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
532 struct s3c24xx_uart_port *ourport = to_ourport(port);
534 ourport->pm_level = level;
538 if (!IS_ERR(ourport->baudclk))
539 clk_disable_unprepare(ourport->baudclk);
541 clk_disable_unprepare(ourport->clk);
545 clk_prepare_enable(ourport->clk);
547 if (!IS_ERR(ourport->baudclk))
548 clk_prepare_enable(ourport->baudclk);
552 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
556 /* baud rate calculation
558 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
559 * of different sources, including the peripheral clock ("pclk") and an
560 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
561 * with a programmable extra divisor.
563 * The following code goes through the clock sources, and calculates the
564 * baud clocks (and the resultant actual baud rates) and then tries to
565 * pick the closest one and select that.
569 #define MAX_CLK_NAME_LENGTH 15
571 static inline int s3c24xx_serial_getsource(struct uart_port *port)
573 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
576 if (info->num_clks == 1)
579 ucon = rd_regl(port, S3C2410_UCON);
580 ucon &= info->clksel_mask;
581 return ucon >> info->clksel_shift;
584 static void s3c24xx_serial_setsource(struct uart_port *port,
585 unsigned int clk_sel)
587 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
590 if (info->num_clks == 1)
593 ucon = rd_regl(port, S3C2410_UCON);
594 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
597 ucon &= ~info->clksel_mask;
598 ucon |= clk_sel << info->clksel_shift;
599 wr_regl(port, S3C2410_UCON, ucon);
602 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
603 unsigned int req_baud, struct clk **best_clk,
604 unsigned int *clk_num)
606 struct s3c24xx_uart_info *info = ourport->info;
609 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
610 char clkname[MAX_CLK_NAME_LENGTH];
611 int calc_deviation, deviation = (1 << 30) - 1;
613 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
614 ourport->info->def_clk_sel;
615 for (cnt = 0; cnt < info->num_clks; cnt++) {
616 if (!(clk_sel & (1 << cnt)))
619 sprintf(clkname, "clk_uart_baud%d", cnt);
620 clk = clk_get(ourport->port.dev, clkname);
624 rate = clk_get_rate(clk);
628 if (ourport->info->has_divslot) {
629 unsigned long div = rate / req_baud;
631 /* The UDIVSLOT register on the newer UARTs allows us to
632 * get a divisor adjustment of 1/16th on the baud clock.
634 * We don't keep the UDIVSLOT value (the 16ths we
635 * calculated by not multiplying the baud by 16) as it
636 * is easy enough to recalculate.
642 quot = (rate + (8 * req_baud)) / (16 * req_baud);
643 baud = rate / (quot * 16);
647 calc_deviation = req_baud - baud;
648 if (calc_deviation < 0)
649 calc_deviation = -calc_deviation;
651 if (calc_deviation < deviation) {
655 deviation = calc_deviation;
664 * This table takes the fractional value of the baud divisor and gives
665 * the recommended setting for the UDIVSLOT register.
667 static u16 udivslot_table[16] = {
686 static void s3c24xx_serial_set_termios(struct uart_port *port,
687 struct ktermios *termios,
688 struct ktermios *old)
690 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
691 struct s3c24xx_uart_port *ourport = to_ourport(port);
692 struct clk *clk = ERR_PTR(-EINVAL);
694 unsigned int baud, quot, clk_sel = 0;
697 unsigned int udivslot = 0;
700 * We don't support modem control lines.
702 termios->c_cflag &= ~(HUPCL | CMSPAR);
703 termios->c_cflag |= CLOCAL;
706 * Ask the core to calculate the divisor for us.
709 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
710 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
711 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
712 quot = port->custom_divisor;
716 /* check to see if we need to change clock source */
718 if (ourport->baudclk != clk) {
719 s3c24xx_serial_setsource(port, clk_sel);
721 if (!IS_ERR(ourport->baudclk)) {
722 clk_disable_unprepare(ourport->baudclk);
723 ourport->baudclk = ERR_PTR(-EINVAL);
726 clk_prepare_enable(clk);
728 ourport->baudclk = clk;
729 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
732 if (ourport->info->has_divslot) {
733 unsigned int div = ourport->baudclk_rate / baud;
735 if (cfg->has_fracval) {
736 udivslot = (div & 15);
737 dbg("fracval = %04x\n", udivslot);
739 udivslot = udivslot_table[div & 15];
740 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
744 switch (termios->c_cflag & CSIZE) {
746 dbg("config: 5bits/char\n");
747 ulcon = S3C2410_LCON_CS5;
750 dbg("config: 6bits/char\n");
751 ulcon = S3C2410_LCON_CS6;
754 dbg("config: 7bits/char\n");
755 ulcon = S3C2410_LCON_CS7;
759 dbg("config: 8bits/char\n");
760 ulcon = S3C2410_LCON_CS8;
764 /* preserve original lcon IR settings */
765 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
767 if (termios->c_cflag & CSTOPB)
768 ulcon |= S3C2410_LCON_STOPB;
770 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
772 if (termios->c_cflag & PARENB) {
773 if (termios->c_cflag & PARODD)
774 ulcon |= S3C2410_LCON_PODD;
776 ulcon |= S3C2410_LCON_PEVEN;
778 ulcon |= S3C2410_LCON_PNONE;
781 spin_lock_irqsave(&port->lock, flags);
783 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
784 ulcon, quot, udivslot);
786 wr_regl(port, S3C2410_ULCON, ulcon);
787 wr_regl(port, S3C2410_UBRDIV, quot);
788 wr_regl(port, S3C2410_UMCON, umcon);
790 if (ourport->info->has_divslot)
791 wr_regl(port, S3C2443_DIVSLOT, udivslot);
793 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
794 rd_regl(port, S3C2410_ULCON),
795 rd_regl(port, S3C2410_UCON),
796 rd_regl(port, S3C2410_UFCON));
799 * Update the per-port timeout.
801 uart_update_timeout(port, termios->c_cflag, baud);
804 * Which character status flags are we interested in?
806 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
807 if (termios->c_iflag & INPCK)
808 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
811 * Which character status flags should we ignore?
813 port->ignore_status_mask = 0;
814 if (termios->c_iflag & IGNPAR)
815 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
816 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
817 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
820 * Ignore all characters if CREAD is not set.
822 if ((termios->c_cflag & CREAD) == 0)
823 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
825 spin_unlock_irqrestore(&port->lock, flags);
828 static const char *s3c24xx_serial_type(struct uart_port *port)
830 switch (port->type) {
844 #define MAP_SIZE (0x100)
846 static void s3c24xx_serial_release_port(struct uart_port *port)
848 release_mem_region(port->mapbase, MAP_SIZE);
851 static int s3c24xx_serial_request_port(struct uart_port *port)
853 const char *name = s3c24xx_serial_portname(port);
854 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
857 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
859 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
861 if (flags & UART_CONFIG_TYPE &&
862 s3c24xx_serial_request_port(port) == 0)
863 port->type = info->type;
867 * verify the new serial_struct (for TIOCSSERIAL).
870 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
872 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
874 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
881 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
883 static struct console s3c24xx_serial_console;
885 static int __init s3c24xx_serial_console_init(void)
887 register_console(&s3c24xx_serial_console);
890 console_initcall(s3c24xx_serial_console_init);
892 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
894 #define S3C24XX_SERIAL_CONSOLE NULL
897 #ifdef CONFIG_CONSOLE_POLL
898 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
899 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
903 static struct uart_ops s3c24xx_serial_ops = {
904 .pm = s3c24xx_serial_pm,
905 .tx_empty = s3c24xx_serial_tx_empty,
906 .get_mctrl = s3c24xx_serial_get_mctrl,
907 .set_mctrl = s3c24xx_serial_set_mctrl,
908 .stop_tx = s3c24xx_serial_stop_tx,
909 .start_tx = s3c24xx_serial_start_tx,
910 .stop_rx = s3c24xx_serial_stop_rx,
911 .enable_ms = s3c24xx_serial_enable_ms,
912 .break_ctl = s3c24xx_serial_break_ctl,
913 .startup = s3c24xx_serial_startup,
914 .shutdown = s3c24xx_serial_shutdown,
915 .set_termios = s3c24xx_serial_set_termios,
916 .type = s3c24xx_serial_type,
917 .release_port = s3c24xx_serial_release_port,
918 .request_port = s3c24xx_serial_request_port,
919 .config_port = s3c24xx_serial_config_port,
920 .verify_port = s3c24xx_serial_verify_port,
921 #ifdef CONFIG_CONSOLE_POLL
922 .poll_get_char = s3c24xx_serial_get_poll_char,
923 .poll_put_char = s3c24xx_serial_put_poll_char,
927 static struct uart_driver s3c24xx_uart_drv = {
928 .owner = THIS_MODULE,
929 .driver_name = "s3c2410_serial",
930 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
931 .cons = S3C24XX_SERIAL_CONSOLE,
932 .dev_name = S3C24XX_SERIAL_NAME,
933 .major = S3C24XX_SERIAL_MAJOR,
934 .minor = S3C24XX_SERIAL_MINOR,
937 static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
940 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
944 .ops = &s3c24xx_serial_ops,
945 .flags = UPF_BOOT_AUTOCONF,
951 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
955 .ops = &s3c24xx_serial_ops,
956 .flags = UPF_BOOT_AUTOCONF,
960 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
964 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
968 .ops = &s3c24xx_serial_ops,
969 .flags = UPF_BOOT_AUTOCONF,
974 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
977 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
981 .ops = &s3c24xx_serial_ops,
982 .flags = UPF_BOOT_AUTOCONF,
989 /* s3c24xx_serial_resetport
991 * reset the fifos and other the settings.
994 static void s3c24xx_serial_resetport(struct uart_port *port,
995 struct s3c2410_uartcfg *cfg)
997 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
998 unsigned long ucon = rd_regl(port, S3C2410_UCON);
999 unsigned int ucon_mask;
1001 ucon_mask = info->clksel_mask;
1002 if (info->type == PORT_S3C2440)
1003 ucon_mask |= S3C2440_UCON0_DIVMASK;
1006 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1008 /* reset both fifos */
1009 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1010 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1012 /* some delay is required after fifo reset */
1017 #ifdef CONFIG_CPU_FREQ
1019 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1020 unsigned long val, void *data)
1022 struct s3c24xx_uart_port *port;
1023 struct uart_port *uport;
1025 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1026 uport = &port->port;
1028 /* check to see if port is enabled */
1030 if (port->pm_level != 0)
1033 /* try and work out if the baudrate is changing, we can detect
1034 * a change in rate, but we do not have support for detecting
1035 * a disturbance in the clock-rate over the change.
1038 if (IS_ERR(port->baudclk))
1041 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1044 if (val == CPUFREQ_PRECHANGE) {
1045 /* we should really shut the port down whilst the
1046 * frequency change is in progress. */
1048 } else if (val == CPUFREQ_POSTCHANGE) {
1049 struct ktermios *termios;
1050 struct tty_struct *tty;
1052 if (uport->state == NULL)
1055 tty = uport->state->port.tty;
1060 termios = &tty->termios;
1062 if (termios == NULL) {
1063 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1067 s3c24xx_serial_set_termios(uport, termios, NULL);
1074 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1076 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1078 return cpufreq_register_notifier(&port->freq_transition,
1079 CPUFREQ_TRANSITION_NOTIFIER);
1082 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1084 cpufreq_unregister_notifier(&port->freq_transition,
1085 CPUFREQ_TRANSITION_NOTIFIER);
1089 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1094 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1099 /* s3c24xx_serial_init_port
1101 * initialise a single serial port from the platform device given
1104 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1105 struct platform_device *platdev)
1107 struct uart_port *port = &ourport->port;
1108 struct s3c2410_uartcfg *cfg = ourport->cfg;
1109 struct resource *res;
1112 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1114 if (platdev == NULL)
1117 if (port->mapbase != 0)
1120 /* setup info for port */
1121 port->dev = &platdev->dev;
1123 /* Startup sequence is different for s3c64xx and higher SoC's */
1124 if (s3c24xx_serial_has_interrupt_mask(port))
1125 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1129 if (cfg->uart_flags & UPF_CONS_FLOW) {
1130 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1131 port->flags |= UPF_CONS_FLOW;
1134 /* sort our the physical and virtual addresses for each UART */
1136 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1138 dev_err(port->dev, "failed to find memory resource for uart\n");
1142 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1144 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1145 if (!port->membase) {
1146 dev_err(port->dev, "failed to remap controller address\n");
1150 port->mapbase = res->start;
1151 ret = platform_get_irq(platdev, 0);
1156 ourport->rx_irq = ret;
1157 ourport->tx_irq = ret + 1;
1160 ret = platform_get_irq(platdev, 1);
1162 ourport->tx_irq = ret;
1164 ourport->clk = clk_get(&platdev->dev, "uart");
1166 /* Keep all interrupts masked and cleared */
1167 if (s3c24xx_serial_has_interrupt_mask(port)) {
1168 wr_regl(port, S3C64XX_UINTM, 0xf);
1169 wr_regl(port, S3C64XX_UINTP, 0xf);
1170 wr_regl(port, S3C64XX_UINTSP, 0xf);
1173 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1174 port->mapbase, port->membase, port->irq,
1175 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1177 /* reset the fifos (and setup the uart) */
1178 s3c24xx_serial_resetport(port, cfg);
1182 static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1183 struct device_attribute *attr,
1186 struct uart_port *port = s3c24xx_dev_to_port(dev);
1187 struct s3c24xx_uart_port *ourport = to_ourport(port);
1189 if (IS_ERR(ourport->baudclk))
1192 return snprintf(buf, PAGE_SIZE, "* %s\n",
1193 ourport->baudclk->name ?: "(null)");
1196 static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1199 /* Device driver serial port probe */
1201 static const struct of_device_id s3c24xx_uart_dt_match[];
1202 static int probe_index;
1204 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1205 struct platform_device *pdev)
1208 if (pdev->dev.of_node) {
1209 const struct of_device_id *match;
1210 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1211 return (struct s3c24xx_serial_drv_data *)match->data;
1214 return (struct s3c24xx_serial_drv_data *)
1215 platform_get_device_id(pdev)->driver_data;
1218 static int s3c24xx_serial_probe(struct platform_device *pdev)
1220 struct s3c24xx_uart_port *ourport;
1223 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
1225 ourport = &s3c24xx_serial_ports[probe_index];
1227 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1228 if (!ourport->drv_data) {
1229 dev_err(&pdev->dev, "could not find driver data\n");
1233 ourport->baudclk = ERR_PTR(-EINVAL);
1234 ourport->info = ourport->drv_data->info;
1235 ourport->cfg = (pdev->dev.platform_data) ?
1236 (struct s3c2410_uartcfg *)pdev->dev.platform_data :
1237 ourport->drv_data->def_cfg;
1239 ourport->port.fifosize = (ourport->info->fifosize) ?
1240 ourport->info->fifosize :
1241 ourport->drv_data->fifosize[probe_index];
1245 dbg("%s: initialising port %p...\n", __func__, ourport);
1247 ret = s3c24xx_serial_init_port(ourport, pdev);
1251 dbg("%s: adding port\n", __func__);
1252 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1253 platform_set_drvdata(pdev, &ourport->port);
1255 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
1257 dev_err(&pdev->dev, "failed to add clock source attr.\n");
1259 ret = s3c24xx_serial_cpufreq_register(ourport);
1261 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1269 static int s3c24xx_serial_remove(struct platform_device *dev)
1271 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1274 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1275 device_remove_file(&dev->dev, &dev_attr_clock_source);
1276 uart_remove_one_port(&s3c24xx_uart_drv, port);
1282 /* UART power management code */
1283 #ifdef CONFIG_PM_SLEEP
1284 static int s3c24xx_serial_suspend(struct device *dev)
1286 struct uart_port *port = s3c24xx_dev_to_port(dev);
1289 uart_suspend_port(&s3c24xx_uart_drv, port);
1294 static int s3c24xx_serial_resume(struct device *dev)
1296 struct uart_port *port = s3c24xx_dev_to_port(dev);
1297 struct s3c24xx_uart_port *ourport = to_ourport(port);
1300 clk_prepare_enable(ourport->clk);
1301 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1302 clk_disable_unprepare(ourport->clk);
1304 uart_resume_port(&s3c24xx_uart_drv, port);
1310 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1311 .suspend = s3c24xx_serial_suspend,
1312 .resume = s3c24xx_serial_resume,
1314 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1316 #else /* !CONFIG_PM_SLEEP */
1318 #define SERIAL_SAMSUNG_PM_OPS NULL
1319 #endif /* CONFIG_PM_SLEEP */
1323 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1325 static struct uart_port *cons_uart;
1328 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1330 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1331 unsigned long ufstat, utrstat;
1333 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1334 /* fifo mode - check amount of data in fifo registers... */
1336 ufstat = rd_regl(port, S3C2410_UFSTAT);
1337 return (ufstat & info->tx_fifofull) ? 0 : 1;
1340 /* in non-fifo mode, we go and use the tx buffer empty */
1342 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1343 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1346 #ifdef CONFIG_CONSOLE_POLL
1348 * Console polling routines for writing and reading from the uart while
1349 * in an interrupt or debug context.
1352 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1354 struct s3c24xx_uart_port *ourport = to_ourport(port);
1355 unsigned int ufstat;
1357 ufstat = rd_regl(port, S3C2410_UFSTAT);
1358 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1359 return NO_POLL_CHAR;
1361 return rd_regb(port, S3C2410_URXH);
1364 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1367 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1369 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1371 wr_regb(cons_uart, S3C2410_UTXH, c);
1374 #endif /* CONFIG_CONSOLE_POLL */
1377 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1379 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1380 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1382 wr_regb(cons_uart, S3C2410_UTXH, ch);
1386 s3c24xx_serial_console_write(struct console *co, const char *s,
1389 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1393 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1394 int *parity, int *bits)
1399 unsigned int ubrdiv;
1401 unsigned int clk_sel;
1402 char clk_name[MAX_CLK_NAME_LENGTH];
1404 ulcon = rd_regl(port, S3C2410_ULCON);
1405 ucon = rd_regl(port, S3C2410_UCON);
1406 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1408 dbg("s3c24xx_serial_get_options: port=%p\n"
1409 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1410 port, ulcon, ucon, ubrdiv);
1412 if ((ucon & 0xf) != 0) {
1413 /* consider the serial port configured if the tx/rx mode set */
1415 switch (ulcon & S3C2410_LCON_CSMASK) {
1416 case S3C2410_LCON_CS5:
1419 case S3C2410_LCON_CS6:
1422 case S3C2410_LCON_CS7:
1426 case S3C2410_LCON_CS8:
1431 switch (ulcon & S3C2410_LCON_PMASK) {
1432 case S3C2410_LCON_PEVEN:
1436 case S3C2410_LCON_PODD:
1440 case S3C2410_LCON_PNONE:
1445 /* now calculate the baud rate */
1447 clk_sel = s3c24xx_serial_getsource(port);
1448 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
1450 clk = clk_get(port->dev, clk_name);
1452 rate = clk_get_rate(clk);
1456 *baud = rate / (16 * (ubrdiv + 1));
1457 dbg("calculated baud %d\n", *baud);
1463 s3c24xx_serial_console_setup(struct console *co, char *options)
1465 struct uart_port *port;
1471 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1472 co, co->index, options);
1474 /* is this a valid port */
1476 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
1479 port = &s3c24xx_serial_ports[co->index].port;
1481 /* is the port configured? */
1483 if (port->mapbase == 0x0)
1488 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1491 * Check whether an invalid uart number has been specified, and
1492 * if so, search for the first available port that does have
1496 uart_parse_options(options, &baud, &parity, &bits, &flow);
1498 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1500 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1502 return uart_set_options(port, co, baud, parity, bits, flow);
1505 static struct console s3c24xx_serial_console = {
1506 .name = S3C24XX_SERIAL_NAME,
1507 .device = uart_console_device,
1508 .flags = CON_PRINTBUFFER,
1510 .write = s3c24xx_serial_console_write,
1511 .setup = s3c24xx_serial_console_setup,
1512 .data = &s3c24xx_uart_drv,
1514 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1516 #ifdef CONFIG_CPU_S3C2410
1517 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1518 .info = &(struct s3c24xx_uart_info) {
1519 .name = "Samsung S3C2410 UART",
1520 .type = PORT_S3C2410,
1522 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1523 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1524 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1525 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1526 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1527 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1528 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1530 .clksel_mask = S3C2410_UCON_CLKMASK,
1531 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1533 .def_cfg = &(struct s3c2410_uartcfg) {
1534 .ucon = S3C2410_UCON_DEFAULT,
1535 .ufcon = S3C2410_UFCON_DEFAULT,
1538 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1540 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1543 #ifdef CONFIG_CPU_S3C2412
1544 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1545 .info = &(struct s3c24xx_uart_info) {
1546 .name = "Samsung S3C2412 UART",
1547 .type = PORT_S3C2412,
1550 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1551 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1552 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1553 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1554 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1555 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1556 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1558 .clksel_mask = S3C2412_UCON_CLKMASK,
1559 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1561 .def_cfg = &(struct s3c2410_uartcfg) {
1562 .ucon = S3C2410_UCON_DEFAULT,
1563 .ufcon = S3C2410_UFCON_DEFAULT,
1566 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1568 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1571 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1572 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1573 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1574 .info = &(struct s3c24xx_uart_info) {
1575 .name = "Samsung S3C2440 UART",
1576 .type = PORT_S3C2440,
1579 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1580 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1581 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1582 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1583 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1584 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1585 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1587 .clksel_mask = S3C2412_UCON_CLKMASK,
1588 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1590 .def_cfg = &(struct s3c2410_uartcfg) {
1591 .ucon = S3C2410_UCON_DEFAULT,
1592 .ufcon = S3C2410_UFCON_DEFAULT,
1595 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1597 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1600 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1601 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1602 defined(CONFIG_CPU_S5PC100)
1603 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1604 .info = &(struct s3c24xx_uart_info) {
1605 .name = "Samsung S3C6400 UART",
1606 .type = PORT_S3C6400,
1609 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1610 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1611 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1612 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1613 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1614 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1615 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1617 .clksel_mask = S3C6400_UCON_CLKMASK,
1618 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1620 .def_cfg = &(struct s3c2410_uartcfg) {
1621 .ucon = S3C2410_UCON_DEFAULT,
1622 .ufcon = S3C2410_UFCON_DEFAULT,
1625 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1627 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1630 #ifdef CONFIG_CPU_S5PV210
1631 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1632 .info = &(struct s3c24xx_uart_info) {
1633 .name = "Samsung S5PV210 UART",
1634 .type = PORT_S3C6400,
1636 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1637 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1638 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1639 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1640 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1641 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1642 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1644 .clksel_mask = S5PV210_UCON_CLKMASK,
1645 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1647 .def_cfg = &(struct s3c2410_uartcfg) {
1648 .ucon = S5PV210_UCON_DEFAULT,
1649 .ufcon = S5PV210_UFCON_DEFAULT,
1651 .fifosize = { 256, 64, 16, 16 },
1653 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1655 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1658 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
1659 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1660 defined(CONFIG_SOC_EXYNOS5440)
1661 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1662 .info = &(struct s3c24xx_uart_info) {
1663 .name = "Samsung Exynos4 UART",
1664 .type = PORT_S3C6400,
1666 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1667 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1668 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1669 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1670 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1671 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1672 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1677 .def_cfg = &(struct s3c2410_uartcfg) {
1678 .ucon = S5PV210_UCON_DEFAULT,
1679 .ufcon = S5PV210_UFCON_DEFAULT,
1682 .fifosize = { 256, 64, 16, 16 },
1684 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1686 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1689 static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1691 .name = "s3c2410-uart",
1692 .driver_data = S3C2410_SERIAL_DRV_DATA,
1694 .name = "s3c2412-uart",
1695 .driver_data = S3C2412_SERIAL_DRV_DATA,
1697 .name = "s3c2440-uart",
1698 .driver_data = S3C2440_SERIAL_DRV_DATA,
1700 .name = "s3c6400-uart",
1701 .driver_data = S3C6400_SERIAL_DRV_DATA,
1703 .name = "s5pv210-uart",
1704 .driver_data = S5PV210_SERIAL_DRV_DATA,
1706 .name = "exynos4210-uart",
1707 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1711 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1714 static const struct of_device_id s3c24xx_uart_dt_match[] = {
1715 { .compatible = "samsung,s3c2410-uart",
1716 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1717 { .compatible = "samsung,s3c2412-uart",
1718 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1719 { .compatible = "samsung,s3c2440-uart",
1720 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1721 { .compatible = "samsung,s3c6400-uart",
1722 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1723 { .compatible = "samsung,s5pv210-uart",
1724 .data = (void *)S5PV210_SERIAL_DRV_DATA },
1725 { .compatible = "samsung,exynos4210-uart",
1726 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
1729 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
1732 static struct platform_driver samsung_serial_driver = {
1733 .probe = s3c24xx_serial_probe,
1734 .remove = s3c24xx_serial_remove,
1735 .id_table = s3c24xx_serial_driver_ids,
1737 .name = "samsung-uart",
1738 .owner = THIS_MODULE,
1739 .pm = SERIAL_SAMSUNG_PM_OPS,
1740 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
1744 /* module initialisation code */
1746 static int __init s3c24xx_serial_modinit(void)
1750 ret = uart_register_driver(&s3c24xx_uart_drv);
1752 pr_err("Failed to register Samsung UART driver\n");
1756 return platform_driver_register(&samsung_serial_driver);
1759 static void __exit s3c24xx_serial_modexit(void)
1761 uart_unregister_driver(&s3c24xx_uart_drv);
1764 module_init(s3c24xx_serial_modinit);
1765 module_exit(s3c24xx_serial_modexit);
1767 MODULE_ALIAS("platform:samsung-uart");
1768 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1769 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1770 MODULE_LICENSE("GPL v2");