drivers/tty/serial/samsung.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7 */
   8
   9 /* Hote on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22 */
  23
  24 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  25 #define SUPPORT_SYSRQ
  26 #endif
  27
  28 #include <linux/dmaengine.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/module.h>
  32 #include <linux/ioport.h>
  33 #include <linux/io.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/init.h>
  36 #include <linux/sysrq.h>
  37 #include <linux/console.h>
  38 #include <linux/tty.h>
  39 #include <linux/tty_flip.h>
  40 #include <linux/serial_core.h>
  41 #include <linux/serial.h>
  42 #include <linux/serial_s3c.h>
  43 #include <linux/delay.h>
  44 #include <linux/clk.h>
  45 #include <linux/cpufreq.h>
  46 #include <linux/of.h>
  47
  48 #include <asm/irq.h>
  49
  50 #include "samsung.h"
  51
  52 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  53         !defined(MODULE)
  54
  55 extern void printascii(const char *);
  56
  57 __printf(1, 2)
  58 static void dbg(const char *fmt, ...)
  59 {
  60         va_list va;
  61         char buff[256];
  62
  63         va_start(va, fmt);
  64         vscnprintf(buff, sizeof(buff), fmt, va);
  65         va_end(va);
  66
  67         printascii(buff);
  68 }
  69
  70 #else
  71 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  72 #endif
  73
  74 /* UART name and device definitions */
  75
  76 #define S3C24XX_SERIAL_NAME     "ttySAC"
  77 #define S3C24XX_SERIAL_MAJOR    204
  78 #define S3C24XX_SERIAL_MINOR    64
  79
  80 #define S3C24XX_TX_PIO                  1
  81 #define S3C24XX_TX_DMA                  2
  82 #define S3C24XX_RX_PIO                  1
  83 #define S3C24XX_RX_DMA                  2
  84 /* macros to change one thing to another */
  85
  86 #define tx_enabled(port) ((port)->unused[0])
  87 #define rx_enabled(port) ((port)->unused[1])
  88
  89 /* flag to ignore all characters coming in */
  90 #define RXSTAT_DUMMY_READ (0x10000000)
  91
  92 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  93 {
  94         return container_of(port, struct s3c24xx_uart_port, port);
  95 }
  96
  97 /* translate a port to the device name */
  98
  99 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 100 {
 101         return to_platform_device(port->dev)->name;
 102 }
 103
 104 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 105 {
 106         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 107 }
 108
 109 /*
 110  * s3c64xx and later SoC's include the interrupt mask and status registers in
 111  * the controller itself, unlike the s3c24xx SoC's which have these registers
 112  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 113  */
 114 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 115 {
 116         return to_ourport(port)->info->type == PORT_S3C6400;
 117 }
 118
 119 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 120 {
 121         unsigned long flags;
 122         unsigned int ucon, ufcon;
 123         int count = 10000;
 124
 125         spin_lock_irqsave(&port->lock, flags);
 126
 127         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 128                 udelay(100);
 129
 130         ufcon = rd_regl(port, S3C2410_UFCON);
 131         ufcon |= S3C2410_UFCON_RESETRX;
 132         wr_regl(port, S3C2410_UFCON, ufcon);
 133
 134         ucon = rd_regl(port, S3C2410_UCON);
 135         ucon |= S3C2410_UCON_RXIRQMODE;
 136         wr_regl(port, S3C2410_UCON, ucon);
 137
 138         rx_enabled(port) = 1;
 139         spin_unlock_irqrestore(&port->lock, flags);
 140 }
 141
 142 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 143 {
 144         unsigned long flags;
 145         unsigned int ucon;
 146
 147         spin_lock_irqsave(&port->lock, flags);
 148
 149         ucon = rd_regl(port, S3C2410_UCON);
 150         ucon &= ~S3C2410_UCON_RXIRQMODE;
 151         wr_regl(port, S3C2410_UCON, ucon);
 152
 153         rx_enabled(port) = 0;
 154         spin_unlock_irqrestore(&port->lock, flags);
 155 }
 156
 157 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 158 {
 159         struct s3c24xx_uart_port *ourport = to_ourport(port);
 160         struct s3c24xx_uart_dma *dma = ourport->dma;
 161         struct circ_buf *xmit = &port->state->xmit;
 162         struct dma_tx_state state;
 163         int count;
 164
 165         if (!tx_enabled(port))
 166                 return;
 167
 168         if (s3c24xx_serial_has_interrupt_mask(port))
 169                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 170         else
 171                 disable_irq_nosync(ourport->tx_irq);
 172
 173         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 174                 dmaengine_pause(dma->tx_chan);
 175                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 176                 dmaengine_terminate_all(dma->tx_chan);
 177                 dma_sync_single_for_cpu(ourport->port.dev,
 178                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 179                 async_tx_ack(dma->tx_desc);
 180                 count = dma->tx_bytes_requested - state.residue;
 181                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 182                 port->icount.tx += count;
 183         }
 184
 185         tx_enabled(port) = 0;
 186         ourport->tx_in_progress = 0;
 187
 188         if (port->flags & UPF_CONS_FLOW)
 189                 s3c24xx_serial_rx_enable(port);
 190
 191         ourport->tx_mode = 0;
 192 }
 193
 194 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 195
 196 static void s3c24xx_serial_tx_dma_complete(void *args)
 197 {
 198         struct s3c24xx_uart_port *ourport = args;
 199         struct uart_port *port = &ourport->port;
 200         struct circ_buf *xmit = &port->state->xmit;
 201         struct s3c24xx_uart_dma *dma = ourport->dma;
 202         struct dma_tx_state state;
 203         unsigned long flags;
 204         int count;
 205
 206
 207         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 208         count = dma->tx_bytes_requested - state.residue;
 209         async_tx_ack(dma->tx_desc);
 210
 211         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 212                                 dma->tx_size, DMA_TO_DEVICE);
 213
 214         spin_lock_irqsave(&port->lock, flags);
 215
 216         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 217         port->icount.tx += count;
 218         ourport->tx_in_progress = 0;
 219
 220         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 221                 uart_write_wakeup(port);
 222
 223         s3c24xx_serial_start_next_tx(ourport);
 224         spin_unlock_irqrestore(&port->lock, flags);
 225 }
 226
 227 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 228 {
 229         struct uart_port *port = &ourport->port;
 230         u32 ucon;
 231
 232         /* Mask Tx interrupt */
 233         if (s3c24xx_serial_has_interrupt_mask(port))
 234                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 235         else
 236                 disable_irq_nosync(ourport->tx_irq);
 237
 238         /* Enable tx dma mode */
 239         ucon = rd_regl(port, S3C2410_UCON);
 240         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 241         ucon |= (dma_get_cache_alignment() >= 16) ?
 242                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 243         ucon |= S3C64XX_UCON_TXMODE_DMA;
 244         wr_regl(port,  S3C2410_UCON, ucon);
 245
 246         ourport->tx_mode = S3C24XX_TX_DMA;
 247 }
 248
 249 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 250 {
 251         struct uart_port *port = &ourport->port;
 252         u32 ucon, ufcon;
 253
 254         /* Set ufcon txtrig */
 255         ourport->tx_in_progress = S3C24XX_TX_PIO;
 256         ufcon = rd_regl(port, S3C2410_UFCON);
 257         wr_regl(port,  S3C2410_UFCON, ufcon);
 258
 259         /* Enable tx pio mode */
 260         ucon = rd_regl(port, S3C2410_UCON);
 261         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 262         ucon |= S3C64XX_UCON_TXMODE_CPU;
 263         wr_regl(port,  S3C2410_UCON, ucon);
 264
 265         /* Unmask Tx interrupt */
 266         if (s3c24xx_serial_has_interrupt_mask(port))
 267                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 268                                   S3C64XX_UINTM);
 269         else
 270                 enable_irq(ourport->tx_irq);
 271
 272         ourport->tx_mode = S3C24XX_TX_PIO;
 273 }
 274
 275 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 276 {
 277         if (ourport->tx_mode != S3C24XX_TX_PIO)
 278                 enable_tx_pio(ourport);
 279 }
 280
 281 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 282                                       unsigned int count)
 283 {
 284         struct uart_port *port = &ourport->port;
 285         struct circ_buf *xmit = &port->state->xmit;
 286         struct s3c24xx_uart_dma *dma = ourport->dma;
 287
 288
 289         if (ourport->tx_mode != S3C24XX_TX_DMA)
 290                 enable_tx_dma(ourport);
 291
 292         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 293         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 294
 295         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 296                                 dma->tx_size, DMA_TO_DEVICE);
 297
 298         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 299                                 dma->tx_transfer_addr, dma->tx_size,
 300                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 301         if (!dma->tx_desc) {
 302                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 303                 return -EIO;
 304         }
 305
 306         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 307         dma->tx_desc->callback_param = ourport;
 308         dma->tx_bytes_requested = dma->tx_size;
 309
 310         ourport->tx_in_progress = S3C24XX_TX_DMA;
 311         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 312         dma_async_issue_pending(dma->tx_chan);
 313         return 0;
 314 }
 315
 316 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 317 {
 318         struct uart_port *port = &ourport->port;
 319         struct circ_buf *xmit = &port->state->xmit;
 320         unsigned long count;
 321
 322         /* Get data size up to the end of buffer */
 323         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 324
 325         if (!count) {
 326                 s3c24xx_serial_stop_tx(port);
 327                 return;
 328         }
 329
 330         if (!ourport->dma || !ourport->dma->tx_chan ||
 331             count < ourport->min_dma_size ||
 332             xmit->tail & (dma_get_cache_alignment() - 1))
 333                 s3c24xx_serial_start_tx_pio(ourport);
 334         else
 335                 s3c24xx_serial_start_tx_dma(ourport, count);
 336 }
 337
 338 static void s3c24xx_serial_start_tx(struct uart_port *port)
 339 {
 340         struct s3c24xx_uart_port *ourport = to_ourport(port);
 341         struct circ_buf *xmit = &port->state->xmit;
 342
 343         if (!tx_enabled(port)) {
 344                 if (port->flags & UPF_CONS_FLOW)
 345                         s3c24xx_serial_rx_disable(port);
 346
 347                 tx_enabled(port) = 1;
 348                 if (!ourport->dma || !ourport->dma->tx_chan)
 349                         s3c24xx_serial_start_tx_pio(ourport);
 350         }
 351
 352         if (ourport->dma && ourport->dma->tx_chan) {
 353                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 354                         s3c24xx_serial_start_next_tx(ourport);
 355         }
 356 }
 357
 358 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 359                 struct tty_port *tty, int count)
 360 {
 361         struct s3c24xx_uart_dma *dma = ourport->dma;
 362         int copied;
 363
 364         if (!count)
 365                 return;
 366
 367         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 368                                 dma->rx_size, DMA_FROM_DEVICE);
 369
 370         ourport->port.icount.rx += count;
 371         if (!tty) {
 372                 dev_err(ourport->port.dev, "No tty port\n");
 373                 return;
 374         }
 375         copied = tty_insert_flip_string(tty,
 376                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 377         if (copied != count) {
 378                 WARN_ON(1);
 379                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 380         }
 381 }
 382
 383 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 384 {
 385         struct s3c24xx_uart_port *ourport = to_ourport(port);
 386         struct s3c24xx_uart_dma *dma = ourport->dma;
 387         struct tty_port *t = &port->state->port;
 388         struct dma_tx_state state;
 389         enum dma_status dma_status;
 390         unsigned int received;
 391
 392         if (rx_enabled(port)) {
 393                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 394                 if (s3c24xx_serial_has_interrupt_mask(port))
 395                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 396                                         S3C64XX_UINTM);
 397                 else
 398                         disable_irq_nosync(ourport->rx_irq);
 399                 rx_enabled(port) = 0;
 400         }
 401         if (dma && dma->rx_chan) {
 402                 dmaengine_pause(dma->tx_chan);
 403                 dma_status = dmaengine_tx_status(dma->rx_chan,
 404                                 dma->rx_cookie, &state);
 405                 if (dma_status == DMA_IN_PROGRESS ||
 406                         dma_status == DMA_PAUSED) {
 407                         received = dma->rx_bytes_requested - state.residue;
 408                         dmaengine_terminate_all(dma->rx_chan);
 409                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 410                 }
 411         }
 412 }
 413
 414 static inline struct s3c24xx_uart_info
 415         *s3c24xx_port_to_info(struct uart_port *port)
 416 {
 417         return to_ourport(port)->info;
 418 }
 419
 420 static inline struct s3c2410_uartcfg
 421         *s3c24xx_port_to_cfg(struct uart_port *port)
 422 {
 423         struct s3c24xx_uart_port *ourport;
 424
 425         if (port->dev == NULL)
 426                 return NULL;
 427
 428         ourport = container_of(port, struct s3c24xx_uart_port, port);
 429         return ourport->cfg;
 430 }
 431
 432 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 433                                      unsigned long ufstat)
 434 {
 435         struct s3c24xx_uart_info *info = ourport->info;
 436
 437         if (ufstat & info->rx_fifofull)
 438                 return ourport->port.fifosize;
 439
 440         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 441 }
 442
 443 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 444 static void s3c24xx_serial_rx_dma_complete(void *args)
 445 {
 446         struct s3c24xx_uart_port *ourport = args;
 447         struct uart_port *port = &ourport->port;
 448
 449         struct s3c24xx_uart_dma *dma = ourport->dma;
 450         struct tty_port *t = &port->state->port;
 451         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 452
 453         struct dma_tx_state state;
 454         unsigned long flags;
 455         int received;
 456
 457         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 458         received  = dma->rx_bytes_requested - state.residue;
 459         async_tx_ack(dma->rx_desc);
 460
 461         spin_lock_irqsave(&port->lock, flags);
 462
 463         if (received)
 464                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 465
 466         if (tty) {
 467                 tty_flip_buffer_push(t);
 468                 tty_kref_put(tty);
 469         }
 470
 471         s3c64xx_start_rx_dma(ourport);
 472
 473         spin_unlock_irqrestore(&port->lock, flags);
 474 }
 475
 476 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 477 {
 478         struct s3c24xx_uart_dma *dma = ourport->dma;
 479
 480         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 481                                 dma->rx_size, DMA_FROM_DEVICE);
 482
 483         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 484                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 485                                 DMA_PREP_INTERRUPT);
 486         if (!dma->rx_desc) {
 487                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 488                 return;
 489         }
 490
 491         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 492         dma->rx_desc->callback_param = ourport;
 493         dma->rx_bytes_requested = dma->rx_size;
 494
 495         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 496         dma_async_issue_pending(dma->rx_chan);
 497 }
 498
 499 /* ? - where has parity gone?? */
 500 #define S3C2410_UERSTAT_PARITY (0x1000)
 501
 502 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 503 {
 504         struct uart_port *port = &ourport->port;
 505         unsigned int ucon;
 506
 507         /* set Rx mode to DMA mode */
 508         ucon = rd_regl(port, S3C2410_UCON);
 509         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 510                         S3C64XX_UCON_TIMEOUT_MASK |
 511                         S3C64XX_UCON_EMPTYINT_EN |
 512                         S3C64XX_UCON_DMASUS_EN |
 513                         S3C64XX_UCON_TIMEOUT_EN |
 514                         S3C64XX_UCON_RXMODE_MASK);
 515         ucon |= S3C64XX_UCON_RXBURST_16 |
 516                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 517                         S3C64XX_UCON_EMPTYINT_EN |
 518                         S3C64XX_UCON_TIMEOUT_EN |
 519                         S3C64XX_UCON_RXMODE_DMA;
 520         wr_regl(port, S3C2410_UCON, ucon);
 521
 522         ourport->rx_mode = S3C24XX_RX_DMA;
 523 }
 524
 525 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 526 {
 527         struct uart_port *port = &ourport->port;
 528         unsigned int ucon;
 529
 530         /* set Rx mode to DMA mode */
 531         ucon = rd_regl(port, S3C2410_UCON);
 532         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 533                         S3C64XX_UCON_EMPTYINT_EN |
 534                         S3C64XX_UCON_DMASUS_EN |
 535                         S3C64XX_UCON_TIMEOUT_EN |
 536                         S3C64XX_UCON_RXMODE_MASK);
 537         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 538                         S3C64XX_UCON_TIMEOUT_EN |
 539                         S3C64XX_UCON_RXMODE_CPU;
 540         wr_regl(port, S3C2410_UCON, ucon);
 541
 542         ourport->rx_mode = S3C24XX_RX_PIO;
 543 }
 544
 545 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 546
 547 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 548 {
 549         unsigned int utrstat, ufstat, received;
 550         struct s3c24xx_uart_port *ourport = dev_id;
 551         struct uart_port *port = &ourport->port;
 552         struct s3c24xx_uart_dma *dma = ourport->dma;
 553         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 554         struct tty_port *t = &port->state->port;
 555         unsigned long flags;
 556         struct dma_tx_state state;
 557
 558         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 559         ufstat = rd_regl(port, S3C2410_UFSTAT);
 560
 561         spin_lock_irqsave(&port->lock, flags);
 562
 563         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 564                 s3c64xx_start_rx_dma(ourport);
 565                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 566                         enable_rx_dma(ourport);
 567                 goto finish;
 568         }
 569
 570         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 571                 dmaengine_pause(dma->rx_chan);
 572                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 573                 dmaengine_terminate_all(dma->rx_chan);
 574                 received = dma->rx_bytes_requested - state.residue;
 575                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 576
 577                 enable_rx_pio(ourport);
 578         }
 579
 580         s3c24xx_serial_rx_drain_fifo(ourport);
 581
 582         if (tty) {
 583                 tty_flip_buffer_push(t);
 584                 tty_kref_put(tty);
 585         }
 586
 587         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 588
 589 finish:
 590         spin_unlock_irqrestore(&port->lock, flags);
 591
 592         return IRQ_HANDLED;
 593 }
 594
 595 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 596 {
 597         struct uart_port *port = &ourport->port;
 598         unsigned int ufcon, ch, flag, ufstat, uerstat;
 599         unsigned int fifocnt = 0;
 600         int max_count = port->fifosize;
 601
 602         while (max_count-- > 0) {
 603                 /*
 604                  * Receive all characters known to be in FIFO
 605                  * before reading FIFO level again
 606                  */
 607                 if (fifocnt == 0) {
 608                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 609                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 610                         if (fifocnt == 0)
 611                                 break;
 612                 }
 613                 fifocnt--;
 614
 615                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 616                 ch = rd_regb(port, S3C2410_URXH);
 617
 618                 if (port->flags & UPF_CONS_FLOW) {
 619                         int txe = s3c24xx_serial_txempty_nofifo(port);
 620
 621                         if (rx_enabled(port)) {
 622                                 if (!txe) {
 623                                         rx_enabled(port) = 0;
 624                                         continue;
 625                                 }
 626                         } else {
 627                                 if (txe) {
 628                                         ufcon = rd_regl(port, S3C2410_UFCON);
 629                                         ufcon |= S3C2410_UFCON_RESETRX;
 630                                         wr_regl(port, S3C2410_UFCON, ufcon);
 631                                         rx_enabled(port) = 1;
 632                                         return;
 633                                 }
 634                                 continue;
 635                         }
 636                 }
 637
 638                 /* insert the character into the buffer */
 639
 640                 flag = TTY_NORMAL;
 641                 port->icount.rx++;
 642
 643                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 644                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 645                             ch, uerstat);
 646
 647                         /* check for break */
 648                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 649                                 dbg("break!\n");
 650                                 port->icount.brk++;
 651                                 if (uart_handle_break(port))
 652                                         continue; /* Ignore character */
 653                         }
 654
 655                         if (uerstat & S3C2410_UERSTAT_FRAME)
 656                                 port->icount.frame++;
 657                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 658                                 port->icount.overrun++;
 659
 660                         uerstat &= port->read_status_mask;
 661
 662                         if (uerstat & S3C2410_UERSTAT_BREAK)
 663                                 flag = TTY_BREAK;
 664                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 665                                 flag = TTY_PARITY;
 666                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 667                                             S3C2410_UERSTAT_OVERRUN))
 668                                 flag = TTY_FRAME;
 669                 }
 670
 671                 if (uart_handle_sysrq_char(port, ch))
 672                         continue; /* Ignore character */
 673
 674                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 675                                  ch, flag);
 676         }
 677
 678         tty_flip_buffer_push(&port->state->port);
 679 }
 680
 681 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 682 {
 683         struct s3c24xx_uart_port *ourport = dev_id;
 684         struct uart_port *port = &ourport->port;
 685         unsigned long flags;
 686
 687         spin_lock_irqsave(&port->lock, flags);
 688         s3c24xx_serial_rx_drain_fifo(ourport);
 689         spin_unlock_irqrestore(&port->lock, flags);
 690
 691         return IRQ_HANDLED;
 692 }
 693
 694
 695 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 696 {
 697         struct s3c24xx_uart_port *ourport = dev_id;
 698
 699         if (ourport->dma && ourport->dma->rx_chan)
 700                 return s3c24xx_serial_rx_chars_dma(dev_id);
 701         return s3c24xx_serial_rx_chars_pio(dev_id);
 702 }
 703
 704 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 705 {
 706         struct s3c24xx_uart_port *ourport = id;
 707         struct uart_port *port = &ourport->port;
 708         struct circ_buf *xmit = &port->state->xmit;
 709         unsigned long flags;
 710         int count, dma_count = 0;
 711
 712         spin_lock_irqsave(&port->lock, flags);
 713
 714         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 715
 716         if (ourport->dma && ourport->dma->tx_chan &&
 717             count >= ourport->min_dma_size) {
 718                 int align = dma_get_cache_alignment() -
 719                         (xmit->tail & (dma_get_cache_alignment() - 1));
 720                 if (count-align >= ourport->min_dma_size) {
 721                         dma_count = count-align;
 722                         count = align;
 723                 }
 724         }
 725
 726         if (port->x_char) {
 727                 wr_regb(port, S3C2410_UTXH, port->x_char);
 728                 port->icount.tx++;
 729                 port->x_char = 0;
 730                 goto out;
 731         }
 732
 733         /* if there isn't anything more to transmit, or the uart is now
 734          * stopped, disable the uart and exit
 735         */
 736
 737         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 738                 s3c24xx_serial_stop_tx(port);
 739                 goto out;
 740         }
 741
 742         /* try and drain the buffer... */
 743
 744         if (count > port->fifosize) {
 745                 count = port->fifosize;
 746                 dma_count = 0;
 747         }
 748
 749         while (!uart_circ_empty(xmit) && count > 0) {
 750                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 751                         break;
 752
 753                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 754                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 755                 port->icount.tx++;
 756                 count--;
 757         }
 758
 759         if (!count && dma_count) {
 760                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 761                 goto out;
 762         }
 763
 764         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 765                 spin_unlock(&port->lock);
 766                 uart_write_wakeup(port);
 767                 spin_lock(&port->lock);
 768         }
 769
 770         if (uart_circ_empty(xmit))
 771                 s3c24xx_serial_stop_tx(port);
 772
 773 out:
 774         spin_unlock_irqrestore(&port->lock, flags);
 775         return IRQ_HANDLED;
 776 }
 777
 778 /* interrupt handler for s3c64xx and later SoC's.*/
 779 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 780 {
 781         struct s3c24xx_uart_port *ourport = id;
 782         struct uart_port *port = &ourport->port;
 783         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 784         irqreturn_t ret = IRQ_HANDLED;
 785
 786         if (pend & S3C64XX_UINTM_RXD_MSK) {
 787                 ret = s3c24xx_serial_rx_chars(irq, id);
 788                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 789         }
 790         if (pend & S3C64XX_UINTM_TXD_MSK) {
 791                 ret = s3c24xx_serial_tx_chars(irq, id);
 792                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 793         }
 794         return ret;
 795 }
 796
 797 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 798 {
 799         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 800         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 801         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 802
 803         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 804                 if ((ufstat & info->tx_fifomask) != 0 ||
 805                     (ufstat & info->tx_fifofull))
 806                         return 0;
 807
 808                 return 1;
 809         }
 810
 811         return s3c24xx_serial_txempty_nofifo(port);
 812 }
 813
 814 /* no modem control lines */
 815 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 816 {
 817         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 818
 819         if (umstat & S3C2410_UMSTAT_CTS)
 820                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 821         else
 822                 return TIOCM_CAR | TIOCM_DSR;
 823 }
 824
 825 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 826 {
 827         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 828
 829         if (mctrl & TIOCM_RTS)
 830                 umcon |= S3C2410_UMCOM_RTS_LOW;
 831         else
 832                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 833
 834         wr_regl(port, S3C2410_UMCON, umcon);
 835 }
 836
 837 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 838 {
 839         unsigned long flags;
 840         unsigned int ucon;
 841
 842         spin_lock_irqsave(&port->lock, flags);
 843
 844         ucon = rd_regl(port, S3C2410_UCON);
 845
 846         if (break_state)
 847                 ucon |= S3C2410_UCON_SBREAK;
 848         else
 849                 ucon &= ~S3C2410_UCON_SBREAK;
 850
 851         wr_regl(port, S3C2410_UCON, ucon);
 852
 853         spin_unlock_irqrestore(&port->lock, flags);
 854 }
 855
 856 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 857 {
 858         struct s3c24xx_uart_dma *dma = p->dma;
 859         int ret;
 860
 861         /* Default slave configuration parameters */
 862         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 863         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 864         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 865         dma->rx_conf.src_maxburst       = 1;
 866
 867         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 868         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 869         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 870         dma->tx_conf.dst_maxburst       = 1;
 871
 872         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 873
 874         if (IS_ERR(dma->rx_chan))
 875                 return PTR_ERR(dma->rx_chan);
 876
 877         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 878
 879         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
 880         if (IS_ERR(dma->tx_chan)) {
 881                 ret = PTR_ERR(dma->tx_chan);
 882                 goto err_release_rx;
 883         }
 884
 885         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 886
 887         /* RX buffer */
 888         dma->rx_size = PAGE_SIZE;
 889
 890         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 891         if (!dma->rx_buf) {
 892                 ret = -ENOMEM;
 893                 goto err_release_tx;
 894         }
 895
 896         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
 897                                 dma->rx_size, DMA_FROM_DEVICE);
 898         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
 899                 ret = -EIO;
 900                 goto err_free_rx;
 901         }
 902
 903         /* TX buffer */
 904         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
 905                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 906         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
 907                 ret = -EIO;
 908                 goto err_unmap_rx;
 909         }
 910
 911         return 0;
 912
 913 err_unmap_rx:
 914         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
 915                          DMA_FROM_DEVICE);
 916 err_free_rx:
 917         kfree(dma->rx_buf);
 918 err_release_tx:
 919         dma_release_channel(dma->tx_chan);
 920 err_release_rx:
 921         dma_release_channel(dma->rx_chan);
 922         return ret;
 923 }
 924
 925 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 926 {
 927         struct s3c24xx_uart_dma *dma = p->dma;
 928
 929         if (dma->rx_chan) {
 930                 dmaengine_terminate_all(dma->rx_chan);
 931                 dma_unmap_single(p->port.dev, dma->rx_addr,
 932                                 dma->rx_size, DMA_FROM_DEVICE);
 933                 kfree(dma->rx_buf);
 934                 dma_release_channel(dma->rx_chan);
 935                 dma->rx_chan = NULL;
 936         }
 937
 938         if (dma->tx_chan) {
 939                 dmaengine_terminate_all(dma->tx_chan);
 940                 dma_unmap_single(p->port.dev, dma->tx_addr,
 941                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 942                 dma_release_channel(dma->tx_chan);
 943                 dma->tx_chan = NULL;
 944         }
 945 }
 946
 947 static void s3c24xx_serial_shutdown(struct uart_port *port)
 948 {
 949         struct s3c24xx_uart_port *ourport = to_ourport(port);
 950
 951         if (ourport->tx_claimed) {
 952                 if (!s3c24xx_serial_has_interrupt_mask(port))
 953                         free_irq(ourport->tx_irq, ourport);
 954                 tx_enabled(port) = 0;
 955                 ourport->tx_claimed = 0;
 956                 ourport->tx_mode = 0;
 957         }
 958
 959         if (ourport->rx_claimed) {
 960                 if (!s3c24xx_serial_has_interrupt_mask(port))
 961                         free_irq(ourport->rx_irq, ourport);
 962                 ourport->rx_claimed = 0;
 963                 rx_enabled(port) = 0;
 964         }
 965
 966         /* Clear pending interrupts and mask all interrupts */
 967         if (s3c24xx_serial_has_interrupt_mask(port)) {
 968                 free_irq(port->irq, ourport);
 969
 970                 wr_regl(port, S3C64XX_UINTP, 0xf);
 971                 wr_regl(port, S3C64XX_UINTM, 0xf);
 972         }
 973
 974         if (ourport->dma)
 975                 s3c24xx_serial_release_dma(ourport);
 976
 977         ourport->tx_in_progress = 0;
 978 }
 979
 980 static int s3c24xx_serial_startup(struct uart_port *port)
 981 {
 982         struct s3c24xx_uart_port *ourport = to_ourport(port);
 983         int ret;
 984
 985         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
 986             port, (unsigned long long)port->mapbase, port->membase);
 987
 988         rx_enabled(port) = 1;
 989
 990         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
 991                           s3c24xx_serial_portname(port), ourport);
 992
 993         if (ret != 0) {
 994                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
 995                 return ret;
 996         }
 997
 998         ourport->rx_claimed = 1;
 999
1000         dbg("requesting tx irq...\n");
1001
1002         tx_enabled(port) = 1;
1003
1004         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1005                           s3c24xx_serial_portname(port), ourport);
1006
1007         if (ret) {
1008                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1009                 goto err;
1010         }
1011
1012         ourport->tx_claimed = 1;
1013
1014         dbg("s3c24xx_serial_startup ok\n");
1015
1016         /* the port reset code should have done the correct
1017          * register setup for the port controls */
1018
1019         return ret;
1020
1021 err:
1022         s3c24xx_serial_shutdown(port);
1023         return ret;
1024 }
1025
1026 static int s3c64xx_serial_startup(struct uart_port *port)
1027 {
1028         struct s3c24xx_uart_port *ourport = to_ourport(port);
1029         unsigned long flags;
1030         unsigned int ufcon;
1031         int ret;
1032
1033         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1034             port, (unsigned long long)port->mapbase, port->membase);
1035
1036         wr_regl(port, S3C64XX_UINTM, 0xf);
1037         if (ourport->dma) {
1038                 ret = s3c24xx_serial_request_dma(ourport);
1039                 if (ret < 0) {
1040                         dev_warn(port->dev,
1041                                  "DMA request failed, DMA will not be used\n");
1042                         devm_kfree(port->dev, ourport->dma);
1043                         ourport->dma = NULL;
1044                 }
1045         }
1046
1047         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1048                           s3c24xx_serial_portname(port), ourport);
1049         if (ret) {
1050                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1051                 return ret;
1052         }
1053
1054         /* For compatibility with s3c24xx Soc's */
1055         rx_enabled(port) = 1;
1056         ourport->rx_claimed = 1;
1057         tx_enabled(port) = 0;
1058         ourport->tx_claimed = 1;
1059
1060         spin_lock_irqsave(&port->lock, flags);
1061
1062         ufcon = rd_regl(port, S3C2410_UFCON);
1063         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1064         if (!uart_console(port))
1065                 ufcon |= S3C2410_UFCON_RESETTX;
1066         wr_regl(port, S3C2410_UFCON, ufcon);
1067
1068         enable_rx_pio(ourport);
1069
1070         spin_unlock_irqrestore(&port->lock, flags);
1071
1072         /* Enable Rx Interrupt */
1073         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1074
1075         dbg("s3c64xx_serial_startup ok\n");
1076         return ret;
1077 }
1078
1079 /* power power management control */
1080
1081 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1082                               unsigned int old)
1083 {
1084         struct s3c24xx_uart_port *ourport = to_ourport(port);
1085         int timeout = 10000;
1086
1087         ourport->pm_level = level;
1088
1089         switch (level) {
1090         case 3:
1091                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1092                         udelay(100);
1093
1094                 if (!IS_ERR(ourport->baudclk))
1095                         clk_disable_unprepare(ourport->baudclk);
1096
1097                 clk_disable_unprepare(ourport->clk);
1098                 break;
1099
1100         case 0:
1101                 clk_prepare_enable(ourport->clk);
1102
1103                 if (!IS_ERR(ourport->baudclk))
1104                         clk_prepare_enable(ourport->baudclk);
1105
1106                 break;
1107         default:
1108                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1109         }
1110 }
1111
1112 /* baud rate calculation
1113  *
1114  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1115  * of different sources, including the peripheral clock ("pclk") and an
1116  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1117  * with a programmable extra divisor.
1118  *
1119  * The following code goes through the clock sources, and calculates the
1120  * baud clocks (and the resultant actual baud rates) and then tries to
1121  * pick the closest one and select that.
1122  *
1123 */
1124
1125 #define MAX_CLK_NAME_LENGTH 15
1126
1127 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1128 {
1129         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1130         unsigned int ucon;
1131
1132         if (info->num_clks == 1)
1133                 return 0;
1134
1135         ucon = rd_regl(port, S3C2410_UCON);
1136         ucon &= info->clksel_mask;
1137         return ucon >> info->clksel_shift;
1138 }
1139
1140 static void s3c24xx_serial_setsource(struct uart_port *port,
1141                         unsigned int clk_sel)
1142 {
1143         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1144         unsigned int ucon;
1145
1146         if (info->num_clks == 1)
1147                 return;
1148
1149         ucon = rd_regl(port, S3C2410_UCON);
1150         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1151                 return;
1152
1153         ucon &= ~info->clksel_mask;
1154         ucon |= clk_sel << info->clksel_shift;
1155         wr_regl(port, S3C2410_UCON, ucon);
1156 }
1157
1158 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1159                         unsigned int req_baud, struct clk **best_clk,
1160                         unsigned int *clk_num)
1161 {
1162         struct s3c24xx_uart_info *info = ourport->info;
1163         struct clk *clk;
1164         unsigned long rate;
1165         unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1166         char clkname[MAX_CLK_NAME_LENGTH];
1167         int calc_deviation, deviation = (1 << 30) - 1;
1168
1169         clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1170                         ourport->info->def_clk_sel;
1171         for (cnt = 0; cnt < info->num_clks; cnt++) {
1172                 if (!(clk_sel & (1 << cnt)))
1173                         continue;
1174
1175                 sprintf(clkname, "clk_uart_baud%d", cnt);
1176                 clk = clk_get(ourport->port.dev, clkname);
1177                 if (IS_ERR(clk))
1178                         continue;
1179
1180                 rate = clk_get_rate(clk);
1181                 if (!rate)
1182                         continue;
1183
1184                 if (ourport->info->has_divslot) {
1185                         unsigned long div = rate / req_baud;
1186
1187                         /* The UDIVSLOT register on the newer UARTs allows us to
1188                          * get a divisor adjustment of 1/16th on the baud clock.
1189                          *
1190                          * We don't keep the UDIVSLOT value (the 16ths we
1191                          * calculated by not multiplying the baud by 16) as it
1192                          * is easy enough to recalculate.
1193                          */
1194
1195                         quot = div / 16;
1196                         baud = rate / div;
1197                 } else {
1198                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1199                         baud = rate / (quot * 16);
1200                 }
1201                 quot--;
1202
1203                 calc_deviation = req_baud - baud;
1204                 if (calc_deviation < 0)
1205                         calc_deviation = -calc_deviation;
1206
1207                 if (calc_deviation < deviation) {
1208                         *best_clk = clk;
1209                         best_quot = quot;
1210                         *clk_num = cnt;
1211                         deviation = calc_deviation;
1212                 }
1213         }
1214
1215         return best_quot;
1216 }
1217
1218 /* udivslot_table[]
1219  *
1220  * This table takes the fractional value of the baud divisor and gives
1221  * the recommended setting for the UDIVSLOT register.
1222  */
1223 static u16 udivslot_table[16] = {
1224         [0] = 0x0000,
1225         [1] = 0x0080,
1226         [2] = 0x0808,
1227         [3] = 0x0888,
1228         [4] = 0x2222,
1229         [5] = 0x4924,
1230         [6] = 0x4A52,
1231         [7] = 0x54AA,
1232         [8] = 0x5555,
1233         [9] = 0xD555,
1234         [10] = 0xD5D5,
1235         [11] = 0xDDD5,
1236         [12] = 0xDDDD,
1237         [13] = 0xDFDD,
1238         [14] = 0xDFDF,
1239         [15] = 0xFFDF,
1240 };
1241
1242 static void s3c24xx_serial_set_termios(struct uart_port *port,
1243                                        struct ktermios *termios,
1244                                        struct ktermios *old)
1245 {
1246         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1247         struct s3c24xx_uart_port *ourport = to_ourport(port);
1248         struct clk *clk = ERR_PTR(-EINVAL);
1249         unsigned long flags;
1250         unsigned int baud, quot, clk_sel = 0;
1251         unsigned int ulcon;
1252         unsigned int umcon;
1253         unsigned int udivslot = 0;
1254
1255         /*
1256          * We don't support modem control lines.
1257          */
1258         termios->c_cflag &= ~(HUPCL | CMSPAR);
1259         termios->c_cflag |= CLOCAL;
1260
1261         /*
1262          * Ask the core to calculate the divisor for us.
1263          */
1264
1265         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1266         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1267         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1268                 quot = port->custom_divisor;
1269         if (IS_ERR(clk))
1270                 return;
1271
1272         /* check to see if we need  to change clock source */
1273
1274         if (ourport->baudclk != clk) {
1275                 clk_prepare_enable(clk);
1276
1277                 s3c24xx_serial_setsource(port, clk_sel);
1278
1279                 if (!IS_ERR(ourport->baudclk)) {
1280                         clk_disable_unprepare(ourport->baudclk);
1281                         ourport->baudclk = ERR_PTR(-EINVAL);
1282                 }
1283
1284                 ourport->baudclk = clk;
1285                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1286         }
1287
1288         if (ourport->info->has_divslot) {
1289                 unsigned int div = ourport->baudclk_rate / baud;
1290
1291                 if (cfg->has_fracval) {
1292                         udivslot = (div & 15);
1293                         dbg("fracval = %04x\n", udivslot);
1294                 } else {
1295                         udivslot = udivslot_table[div & 15];
1296                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1297                 }
1298         }
1299
1300         switch (termios->c_cflag & CSIZE) {
1301         case CS5:
1302                 dbg("config: 5bits/char\n");
1303                 ulcon = S3C2410_LCON_CS5;
1304                 break;
1305         case CS6:
1306                 dbg("config: 6bits/char\n");
1307                 ulcon = S3C2410_LCON_CS6;
1308                 break;
1309         case CS7:
1310                 dbg("config: 7bits/char\n");
1311                 ulcon = S3C2410_LCON_CS7;
1312                 break;
1313         case CS8:
1314         default:
1315                 dbg("config: 8bits/char\n");
1316                 ulcon = S3C2410_LCON_CS8;
1317                 break;
1318         }
1319
1320         /* preserve original lcon IR settings */
1321         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1322
1323         if (termios->c_cflag & CSTOPB)
1324                 ulcon |= S3C2410_LCON_STOPB;
1325
1326         if (termios->c_cflag & PARENB) {
1327                 if (termios->c_cflag & PARODD)
1328                         ulcon |= S3C2410_LCON_PODD;
1329                 else
1330                         ulcon |= S3C2410_LCON_PEVEN;
1331         } else {
1332                 ulcon |= S3C2410_LCON_PNONE;
1333         }
1334
1335         spin_lock_irqsave(&port->lock, flags);
1336
1337         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1338             ulcon, quot, udivslot);
1339
1340         wr_regl(port, S3C2410_ULCON, ulcon);
1341         wr_regl(port, S3C2410_UBRDIV, quot);
1342
1343         umcon = rd_regl(port, S3C2410_UMCON);
1344         if (termios->c_cflag & CRTSCTS) {
1345                 umcon |= S3C2410_UMCOM_AFC;
1346                 /* Disable RTS when RX FIFO contains 63 bytes */
1347                 umcon &= ~S3C2412_UMCON_AFC_8;
1348         } else {
1349                 umcon &= ~S3C2410_UMCOM_AFC;
1350         }
1351         wr_regl(port, S3C2410_UMCON, umcon);
1352
1353         if (ourport->info->has_divslot)
1354                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1355
1356         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1357             rd_regl(port, S3C2410_ULCON),
1358             rd_regl(port, S3C2410_UCON),
1359             rd_regl(port, S3C2410_UFCON));
1360
1361         /*
1362          * Update the per-port timeout.
1363          */
1364         uart_update_timeout(port, termios->c_cflag, baud);
1365
1366         /*
1367          * Which character status flags are we interested in?
1368          */
1369         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1370         if (termios->c_iflag & INPCK)
1371                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1372                         S3C2410_UERSTAT_PARITY;
1373         /*
1374          * Which character status flags should we ignore?
1375          */
1376         port->ignore_status_mask = 0;
1377         if (termios->c_iflag & IGNPAR)
1378                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1379         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1380                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1381
1382         /*
1383          * Ignore all characters if CREAD is not set.
1384          */
1385         if ((termios->c_cflag & CREAD) == 0)
1386                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1387
1388         spin_unlock_irqrestore(&port->lock, flags);
1389 }
1390
1391 static const char *s3c24xx_serial_type(struct uart_port *port)
1392 {
1393         switch (port->type) {
1394         case PORT_S3C2410:
1395                 return "S3C2410";
1396         case PORT_S3C2440:
1397                 return "S3C2440";
1398         case PORT_S3C2412:
1399                 return "S3C2412";
1400         case PORT_S3C6400:
1401                 return "S3C6400/10";
1402         default:
1403                 return NULL;
1404         }
1405 }
1406
1407 #define MAP_SIZE (0x100)
1408
1409 static void s3c24xx_serial_release_port(struct uart_port *port)
1410 {
1411         release_mem_region(port->mapbase, MAP_SIZE);
1412 }
1413
1414 static int s3c24xx_serial_request_port(struct uart_port *port)
1415 {
1416         const char *name = s3c24xx_serial_portname(port);
1417         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1418 }
1419
1420 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1421 {
1422         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1423
1424         if (flags & UART_CONFIG_TYPE &&
1425             s3c24xx_serial_request_port(port) == 0)
1426                 port->type = info->type;
1427 }
1428
1429 /*
1430  * verify the new serial_struct (for TIOCSSERIAL).
1431  */
1432 static int
1433 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1434 {
1435         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1436
1437         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1438                 return -EINVAL;
1439
1440         return 0;
1441 }
1442
1443
1444 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1445
1446 static struct console s3c24xx_serial_console;
1447
1448 static int __init s3c24xx_serial_console_init(void)
1449 {
1450         register_console(&s3c24xx_serial_console);
1451         return 0;
1452 }
1453 console_initcall(s3c24xx_serial_console_init);
1454
1455 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1456 #else
1457 #define S3C24XX_SERIAL_CONSOLE NULL
1458 #endif
1459
1460 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1461 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1462 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1463                          unsigned char c);
1464 #endif
1465
1466 static struct uart_ops s3c24xx_serial_ops = {
1467         .pm             = s3c24xx_serial_pm,
1468         .tx_empty       = s3c24xx_serial_tx_empty,
1469         .get_mctrl      = s3c24xx_serial_get_mctrl,
1470         .set_mctrl      = s3c24xx_serial_set_mctrl,
1471         .stop_tx        = s3c24xx_serial_stop_tx,
1472         .start_tx       = s3c24xx_serial_start_tx,
1473         .stop_rx        = s3c24xx_serial_stop_rx,
1474         .break_ctl      = s3c24xx_serial_break_ctl,
1475         .startup        = s3c24xx_serial_startup,
1476         .shutdown       = s3c24xx_serial_shutdown,
1477         .set_termios    = s3c24xx_serial_set_termios,
1478         .type           = s3c24xx_serial_type,
1479         .release_port   = s3c24xx_serial_release_port,
1480         .request_port   = s3c24xx_serial_request_port,
1481         .config_port    = s3c24xx_serial_config_port,
1482         .verify_port    = s3c24xx_serial_verify_port,
1483 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1484         .poll_get_char = s3c24xx_serial_get_poll_char,
1485         .poll_put_char = s3c24xx_serial_put_poll_char,
1486 #endif
1487 };
1488
1489 static struct uart_driver s3c24xx_uart_drv = {
1490         .owner          = THIS_MODULE,
1491         .driver_name    = "s3c2410_serial",
1492         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1493         .cons           = S3C24XX_SERIAL_CONSOLE,
1494         .dev_name       = S3C24XX_SERIAL_NAME,
1495         .major          = S3C24XX_SERIAL_MAJOR,
1496         .minor          = S3C24XX_SERIAL_MINOR,
1497 };
1498
1499 #define __PORT_LOCK_UNLOCKED(i) \
1500         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1501 static struct s3c24xx_uart_port
1502 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1503         [0] = {
1504                 .port = {
1505                         .lock           = __PORT_LOCK_UNLOCKED(0),
1506                         .iotype         = UPIO_MEM,
1507                         .uartclk        = 0,
1508                         .fifosize       = 16,
1509                         .ops            = &s3c24xx_serial_ops,
1510                         .flags          = UPF_BOOT_AUTOCONF,
1511                         .line           = 0,
1512                 }
1513         },
1514         [1] = {
1515                 .port = {
1516                         .lock           = __PORT_LOCK_UNLOCKED(1),
1517                         .iotype         = UPIO_MEM,
1518                         .uartclk        = 0,
1519                         .fifosize       = 16,
1520                         .ops            = &s3c24xx_serial_ops,
1521                         .flags          = UPF_BOOT_AUTOCONF,
1522                         .line           = 1,
1523                 }
1524         },
1525 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1526
1527         [2] = {
1528                 .port = {
1529                         .lock           = __PORT_LOCK_UNLOCKED(2),
1530                         .iotype         = UPIO_MEM,
1531                         .uartclk        = 0,
1532                         .fifosize       = 16,
1533                         .ops            = &s3c24xx_serial_ops,
1534                         .flags          = UPF_BOOT_AUTOCONF,
1535                         .line           = 2,
1536                 }
1537         },
1538 #endif
1539 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1540         [3] = {
1541                 .port = {
1542                         .lock           = __PORT_LOCK_UNLOCKED(3),
1543                         .iotype         = UPIO_MEM,
1544                         .uartclk        = 0,
1545                         .fifosize       = 16,
1546                         .ops            = &s3c24xx_serial_ops,
1547                         .flags          = UPF_BOOT_AUTOCONF,
1548                         .line           = 3,
1549                 }
1550         }
1551 #endif
1552 };
1553 #undef __PORT_LOCK_UNLOCKED
1554
1555 /* s3c24xx_serial_resetport
1556  *
1557  * reset the fifos and other the settings.
1558 */
1559
1560 static void s3c24xx_serial_resetport(struct uart_port *port,
1561                                    struct s3c2410_uartcfg *cfg)
1562 {
1563         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1564         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1565         unsigned int ucon_mask;
1566
1567         ucon_mask = info->clksel_mask;
1568         if (info->type == PORT_S3C2440)
1569                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1570
1571         ucon &= ucon_mask;
1572         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1573
1574         /* reset both fifos */
1575         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1576         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1577
1578         /* some delay is required after fifo reset */
1579         udelay(1);
1580 }
1581
1582
1583 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1584
1585 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1586                                              unsigned long val, void *data)
1587 {
1588         struct s3c24xx_uart_port *port;
1589         struct uart_port *uport;
1590
1591         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1592         uport = &port->port;
1593
1594         /* check to see if port is enabled */
1595
1596         if (port->pm_level != 0)
1597                 return 0;
1598
1599         /* try and work out if the baudrate is changing, we can detect
1600          * a change in rate, but we do not have support for detecting
1601          * a disturbance in the clock-rate over the change.
1602          */
1603
1604         if (IS_ERR(port->baudclk))
1605                 goto exit;
1606
1607         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1608                 goto exit;
1609
1610         if (val == CPUFREQ_PRECHANGE) {
1611                 /* we should really shut the port down whilst the
1612                  * frequency change is in progress. */
1613
1614         } else if (val == CPUFREQ_POSTCHANGE) {
1615                 struct ktermios *termios;
1616                 struct tty_struct *tty;
1617
1618                 if (uport->state == NULL)
1619                         goto exit;
1620
1621                 tty = uport->state->port.tty;
1622
1623                 if (tty == NULL)
1624                         goto exit;
1625
1626                 termios = &tty->termios;
1627
1628                 if (termios == NULL) {
1629                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1630                         goto exit;
1631                 }
1632
1633                 s3c24xx_serial_set_termios(uport, termios, NULL);
1634         }
1635
1636 exit:
1637         return 0;
1638 }
1639
1640 static inline int
1641 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1642 {
1643         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1644
1645         return cpufreq_register_notifier(&port->freq_transition,
1646                                          CPUFREQ_TRANSITION_NOTIFIER);
1647 }
1648
1649 static inline void
1650 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1651 {
1652         cpufreq_unregister_notifier(&port->freq_transition,
1653                                     CPUFREQ_TRANSITION_NOTIFIER);
1654 }
1655
1656 #else
1657 static inline int
1658 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1659 {
1660         return 0;
1661 }
1662
1663 static inline void
1664 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1665 {
1666 }
1667 #endif
1668
1669 /* s3c24xx_serial_init_port
1670  *
1671  * initialise a single serial port from the platform device given
1672  */
1673
1674 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1675                                     struct platform_device *platdev)
1676 {
1677         struct uart_port *port = &ourport->port;
1678         struct s3c2410_uartcfg *cfg = ourport->cfg;
1679         struct resource *res;
1680         int ret;
1681
1682         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1683
1684         if (platdev == NULL)
1685                 return -ENODEV;
1686
1687         if (port->mapbase != 0)
1688                 return -EINVAL;
1689
1690         /* setup info for port */
1691         port->dev       = &platdev->dev;
1692
1693         /* Startup sequence is different for s3c64xx and higher SoC's */
1694         if (s3c24xx_serial_has_interrupt_mask(port))
1695                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1696
1697         port->uartclk = 1;
1698
1699         if (cfg->uart_flags & UPF_CONS_FLOW) {
1700                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1701                 port->flags |= UPF_CONS_FLOW;
1702         }
1703
1704         /* sort our the physical and virtual addresses for each UART */
1705
1706         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1707         if (res == NULL) {
1708                 dev_err(port->dev, "failed to find memory resource for uart\n");
1709                 return -EINVAL;
1710         }
1711
1712         dbg("resource %pR)\n", res);
1713
1714         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1715         if (!port->membase) {
1716                 dev_err(port->dev, "failed to remap controller address\n");
1717                 return -EBUSY;
1718         }
1719
1720         port->mapbase = res->start;
1721         ret = platform_get_irq(platdev, 0);
1722         if (ret < 0)
1723                 port->irq = 0;
1724         else {
1725                 port->irq = ret;
1726                 ourport->rx_irq = ret;
1727                 ourport->tx_irq = ret + 1;
1728         }
1729
1730         ret = platform_get_irq(platdev, 1);
1731         if (ret > 0)
1732                 ourport->tx_irq = ret;
1733         /*
1734          * DMA is currently supported only on DT platforms, if DMA properties
1735          * are specified.
1736          */
1737         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1738                                                      "dmas", NULL)) {
1739                 ourport->dma = devm_kzalloc(port->dev,
1740                                             sizeof(*ourport->dma),
1741                                             GFP_KERNEL);
1742                 if (!ourport->dma) {
1743                         ret = -ENOMEM;
1744                         goto err;
1745                 }
1746         }
1747
1748         ourport->clk    = clk_get(&platdev->dev, "uart");
1749         if (IS_ERR(ourport->clk)) {
1750                 pr_err("%s: Controller clock not found\n",
1751                                 dev_name(&platdev->dev));
1752                 ret = PTR_ERR(ourport->clk);
1753                 goto err;
1754         }
1755
1756         ret = clk_prepare_enable(ourport->clk);
1757         if (ret) {
1758                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1759                 clk_put(ourport->clk);
1760                 goto err;
1761         }
1762
1763         /* Keep all interrupts masked and cleared */
1764         if (s3c24xx_serial_has_interrupt_mask(port)) {
1765                 wr_regl(port, S3C64XX_UINTM, 0xf);
1766                 wr_regl(port, S3C64XX_UINTP, 0xf);
1767                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1768         }
1769
1770         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1771             &port->mapbase, port->membase, port->irq,
1772             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1773
1774         /* reset the fifos (and setup the uart) */
1775         s3c24xx_serial_resetport(port, cfg);
1776
1777         return 0;
1778
1779 err:
1780         port->mapbase = 0;
1781         return ret;
1782 }
1783
1784 /* Device driver serial port probe */
1785
1786 static const struct of_device_id s3c24xx_uart_dt_match[];
1787 static int probe_index;
1788
1789 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1790                         struct platform_device *pdev)
1791 {
1792 #ifdef CONFIG_OF
1793         if (pdev->dev.of_node) {
1794                 const struct of_device_id *match;
1795                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1796                 return (struct s3c24xx_serial_drv_data *)match->data;
1797         }
1798 #endif
1799         return (struct s3c24xx_serial_drv_data *)
1800                         platform_get_device_id(pdev)->driver_data;
1801 }
1802
1803 static int s3c24xx_serial_probe(struct platform_device *pdev)
1804 {
1805         struct device_node *np = pdev->dev.of_node;
1806         struct s3c24xx_uart_port *ourport;
1807         int index = probe_index;
1808         int ret;
1809
1810         if (np) {
1811                 ret = of_alias_get_id(np, "serial");
1812                 if (ret >= 0)
1813                         index = ret;
1814         }
1815
1816         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1817
1818         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1819                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1820                 return -EINVAL;
1821         }
1822         ourport = &s3c24xx_serial_ports[index];
1823
1824         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1825         if (!ourport->drv_data) {
1826                 dev_err(&pdev->dev, "could not find driver data\n");
1827                 return -ENODEV;
1828         }
1829
1830         ourport->baudclk = ERR_PTR(-EINVAL);
1831         ourport->info = ourport->drv_data->info;
1832         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1833                         dev_get_platdata(&pdev->dev) :
1834                         ourport->drv_data->def_cfg;
1835
1836         if (np)
1837                 of_property_read_u32(np,
1838                         "samsung,uart-fifosize", &ourport->port.fifosize);
1839
1840         if (ourport->drv_data->fifosize[index])
1841                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1842         else if (ourport->info->fifosize)
1843                 ourport->port.fifosize = ourport->info->fifosize;
1844
1845         /*
1846          * DMA transfers must be aligned at least to cache line size,
1847          * so find minimal transfer size suitable for DMA mode
1848          */
1849         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1850                                     dma_get_cache_alignment());
1851
1852         dbg("%s: initialising port %p...\n", __func__, ourport);
1853
1854         ret = s3c24xx_serial_init_port(ourport, pdev);
1855         if (ret < 0)
1856                 return ret;
1857
1858         if (!s3c24xx_uart_drv.state) {
1859                 ret = uart_register_driver(&s3c24xx_uart_drv);
1860                 if (ret < 0) {
1861                         pr_err("Failed to register Samsung UART driver\n");
1862                         return ret;
1863                 }
1864         }
1865
1866         dbg("%s: adding port\n", __func__);
1867         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1868         platform_set_drvdata(pdev, &ourport->port);
1869
1870         /*
1871          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1872          * so that a potential re-enablement through the pm-callback overlaps
1873          * and keeps the clock enabled in this case.
1874          */
1875         clk_disable_unprepare(ourport->clk);
1876
1877         ret = s3c24xx_serial_cpufreq_register(ourport);
1878         if (ret < 0)
1879                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1880
1881         probe_index++;
1882
1883         return 0;
1884 }
1885
1886 static int s3c24xx_serial_remove(struct platform_device *dev)
1887 {
1888         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1889
1890         if (port) {
1891                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1892                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1893         }
1894
1895         uart_unregister_driver(&s3c24xx_uart_drv);
1896
1897         return 0;
1898 }
1899
1900 /* UART power management code */
1901 #ifdef CONFIG_PM_SLEEP
1902 static int s3c24xx_serial_suspend(struct device *dev)
1903 {
1904         struct uart_port *port = s3c24xx_dev_to_port(dev);
1905
1906         if (port)
1907                 uart_suspend_port(&s3c24xx_uart_drv, port);
1908
1909         return 0;
1910 }
1911
1912 static int s3c24xx_serial_resume(struct device *dev)
1913 {
1914         struct uart_port *port = s3c24xx_dev_to_port(dev);
1915         struct s3c24xx_uart_port *ourport = to_ourport(port);
1916
1917         if (port) {
1918                 clk_prepare_enable(ourport->clk);
1919                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1920                 clk_disable_unprepare(ourport->clk);
1921
1922                 uart_resume_port(&s3c24xx_uart_drv, port);
1923         }
1924
1925         return 0;
1926 }
1927
1928 static int s3c24xx_serial_resume_noirq(struct device *dev)
1929 {
1930         struct uart_port *port = s3c24xx_dev_to_port(dev);
1931         struct s3c24xx_uart_port *ourport = to_ourport(port);
1932
1933         if (port) {
1934                 /* restore IRQ mask */
1935                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1936                         unsigned int uintm = 0xf;
1937                         if (tx_enabled(port))
1938                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1939                         if (rx_enabled(port))
1940                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1941                         clk_prepare_enable(ourport->clk);
1942                         wr_regl(port, S3C64XX_UINTM, uintm);
1943                         clk_disable_unprepare(ourport->clk);
1944                 }
1945         }
1946
1947         return 0;
1948 }
1949
1950 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1951         .suspend = s3c24xx_serial_suspend,
1952         .resume = s3c24xx_serial_resume,
1953         .resume_noirq = s3c24xx_serial_resume_noirq,
1954 };
1955 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1956
1957 #else /* !CONFIG_PM_SLEEP */
1958
1959 #define SERIAL_SAMSUNG_PM_OPS   NULL
1960 #endif /* CONFIG_PM_SLEEP */
1961
1962 /* Console code */
1963
1964 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1965
1966 static struct uart_port *cons_uart;
1967
1968 static int
1969 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1970 {
1971         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1972         unsigned long ufstat, utrstat;
1973
1974         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1975                 /* fifo mode - check amount of data in fifo registers... */
1976
1977                 ufstat = rd_regl(port, S3C2410_UFSTAT);
1978                 return (ufstat & info->tx_fifofull) ? 0 : 1;
1979         }
1980
1981         /* in non-fifo mode, we go and use the tx buffer empty */
1982
1983         utrstat = rd_regl(port, S3C2410_UTRSTAT);
1984         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1985 }
1986
1987 static bool
1988 s3c24xx_port_configured(unsigned int ucon)
1989 {
1990         /* consider the serial port configured if the tx/rx mode set */
1991         return (ucon & 0xf) != 0;
1992 }
1993
1994 #ifdef CONFIG_CONSOLE_POLL
1995 /*
1996  * Console polling routines for writing and reading from the uart while
1997  * in an interrupt or debug context.
1998  */
1999
2000 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2001 {
2002         struct s3c24xx_uart_port *ourport = to_ourport(port);
2003         unsigned int ufstat;
2004
2005         ufstat = rd_regl(port, S3C2410_UFSTAT);
2006         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2007                 return NO_POLL_CHAR;
2008
2009         return rd_regb(port, S3C2410_URXH);
2010 }
2011
2012 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2013                 unsigned char c)
2014 {
2015         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2016         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2017
2018         /* not possible to xmit on unconfigured port */
2019         if (!s3c24xx_port_configured(ucon))
2020                 return;
2021
2022         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2023                 cpu_relax();
2024         wr_regb(port, S3C2410_UTXH, c);
2025 }
2026
2027 #endif /* CONFIG_CONSOLE_POLL */
2028
2029 static void
2030 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2031 {
2032         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2033
2034         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2035                 cpu_relax();
2036         wr_regb(port, S3C2410_UTXH, ch);
2037 }
2038
2039 static void
2040 s3c24xx_serial_console_write(struct console *co, const char *s,
2041                              unsigned int count)
2042 {
2043         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2044
2045         /* not possible to xmit on unconfigured port */
2046         if (!s3c24xx_port_configured(ucon))
2047                 return;
2048
2049         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2050 }
2051
2052 static void __init
2053 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2054                            int *parity, int *bits)
2055 {
2056         struct clk *clk;
2057         unsigned int ulcon;
2058         unsigned int ucon;
2059         unsigned int ubrdiv;
2060         unsigned long rate;
2061         unsigned int clk_sel;
2062         char clk_name[MAX_CLK_NAME_LENGTH];
2063
2064         ulcon  = rd_regl(port, S3C2410_ULCON);
2065         ucon   = rd_regl(port, S3C2410_UCON);
2066         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2067
2068         dbg("s3c24xx_serial_get_options: port=%p\n"
2069             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2070             port, ulcon, ucon, ubrdiv);
2071
2072         if (s3c24xx_port_configured(ucon)) {
2073                 switch (ulcon & S3C2410_LCON_CSMASK) {
2074                 case S3C2410_LCON_CS5:
2075                         *bits = 5;
2076                         break;
2077                 case S3C2410_LCON_CS6:
2078                         *bits = 6;
2079                         break;
2080                 case S3C2410_LCON_CS7:
2081                         *bits = 7;
2082                         break;
2083                 case S3C2410_LCON_CS8:
2084                 default:
2085                         *bits = 8;
2086                         break;
2087                 }
2088
2089                 switch (ulcon & S3C2410_LCON_PMASK) {
2090                 case S3C2410_LCON_PEVEN:
2091                         *parity = 'e';
2092                         break;
2093
2094                 case S3C2410_LCON_PODD:
2095                         *parity = 'o';
2096                         break;
2097
2098                 case S3C2410_LCON_PNONE:
2099                 default:
2100                         *parity = 'n';
2101                 }
2102
2103                 /* now calculate the baud rate */
2104
2105                 clk_sel = s3c24xx_serial_getsource(port);
2106                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2107
2108                 clk = clk_get(port->dev, clk_name);
2109                 if (!IS_ERR(clk))
2110                         rate = clk_get_rate(clk);
2111                 else
2112                         rate = 1;
2113
2114                 *baud = rate / (16 * (ubrdiv + 1));
2115                 dbg("calculated baud %d\n", *baud);
2116         }
2117
2118 }
2119
2120 static int __init
2121 s3c24xx_serial_console_setup(struct console *co, char *options)
2122 {
2123         struct uart_port *port;
2124         int baud = 9600;
2125         int bits = 8;
2126         int parity = 'n';
2127         int flow = 'n';
2128
2129         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2130             co, co->index, options);
2131
2132         /* is this a valid port */
2133
2134         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2135                 co->index = 0;
2136
2137         port = &s3c24xx_serial_ports[co->index].port;
2138
2139         /* is the port configured? */
2140
2141         if (port->mapbase == 0x0)
2142                 return -ENODEV;
2143
2144         cons_uart = port;
2145
2146         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2147
2148         /*
2149          * Check whether an invalid uart number has been specified, and
2150          * if so, search for the first available port that does have
2151          * console support.
2152          */
2153         if (options)
2154                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2155         else
2156                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2157
2158         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2159
2160         return uart_set_options(port, co, baud, parity, bits, flow);
2161 }
2162
2163 static struct console s3c24xx_serial_console = {
2164         .name           = S3C24XX_SERIAL_NAME,
2165         .device         = uart_console_device,
2166         .flags          = CON_PRINTBUFFER,
2167         .index          = -1,
2168         .write          = s3c24xx_serial_console_write,
2169         .setup          = s3c24xx_serial_console_setup,
2170         .data           = &s3c24xx_uart_drv,
2171 };
2172 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2173
2174 #ifdef CONFIG_CPU_S3C2410
2175 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2176         .info = &(struct s3c24xx_uart_info) {
2177                 .name           = "Samsung S3C2410 UART",
2178                 .type           = PORT_S3C2410,
2179                 .fifosize       = 16,
2180                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2181                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2182                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2183                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2184                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2185                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2186                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2187                 .num_clks       = 2,
2188                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2189                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2190         },
2191         .def_cfg = &(struct s3c2410_uartcfg) {
2192                 .ucon           = S3C2410_UCON_DEFAULT,
2193                 .ufcon          = S3C2410_UFCON_DEFAULT,
2194         },
2195 };
2196 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2197 #else
2198 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2199 #endif
2200
2201 #ifdef CONFIG_CPU_S3C2412
2202 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2203         .info = &(struct s3c24xx_uart_info) {
2204                 .name           = "Samsung S3C2412 UART",
2205                 .type           = PORT_S3C2412,
2206                 .fifosize       = 64,
2207                 .has_divslot    = 1,
2208                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2209                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2210                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2211                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2212                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2213                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2214                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2215                 .num_clks       = 4,
2216                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2217                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2218         },
2219         .def_cfg = &(struct s3c2410_uartcfg) {
2220                 .ucon           = S3C2410_UCON_DEFAULT,
2221                 .ufcon          = S3C2410_UFCON_DEFAULT,
2222         },
2223 };
2224 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2225 #else
2226 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2227 #endif
2228
2229 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2230         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2231 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2232         .info = &(struct s3c24xx_uart_info) {
2233                 .name           = "Samsung S3C2440 UART",
2234                 .type           = PORT_S3C2440,
2235                 .fifosize       = 64,
2236                 .has_divslot    = 1,
2237                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2238                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2239                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2240                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2241                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2242                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2243                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2244                 .num_clks       = 4,
2245                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2246                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2247         },
2248         .def_cfg = &(struct s3c2410_uartcfg) {
2249                 .ucon           = S3C2410_UCON_DEFAULT,
2250                 .ufcon          = S3C2410_UFCON_DEFAULT,
2251         },
2252 };
2253 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2254 #else
2255 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2256 #endif
2257
2258 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2259 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2260         .info = &(struct s3c24xx_uart_info) {
2261                 .name           = "Samsung S3C6400 UART",
2262                 .type           = PORT_S3C6400,
2263                 .fifosize       = 64,
2264                 .has_divslot    = 1,
2265                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2266                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2267                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2268                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2269                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2270                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2271                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2272                 .num_clks       = 4,
2273                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2274                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2275         },
2276         .def_cfg = &(struct s3c2410_uartcfg) {
2277                 .ucon           = S3C2410_UCON_DEFAULT,
2278                 .ufcon          = S3C2410_UFCON_DEFAULT,
2279         },
2280 };
2281 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2282 #else
2283 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2284 #endif
2285
2286 #ifdef CONFIG_CPU_S5PV210
2287 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2288         .info = &(struct s3c24xx_uart_info) {
2289                 .name           = "Samsung S5PV210 UART",
2290                 .type           = PORT_S3C6400,
2291                 .has_divslot    = 1,
2292                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2293                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2294                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2295                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2296                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2297                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2298                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2299                 .num_clks       = 2,
2300                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2301                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2302         },
2303         .def_cfg = &(struct s3c2410_uartcfg) {
2304                 .ucon           = S5PV210_UCON_DEFAULT,
2305                 .ufcon          = S5PV210_UFCON_DEFAULT,
2306         },
2307         .fifosize = { 256, 64, 16, 16 },
2308 };
2309 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2310 #else
2311 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2312 #endif
2313
2314 #if defined(CONFIG_ARCH_EXYNOS)
2315 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2316         .info = &(struct s3c24xx_uart_info) {                   \
2317                 .name           = "Samsung Exynos UART",        \
2318                 .type           = PORT_S3C6400,                 \
2319                 .has_divslot    = 1,                            \
2320                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2321                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2322                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2323                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2324                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2325                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2326                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2327                 .num_clks       = 1,                            \
2328                 .clksel_mask    = 0,                            \
2329                 .clksel_shift   = 0,                            \
2330         },                                                      \
2331         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2332                 .ucon           = S5PV210_UCON_DEFAULT,         \
2333                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2334                 .has_fracval    = 1,                            \
2335         }                                                       \
2336
2337 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2338         EXYNOS_COMMON_SERIAL_DRV_DATA,
2339         .fifosize = { 256, 64, 16, 16 },
2340 };
2341
2342 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2343         EXYNOS_COMMON_SERIAL_DRV_DATA,
2344         .fifosize = { 64, 256, 16, 256 },
2345 };
2346
2347 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2348 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2349 #else
2350 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2351 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2352 #endif
2353
2354 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2355         {
2356                 .name           = "s3c2410-uart",
2357                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2358         }, {
2359                 .name           = "s3c2412-uart",
2360                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2361         }, {
2362                 .name           = "s3c2440-uart",
2363                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2364         }, {
2365                 .name           = "s3c6400-uart",
2366                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2367         }, {
2368                 .name           = "s5pv210-uart",
2369                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2370         }, {
2371                 .name           = "exynos4210-uart",
2372                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2373         }, {
2374                 .name           = "exynos5433-uart",
2375                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2376         },
2377         { },
2378 };
2379 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2380
2381 #ifdef CONFIG_OF
2382 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2383         { .compatible = "samsung,s3c2410-uart",
2384                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2385         { .compatible = "samsung,s3c2412-uart",
2386                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2387         { .compatible = "samsung,s3c2440-uart",
2388                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2389         { .compatible = "samsung,s3c6400-uart",
2390                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2391         { .compatible = "samsung,s5pv210-uart",
2392                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2393         { .compatible = "samsung,exynos4210-uart",
2394                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2395         { .compatible = "samsung,exynos5433-uart",
2396                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2397         {},
2398 };
2399 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2400 #endif
2401
2402 static struct platform_driver samsung_serial_driver = {
2403         .probe          = s3c24xx_serial_probe,
2404         .remove         = s3c24xx_serial_remove,
2405         .id_table       = s3c24xx_serial_driver_ids,
2406         .driver         = {
2407                 .name   = "samsung-uart",
2408                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2409                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2410         },
2411 };
2412
2413 module_platform_driver(samsung_serial_driver);
2414
2415 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2416 /*
2417  * Early console.
2418  */
2419
2420 struct samsung_early_console_data {
2421         u32 txfull_mask;
2422 };
2423
2424 static void samsung_early_busyuart(struct uart_port *port)
2425 {
2426         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2427                 ;
2428 }
2429
2430 static void samsung_early_busyuart_fifo(struct uart_port *port)
2431 {
2432         struct samsung_early_console_data *data = port->private_data;
2433
2434         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2435                 ;
2436 }
2437
2438 static void samsung_early_putc(struct uart_port *port, int c)
2439 {
2440         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2441                 samsung_early_busyuart_fifo(port);
2442         else
2443                 samsung_early_busyuart(port);
2444
2445         writeb(c, port->membase + S3C2410_UTXH);
2446 }
2447
2448 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2449 {
2450         struct earlycon_device *dev = con->data;
2451
2452         uart_console_write(&dev->port, s, n, samsung_early_putc);
2453 }
2454
2455 static int __init samsung_early_console_setup(struct earlycon_device *device,
2456                                               const char *opt)
2457 {
2458         if (!device->port.membase)
2459                 return -ENODEV;
2460
2461         device->con->write = samsung_early_write;
2462         return 0;
2463 }
2464
2465 /* S3C2410 */
2466 static struct samsung_early_console_data s3c2410_early_console_data = {
2467         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2468 };
2469
2470 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2471                                               const char *opt)
2472 {
2473         device->port.private_data = &s3c2410_early_console_data;
2474         return samsung_early_console_setup(device, opt);
2475 }
2476 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2477                         s3c2410_early_console_setup);
2478
2479 /* S3C2412, S3C2440, S3C64xx */
2480 static struct samsung_early_console_data s3c2440_early_console_data = {
2481         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2482 };
2483
2484 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2485                                               const char *opt)
2486 {
2487         device->port.private_data = &s3c2440_early_console_data;
2488         return samsung_early_console_setup(device, opt);
2489 }
2490 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2491                         s3c2440_early_console_setup);
2492 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2493                         s3c2440_early_console_setup);
2494 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2495                         s3c2440_early_console_setup);
2496
2497 /* S5PV210, EXYNOS */
2498 static struct samsung_early_console_data s5pv210_early_console_data = {
2499         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2500 };
2501
2502 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2503                                               const char *opt)
2504 {
2505         device->port.private_data = &s5pv210_early_console_data;
2506         return samsung_early_console_setup(device, opt);
2507 }
2508 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2509                         s5pv210_early_console_setup);
2510 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2511                         s5pv210_early_console_setup);
2512 #endif
2513
2514 MODULE_ALIAS("platform:samsung-uart");
2515 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2516 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2517 MODULE_LICENSE("GPL v2");